diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2017-09-05 17:46:09 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2017-09-07 13:00:07 +0200 |
| commit | 22f5dfd300f791ecd2c79565731a72074bc7562f (patch) | |
| tree | b921387598c242aa5b1185d3a76f613576dc78f7 | |
| parent | 17dd4856a68621ab7107975df8239fb2963a57bb (diff) | |
radeonsi: don't read the number of TCS out vertices from an SGPR in TCS
-16 bytes in one shader binary.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 861d82fff7..61ee040ec7 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -385,6 +385,19 @@ get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx) ""); } +static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx) +{ + unsigned tcs_out_vertices = + ctx->shader->selector ? + ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0; + + /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */ + if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices) + return LLVMConstInt(ctx->i32, tcs_out_vertices, 0); + + return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6); +} + static LLVMValueRef get_instance_index_for_fetch( struct si_shader_context *ctx, unsigned param_start_instance, LLVMValueRef divisor) @@ -804,7 +817,7 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx, LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices; LLVMValueRef param_stride, constant16; - vertices_per_patch = unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6); + vertices_per_patch = get_num_tcs_out_vertices(ctx); num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6); total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch, num_patches, ""); @@ -1622,7 +1635,7 @@ void si_load_system_value(struct si_shader_context *ctx, if (ctx->type == PIPE_SHADER_TESS_CTRL) value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6); else if (ctx->type == PIPE_SHADER_TESS_EVAL) - value = unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6); + value = get_num_tcs_out_vertices(ctx); else assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN"); break; |