radv: calculate non-draw related ia_multi_vgt_param bits in pipeline

This moves a bunch of non-draw dependent calcs into the pipeline code,
to reduce CPU overheads in the draw path.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

3 files changed, 76 insertions, 60 deletions

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 590dd67c46..b95b4f85c0 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2014,6 +2014,72 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
 	else
 		pipeline->graphics.primgroup_size = 128; /* recommended without a GS */
 
+	pipeline->graphics.partial_es_wave = false;
+	if (pipeline->device->has_distributed_tess) {
+		if (radv_pipeline_has_gs(pipeline)) {
+			if (device->physical_device->rad_info.chip_class <= VI)
+				pipeline->graphics.partial_es_wave = true;
+		}
+	}
+	/* GS requirement. */
+	if (SI_GS_PER_ES / pipeline->graphics.primgroup_size >= pipeline->device->gs_table_depth - 3)
+		pipeline->graphics.partial_es_wave = true;
+
+	pipeline->graphics.wd_switch_on_eop = false;
+	if (device->physical_device->rad_info.chip_class >= CIK) {
+		unsigned prim = pipeline->graphics.prim;
+		/* WD_SWITCH_ON_EOP has no effect on GPUs with less than
+		 * 4 shader engines. Set 1 to pass the assertion below.
+		 * The other cases are hardware requirements. */
+		if (device->physical_device->rad_info.max_se < 4 ||
+		    prim == V_008958_DI_PT_POLYGON ||
+		    prim == V_008958_DI_PT_LINELOOP ||
+		    prim == V_008958_DI_PT_TRIFAN ||
+		    prim == V_008958_DI_PT_TRISTRIP_ADJ ||
+		    (pipeline->graphics.prim_restart_enable &&
+		     (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
+		      (prim != V_008958_DI_PT_POINTLIST &&
+		       prim != V_008958_DI_PT_LINESTRIP &&
+		       prim != V_008958_DI_PT_TRISTRIP))))
+			pipeline->graphics.wd_switch_on_eop = true;
+	}
+
+	pipeline->graphics.ia_switch_on_eoi = false;
+	if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
+		pipeline->graphics.ia_switch_on_eoi = true;
+	if (radv_pipeline_has_gs(pipeline) &&
+	    pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
+		pipeline->graphics.ia_switch_on_eoi = true;
+	if (radv_pipeline_has_tess(pipeline)) {
+		/* SWITCH_ON_EOI must be set if PrimID is used. */
+		if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
+		    pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
+			pipeline->graphics.ia_switch_on_eoi = true;
+	}
+
+	pipeline->graphics.partial_vs_wave = false;
+	if (radv_pipeline_has_tess(pipeline)) {
+		/* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
+		if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
+		     device->physical_device->rad_info.family == CHIP_PITCAIRN ||
+		     device->physical_device->rad_info.family == CHIP_BONAIRE) &&
+		    radv_pipeline_has_gs(pipeline))
+			pipeline->graphics.partial_vs_wave = true;
+		/* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
+		if (device->has_distributed_tess) {
+			if (radv_pipeline_has_gs(pipeline)) {
+				if (device->physical_device->rad_info.family == CHIP_TONGA ||
+				    device->physical_device->rad_info.family == CHIP_FIJI ||
+				    device->physical_device->rad_info.family == CHIP_POLARIS10 ||
+				    device->physical_device->rad_info.family == CHIP_POLARIS11 ||
+				    device->physical_device->rad_info.family == CHIP_POLARIS12)
+					pipeline->graphics.partial_vs_wave = true;
+			} else {
+				pipeline->graphics.partial_vs_wave = true;
+			}
+		}
+	}
+
 	const VkPipelineVertexInputStateCreateInfo *vi_info =
 		pCreateInfo->pVertexInputState;
 	struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index c647efdcbc..af3024f30e 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1044,6 +1044,8 @@ struct radv_vertex_elements_info {
 	uint32_t count;
 };
 
+#define SI_GS_PER_ES 128
+
 struct radv_pipeline {
 	struct radv_device *                          device;
 	uint32_t                                     dynamic_state_mask;
@@ -1075,6 +1077,7 @@ struct radv_pipeline {
 			uint32_t vgt_gs_mode;
 			bool vgt_primitiveid_en;
 			bool prim_restart_enable;
+			bool partial_es_wave;
 			uint8_t primgroup_size;
 			unsigned esgs_ring_size;
 			unsigned gsvs_ring_size;
@@ -1083,6 +1086,9 @@ struct radv_pipeline {
 			uint32_t pa_cl_vs_out_cntl;
 			uint32_t vgt_shader_stages_en;
 			uint32_t vtx_base_sgpr;
+			bool wd_switch_on_eop;
+			bool ia_switch_on_eoi;
+			bool partial_vs_wave;
 			uint8_t vtx_emit_num;
 			struct radv_prim_vertex_count prim_vertex_count;
  			bool can_use_guardband;
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 9abd05583c..178855faac 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -35,8 +35,6 @@
 #include "radv_util.h"
 #include "main/macros.h"
 
-#define SI_GS_PER_ES 128
-
 static void
 si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
                                   struct radeon_winsys_cs *cs,
@@ -689,7 +687,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
 	bool ia_switch_on_eop = false;
 	bool ia_switch_on_eoi = false;
 	bool partial_vs_wave = false;
-	bool partial_es_wave = false;
+	bool partial_es_wave = cmd_buffer->state.pipeline->graphics.partial_es_wave;
 	bool multi_instances_smaller_than_primgroup;
 
 	multi_instances_smaller_than_primgroup = indirect_draw;
@@ -699,56 +697,11 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
 			multi_instances_smaller_than_primgroup = true;
 	}
 
-	if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
-		ia_switch_on_eoi = true;
-
-	if (radv_pipeline_has_tess(cmd_buffer->state.pipeline)) {
-		/* SWITCH_ON_EOI must be set if PrimID is used. */
-		if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.uses_prim_id ||
-		    cmd_buffer->state.pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.uses_prim_id)
-			ia_switch_on_eoi = true;
-
-		/* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
-		if ((family == CHIP_TAHITI ||
-		     family == CHIP_PITCAIRN ||
-		     family == CHIP_BONAIRE) &&
-		    radv_pipeline_has_gs(cmd_buffer->state.pipeline))
-			partial_vs_wave = true;
-
-		/* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
-		if (cmd_buffer->device->has_distributed_tess) {
-			if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
-				if (chip_class <= VI)
-					partial_es_wave = true;
-
-				if (family == CHIP_TONGA ||
-				    family == CHIP_FIJI ||
-				    family == CHIP_POLARIS10 ||
-				    family == CHIP_POLARIS11 ||
-				    family == CHIP_POLARIS12)
-					partial_vs_wave = true;
-			} else {
-				partial_vs_wave = true;
-			}
-		}
-	}
-	/* TODO linestipple */
+	ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_switch_on_eoi;
+	partial_vs_wave = cmd_buffer->state.pipeline->graphics.partial_vs_wave;
 
 	if (chip_class >= CIK) {
-		/* WD_SWITCH_ON_EOP has no effect on GPUs with less than
-		 * 4 shader engines. Set 1 to pass the assertion below.
-		 * The other cases are hardware requirements. */
-		if (info->max_se < 4 ||
-		    prim == V_008958_DI_PT_POLYGON ||
-		    prim == V_008958_DI_PT_LINELOOP ||
-		    prim == V_008958_DI_PT_TRIFAN ||
-		    prim == V_008958_DI_PT_TRISTRIP_ADJ ||
-		    (cmd_buffer->state.pipeline->graphics.prim_restart_enable &&
-		     (family < CHIP_POLARIS10 ||
-		      (prim != V_008958_DI_PT_POINTLIST &&
-		      prim != V_008958_DI_PT_LINESTRIP &&
-		       prim != V_008958_DI_PT_TRISTRIP))))
-			wd_switch_on_eop = true;
+		wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.wd_switch_on_eop;
 
 		/* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
 		 * We don't know that for indirect drawing, so treat it as
@@ -791,15 +744,6 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
 		partial_es_wave = true;
 
 	if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
-
-		if (radv_pipeline_has_gs(cmd_buffer->state.pipeline) &&
-		    cmd_buffer->state.pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.uses_prim_id)
-			ia_switch_on_eoi = true;
-
-		/* GS requirement. */
-		if (SI_GS_PER_ES / cmd_buffer->state.pipeline->graphics.primgroup_size >= cmd_buffer->device->gs_table_depth - 3)
-			partial_es_wave = true;
-
 		/* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
 		 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
 		 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.