diff options
| author | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2017-07-04 10:23:49 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2017-07-31 14:55:30 +0200 |
| commit | e044e9eb2af2835446a9d72ad1e555f8c2e7cb80 (patch) | |
| tree | 3bb2d655b5e6ca603697c20902c5ecff2ed97780 | |
| parent | c5f97eab094c43cedcb2218599a1f0aa51b16238 (diff) | |
st/glsl_to_nir: move nir_lower_io to drivers
This allows drivers more freedom in how exactly they want to lower I/O,
e.g. first lowering I/O to temporaries.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
| -rw-r--r-- | src/gallium/drivers/freedreno/ir3/ir3_shader.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/vc4/vc4_program.c | 3 | ||||
| -rw-r--r-- | src/mesa/state_tracker/st_glsl_to_nir.cpp | 3 |
3 files changed, 10 insertions, 2 deletions
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.c b/src/gallium/drivers/freedreno/ir3/ir3_shader.c index 636111b103..ec8834235c 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_shader.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.c @@ -296,6 +296,9 @@ ir3_shader_create(struct ir3_compiler *compiler, if (cso->type == PIPE_SHADER_IR_NIR) { /* we take ownership of the reference: */ nir = cso->ir.nir; + + NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, + (nir_lower_io_options)0); } else { debug_assert(cso->type == PIPE_SHADER_IR_TGSI); if (fd_mesa_debug & FD_DBG_DISASM) { @@ -342,6 +345,9 @@ ir3_shader_create_compute(struct ir3_compiler *compiler, if (cso->ir_type == PIPE_SHADER_IR_NIR) { /* we take ownership of the reference: */ nir = (nir_shader *)cso->prog; + + NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, + (nir_lower_io_options)0); } else { debug_assert(cso->ir_type == PIPE_SHADER_IR_TGSI); if (fd_mesa_debug & FD_DBG_DISASM) { diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c index 3beac61f31..999c154b86 100644 --- a/src/gallium/drivers/vc4/vc4_program.c +++ b/src/gallium/drivers/vc4/vc4_program.c @@ -2427,6 +2427,9 @@ vc4_shader_state_create(struct pipe_context *pctx, * creation. */ s = cso->ir.nir; + + NIR_PASS_V(s, nir_lower_io, nir_var_all, type_size, + (nir_lower_io_options)0); } else { assert(cso->type == PIPE_SHADER_IR_TGSI); diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp b/src/mesa/state_tracker/st_glsl_to_nir.cpp index dd3d6faa75..7f5a9afda8 100644 --- a/src/mesa/state_tracker/st_glsl_to_nir.cpp +++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp @@ -377,8 +377,7 @@ st_finalize_nir(struct st_context *st, struct gl_program *prog, nir_shader *nir) &nir->uniforms, &nir->num_uniforms); NIR_PASS_V(nir, nir_lower_system_values); - NIR_PASS_V(nir, nir_lower_io, nir_var_all, type_size, - (nir_lower_io_options)0); + if (screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF)) NIR_PASS_V(nir, nir_lower_samplers_as_deref, shader_program); else |