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authorSamuel Pitoiset <samuel.pitoiset@gmail.com>2016-11-25 12:25:58 +0100
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>2016-11-26 19:05:11 +0100
commit8fdb800bdaa28f4ca563829f70e8b187f867c0ac (patch)
tree8249cbff9d94cc12415a245abf060818957fe2a9
parent948cce01964c1dd7365c49381f9a6cf1b6e5f7f9 (diff)
gm107/ir: optimize 32-bit CONST load to mov
This is not allowed for indirect accesses because the source GPR might be erased by a subsequent instruction (WaR hazard) if we don't emit a read dep bar. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp16
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h1
2 files changed, 17 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
index 84ef4e0fb7..371ebae40c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp
@@ -61,6 +61,19 @@ GM107LegalizeSSA::handlePFETCH(Instruction *i)
i->setSrc(1, NULL);
}
+void
+GM107LegalizeSSA::handleLOAD(Instruction *i)
+{
+ if (i->src(0).getFile() != FILE_MEMORY_CONST)
+ return;
+ if (i->src(0).isIndirect(0))
+ return;
+ if (typeSizeof(i->dType) != 4)
+ return;
+
+ i->op = OP_MOV;
+}
+
bool
GM107LegalizeSSA::visit(Instruction *i)
{
@@ -68,6 +81,9 @@ GM107LegalizeSSA::visit(Instruction *i)
case OP_PFETCH:
handlePFETCH(i);
break;
+ case OP_LOAD:
+ handleLOAD(i);
+ break;
default:
break;
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
index 81749bf57e..d0737beda6 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.h
@@ -21,6 +21,7 @@ private:
virtual bool visit(Instruction *);
void handlePFETCH(Instruction *);
+ void handleLOAD(Instruction *);
};
} // namespace nv50_ir