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AgeCommit message (Expand)AuthorFilesLines
2014-07-21[DAG] Refactor some logic. No functional change.Andrea Di Biagio1-28/+6
2014-07-18X86: support fpext/fptrunc operations to and from 16-bit floats.Tim Northover1-0/+5
2014-07-18X86: Constant fold converting vector setcc results to float.Jim Grosbach1-0/+51
2014-07-17ms inline asm: Don't add x86 segment registers to the clobber list.Nico Weber1-0/+5
2014-07-17[X86] AVX512: Add disassembler support for compressed displacementAdam Nemet3-3/+21
2014-07-17[X86] AVX512: Rename EVEX_CD8V to CD8_FormAdam Nemet1-5/+5
2014-07-17[X86] AVX512: Use the TD version of CD8_Scale in the assemblerAdam Nemet3-62/+16
2014-07-17[X86] AVX512: Move compressed displacement logic to TDAdam Nemet2-0/+34
2014-07-17MC: fix MCAsmInfo usage for windows-itaniumSaleem Abdulrasool1-1/+2
2014-07-17CodeGen: generate single libcall for fptrunc -> f16 operations.Tim Northover1-1/+3
2014-07-17X86: support double extension of f16 type.Tim Northover1-0/+4
2014-07-17CodeGen: extend f16 conversions to permit types > float.Tim Northover2-5/+5
2014-07-16Remove Atom references in description.Sanjay Patel1-4/+3
2014-07-16CodeGen: don't form illegail EXTLOAD operations.Tim Northover1-1/+6
2014-07-16[X86] Add a check for 'isMOVHLPSMask' within method 'isShuffleMaskLegal'.Andrea Di Biagio1-0/+1
2014-07-15X86: Simplify X86WindowsTargetObjectFile::getSectionForConstantDavid Majnemer1-9/+3
2014-07-15Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel5-25/+9
2014-07-15Revert r213070. It's breaking the build in MCELFStreamer::EmitInstToData(...).Cameron McInally1-6/+0
2014-07-15Add x86 patterns to match a specific add-with-carry. Cameron McInally1-0/+6
2014-07-15Silence a warning in conditional expression.Andrea Di Biagio1-1/+1
2014-07-15Fix typo in commentDavid Majnemer1-1/+1
2014-07-15[FastISel][X86] Remove no longer needed functions.Juergen Ributzka1-462/+0
2014-07-15[FastISel][X86] Implement the FastLowerIntrinsicCall hook.Juergen Ributzka1-41/+41
2014-07-15[FastISel][X86] Implement the FastLowerCall hook.Juergen Ributzka1-9/+400
2014-07-15Revert "[FastISel][X86] Remove no longer needed functions."Juergen Ributzka1-244/+315
2014-07-15CodeGen: Handle ConstantVector and undef in WinCOFF constant poolsDavid Majnemer1-13/+21
2014-07-15[FastISel][X86] Remove no longer needed functions.Juergen Ributzka1-462/+0
2014-07-15[FastISel][X86] Implement the FastLowerIntrinsicCall hook.Juergen Ributzka1-41/+41
2014-07-15[FastISel][X86] Implement the FastLowerCall hook.Juergen Ributzka1-9/+400
2014-07-14[X86] Specify all TSFlags bit-offsets symbolicallyAdam Nemet1-3/+6
2014-07-14CodeGen: Stick constant pool entries in COMDAT sections for WinCOFFDavid Majnemer4-0/+91
2014-07-14X86: correct 64-bit atomics on 32-bitSaleem Abdulrasool1-12/+8
2014-07-14X86: remove temporary atomicrmw used during lowering.Tim Northover1-2/+5
2014-07-13MC: make DWARF and Windows unwinding handling more similarSaleem Abdulrasool1-2/+2
2014-07-11Revert "[FastISel][X86] Implement the FastLowerIntrinsicCall hook."Juergen Ributzka1-38/+42
2014-07-11[FastISel][X86] Implement the FastLowerIntrinsicCall hook.Juergen Ributzka1-42/+38
2014-07-11[X86] Fix the inversion of low and high bits for the lowering of MUL_LOHI.Quentin Colombet1-9/+41
2014-07-11[X86] AVX512: Improve readability of isCDisp8Adam Nemet1-3/+12
2014-07-11[X86] AVX512: Simplify logic in isCDisp8Adam Nemet1-6/+6
2014-07-10[X86] Mark pseudo instruction TEST8ri_NOEREX as hasSIdeEffects=0.Akira Hatanaka2-2/+5
2014-07-10[x32] Add AsmBackend for X32 which uses ELF32 with x86_64 (the author is Pave...Zinovy Nis1-0/+14
2014-07-10[x86] Add another combine that is particularly useful for the new vectorChandler Carruth1-0/+41
2014-07-10[x86] Expand the target DAG combining for PSHUFD nodes to be able toChandler Carruth1-1/+34
2014-07-10[x86] Tweak the v16i8 single input special case lowering for shufflesChandler Carruth1-34/+44
2014-07-10[x86] Initial improvements to the new shuffle lowering for v16i8Chandler Carruth1-10/+36
2014-07-10[x86] Refactor some of the new code for lowering v16i8 shuffles toChandler Carruth1-17/+17
2014-07-09[SDAG] Make the new zext-vector-inreg node default to expand so targetsChandler Carruth1-1/+0
2014-07-09TargetRegisterInfo: Remove function that fell out of use years ago.Benjamin Kramer2-19/+0
2014-07-09[X86] AVX512: Enable it in the Loop VectorizerAdam Nemet1-1/+5
2014-07-09X86: When lowering v8i32 himuls use the correct shuffle masks for AVX2.Benjamin Kramer1-5/+13
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