summaryrefslogtreecommitdiff
path: root/lib/Target/X86/X86Schedule.td
AgeCommit message (Expand)AuthorFilesLines
2014-09-26[X86][SchedModel] SSE reciprocal square root instruction latencies.Andrea Di Biagio1-6/+12
2014-09-09Add a scheduling model for AMD 16H Jaguar (btver2).Sanjay Patel1-0/+2
2014-07-15Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel1-0/+1
2014-02-24[X86][SchedModel] Add missing scheduling model for SSE related instructions.Quentin Colombet1-1/+36
2014-01-24Fix known typosAlp Toker1-1/+1
2013-09-13Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd1-8/+40
2013-06-21Fix IMULX machine model. Multiple def operands require multiple SchedWrites.Andrew Trick1-0/+1
2013-06-15Update machine models. Specify buffer sizes for OOO processors.Andrew Trick1-3/+4
2013-06-15Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick1-5/+0
2013-05-07Corrected Atom latencies for SSE SQRT instructions.Preston Gurd1-4/+8
2013-03-28Add the X86 FMAs to the scheduling model.Nadav Rotem1-0/+4
2013-03-28Add the Haswell machine model.Nadav Rotem1-0/+1
2013-03-26Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen1-0/+1
2013-03-25Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen1-1/+0
2013-03-21Add a WriteMicrocoded for ancient microcoded instructions.Jakob Stoklund Olesen1-0/+3
2013-03-20Add a catch-all WriteSystem SchedWrite type.Jakob Stoklund Olesen1-0/+3
2013-03-19Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen1-0/+4
2013-03-16Define more SchedWrites for annotating X86 instructions.Jakob Stoklund Olesen1-11/+57
2013-03-14Prepare for adding InstrSchedModel annotations to X86 instructions.Jakob Stoklund Olesen1-0/+26
2013-01-09MIsched: add an ILP window property to machine model.Andrew Trick1-0/+5
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick1-9/+7
2012-06-05X86 itinerary properties.Andrew Trick1-1/+23
2012-06-05whitespaceAndrew Trick1-4/+1
2012-05-11Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd1-0/+36
2012-05-10Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd1-0/+64
2012-05-04Adds Intel Atom scheduling latencies to X86InstrSystem.td.Preston Gurd1-0/+53
2012-05-02This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd1-0/+38
2012-03-19This patch adds X86 instruction itineraries for non-pseudo opcodes inPreston Gurd1-0/+11
2012-02-29Intel Atom instruction itineraries for mov sign extension and mov zero extens...Andrew Trick1-0/+11
2012-02-27This patch adds instruction latencies for the SSE instructionsPreston Gurd1-0/+136
2012-02-18Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu1-1/+1
2012-02-01Instruction scheduling itinerary for Intel Atom.Andrew Trick1-0/+115