~nh/llvm - Misc LLVM things, mostly radeonsi (AMDGPU)

Age	Commit message (Expand)	Author	Files	Lines
2014-09-26	[X86][SchedModel] SSE reciprocal square root instruction latencies.	Andrea Di Biagio	1	-0/+1
2014-05-08	Move late partial-unrolling thresholds into the processor definitions	Hal Finkel	1	-0/+3
2014-02-24	[X86][SchedModel] Add missing scheduling model for SSE related instructions.	Quentin Colombet	1	-0/+115
2013-09-25	Mark the x86 machine model as incomplete. PR17367.	Andrew Trick	1	-0/+4
2013-06-21	Fix IMULX machine model. Multiple def operands require multiple SchedWrites.	Andrew Trick	1	-0/+1
2013-06-15	Support BufferSize on ProcResGroup for unified MOp schedulers.	Andrew Trick	1	-0/+5
2013-06-15	Update machine models. Specify buffer sizes for OOO processors.	Andrew Trick	1	-1/+1
2013-06-15	Machine Model: Add MicroOpBufferSize and resource BufferSize.	Andrew Trick	1	-1/+0
2013-04-13	X86 machine model: reduce SandyBridge and Haswell ILPWindow.	Andrew Trick	1	-1/+1
2013-04-02	The divide unit is not pipeline, but it is still buffered.	Andrew Trick	1	-2/+2
2013-03-28	Remove the unused port from the SandyBridge machine model	Nadav Rotem	1	-1/+0
2013-03-25	Add a scheduling model for Intel Sandy Bridge microarchitecture.	Jakob Stoklund Olesen	1	-0/+123