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2015-05-08[mips] Only use FGR_{32,64} in TableGen descriptions. NFC.Toma Tabacu1-30/+20
Summary: Instead of explicitly adding the IsFP64bit and NotFP64bit predicates through AdditionalRequires. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9566 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236835 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-07Rename the MIPS routine abiUsesSoftFloat -> useSoftFloat to matchEric Christopher1-1/+1
some incoming changes and the general scheme used by features (use/has). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-07[mips] Add the SoftFloat MipsSubtarget feature.Toma Tabacu1-22/+27
Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236713 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-21[mips] Cleanup old floating-point flag conditions definitions. NFC.Vasileios Kalintiris1-22/+0
Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D7947 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235377 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-25[MIPS]Multiple and add instructions for Mips are currently available in ↵Vladimir Medic1-14/+14
mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230500 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-04[mips] Move COP2 & COP3 load/store instructions from MipsInstrFPU.td to ↵Vasileios Kalintiris1-56/+0
MipsInstrInfo.td. NFC. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5843 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221300 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-17[mips] Add support for COP1's Branch-On-Cond-Likely instructionsVasileios Kalintiris1-2/+10
Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220042 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-01[mips] Fix disassembly of [ls][wd]c[23], cache, and pref ↵Daniel Sanders1-8/+40
Fixes PR21015, and PR20993. Patch by Jun Koi git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218745 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-17Revert: r215698 - Current implementation of c.cond.fmt instructions only ↵Daniel Sanders1-49/+13
accept default cc0 register... It causes a number of regressions when -fintegrated-as is enabled. This happens because there are codegen-only instructions that incorrectly uses the first operand as the encoding for the $fcc register. The regressions do not occur when -via-file-asm is also given. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215847 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-15Current implementation of c.cond.fmt instructions only accept default cc0 ↵Vladimir Medic1-13/+49
register. This patch enables the instruction to accept other fcc registers. The aliases with default fcc0 registers are also defined. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215698 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14[mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders1-4/+8
FP64 moves Summary: This is similar to r210771 which did the same thing for MTHC1. Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the wrong definitions. Differential Revision: http://reviews.llvm.org/D4483 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212936 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10Make it possible for the Subtarget to change between functionEric Christopher1-4/+4
passes in the mips back end. This, unfortunately, required a bit of churn in the various predicates to use a pointer rather than a reference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212744 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-16[mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates ↵Daniel Sanders1-4/+8
rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211012 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13[mips] Add cache and pref instructionsDaniel Sanders1-4/+8
Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210900 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6Daniel Sanders1-4/+6
Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210787 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6Daniel Sanders1-10/+10
Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210784 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available ↵Daniel Sanders1-6/+7
on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210777 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12[mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders1-2/+15
FP64 Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210771 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12[mips][mips64r6] madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not ↵Daniel Sanders1-12/+12
available on MIPS32r6/MIPS64r6 Summary: This patch updates both the assembler and the code generator. MIPS32r6/MIPS64r6 replaces them with maddf.[ds] and msubf.[ds] which are fused multiply-add/sub operations. We don't emit these yet, this patch only prevents the removed instructions from being emitted. Depends on D3955 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3956 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210763 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-13[mips] Marked up instructions added in MIPS32r2 and tested that IAS for ↵Daniel Sanders1-4/+4
-mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208690 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12[mips] Marked up instructions added in MIPS-V and tested that IAS for ↵Daniel Sanders1-4/+6
-mcpu=mips[1234] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-V that was available in MIPS32R2 Most of these instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. It happens because many of the MIPS V instructions have not been implemented. Depends on D3694 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208546 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12[mips] Replace FeatureFPIdx with FeatureMips4_32r2Daniel Sanders1-9/+11
Summary: No functional change. The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions) Depends on D3677 Reviewers: rkotler, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3690 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208541 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-09[mips] Marked up instructions added in MIPS-III and tested that IAS for ↵Daniel Sanders1-4/+4
-mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208408 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08[mips] Add PredicateControl to InstAlias'sDaniel Sanders1-2/+2
Summary: No functional change Depends on D3649 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3672 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208334 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08[mips] Implement l[wd]c3, and s[wd]c3.Daniel Sanders1-1/+11
Summary: These instructions were added in MIPS-I, and MIPS-II but were removed in MIPS-III. Interestingly, GAS continues to accept them when assembling for MIPS-III. For the moment, these instructions will follow GAS and accept them for MIPS-III and newer but this will be tightened up when the invalid-*.s tests are added. Depends on D3647 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3648 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208311 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-08[mips] Marked up instructions added in MIPS-II and tested that IAS for ↵Daniel Sanders1-16/+19
-mcpu=mips1 does not accept them Summary: A small number of instructions are rejected with the wrong error message. These have been placed in a separate test for now. There seems to be some parsing quirk that triggers when these instructions are disabled. Depends on D3571 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3647 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208305 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of ↵Daniel Sanders1-104/+101
FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208213 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07[mips] Add ISA_<name> adverbs and start using them instead of ↵Daniel Sanders1-22/+19
AdditionalPredicates overrides Summary: One small functional change. The recently added PAUSE instruction now has the HasStdEnc predicate which was accidentally removed by a Requires<>. Depends on D3640 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3641 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208209 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07[mips] Continue splitting Instruction.Predicates into smaller lists and ↵Daniel Sanders1-18/+23
re-join them with !listconcat Summary: Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates No functional change (confirmed by diffing tablegen-erated files). Depends on D3639 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3640 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208201 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07[mips] Move IsFP64bit/NotFP64bit to the front of the AdditionalPredicates listDaniel Sanders1-6/+6
Summary: This makes it easier to prove a more complicated change in the next commit is non-functional. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3639 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208197 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07[mips] Split Instruction.Predicates into smaller lists and re-join them with ↵Daniel Sanders1-37/+37
!listconcat Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208184 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-07[mips] Move HasStdEnc to the front of the predicates lists.Daniel Sanders1-36/+36
Summary: This will make it easier to prove that a more complicated change in the following commit is non-functional. No functional change. Depends on D3506 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3549 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208179 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29[mips] Remove more redundant 'let Predicates = [HasStdEnc]' statementsDaniel Sanders1-10/+6
Summary: The InstSE class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207551 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29[mips] Remove redundant 'let Predicates = [HasStdEnc]' statementsDaniel Sanders1-4/+2
Summary: The MipsPat class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3546 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207548 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of ↵Daniel Sanders1-8/+6
-enable-no-nans-fp-math Summary: They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies). nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008. Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3274 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205844 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07Reverting commit r205628 due to mips64 issues.Reed Kotler1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205741 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04[mips] abs.[ds], and neg.[ds] should be allowed regardless of ↵Daniel Sanders1-1/+1
-enable-no-nans-fp-math Summary: They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies). nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3274 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205628 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05[mips] Add NaCl target and forbid indexed loads and stores for itPetar Jovanovic1-3/+6
This patch adds NaCl target for Mips. It also forbids indexed loads and stores if the target is NaCl. Patch by Sasa Stankovic. Differential Revision: http://llvm-reviews.chandlerc.com/D2690 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200855 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21[mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1Daniel Sanders1-6/+6
No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199748 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21[mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1Daniel Sanders1-8/+8
No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199747 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21[mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1Daniel Sanders1-10/+9
No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21[mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and ↵Daniel Sanders1-3/+3
II_SQRT_D respectively No functional change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199741 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21[mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and ↵Daniel Sanders1-2/+2
II_DIV_D respectively No functional change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199738 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, ↵Daniel Sanders1-9/+9
II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199737 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, ↵Daniel Sanders1-5/+5
II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199734 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS]Daniel Sanders1-4/+4
No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199732 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21[mips][sched] Split IIFcmp into II_C_CC_[SD]Daniel Sanders1-28/+31
No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199728 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD]Daniel Sanders1-5/+5
No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199727 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEGDaniel Sanders1-38/+38
No functional change since the InstrItinData's have been duplicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199722 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25Support for microMIPS FPU instructions 2.Zoran Jovanovic1-20/+21
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198009 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 00:39:12 +0000