| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-05-28 | [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs. | Kai Nacke | 1 | -0/+12 |
| 2015-05-26 | Use std::bitset for SubtargetFeatures. | Michael Kuperstein | 1 | -5/+5 |
| 2015-05-13 | MC: Modernize MCOperand API naming. NFC. | Jim Grosbach | 1 | -146/+146 |
| 2015-05-13 | Reverting r237234, "Use std::bitset for SubtargetFeatures" | Michael Kuperstein | 1 | -5/+5 |
| 2015-05-13 | Use std::bitset for SubtargetFeatures | Michael Kuperstein | 1 | -5/+5 |
| 2015-04-20 | [mips][microMIPSr6] Implement disassembler support | Jozef Kolek | 1 | -4/+11 |
| 2015-03-24 | Revert "Use std::bitset for SubtargetFeatures" | Michael Kuperstein | 1 | -5/+5 |
| 2015-03-24 | Use std::bitset for SubtargetFeatures | Michael Kuperstein | 1 | -5/+5 |
| 2015-02-19 | Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures. | Michael Kuperstein | 1 | -5/+5 |
| 2015-02-19 | Use std::bitset for SubtargetFeatures | Michael Kuperstein | 1 | -5/+5 |
| 2015-02-11 | [mips] Merge disassemblers into a single implementation. | Daniel Sanders | 1 | -84/+18 |
| 2015-02-10 | [mips][microMIPS] Implement movep instruction | Zoran Jovanovic | 1 | -0/+65 |
| 2015-02-10 | [mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 an... | Jozef Kolek | 1 | -7/+23 |
| 2015-01-29 | [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 i... | Vladimir Medic | 1 | -0/+22 |
| 2015-01-28 | [mips][microMIPS] Implement LWGP instruction | Jozef Kolek | 1 | -0/+21 |
| 2015-01-23 | [mips] fix spelling of 'disassembler' | Alexei Starovoitov | 1 | -3/+3 |
| 2015-01-21 | [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B | Jozef Kolek | 1 | -0/+16 |
| 2015-01-21 | [mips][microMIPS] Implement ADDIUPC instruction | Jozef Kolek | 1 | -0/+9 |
| 2015-01-21 | [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 ins... | Vladimir Medic | 1 | -0/+21 |
| 2015-01-20 | Reverted revision 226577. | Jozef Kolek | 1 | -16/+0 |
| 2015-01-20 | [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B | Jozef Kolek | 1 | -0/+16 |
| 2015-01-12 | [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions | Jozef Kolek | 1 | -0/+16 |
| 2014-12-23 | [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions | Jozef Kolek | 1 | -0/+22 |
| 2014-12-23 | [mips][microMIPS] Implement LWSP and SWSP instructions | Jozef Kolek | 1 | -0/+21 |
| 2014-12-23 | Fix UBSan bootstrap: replace shift of negative value with multiplication. | Alexey Samsonov | 1 | -1/+1 |
| 2014-12-16 | The single check for N64 inside MipsDisassemblerBase's subclasses is actually... | Vladimir Medic | 1 | -4/+4 |
| 2014-12-16 | [mips][microMIPS] Implement SWP and LWP instructions | Zoran Jovanovic | 1 | -0/+3 |
| 2014-12-15 | Add disassembler tests for mips3 platform. There are no functional changes. | Vladimir Medic | 1 | -1/+2 |
| 2014-12-01 | The andi16, addiusp and jraddiusp micromips instructions were missing dedicat... | Vladimir Medic | 1 | -0/+39 |
| 2014-11-27 | [mips][microMIPS] Implement SWM16 and LWM16 instructions | Zoran Jovanovic | 1 | -0/+24 |
| 2014-11-27 | [mips] Add synci instruction. | Daniel Sanders | 1 | -0/+20 |
| 2014-11-27 | [mips][microMIPS] Implement disassembler support for 16-bit instructions LI16... | Jozef Kolek | 1 | -0/+60 |
| 2014-11-26 | [mips][microMIPS] Implement disassembler support for 16-bit instructions LBU1... | Jozef Kolek | 1 | -1/+62 |
| 2014-11-24 | [mips][microMIPS] Implement 16-bit instructions registers including ZERO inst... | Jozef Kolek | 1 | -0/+12 |
| 2014-11-24 | [mips][microMIPS] Implement disassembler support for 16-bit instructions | Jozef Kolek | 1 | -11/+54 |
| 2014-11-19 | [mips][micromips] Implement SWM32 and LWM32 instructions | Zoran Jovanovic | 1 | -5/+43 |
| 2014-11-12 | Pass an ArrayRef to MCDisassembler::getInstruction. | Rafael Espindola | 1 | -15/+11 |
| 2014-11-10 | Misc style fixes. NFC. | Rafael Espindola | 1 | -78/+53 |
| 2014-10-21 | [mips][microMIPS] Implement microMIPS 16-bit instructions registers | Zoran Jovanovic | 1 | -0/+12 |
| 2014-10-01 | [mips] Fix disassembly of [ls][wd]c[23], cache, and pref ... | Daniel Sanders | 1 | -0/+66 |
| 2014-09-02 | Fix left shifts of negative values in MipsDisassembler. | Alexey Samsonov | 1 | -15/+15 |
| 2014-07-24 | Prune dependency to MC from each target disassembler. | NAKAMURA Takumi | 1 | -1/+1 |
| 2014-07-24 | Update library dependencies. | NAKAMURA Takumi | 1 | -1/+1 |
| 2014-07-14 | [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and ... | Daniel Sanders | 1 | -17/+0 |
| 2014-06-18 | [mips][mips64r6] Add BLTC and BLTUC instructions | Zoran Jovanovic | 1 | -4/+15 |
| 2014-06-16 | [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. | Daniel Sanders | 1 | -0/+26 |
| 2014-06-13 | [mips] Add cache and pref instructions | Daniel Sanders | 1 | -8/+24 |
| 2014-06-12 | [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available ... | Daniel Sanders | 1 | -0/+30 |
| 2014-06-12 | [mips][mips64r6] Add bgec and bgeuc instructions | Zoran Jovanovic | 1 | -2/+56 |
| 2014-06-09 | [mips][mips64r6] Add LDPC instruction | Zoran Jovanovic | 1 | -0/+9 |
