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2015-12-22REVIEW COMMENTSfold-subregsNicolai Hähnle5-0/+32
2015-12-22REVIEW Axel Davy's schedulerNicolai Hähnle8-3/+2532
2015-12-22EXPERIMENT only fold subreg operands when they aren't used oftenNicolai Hähnle1-3/+12
2015-12-22AMDGPU/SI: Fold operands with sub-registersNicolai Hähnle7-21/+45
Multi-dword constant loads generated unnecessary moves from SGPRs into VGPRs, increasing the code size and VGPR pressure. These moves are now folded away. Note that this lack of operand folding was not a problem for VMEM loads, because COPY nodes from VReg_Nnn to VGPR32 are eliminated by the register coalescer. Some tests are updated, note that the fsub.ll test explicitly checks that the move is elided.
2015-12-22AMDGPU/SI: fix scratch resource register allocation on Tonga & IcelandNicolai Hähnle1-1/+6
Summary: The correct number of available SGPRs needs to be taken into account here. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15724
2015-12-21[AVR] Added configuration file and machine function information classDylan McKay2-0/+88
This commit adds the 'AVRMachineFunctionInfo' class, which simply stores basic properties about generated machine functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256213 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Fix line endings after r256155. NFC.Eric Christopher1-198/+198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256211 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Fix test case comment (NFC)Xinliang David Li1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256206 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[cfi] Fix LowerBitSets on 32-bit targets.Evgeniy Stepanov2-1/+22
This code attempts to truncate IntPtrTy to i32, which may be the same type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256205 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[MC, COFF] Support link /incremental conditionallyDavid Majnemer18-30/+71
Today, we always take into account the possibility that object files produced by MC may be consumed by an incremental linker. This results in us initialing fields which vary with time (TimeDateStamp) which harms hermetic builds (e.g. verifying a self-host went well) and produces sub-optimal code because we cannot assume anything about the relative position of functions within a section (call sites can get redirected through incremental linker thunks). Let's provide an MCTargetOption which controls this behavior so that we can disable this functionality if we know a-priori that the build will not rely on /incremental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256203 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Enhance BranchProbabilityInfo::calcUnreachableHeuristics for InvokeInstJun Bum Lim5-4/+61
This is recommit of r256028 with minor fixes in unittests: CodeGen/Mips/eh.ll CodeGen/Mips/insn-zero-size-bb.ll Original commit message: When identifying blocks post-dominated by an unreachable-terminated block in BranchProbabilityInfo, consider only the edge to the normal destination block if the terminator is InvokeInst and let calcInvokeHeuristics() decide edge weights for the InvokeInst. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256202 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Resubmit r256193 with test fix: assertion failure analyzedXinliang David Li2-2/+18
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256201 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Revert r256193: build bot failure triggeredXinliang David Li2-19/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256198 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[X86][SSE] Transform truncations between vectors of integers into ↵Cong Hou4-163/+353
X86ISD::PACKUS/PACKSS operations during DAG combine. This patch transforms truncation between vectors of integers into X86ISD::PACKUS/PACKSS operations during DAG combine. We don't do it in lowering phase because after type legalization, the original truncation will be turned into a BUILD_VECTOR with each element that is extracted from a vector and then truncated, and from them it is difficult to do this optimization. This greatly improves the performance of truncations on some specific types. Cost table is updated accordingly. Differential revision: http://reviews.llvm.org/D14588 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256194 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[PGO] Fix profile var comdat generation problem with COFFXinliang David Li2-2/+19
When targeting COFF, it is required that a comdat section to have a global obj with the same name as the comdat (except for comdats with select kind to be associative). This fix makes sure that the comdat is keyed on the data variable for COFF. Also improved test coverage for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256193 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[ValueTracking] Properly handle non-sized types in isAligned function.Michael Zolotukhin2-1/+25
Reviewers: apilipenko, reames, sanjoy, hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15597 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256192 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Fix PR24563 (LiveDebugVariables unconditionally propagates all DBG_VALUEs)Adrian Prantl3-54/+138
LiveDebugVariables unconditionally propagates all DBG_VALUE down the dominator tree, which happens to work fine if there already is another DBG_VALUE or the DBG_VALUE happends to describe a single-assignment vreg but is otherwise wrong if the DBG_VALUE is coming from only one of the predecessors. In r255759 we introduced a proper data flow analysis scheduled after LiveDebugVariables that correctly propagates DBG_VALUEs across basic block boundaries. With the new pass in place, the incorrect propagation in LiveDebugVariables can be retired witout loosing any of the benefits where LiveDebugVariables happened to do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256188 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Convert the CodeGen/ARM/sched-it-debug-nodes.ll testcase from IR -> MIR.Adrian Prantl2-88/+160
NFC PR24563 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256187 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Teach ARMLoadStoreOptimizer to ignore DBG_VALUE instructions when mergingAdrian Prantl2-1/+170
instructions. As noted in PR24563. rdar://problem/23963293 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256183 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21fix leak in a test, make the sanitizer bot greenKostya Serebryany1-1/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256179 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VITom Stellard6-21/+84
Summary: These register has different encodings on CI and VI, so we add pseudo FLAT_SCRACTH registers to be used before MC, and subtarget specific registers to be used by the MC layer. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15661 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256178 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21AMDGPU/SI: Change assembly name for flat scratch registers to flat_scratchTom Stellard1-3/+3
This matches what the assembler accepts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256177 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[AArch64] Add additional extract-extend patterns for smovMatthew Simpson2-9/+15
This patch adds to the target description two additional patterns for matching extract-extend operations to SMOV. The patterns catch the v16i8-to-i64 and v8i16-to-i64 cases. The existing patterns miss these cases because the extracted elements must first be legalized to i32, resulting in any_extend nodes. This was originally implemented as a DAG combine (r255895), but was reverted due to failing out-of-tree tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256176 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Add testcase for r256161 (PR25907)Teresa Johnson1-0/+28
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256174 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Remove extra whitespace. NFC.Chad Rosier1-3/+3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256173 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[ThinLTO] Rename variable to reflect bulk importing change (NFC)Teresa Johnson1-10/+11
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256171 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[WebAssembly] Convert a regular for loop to a range-based for loop.Dan Gohman1-2/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256169 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[WebAssembly] Clean up comments and fix a missing #include dependency.Dan Gohman1-13/+7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256168 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[WebAssembly] Remove an unneeded empty destructor.Dan Gohman1-4/+0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256167 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[WebAssembly] Enclose the operand variables for load and store instructions ↵Dan Gohman1-23/+23
in braces. This allows the AsmMatcherEmitter to properly tokenize the AsmStrings for load and store instructions. This is a step towards asm parsing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256166 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[WebAssembly] Mark the ARGUMENT pseudo-instructions as CodeGenOnly.Dan Gohman1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256165 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[WebAssembly] Add some comments and make some minor source cleanups.Dan Gohman1-3/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256164 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Teach MCOperand::print how to print FPImm operands.Dan Gohman1-0/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256163 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Remove unused functions from ModuleLinker (NFC)Teresa Johnson1-54/+0
Remove a couple ModuleLinker methods and a related static function that are no longer used after the linker split. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256162 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Remove overly strict new assert in BitcodeReader.Teresa Johnson1-16/+1
This fixes a bug introduced by the ThinLTO metadata linking patch r255909. The assert is overly-strict and while useful in development of the patch, doesn't seem interesting to keep. Fixes PR25907. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256161 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Revert "[AArch64] Promote loads from stores"Jun Bum Lim4-951/+8
This reverts commit r256004 due to a failure in cortex-a53. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256160 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[LIR] Refactor code to enable future patch. NFC.Chad Rosier1-41/+41
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256159 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[AArch64] Enable PostRAScheduler for AArch64 generic build.Chad Rosier22-30/+31
Disable post-ra scheduler for perturbed tests to appease the bots and to preserve the history of the tests. http://reviews.llvm.org/D15652 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256158 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21AVX512BW: Enable AND/OR/XOR vector byte/word paked operation by promoting to ↵Igor Breger2-29/+144
qword that natively suppored. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256157 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[llvm-objdump] Use appropriate helper. NFC.Davide Italiano1-2/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256156 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21Implemented Support of IA interrupt and exception handlers:Amjad Aboud16-198/+485
http://lists.llvm.org/pipermail/cfe-dev/2015-September/045171.html Differential Revision: http://reviews.llvm.org/D15567 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256155 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[mips][microMIPS] Implement DERET and DI instructions and check size operand ↵Zlatko Buljan19-69/+126
for EXT and DEXT* instructions Differential Revision: http://reviews.llvm.org/D15570 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256152 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21check-llvm: Tweak the feature "timestamps" for autoconf.NAKAMURA Takumi2-1/+2
Note, ENABLE_TIMESTAMPS is either 1 or 0 in Makefile.config. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256138 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[MC, COFF] Unbreak support for COFF timestampsDavid Majnemer4-1/+9
Support for COFF timestamps was unintentionally broken in r246905 when it was conditionally available depending on whether or not LLVM was configured with LLVM_ENABLE_TIMESTAMPS. However, Config/config.h was never included which essentially broke the feature. Due to lax testing, the breakage was never identified until we observed strange failures during incremental links of Chromium. This issue is resolved by simply including Config/config.h in WinCOFFObjectWriter and teaching lit that the MC/COFF/timestamp.s test is conditionally supported depending on LLVM_ENABLE_TIMESTAMPS. With this in place, we can strengthen the test to ensure that it will not accidentally get broken in the future. This fixes PR25891. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256137 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[Cygwin] Enable TLS as emutls.NAKAMURA Takumi2-0/+14
It resolves clang selfhosting with std::once() for Cygwin. FIXME: It may be EmulatedTLS-generic also for X86-Android. FIXME: Pass EmulatedTLS to LLVM CodeGen from Clang with -femulated-tls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256134 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[RS4GC] Add an assert which fails if there is a (yet unsupported) addrspacecast.Manuel Jacob1-0/+5
The slightly strange indentation comes from clang-format. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256132 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-21[InstCombine] Fix indentation. NFC.Craig Topper1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256131 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-20[AVR] Added AVRCallingConv.tdDylan McKay3-1/+67
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256130 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-20[X86] Use range-based for loop. NFCCraig Topper1-3/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256127 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-20[X86] Prevent constant hoisting for a couple compare immediates that the ↵Craig Topper2-1/+38
selection DAG knows how to optimize into a shift. This allows "icmp ugt %a, 4294967295" and "icmp uge %a, 4294967296" to be optimized into right shifts by 32 which can fold the immediate into the shift instruction. These patterns show up with some regularity in real code. Unfortunately, since getImmCost can't see the icmp predicate we can't be tell if we're only catching these specific cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256126 91177308-0d34-0410-b5e6-96231b3b80d8
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