diff options
Diffstat (limited to 'lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp')
| -rw-r--r-- | lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 1c5a7951876..f525e4ab435 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -93,7 +93,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, O << "\tsev"; break; case 5: - if ((STI.getFeatureBits() & ARM::HasV8Ops)) { + if (STI.getFeatureBits()[ARM::HasV8Ops]) { O << "\tsevl"; break; } // Fallthrough for non-v8 @@ -302,7 +302,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, case ARM::t2SUBS_PC_LR: { if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() && MI->getOperand(0).getImm() == 0 && - (STI.getFeatureBits() & ARM::FeatureVirtualization)) { + STI.getFeatureBits()[ARM::FeatureVirtualization]) { O << "\teret"; printPredicateOperand(MI, 1, STI, O); printAnnotation(O, Annot); @@ -695,7 +695,7 @@ void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned val = MI->getOperand(OpNum).getImm(); - O << ARM_MB::MemBOptToString(val, (STI.getFeatureBits() & ARM::HasV8Ops)); + O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]); } void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum, @@ -795,14 +795,14 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCOperand &Op = MI->getOperand(OpNum); unsigned SpecRegRBit = Op.getImm() >> 4; unsigned Mask = Op.getImm() & 0xf; - uint64_t FeatureBits = STI.getFeatureBits(); + const FeatureBitset &FeatureBits = STI.getFeatureBits(); - if (FeatureBits & ARM::FeatureMClass) { + if (FeatureBits[ARM::FeatureMClass]) { unsigned SYSm = Op.getImm(); unsigned Opcode = MI->getOpcode(); // For writes, handle extended mask bits if the DSP extension is present. - if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) { + if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) { switch (SYSm) { case 0x400: O << "apsr_g"; @@ -834,7 +834,7 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, // Handle the basic 8-bit mask. SYSm &= 0xff; - if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) { + if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an // alias for MSR APSR_nzcvq. switch (SYSm) { |