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Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassembler.cpp78
1 files changed, 43 insertions, 35 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 4c169a8ef55..f0de58ab9b8 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -435,7 +435,7 @@ DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
raw_ostream &CS) const {
CommentStream = &CS;
- assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
+ assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
"Asked to disassemble an ARM instruction but Subtarget is in Thumb "
"mode!");
@@ -700,7 +700,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
raw_ostream &CS) const {
CommentStream = &CS;
- assert((STI.getFeatureBits() & ARM::ModeThumb) &&
+ assert(STI.getFeatureBits()[ARM::ModeThumb] &&
"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
// We want to read exactly 2 bytes of data.
@@ -1026,9 +1026,10 @@ static const uint16_t DPRDecoderTable[] = {
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder) {
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- bool hasD16 = featureBits & ARM::FeatureD16;
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ bool hasD16 = featureBits[ARM::FeatureD16];
if (RegNo > 31 || (hasD16 && RegNo > 15))
return MCDisassembler::Fail;
@@ -1373,9 +1374,9 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
break;
}
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+ if (featureBits[ARM::HasV8Ops] && (coproc != 14))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(coproc));
@@ -2151,9 +2152,10 @@ static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
unsigned Imm = fieldFromInstruction(Insn, 9, 1);
const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
- uint64_t FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
- if ((FeatureBits & ARM::HasV8_1aOps) == 0 ||
- (FeatureBits & ARM::HasV8Ops) == 0 )
+ const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
+
+ if (!FeatureBits[ARM::HasV8_1aOps] ||
+ !FeatureBits[ARM::HasV8Ops])
return MCDisassembler::Fail;
// Decoder can be called from DecodeTST, which does not check the full
@@ -3319,10 +3321,11 @@ static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
unsigned Rt = fieldFromInstruction(Insn, 12, 4);
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- bool hasMP = featureBits & ARM::FeatureMP;
- bool hasV7Ops = featureBits & ARM::HasV7Ops;
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ bool hasMP = featureBits[ARM::FeatureMP];
+ bool hasV7Ops = featureBits[ARM::HasV7Ops];
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3405,10 +3408,11 @@ static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
imm |= (Rn << 9);
unsigned add = fieldFromInstruction(Insn, 9, 1);
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- bool hasMP = featureBits & ARM::FeatureMP;
- bool hasV7Ops = featureBits & ARM::HasV7Ops;
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ bool hasMP = featureBits[ARM::FeatureMP];
+ bool hasV7Ops = featureBits[ARM::HasV7Ops];
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3485,10 +3489,11 @@ static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
unsigned imm = fieldFromInstruction(Insn, 0, 12);
imm |= (Rn << 13);
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- bool hasMP = (featureBits & ARM::FeatureMP);
- bool hasV7Ops = (featureBits & ARM::HasV7Ops);
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ bool hasMP = featureBits[ARM::FeatureMP];
+ bool hasV7Ops = featureBits[ARM::HasV7Ops];
if (Rn == 15) {
switch (Inst.getOpcode()) {
@@ -3602,9 +3607,10 @@ static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
unsigned U = fieldFromInstruction(Insn, 23, 1);
int imm = fieldFromInstruction(Insn, 0, 12);
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- bool hasV7Ops = (featureBits & ARM::HasV7Ops);
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ bool hasV7Ops = featureBits[ARM::HasV7Ops];
if (Rt == 15) {
switch (Inst.getOpcode()) {
@@ -3925,9 +3931,10 @@ static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
if (Val == 0xA || Val == 0xB)
return MCDisassembler::Fail;
- uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
+ const FeatureBitset &featureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
@@ -4077,9 +4084,10 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
- uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
- .getFeatureBits();
- if (FeatureBits & ARM::FeatureMClass) {
+ const FeatureBitset &FeatureBits =
+ ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+ if (FeatureBits[ARM::FeatureMClass]) {
unsigned ValLow = Val & 0xff;
// Validate the SYSm value first.
@@ -4099,7 +4107,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
case 17: // basepri
case 18: // basepri_max
case 19: // faultmask
- if (!(FeatureBits & ARM::HasV7Ops))
+ if (!(FeatureBits[ARM::HasV7Ops]))
// Values basepri, basepri_max and faultmask are only valid for v7m.
return MCDisassembler::Fail;
break;
@@ -4109,7 +4117,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
if (Inst.getOpcode() == ARM::t2MSR_M) {
unsigned Mask = fieldFromInstruction(Val, 10, 2);
- if (!(FeatureBits & ARM::HasV7Ops)) {
+ if (!(FeatureBits[ARM::HasV7Ops])) {
// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
// unpredictable.
if (Mask != 2)
@@ -4123,7 +4131,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
// only if the processor includes the DSP extension.
if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
- (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
+ (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
S = MCDisassembler::SoftFail;
}
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 15:59:01 +0000