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authorMatt Arsenault <Matthew.Arsenault@amd.com>2015-12-19 01:39:48 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2015-12-19 01:39:48 +0000
commit4b9d868cc774eba681a93a61f056105b7dfd9c8f (patch)
treef86bc3f9a1e9591f5800a3f804d114de77e658a1 /lib
parent0589c22ae9ea6c0fa93f666d2f35d6669a82384b (diff)
Fix broken type legalization of min/max
This was using an anyext when promoting the type when zext/sext is required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256074 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp21
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeTypes.h1
2 files changed, 20 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 63c9cc52871..3131ca10145 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -76,9 +76,10 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
case ISD::SMIN:
- case ISD::SMAX:
+ case ISD::SMAX: Res = PromoteIntRes_SExtOrZExtIntBinOp(N, true); break;
case ISD::UMIN:
- case ISD::UMAX: Res = PromoteIntRes_SimpleIntBinOp(N); break;
+ case ISD::UMAX: Res = PromoteIntRes_SExtOrZExtIntBinOp(N, false); break;
+
case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
case ISD::SIGN_EXTEND_INREG:
Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
@@ -660,6 +661,22 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
LHS.getValueType(), LHS, RHS);
}
+SDValue DAGTypeLegalizer::PromoteIntRes_SExtOrZExtIntBinOp(SDNode *N,
+ bool Signed) {
+ SDValue LHS, RHS;
+
+ if (Signed) {
+ LHS = SExtPromotedInteger(N->getOperand(0));
+ RHS = SExtPromotedInteger(N->getOperand(1));
+ } else {
+ LHS = ZExtPromotedInteger(N->getOperand(0));
+ RHS = ZExtPromotedInteger(N->getOperand(1));
+ }
+
+ return DAG.getNode(N->getOpcode(), SDLoc(N),
+ LHS.getValueType(), LHS, RHS);
+}
+
SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 267a1145a0a..e121e3bc6fa 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -276,6 +276,7 @@ private:
SDValue PromoteIntRes_SETCC(SDNode *N);
SDValue PromoteIntRes_SHL(SDNode *N);
SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N);
+ SDValue PromoteIntRes_SExtOrZExtIntBinOp(SDNode *N, bool Signed);
SDValue PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
SDValue PromoteIntRes_SRA(SDNode *N);
SDValue PromoteIntRes_SRL(SDNode *N);