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authorQuentin Colombet <qcolombet@apple.com>2014-08-07 00:20:44 +0000
committerQuentin Colombet <qcolombet@apple.com>2014-08-07 00:20:44 +0000
commit15c8452584f38d29a73e98d7b123e408617e55c9 (patch)
tree5ee4004b49a6729ab3be459cf64ab797a076e7d7 /lib/Target/X86/X86InstrMMX.td
parent75d423feed899baff90adab26b77195fb19128cc (diff)
[X86][SchedModel] Fixed missing/wrong scheduling model found by code inspection.
Source: Agner Fog's Instruction tables. Related to <rdar://problem/15607571> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215045 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrMMX.td')
-rw-r--r--lib/Target/X86/X86InstrMMX.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td
index abc244b34a2..9001fbaa894 100644
--- a/lib/Target/X86/X86InstrMMX.td
+++ b/lib/Target/X86/X86InstrMMX.td
@@ -199,11 +199,11 @@ multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
(ins DstRC:$src1, SrcRC:$src2), asm,
[(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
- NoItinerary, d>;
+ NoItinerary, d>, Sched<[WriteCvtI2F]>;
def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
(ins DstRC:$src1, x86memop:$src2), asm,
[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
- NoItinerary, d>;
+ NoItinerary, d>, Sched<[WriteCvtI2FLd]>;
}
//===----------------------------------------------------------------------===//