diff options
Diffstat (limited to 'arch/powerpc/boot/dts')
-rw-r--r-- | arch/powerpc/boot/dts/mpc8377_mds.dts | 35 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/mpc8377_rdb.dts | 8 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/mpc8378_rdb.dts | 8 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/mpc8379_rdb.dts | 8 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/mpc8548cds.dts | 4 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/mpc8610_hpcd.dts | 93 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/sbc8548.dts | 94 | ||||
-rw-r--r-- | arch/powerpc/boot/dts/sequoia.dts | 9 |
8 files changed, 225 insertions, 34 deletions
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts index eac8e1b59496..fea592574004 100644 --- a/arch/powerpc/boot/dts/mpc8377_mds.dts +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts @@ -268,6 +268,41 @@ interrupt-parent = <&ipic>; }; + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8377-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <0x47 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <0x47 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <0x47 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <0x47 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <0x47 8>; + }; + }; + /* IPIC * interrupts cell = <intr #, sense> * sense values match linux IORESOURCE_IRQ_* defines: diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts index 5bc09ad016f5..f3083c779b66 100644 --- a/arch/powerpc/boot/dts/mpc8377_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts @@ -164,12 +164,6 @@ reg = <0x2>; device_type = "ethernet-phy"; }; - phy3: ethernet-phy@3 { - interrupt-parent = <&ipic>; - interrupts = <18 0x8>; - reg = <0x3>; - device_type = "ethernet-phy"; - }; }; enet0: ethernet@24000 { @@ -195,7 +189,7 @@ interrupts = <35 0x8 36 0x8 37 0x8>; phy-connection-type = "mii"; interrupt-parent = <&ipic>; - phy-handle = <&phy3>; + fixed-link = <1 1 1000 0 0>; }; serial0: serial@4500 { diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts index 711f9a30f9ab..0e872a60e091 100644 --- a/arch/powerpc/boot/dts/mpc8378_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts @@ -164,12 +164,6 @@ reg = <0x2>; device_type = "ethernet-phy"; }; - phy3: ethernet-phy@3 { - interrupt-parent = <&ipic>; - interrupts = <18 0x8>; - reg = <0x3>; - device_type = "ethernet-phy"; - }; }; enet0: ethernet@24000 { @@ -195,7 +189,7 @@ interrupts = <35 0x8 36 0x8 37 0x8>; phy-connection-type = "mii"; interrupt-parent = <&ipic>; - phy-handle = <&phy3>; + fixed-link = <1 1 1000 0 0>; }; serial0: serial@4500 { diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts index c11ceb7d3299..1eb8defaff6f 100644 --- a/arch/powerpc/boot/dts/mpc8379_rdb.dts +++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts @@ -164,12 +164,6 @@ reg = <0x2>; device_type = "ethernet-phy"; }; - phy3: ethernet-phy@3 { - interrupt-parent = <&ipic>; - interrupts = <18 0x8>; - reg = <0x3>; - device_type = "ethernet-phy"; - }; }; enet0: ethernet@24000 { @@ -195,7 +189,7 @@ interrupts = <35 0x8 36 0x8 37 0x8>; phy-connection-type = "mii"; interrupt-parent = <&ipic>; - phy-handle = <&phy3>; + fixed-link = <1 1 1000 0 0>; }; serial0: serial@4500 { diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts index fa298a8c81cc..4811b8107415 100644 --- a/arch/powerpc/boot/dts/mpc8548cds.dts +++ b/arch/powerpc/boot/dts/mpc8548cds.dts @@ -409,7 +409,7 @@ interrupts = <26 2>; bus-range = <0 255>; ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 - 0x1000000 0x0 0x0 0xe3000000 0x0 0x8000000>; + 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; clock-frequency = <33333333>; #interrupt-cells = <1>; #size-cells = <2>; @@ -428,7 +428,7 @@ 0x1000000 0x0 0x0 0x1000000 0x0 0x0 - 0x0 0x8000000>; + 0x0 0x100000>; }; }; }; diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts index 1f2f1e0a5571..fa9b6bbeb5af 100644 --- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts @@ -21,6 +21,7 @@ serial1 = &serial1; pci0 = &pci0; pci1 = &pci1; + pci2 = &pci2; }; cpus { @@ -45,9 +46,63 @@ reg = <0x00000000 0x20000000>; // 512M at 0x0 }; - board-control@e8000000 { - compatible = "fsl,fpga-pixis"; - reg = <0xe8000000 32>; // pixis at 0xe8000000 + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus"; + reg = <0xe0005000 0x1000>; + interrupts = <19 2>; + interrupt-parent = <&mpic>; + ranges = <0 0 0xf8000000 0x08000000 + 1 0 0xf0000000 0x08000000 + 2 0 0xe8400000 0x00008000 + 4 0 0xe8440000 0x00008000 + 5 0 0xe8480000 0x00008000 + 6 0 0xe84c0000 0x00008000 + 3 0 0xe8000000 0x00000020>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + flash@1,0 { + compatible = "cfi-flash"; + reg = <1 0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + flash@2,0 { + compatible = "fsl,mpc8610-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <2 0 0x8000>; + }; + + flash@4,0 { + compatible = "fsl,mpc8610-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <4 0 0x8000>; + }; + + flash@5,0 { + compatible = "fsl,mpc8610-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <5 0 0x8000>; + }; + + flash@6,0 { + compatible = "fsl,mpc8610-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <6 0 0x8000>; + }; + + board-control@3,0 { + compatible = "fsl,fpga-pixis"; + reg = <3 0 0x20>; + }; }; soc@e0000000 { @@ -105,7 +160,7 @@ compatible = "ns16550"; reg = <0x4600 0x100>; clock-frequency = <0>; - interrupts = <28 2>; + interrupts = <42 2>; interrupt-parent = <&mpic>; }; @@ -196,14 +251,14 @@ dma@c300 { #address-cells = <1>; #size-cells = <1>; - compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma"; + compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma"; cell-index = <1>; reg = <0xc300 0x4>; /* DMA general status register */ ranges = <0x0 0xc100 0x200>; dma-channel@0 { compatible = "fsl,mpc8610-dma-channel", - "fsl,mpc8540-dma-channel"; + "fsl,eloplus-dma-channel"; cell-index = <0>; reg = <0x0 0x80>; interrupt-parent = <&mpic>; @@ -211,7 +266,7 @@ }; dma-channel@1 { compatible = "fsl,mpc8610-dma-channel", - "fsl,mpc8540-dma-channel"; + "fsl,eloplus-dma-channel"; cell-index = <1>; reg = <0x80 0x80>; interrupt-parent = <&mpic>; @@ -219,7 +274,7 @@ }; dma-channel@2 { compatible = "fsl,mpc8610-dma-channel", - "fsl,mpc8540-dma-channel"; + "fsl,eloplus-dma-channel"; cell-index = <2>; reg = <0x100 0x80>; interrupt-parent = <&mpic>; @@ -227,7 +282,7 @@ }; dma-channel@3 { compatible = "fsl,mpc8610-dma-channel", - "fsl,mpc8540-dma-channel"; + "fsl,eloplus-dma-channel"; cell-index = <3>; reg = <0x180 0x80>; interrupt-parent = <&mpic>; @@ -322,4 +377,24 @@ }; }; }; + + pci2: pcie@e0009000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8641-pcie"; + reg = <0xe0009000 0x00001000>; + ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 + 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0000 0 0 1 &mpic 4 1 + 0x0000 0 0 2 &mpic 5 1 + 0x0000 0 0 3 &mpic 6 1 + 0x0000 0 0 4 &mpic 7 1>; + interrupt-parent = <&mpic>; + interrupts = <25 2>; + clock-frequency = <33333333>; + }; }; diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index b86e65d926c1..22d967178fe9 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts @@ -52,6 +52,99 @@ reg = <0x00000000 0x10000000>; }; + localbus@e0000000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "simple-bus"; + reg = <0xe0000000 0x5000>; + interrupt-parent = <&mpic>; + + ranges = <0x0 0x0 0xff800000 0x00800000 /*8MB Flash*/ + 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/ + 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/ + 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */ + 0x6 0x0 0xfb800000 0x04000000>; /*64MB Flash*/ + + + flash@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x800000>; + bank-width = <1>; + device-width = <1>; + partition@0x0 { + label = "space"; + reg = <0x00000000 0x00100000>; + }; + partition@0x100000 { + label = "bootloader"; + reg = <0x00100000 0x00700000>; + read-only; + }; + }; + + epld@5,0 { + compatible = "wrs,epld-localbus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x5 0x0 0x00b10000>; + ranges = < + 0x0 0x0 0x5 0x000000 0x1fff /* LED */ + 0x1 0x0 0x5 0x100000 0x1fff /* Switches */ + 0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */ + 0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */ + >; + + led@0,0 { + compatible = "led"; + reg = <0x0 0x0 0x1fff>; + }; + + switches@1,0 { + compatible = "switches"; + reg = <0x1 0x0 0x1fff>; + }; + + hw-rev@3,0 { + compatible = "hw-rev"; + reg = <0x3 0x0 0x1fff>; + }; + + eeprom@b,0 { + compatible = "eeprom"; + reg = <0xb 0 0x1fff>; + }; + + }; + + alt-flash@6,0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x6 0x0 0x04000000>; + compatible = "cfi-flash"; + bank-width = <4>; + device-width = <1>; + partition@0x0 { + label = "bootloader"; + reg = <0x00000000 0x00100000>; + read-only; + }; + partition@0x00100000 { + label = "file-system"; + reg = <0x00100000 0x01f00000>; + }; + partition@0x02000000 { + label = "boot-config"; + reg = <0x02000000 0x00100000>; + }; + partition@0x02100000 { + label = "space"; + reg = <0x02100000 0x01f00000>; + }; + }; + }; + soc8548@e0000000 { #address-cells = <1>; #size-cells = <1>; @@ -59,6 +152,7 @@ ranges = <0x00000000 0xe0000000 0x00100000>; reg = <0xe0000000 0x00001000>; // CCSRBAR bus-frequency = <0>; + compatible = "simple-bus"; memory-controller@2000 { compatible = "fsl,8548-memory-controller"; diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts index a1ae4d6ec990..72d67564bdfc 100644 --- a/arch/powerpc/boot/dts/sequoia.dts +++ b/arch/powerpc/boot/dts/sequoia.dts @@ -342,9 +342,14 @@ /* Outbound ranges, one memory and one IO, * later cannot be changed. Chip supports a second * IO range but we don't use it for now + * From the 440EPx user manual: + * PCI 1 Memory 1 8000 0000 1 BFFF FFFF 1GB + * I/O 1 E800 0000 1 E800 FFFF 64KB + * I/O 1 E880 0000 1 EBFF FFFF 56MB */ - ranges = <02000000 0 80000000 1 80000000 0 10000000 - 01000000 0 00000000 1 e8000000 0 00100000>; + ranges = <02000000 0 80000000 1 80000000 0 40000000 + 01000000 0 00000000 1 e8000000 0 00010000 + 01000000 0 00000000 1 e8800000 0 03800000>; /* Inbound 2GB range starting at 0 */ dma-ranges = <42000000 0 0 0 0 0 80000000>; |