diff options
| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2018-09-11 11:21:31 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2018-10-29 17:09:08 +0100 |
| commit | 4649471a9e5fef200ea69673bcc0e2b0e4c561c1 (patch) | |
| tree | 972ee9943e3e329b86316b87322b2019aebcbfa6 /src | |
| parent | 8e428e24a833175c108e4151676a85a31bd99efd (diff) | |
radv: adjust the GSVS ring sizes based on the number of components
For multiple streams support we have to set the different ring
buffer sizes correctly. This relies on the number of output
components per stream.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 90356a49f94..e1d50163444 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2988,20 +2988,33 @@ radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *cs, const struct radv_gs_state *gs_state) { struct radv_shader_variant *gs; + unsigned gs_max_out_vertices; + uint8_t *num_components; + uint8_t max_stream; + unsigned offset; uint64_t va; gs = pipeline->shaders[MESA_SHADER_GEOMETRY]; if (!gs) return; - uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2; + gs_max_out_vertices = gs->info.gs.vertices_out; + max_stream = gs->info.info.gs.max_stream; + num_components = gs->info.info.gs.num_stream_output_components; - radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3); - radeon_emit(cs, gsvs_itemsize); - radeon_emit(cs, gsvs_itemsize); - radeon_emit(cs, gsvs_itemsize); + offset = num_components[0] * gs_max_out_vertices; - radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize); + radeon_set_context_reg_seq(cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3); + radeon_emit(cs, offset); + if (max_stream >= 1) + offset += num_components[1] * gs_max_out_vertices; + radeon_emit(cs, offset); + if (max_stream >= 2) + offset += num_components[2] * gs_max_out_vertices; + radeon_emit(cs, offset); + if (max_stream >= 3) + offset += num_components[3] * gs_max_out_vertices; + radeon_set_context_reg(cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset); radeon_set_context_reg(cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out); |