diff options
author | Nanley Chery <nanley.g.chery@intel.com> | 2018-05-24 17:27:19 -0700 |
---|---|---|
committer | Nanley Chery <nanley.g.chery@intel.com> | 2018-07-13 08:44:09 -0700 |
commit | c47e66719c06abf4fd1fb72274a927fd17891efe (patch) | |
tree | 11d49e8308cb76574fbf5b575dfed87fe3d35c05 | |
parent | 508136c4ab5fa41b2b70b078e2dfc18ed3caa368 (diff) |
i965/miptree: Allow blit maps with BLORP on gen4-5
The BLORP fallback can handle Y-tiling and large row pitches.
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 19 |
1 files changed, 2 insertions, 17 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index aafb2ecde03..1a6e62acca4 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -3528,17 +3528,6 @@ intel_miptree_release_map(struct intel_mipmap_tree *mt, } static bool -can_blit_slice(struct intel_mipmap_tree *mt, - unsigned int level, unsigned int slice) -{ - /* See intel_miptree_blit() for details on the 32k pitch limit. */ - if (intel_miptree_blt_pitch(mt) >= 32768) - return false; - - return true; -} - -static bool use_intel_mipree_map_blit(struct brw_context *brw, struct intel_mipmap_tree *mt, GLbitfield mode, @@ -3553,17 +3542,13 @@ use_intel_mipree_map_blit(struct brw_context *brw, */ !(mode & GL_MAP_WRITE_BIT) && !mt->compressed && - (mt->surf.tiling == ISL_TILING_X || - /* Prior to Sandybridge, the blitter can't handle Y tiling */ - (devinfo->gen >= 6 && mt->surf.tiling == ISL_TILING_Y0) || + (mt->surf.tiling != ISL_TILING_LINEAR || /* Fast copy blit on skl+ supports all tiling formats. */ - devinfo->gen >= 9) && - can_blit_slice(mt, level, slice)) + devinfo->gen >= 9)) return true; if (mt->surf.tiling != ISL_TILING_LINEAR && mt->bo->size >= brw->max_gtt_map_object_size) { - assert(can_blit_slice(mt, level, slice)); return true; } |