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authorNanley Chery <nanley.g.chery@intel.com>2018-06-11 10:35:28 -0700
committerNanley Chery <nanley.g.chery@intel.com>2018-07-13 08:31:21 -0700
commit32b22592a883b527c7207818e209300542b15edc (patch)
tree57dbd03d0ff1250bcb5863b72100e02d7a737f9b
parent2321e85759b5737ffeaebeef0c92c8baf4be612c (diff)
i965/miptree: Share alloc_flags in miptree_create
Note that this maintains BO_ALLOC_BUSY for depth renderbuffers, but not depth textures. v2: Add note about BO_ALLOC_BUSY in message (Topi). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 6ccfbe6ab23..5ec95d2cb5d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -686,6 +686,8 @@ miptree_create(struct brw_context *brw,
enum intel_miptree_create_flags flags)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
+ const uint32_t alloc_flags = (flags & MIPTREE_CREATE_BUSY) ?
+ BO_ALLOC_BUSY : 0;
isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
/* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
@@ -709,7 +711,7 @@ miptree_create(struct brw_context *brw,
tiling_flags,
ISL_SURF_USAGE_STENCIL_BIT |
ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_BUSY,
+ alloc_flags,
0,
NULL);
@@ -721,7 +723,7 @@ miptree_create(struct brw_context *brw,
first_level, last_level,
width0, height0, depth0, num_samples, tiling_flags,
ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
- BO_ALLOC_BUSY, 0, NULL);
+ alloc_flags, 0, NULL);
if (needs_separate_stencil(brw, mt, format) &&
!make_separate_stencil_surface(brw, mt)) {
@@ -735,11 +737,6 @@ miptree_create(struct brw_context *brw,
return mt;
}
- uint32_t alloc_flags = 0;
-
- if (flags & MIPTREE_CREATE_BUSY)
- alloc_flags |= BO_ALLOC_BUSY;
-
struct intel_mipmap_tree *mt = make_surface(
brw, target, mt_fmt,
first_level, last_level,