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| author | Nanley Chery <nanley.g.chery@intel.com> | 2018-07-19 16:31:55 -0700 |
|---|---|---|
| committer | Nanley Chery <nanley.g.chery@intel.com> | 2018-07-19 16:40:25 -0700 |
| commit | 3a0a581705988d1093d0ddb851af1b3178b432d2 (patch) | |
| tree | 8d7be1c6641b751bead327d873d021a44ab16396 | |
| parent | 409a60df3ba2cd0e05623dcb895034edcbe1342d (diff) | |
i965: Change default color tilingwip/fix/same-tiling
The PRMs say that the depth and color buffers should have the same
tile walk. This is usualy true for gen > 6, and false for gen < 6.
Flip this around and see what happens.
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index a18d5ac3624..c237682b827 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -683,8 +683,8 @@ miptree_create(struct brw_context *brw, (flags & MIPTREE_CREATE_BUSY || num_samples > 1) ? BO_ALLOC_BUSY : 0; isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK; - /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */ - if (devinfo->gen < 6 && _mesa_is_format_color_format(format)) + if (devinfo->gen > 6 && _mesa_is_format_color_format(format) && + !_mesa_is_astc_format(format)) tiling_flags &= ~ISL_TILING_Y0_BIT; mesa_format mt_fmt; |