/* * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef _ASM_ARC_ARCREGS_H #define _ASM_ARC_ARCREGS_H /* Build Configuration Registers */ #define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */ #define ARC_REG_CRC_BCR 0x62 #define ARC_REG_VECBASE_BCR 0x68 #define ARC_REG_PERIBASE_BCR 0x69 #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */ #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */ #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */ #define ARC_REG_SLC_BCR 0xce #define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */ #define ARC_REG_TIMERS_BCR 0x75 #define ARC_REG_AP_BCR 0x76 #define ARC_REG_ICCM_BCR 0x78 #define ARC_REG_XY_MEM_BCR 0x79 #define ARC_REG_MAC_BCR 0x7a #define ARC_REG_MUL_BCR 0x7b #define ARC_REG_SWAP_BCR 0x7c #define ARC_REG_NORM_BCR 0x7d #define ARC_REG_MIXMAX_BCR 0x7e #define ARC_REG_BARREL_BCR 0x7f #define ARC_REG_D_UNCACH_BCR 0x6A #define ARC_REG_BPU_BCR 0xc0 #define ARC_REG_ISA_CFG_BCR 0xc1 #define ARC_REG_RTT_BCR 0xF2 #define ARC_REG_IRQ_BCR 0xF3 #define ARC_REG_SMART_BCR 0xFF /* status32 Bits Positions */ #define STATUS_AE_BIT 5 /* Exception active */ #define STATUS_DE_BIT 6 /* PC is in delay slot */ #define STATUS_U_BIT 7 /* User/Kernel mode */ #define STATUS_L_BIT 12 /* Loop inhibit */ /* These masks correspond to the status word(STATUS_32) bits */ #define STATUS_AE_MASK (1<> 10) #define TO_MB(bytes) (TO_KB(bytes) >> 10) #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) /* *************************************************************** * Build Configuration Registers, with encoded hardware config */ struct bcr_identity { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int chip_id:16, cpu_id:8, family:8; #else unsigned int family:8, cpu_id:8, chip_id:16; #endif }; struct bcr_isa { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1, pad1:11, atomic1:1, ver:8; #else unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1, ldd:1, pad2:4, div_rem:4; #endif }; struct bcr_mpy { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; #else unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8; #endif }; struct bcr_extn_xymem { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8; #else unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2; #endif }; struct bcr_perip { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int start:8, pad2:8, sz:8, pad:8; #else unsigned int pad:8, sz:8, pad2:8, start:8; #endif }; struct bcr_iccm { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int base:16, pad:5, sz:3, ver:8; #else unsigned int ver:8, sz:3, pad:5, base:16; #endif }; /* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */ struct bcr_dccm_base { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int addr:24, ver:8; #else unsigned int ver:8, addr:24; #endif }; /* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */ struct bcr_dccm { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int res:21, sz:3, ver:8; #else unsigned int ver:8, sz:3, res:21; #endif }; /* ARCompact: Both SP and DP FPU BCRs have same format */ struct bcr_fp_arcompact { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int fast:1, ver:8; #else unsigned int ver:8, fast:1; #endif }; struct bcr_fp_arcv2 { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8; #else unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15; #endif }; struct bcr_timer { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; #else unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; #endif }; struct bcr_bpu_arcompact { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8; #else unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19; #endif }; struct bcr_bpu_arcv2 { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8; #else unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6; #endif }; struct bcr_generic { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad:24, ver:8; #else unsigned int ver:8, pad:24; #endif }; /* ******************************************************************* * Generic structures to hold build configuration used at runtime */ struct cpuinfo_arc_mmu { unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, u_dtlb:6, u_itlb:6; unsigned int num_tlb:16, sets:12, ways:4; }; struct cpuinfo_arc_cache { unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1; }; struct cpuinfo_arc_bpu { unsigned int ver, full, num_cache, num_pred; }; struct cpuinfo_arc_ccm { unsigned int base_addr, sz; }; struct cpuinfo_arc { struct cpuinfo_arc_cache icache, dcache, slc; struct cpuinfo_arc_mmu mmu; struct cpuinfo_arc_bpu bpu; struct bcr_identity core; struct bcr_isa isa; struct bcr_timer timers; unsigned int vec_base; struct cpuinfo_arc_ccm iccm, dccm; struct { unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3, fpu_sp:1, fpu_dp:1, pad2:6, debug:1, ap:1, smart:1, rtt:1, pad3:4, pad4:8; } extn; struct bcr_mpy extn_mpy; struct bcr_extn_xymem extn_xymem; }; extern struct cpuinfo_arc cpuinfo_arc700[]; static inline int is_isa_arcv2(void) { return IS_ENABLED(CONFIG_ISA_ARCV2); } static inline int is_isa_arcompact(void) { return IS_ENABLED(CONFIG_ISA_ARCOMPACT); } #if defined(CONFIG_ISA_ARCOMPACT) && !defined(_CPU_DEFAULT_A7) #error "Toolchain not configured for ARCompact builds" #elif defined(CONFIG_ISA_ARCV2) && !defined(_CPU_DEFAULT_HS) #error "Toolchain not configured for ARCv2 builds" #endif #endif /* __ASEMBLY__ */ #endif /* _ASM_ARC_ARCREGS_H */