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path: root/drivers/clk/imx
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2017-06-19clk: imx7d: create clocks behind rawnand clock gateStefan Agner1-2/+4
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-06clk: imx7d: Fix the DDR PLL enable bitFabio Estevam1-1/+1
Commit ad14972422899b6 ("clk: imx7d: Fix the powerdown bit location of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case. Fix it accordingly to avoid a kernel hang. Reported-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-01clk: imx7d: Fix the powerdown bit location of PLL DDRFabio Estevam3-1/+7
According to the MX7D Reference Manual the powerdown bit of CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: imx7d: fix USDHC NAND clockStefan Agner1-2/+1
The USDHC NAND root clock is not gated by any CCM clock gate. Remove the bogus gate definition. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: imx7d: add the missing ipg_root_clkDong Aisheng1-1/+2
Add the missing ipg_root_clk which actually is already used by many orphan clks in current tree. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Tested-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: clk-imx7d: fix ahb clk definitionDong Aisheng1-3/+2
MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200 used actually is for adc, not ahb. After fix, correct ocram_s_clk parent accordingly as well. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Tested-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-12clk: imx: correct uart4_serial clock name in driver for i.MX6ULRobin van der Gracht1-1/+1
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2017-04-12clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clockRobin van der Gracht1-4/+5
The clock was mapped on CG15 (gpio2_clocks) in the CCRG0 register. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2017-01-26Merge branch 'clk-imx7', 'clk-bcm2835' into clk-nextStephen Boyd1-0/+1
* clk-imx7: clk: imx7d: Add the OCOTP clock * clk-bcm2835: clk: bcm2835: Add leaf clock measurement support, disabled by default clk: bcm2835: Register the DSI0/DSI1 pixel clocks. clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.
2017-01-20clk: imx7d: Add the OCOTP clockFabio Estevam1-0/+1
Add the OCOTP so that this hardware block can be used. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: imx6: don't restrict LDB mux changes on QuadPlusLucas Stach1-8/+13
The LDB mux/gate layout has been fixed on QuadPlus, so there is no need to restrict the LDB mux changes on this hardware, as the erratum preventing this from working properly is gone. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2Nikita Yushchenko3-2/+102
On vf610, PLL1 and PLL2 have registers to configure fractional part of frequency multiplier. This patch adds support for these registers. This fixes "fast system clock" issue on boards where bootloader sets fractional multiplier for PLL1. Suggested-by: Andrey Smirnov <andrew.smirnov@gmail.com> CC: Chris Healy <cphealy@gmail.com> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-15Merge tag 'armsoc-fixes-nc' of ↵Linus Torvalds1-26/+26
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC non-urgent fixes from Arnd Bergmann: "As usual, we queue up a few fixes that don't seem urgent enough to go in through -rc, or that just came a little too late given their size. The zx fixes make the platform finally boot on real hardware, the davinci and imx31 get the DT support working better for some of the machines that are still normally used with classic board files. One tegra fix is important for new bootloader versions, but the bug has been around for a while without anyone noticing. The other changes are mostly cosmetic" * tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits) arm64: tegra: Add missing Smaug revision arm64: tegra: Add VDD_GPU regulator to Jetson TX1 arm64: dts: zte: clean up gic-v3 redistributor properties arm64: dts: zx: Fix gic GICR property bus: vexpress-config: fix device reference leak soc: ti: qmss: fix the case when !SMP ARM: lpc32xx: drop duplicate header device.h ARM: ixp4xx: drop duplicate header gpio.h ARM: socfpga: fix spelling mistake in error message ARM: dts: imx6q-cm-fx6: fix fec pinctrl ARM: dts: imx7d-pinfunc: fix UART pinmux defines ARM: dts: imx6qp: correct LDB clock inputs ARM: OMAP2+: pm-debug: Use seq_putc() in two functions ARM: OMAP2+: Remove the omapdss_early_init_of() function mfd: tps65217: Fix mismatched interrupt number ARM: zx: Fix error handling ARM: spear: Fix error handling ARM: davinci: da850: Fix pwm name matching ARM: clk: imx31: properly init clocks for machines with DT clk: imx31: fix rewritten input argument of mx31_clocks_init() ...
2016-11-16Merge tag 'imx-clk-4.10' of ↵Stephen Boyd3-21/+342
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull i.MX clock updates from Shawn Guo: - A patch series to fix the long standing issue with glitchy parent mux of ldb_di_clk, which can hang up LVDS display when ipu_di_clk is sourced from ldb_di_clk. - A patch to add imx6ull clock support on top of imx6ul clock driver. * tag 'imx-clk-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx: clk-imx6ul: add clk support for imx6ull clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podf
2016-11-15clk: imx: clk-imx6ul: add clk support for imx6ullBai Ping1-11/+61
imx6ull is the derived SoC from imx6ul Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-11-01clk: imx: improve precision of AV PLL to 1 HzEmil Lundmark1-0/+8
The audio and video PLLs are designed to have a precision of 1 Hz if some conditions are met. The current implementation only allows a precision that depends on the rate of the parent clock. E.g., if the parent clock is 24 MHz, the precision will be 24 Hz; or more generally the precision will be p / 10^6 Hz where p is the parent clock rate. This comes down to how the register values for the PLL's fractional loop divider are chosen. The clock rate calculation for the PLL is PLL output frequency = Fref * (DIV_SELECT + NUM / DENOM) or with a shorter notation r = p * (d + a / b) In addition to all variables being integers, we also have the following conditions: 27 <= d <= 54 -2^29 <= a <= 2^29-1 0 < b <= 2^30-1 |a| < b Here, d, a and b are register values for the fractional loop divider. We want to chose d, a and b such that f(p, r) = p, i.e. f is our round_rate function. Currently, d and b are chosen as d = r / p b = 10^6 hence we get the poor precision. And a is defined in terms of r, d, p and b: a = (r - d * p) * b / p I propose that if p <= 2^30-1 (i.e., the max value for b), we chose b as b = p We can do this since |a| < b |(r - d * p) * b / p| < b |r - d * p| < p Which have two solutions, one of them is when p < 0, so we can skip that one. The other is when p > 0 and p * (d - 1) < r < p * (d + 1) Substitute d = r / p: (r - p) < r < (r + p) <=> p > 0 So, as long as p > 0, we can chose b = p. This is a good choise for b since a = (r - d * p) * b / p = (r - d * p) * p / p = r - d * p r = p * (d + a / b) = p * d + p * a / b = p * d + p * a / p = p * d + a and if d = r / p: a = r - d * p = r - r / p * p = 0 r = p * d + a = p * d + 0 = p * r / p = r I reckon this is the intention by the design of the clock rate formula. Signed-off-by: Emil Lundmark <emil@limesaudio.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: imx: fix integer overflow in AV PLL round rateEmil Lundmark1-2/+6
Since 'parent_rate * mfn' may overflow 32 bits, the result should be stored using 64 bits. The problem was discovered when trying to set the rate of the audio PLL (pll4_post_div) on an i.MX6Q. The desired rate was 196.608 MHz, but the actual rate returned was 192.000570 MHz. The round rate function should have been able to return 196.608 MHz, i.e., the desired rate. Fixes: ba7f4f557eb6 ("clk: imx: correct AV PLL rate formula") Cc: Anson Huang <b20788@freescale.com> Signed-off-by: Emil Lundmark <emil@limesaudio.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: imx6: Fix procedure to switch the parent of LDB_DI_CLKFabio Estevam1-5/+259
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. This patch ensures that correct steps are followed when ldb_di_clk parent is switched in the beginning of boot. The glitchy muxes are then registered as read-only. The clock parent can be selected using the assigned-clocks and assigned-clock-parents properties of the ccm device tree node: &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>, <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; }; The issue is explained in detail in EB821 ("LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines") [1]. [1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com> Tested-by Joshua Clayton <stillcompiling@gmail.com> Tested-by: Charles Kang <Charles.Kang@advantech.com.tw> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-11-01clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-onlyPhilipp Zabel2-8/+10
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. As this can not be guaranteed by the clock framework during runtime, make the ldb_di[x]_sel muxes read-only. A workaround to set the muxes once during boot could be added to the kernel or bootloader. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-11-01clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podfPhilipp Zabel1-0/+15
MMDC CH1 is not used on i.MX6Q, so the handshake needed to change the parent of periph2_sel or the divider of mmdc_ch1_axi_podf will never succeed. Disable the handshake mechanism to allow changing the frequency of mmdc_ch1_axi, allowing to use it as a possible source for the LDB DI clock. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-11-01ARM: clk: imx31: properly init clocks for machines with DTVladimir Zapolskiy1-24/+26
Clock initialization for i.MX31 powered machines with DT support should be done by a call of an init function registered with CLK_OF_DECLARE() in common clock framework. The change converts exported mx31_clocks_init_dt() into a static initialization function registered by CLK_OF_DECLARE(). Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-11-01clk: imx31: fix rewritten input argument of mx31_clocks_init()Vladimir Zapolskiy1-3/+1
Function mx31_clocks_init() is called during clock intialization on legacy boards with reference clock frequency passed as its input argument, this can be verified by examination of the function declaration found in arch/arm/mach-imx/common.h and actual function users which include that header file. Inside CCF driver the function ignores its input argument, by chance the used value in the function body is the same as input arguments on side of all callers. Fixes: d9388c843237 ("clk: imx31: Do not call mxc_timer_init twice when booting with DT") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-10-07Merge tag 'armsoc-cleanup' of ↵Linus Torvalds1-41/+5
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Arnd Bergmann: "The cleanups for v4.9 are a little larger that usual, but thankfully that is almost exclusively due to removing a significant number of files that have become obsolete after the still ongoing conversion of old board files to devicetree. - for mach-omap2, which is still the largest platform in arch/arm/, the conversion to DT is finally complete after the Nokia N900 is now fully supported there, along with the omap3 LDP, and we can remove those two board files. If no regressions are found, another large cleanup for the platform will happen as a follow-up, removing dead code and restructuring the platform based on being DT-only. - In mach-imx, similar work is ongoing, but has not come that far. This time, we remove the obsolete board file for the i.MX1 generation, which like i.MX25, i.MX5, i.MX6, and i.MX7 is now DT-only. The remaining board files are for i.MX2 and i.MX3 machines based on old ARM926 or ARM1136 cores that should work with DT in principle. - realview has just been converted from board files to DT, and a lot of code gets removed in the process. This is the last ARM/Keil/Versatile derived platform that was still using board files, the other ones being integrator, versatile and vexpress. We can probably merge the remaining code into a single directory in the near future. - clps711x had completed the conversion in v4.8, but we accidentally left the files in place that should have been deleted then" * tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (21 commits) ARM: select PCI_DOMAINS config from ARCH_MULTIPLATFORM ARM: stop *MIGHT_HAVE_PCI* config from being selected redundantly ARM: imx: (trivial) fix typo and grammar ARM: clps711x: remove extraneous files ARM: imx: use IS_ENABLED() instead of checking for built-in or module ARM: OMAP2+: use IS_ENABLED() instead of checking for built-in or module ARM: OMAP1: use IS_ENABLED() instead of checking for built-in or module ARM: imx: remove platform-mxc_rnga ARM: realview: imply device tree boot ARM: realview: no need to select SMP_ON_UP explicitly ARM: realview: delete the RealView board files ARM: imx: no need to select SMP_ON_UP explicitly ARM: i.MX: Move SOC_IMX1 into 'Device tree only' ARM: i.MX: Remove i.MX1 non-DT support ARM: i.MX: Remove i.MX1 Synertronixx SCB9328 board support ARM: i.MX: Remove i.MX1 Armadeus APF9328 board support ARM: mxs: remove obsolete startup code for TX28 ARM: i.MX31 iomux: remove duplicates with alternate name ARM: i.MX31 iomux: remove plain duplicates ARM: OMAP2+: Drop legacy board file for LDP ...
2016-09-20clk: imx6: initialize GPU clocksLucas Stach1-0/+18
Initialize the GPU clock muxes to sane inputs. Until now they have not been changed from their default values, which means that both GPU3D shader and GPU2D core were fed by clock inputs whose rates exceed the maximium allowed frequency of the cores by as much as 200MHz. This fixes a severe GPU stability issue on i.MX6DL. Cc: stable@vger.kernel.org Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-20clk: imx6: fix i.MX6DL clock tree to reflect realityLucas Stach1-12/+16
The current clock tree only implements the minimal set of differences between the i.MX6Q and the i.MX6DL, but that doesn't really reflect reality. Apply the following fixes to match the RM: - DL has no GPU3D_SHADER_SEL/PODF, the shader domain is clocked by GPU3D_CORE - GPU3D_SHADER_SEL/PODF has been repurposed as GPU2D_CORE_SEL/PODF - GPU2D_CORE_SEL/PODF has been repurposed as MLB_SEL/PODF Cc: stable@vger.kernel.org Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-20clk: imx53: Add clocks configurationKalle Kankare1-0/+20
Add clocks configuration for CSI, FIRI and IEEE1588. Signed-off-by: Fabien Lahoudere <fabien.lahoudere@collabora.co.uk> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14ARM: clk-imx35: annotate clk enum with number valuesUwe Kleine-König1-14/+16
This helps to decode error messages like: [ 0.000000] i.MX clk 82: register failed with -17 Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14ARM: clk-imx35: fix name for ckil clkUwe Kleine-König1-1/+1
This fixes [ 0.000000] i.MX clk 82: register failed with -17 because the name is duplicated. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Fixes: 3713e3f5e927 ("clk: imx35: define two clocks for rtc") Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-30clk: imx7d: Add PLL_AUDIO_TEST_DIV/POST_DIV clocksFabio Estevam1-40/+61
Currently we see the following error when using the SAI audio driver on mx7: Division by zero in kernel. CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0-rc3-next-20160823 Hardware name: Freescale i.MX7 Dual (Device Tree) Backtrace: [<c010b70c>] (dump_backtrace) from [<c010b8a8>] (show_stack+0x18) r6:60000013 r5:ffffffff r4:00000000 r3:00000000 [<c010b890>] (show_stack) from [<c03e9324>] (dump_stack+0xb0/0xe) [<c03e9274>] (dump_stack) from [<c010b578>] (__div0+0x18/0x20) r8:00000000 r7:ffffffff r6:ffffffff r5:00000000 r4:00000000 r3:0 [<c010b560>] (__div0) from [<c03e795c>] (Ldiv0_64+0x8/0x18) [<c06cd860>] (divider_get_val) from [<c06cda28>] (clk_divider_se) This error happens due to the lack of definition of the IMX7D_PLL_AUDIO_TEST_DIV/IMX7D_PLL_AUDIO_POST_DIV clocks. Add support for them. Tested on a imx7s-warp board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19clk: imx7d: Add SAI IPG clocksFabio Estevam1-3/+10
The SAI_IPG clocks are enabled by the same bits that control SAI_ROOT_CLK clocks, so represent them as shared clocks. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19clk: imx: Introduce clk_register_gate2()Fabio Estevam1-0/+9
Introduce imx_clk_gate2_shared2() which is similar to the existing imx_clk_gate2_shared() and passes CLK_OPS_PARENT_ENABLE flag, which is useful for i.MX7 shared clocks. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19clk: imx7d: Add the clock for SDMAFabio Estevam1-0/+1
Add IMX7D_SDMA_CORE_CLK clock so that SDMA can be functional. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-11clk: imx7d: do not set the parent of IMX7D_ENET_AXI_ROOT_SRCFabio Estevam1-2/+0
Booting the kernel on a imx7s-warp leads to several warnings like these: [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:3536 lock_release+0x2f8/0x330 [ 0.000000] releasing a pinned lock [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:2722 trace_hardirqs_on_caller+0x1ac/0x1f4 [ 0.000000] DEBUG_LOCKS_WARN_ON(unlikely(early_boot_irqs_disabled)) [ 0.000000] ---[ end trace cb88537fdc8fa201 ]--- [ 0.000000] bad: scheduling from the idle thread! [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 4.7.0-rc7-next-20160715 #404 [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8 [ 0.000000] Modules linked in: [ 0.000591] ------------[ cut here ]------------ [ 0.000610] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8 [ 0.002084] ------------[ cut here ]------------ [ 0.002104] WARNING: CPU: 0 PID: 0 at init/main.c:576 start_kernel+0x258/0x3b0 [ 0.002114] Interrupts were enabled early This fix is along the same lines as 5e33ebff7edd ("clk: imx7d: do not set parent of ethernet time/ref clocks") and the explanation from that commit is: "The reason for the warning is that setting the parent enables the ENET PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can cause clk_pllv3_wait_lock to sleep. See also: commit fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")." imx7s-warp does not even use the FEC interface, so we should not really configure the parent of IMX7D_ENET_AXI_ROOT_SRC in the common MX7 clock driver code. The dts file should use the assigned-clocks/assigned-clock-parents method, so simply remove the configuration of IMX7D_ENET_AXI_ROOT_SRC parent. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-09ARM: i.MX: Remove i.MX1 non-DT supportAlexander Shiyan1-41/+5
This patch removes registration helpers and support files, used for non-DT i.MX1 targets. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-07-12clk: imx7d: do not set parent of ethernet time/ref clocksStefan Agner1-9/+0
All device trees currently in mainline specify the time clock parent using the assigned-clocks/assigned-clock-parents method, there is no need to statically assign the parent in the core clock driver. Also all current boards provide an Ethernet reference clock for the PHY externally, hence configuring the internal PHY reference clock. Furthermore, and the actual driver of this patch, specify ethernet related parents at that early point in boot leads to a warning: bad: scheduling from the idle thread! The reason for the warning is that setting the parent enables the ENET PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can cause clk_pllv3_wait_lock to sleep. See also: commit fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)"). Note that setting the ENET AXI root clock parent also requires ENET PLL to be enabled. However, U-Boot typically leaves the ENET PLL on, hence when the framework sets the parent of the first clock, it does not need to wait for the PLL to come up. But because there is currently no user of that clock, the PLL gets disabled after setting the parent. Therefore, subsequent reparenting calls of any clock which somehow rely on the ENET PLL, need to reenable the ENET PLL which leads to a sleep. Removing those subsequent reparenting calls works around this issue. Also remove comments. The code is really verbose enough. Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160703174813.13970-1-stefan@agner.ch
2016-07-08clk: imx: vf610: Disable automatic clock gating for lpuart in LPSTOP modeStefan Agner1-6/+6
In order to allow wake support in STOP sleep mode, clocks are needed. Use imx_clk_gate2_cgr to disable automatic clock gating in low power mode STOP. This allows to enable wake by UART using: echo enabled > /sys/class/tty/ttyLP0/power/wakeup However, if wake is not enabled, the driver should disable the clocks explicitly to save power. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160628053235.5114-3-bhuvanchandra.dv@toradex.com
2016-07-01clk: imx7d: only enable minimum required clocksDong Aisheng1-8/+10
Formerly clk core does not support imx7d clock type well that all its clock operations requires the parent clock on. Therefore we enabled all clocks by default in clock driver initialization for other module clocks operate well. After patch 'clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE', clk core can handle such clock type well, so we don't have to enable them all by default anymore. Instead, we only enable a minimum required set of clocks. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-01clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLEDong Aisheng1-357/+357
i.MX7D requires all clocks operations including enable/disable, rate change and re-parent with its parent clock on. Changing to the correct APIs to tell clk core such requirement. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-01clk: imx: add clk api for supporting CLK_OPS_PARENT_ENABLE clocksDong Aisheng1-0/+32
IMX SoCs like i.MX7D requires using CLK_OPS_PARENT_ENABLE flags, adding the corresponding clock APIs variants for easily to use. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-01clk: imx: re-order and concentrate the same type of clk apiDong Aisheng1-29/+29
Re-order and concentrate the same type of clk api for better code maintenance. Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-16clk: imx6ul: fix gpt2 clock namesDong Aisheng1-2/+2
fix gpt2 clock names Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-16clk: imx: refine the powerdown bit of clk-pllv3Dong Aisheng1-10/+10
The powerdown bit is a bit confused, let's change it to power_bit to relfect both powerdown and powerup case according to different plls. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-13clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bitDong Aisheng1-4/+4
After commit f53947456f98 ("ARM: clk: imx: update pllv3 to support imx7"), the former used BM_PLL_POWER bit is not correct anymore for IMX7 ENET. Instead, pll->powerdown holds the correct bit, so using powerdown bit in clk_pllv3_{prepare | unprepare} functions. Fixes: f53947456f98 ("ARM: clk: imx: update pllv3 to support imx7") Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12clk: imx: fix pll clock parentsDong Aisheng5-34/+34
pllx_bypass_src mux shouldn't be the parent of pllx clock since it's only valid when when pllx BYPASS bit is set. Thus it is actually one parent of pllx_bypass only. Instead, pllx parent should be fixed to osc according to reference manual. Other plls have the same issue. e.g. before fix, the pll tree is: osc 6 6 24000000 0 0 pll1_bypass_src 0 0 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 After the fix, it's: osc 6 6 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12clk: imx7d: correct dram pll typeAnson Huang1-1/+1
DRAM PLL is a audio/video type PLL, need to correct it to get correct ops of PLL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12clk: imx7d: correct dram root clk parent selectAnson Huang1-1/+1
DRAM root clk should be either from pll dram main clk or dram alt root clk. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12clk: imx: correct AV PLL rate formulaAnson Huang1-2/+6
The audio/video PLL's rate calculation is as below in RM: Fref * (DIV_SELECT + NUM / DENOM), in origin clk-pllv3's code, below code is used: (parent_rate * div) + ((parent_rate / mfd) * mfn as it does NOT consider the float data using div, so below formula should be used as a decent method: (parent_rate * div) + ((parent_rate * mfn) / mfd) and we also need to consider parent_rate * mfd may overflow a 32 bit value, 64 bit value should be used. After updating this formula, the dram PLL's rate is 1066MHz, which is correct, while the old formula gets 1056MHz. [Aisheng: fix clk_pllv3_av_round_rate too] Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-05-12Merge tag 'imx-clk-fixes-4.6-2' of ↵Stephen Boyd2-3/+3
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull some non-critical i.MX clk fixes from Shawn Guo: * Fix the commit 3713e3f5e927 ("clk: imx35: define two clocks for rtc") which messed up the clock enumeration when adding new clock. * tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx35: restore existing used clock enumeration clk: imx6q: fix typo in CAN clock definition
2016-05-03clk: imx7d: fix ahb clock mux 1Stefan Agner1-1/+1
The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-27clk: imx: return correct frequency for Ethernet PLLStefan Agner1-1/+8
The i.MX 7 designs Ethernet PLL provides a 1000MHz reference clock. Store the reference clock in the clk_pllv3 structure according to the PLL type. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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