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authorKaleb Keithley <kaleb@freedesktop.org>2003-11-14 15:54:54 +0000
committerKaleb Keithley <kaleb@freedesktop.org>2003-11-14 15:54:54 +0000
commitded6147bfb5d75ff1e67c858040a628b61bc17d1 (patch)
tree82355105e93cdac89ef7d987424351c77545faf0 /hw/xfree86/utils
parentcb6ef07bf01e72d1a6e6e83ceb7f76d6534da941 (diff)
R6.6 is the Xorg base-lineXORG-MAIN
Diffstat (limited to 'hw/xfree86/utils')
-rw-r--r--hw/xfree86/utils/kbd_mode/bsd-kbd_mode.c96
-rw-r--r--hw/xfree86/utils/kbd_mode/bsd-kbd_mode.man.pre36
-rw-r--r--hw/xfree86/utils/kbd_mode/sun-kbd_mode.c150
-rw-r--r--hw/xfree86/utils/kbd_mode/sun-kbd_mode.man.pre50
-rw-r--r--hw/xfree86/utils/scanpci/scanpci.c1790
-rw-r--r--hw/xfree86/utils/xorgconfig/Cards2003
-rw-r--r--hw/xfree86/utils/xorgconfig/cards.c285
-rw-r--r--hw/xfree86/utils/xorgconfig/cards.h36
8 files changed, 4446 insertions, 0 deletions
diff --git a/hw/xfree86/utils/kbd_mode/bsd-kbd_mode.c b/hw/xfree86/utils/kbd_mode/bsd-kbd_mode.c
new file mode 100644
index 000000000..37c23cfea
--- /dev/null
+++ b/hw/xfree86/utils/kbd_mode/bsd-kbd_mode.c
@@ -0,0 +1,96 @@
+/* $XFree86: xc/programs/Xserver/hw/xfree86/etc/kbd_mode.c,v 3.5 1996/12/23 06:47:13 dawes Exp $ */
+
+
+/* Keyboard mode control program for 386BSD */
+
+
+/* $Xorg: kbd_mode.c,v 1.3 2000/08/17 19:51:09 cpqbld Exp $ */
+
+#include <sys/types.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <ctype.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "X.h"
+#include "input.h"
+#include "scrnintstr.h"
+
+#include "xf86.h"
+#include "xf86_OSlib.h"
+
+static int fd;
+
+void
+msg (char* s)
+{
+ perror (s);
+ close (fd);
+ exit (-1);
+}
+
+int
+main(int argc, char** argv)
+{
+#if defined(SYSCONS_SUPPORT) || defined(PCVT_SUPPORT)
+ vtmode_t vtmode;
+#endif
+ Bool syscons = FALSE;
+
+ if ((fd = open("/dev/vga",O_RDONLY,0)) <0)
+ msg ("Cannot open /dev/vga");
+
+#if defined(SYSCONS_SUPPORT) || defined(PCVT_SUPPORT)
+ /* Check if syscons */
+ if (ioctl(fd, VT_GETMODE, &vtmode) >= 0)
+ syscons = TRUE;
+#endif
+
+ if (0 == strcmp (argv[1], "-u"))
+ {
+ if (syscons)
+ {
+#if defined(SYSCONS_SUPPORT) || defined(PCVT_SUPPORT)
+ ioctl (fd, KDSKBMODE, K_RAW);
+#endif
+ }
+ else
+ {
+ if (ioctl (fd, CONSOLE_X_MODE_ON, 0) < 0)
+ {
+ close (fd);
+ exit (0); /* Assume codrv, so nothing to do */
+ }
+ }
+ }
+ else if (0 == strcmp (argv[1], "-a"))
+ {
+ if (syscons)
+ {
+#if defined(SYSCONS_SUPPORT) || defined(PCVT_SUPPORT)
+ ioctl (fd, KDSKBMODE, K_XLATE);
+#endif
+ }
+ else
+ {
+ if (ioctl (fd, CONSOLE_X_MODE_OFF, 0) < 0)
+ {
+ close (fd);
+ exit (0); /* Assume codrv, so nothing to do */
+ }
+ }
+ }
+ else
+ {
+ close (fd);
+ fprintf (stderr,"Usage: %s [-u|-a]\n",argv[0]);
+ fprintf (stderr,"-u for sending up down key events in x mode.\n");
+ fprintf (stderr,"-a for sending ascii keys in normal use.\n");
+ exit (-1);
+ }
+ close (fd);
+ exit (0);
+}
diff --git a/hw/xfree86/utils/kbd_mode/bsd-kbd_mode.man.pre b/hw/xfree86/utils/kbd_mode/bsd-kbd_mode.man.pre
new file mode 100644
index 000000000..c959d2332
--- /dev/null
+++ b/hw/xfree86/utils/kbd_mode/bsd-kbd_mode.man.pre
@@ -0,0 +1,36 @@
+.\" $XFree86: xc/programs/Xserver/hw/xfree86/etc/kbd_mode.man,v 3.2 1996/12/23 06:47:14 dawes Exp $
+.TH KBD_MODE 1 "Release 6.3 (XFree86 3.2)" "X Version 11"
+.SH NAME
+kbd_mode \- recover the PC console keyboard
+.SH SYNOPSIS
+.B kbd_mode
+[ -a -u ]
+.SH DESCRIPTION
+.I Kbd_mode
+resets the PC console keyboard to a rational state.
+.SH OPTIONS
+The following options are supported:
+.TP 8
+.B \-a
+Set the keyboard so that ASCII characters are read from the console.
+.TP 8
+.B \-u
+Set the keyboard so that undecoded keyboard values are read from the
+console.
+.SH EXAMPLES
+If the server crashes or otherwise fails to put the keyboard back in
+ascii mode when it exits, it can leave your keyboard dead. If you are
+able to login remotely, you can reset it typing:
+.sp
+ kbd_mode -a
+.sp
+.PP
+Conversely, changing the keyboard to ascii mode while the server is
+running will make the keyboard appear to be dead while the the mouse
+continues to work. Again, if you are able to login remotely, you can
+reset it typing:
+.sp
+ kbd_mode -u
+.sp
+
+.\" $Xorg: kbd_mode.man,v 1.3 2000/08/17 19:51:10 cpqbld Exp $
diff --git a/hw/xfree86/utils/kbd_mode/sun-kbd_mode.c b/hw/xfree86/utils/kbd_mode/sun-kbd_mode.c
new file mode 100644
index 000000000..294787354
--- /dev/null
+++ b/hw/xfree86/utils/kbd_mode/sun-kbd_mode.c
@@ -0,0 +1,150 @@
+/* $Xorg: kbd_mode.c,v 1.3 2000/08/17 19:48:29 cpqbld Exp $ */
+/************************************************************
+Copyright 1987 by Sun Microsystems, Inc. Mountain View, CA.
+
+ All Rights Reserved
+
+Permission to use, copy, modify, and distribute this
+software and its documentation for any purpose and without
+fee is hereby granted, provided that the above copyright no-
+tice appear in all copies and that both that copyright no-
+tice and this permission notice appear in supporting docu-
+mentation, and that the names of Sun or The Open Group
+not be used in advertising or publicity pertaining to
+distribution of the software without specific prior
+written permission. Sun and The Open Group make no
+representations about the suitability of this software for
+any purpose. It is provided "as is" without any express or
+implied warranty.
+
+SUN DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT-
+NESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL SUN BE LI-
+ABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR
+ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH
+THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+********************************************************/
+
+#ifndef lint
+static char sccsid[] = "@(#)kbd_mode.c 7.1 87/04/13";
+#endif
+
+/*
+ * Copyright 1986 by Sun Microsystems, Inc.
+ *
+ * kbd_mode: set keyboard encoding mode
+ */
+
+#include <sys/types.h>
+#include <sys/file.h>
+#include <sys/ioctl.h>
+#if defined(SVR4) || defined(__bsdi_)
+#include <fcntl.h>
+#ifndef __bsdi__
+#include <sys/kbio.h>
+#include <sys/kbd.h>
+#else
+#include <unistd.h>
+#include </sys/sparc/dev/kbio.h>
+#include </sys/sparc/dev/kbd.h>
+#endif
+#else
+#ifndef CSRG_BASED
+#include <sundev/kbio.h>
+#include <sundev/kbd.h>
+#else
+#include <machine/kbio.h>
+#include <machine/kbd.h>
+#endif
+#endif
+#include <stdio.h>
+
+static void die(), usage();
+static int kbd_fd;
+
+main(argc, argv)
+ int argc;
+ char** argv;
+{
+ int code, translate, direct = -1;
+ char led;
+ int click;
+
+ if ((kbd_fd = open("/dev/kbd", O_RDONLY, 0)) < 0) {
+ die("Couldn't open /dev/kbd");
+ }
+ argc--; argv++;
+ if (argc-- && **argv == '-') {
+ code = *(++*argv);
+ } else {
+ usage();
+ }
+ switch (code) {
+ case 'a':
+ case 'A':
+ translate = TR_ASCII;
+ direct = 0;
+ break;
+ case 'e':
+ case 'E':
+ translate = TR_EVENT;
+ break;
+ case 'n':
+ case 'N':
+ translate = TR_NONE;
+ break;
+ case 'u':
+ case 'U':
+ translate = TR_UNTRANS_EVENT;
+ break;
+ default:
+ usage();
+ }
+#ifdef KIOCSLED
+ led = 0;
+ if (ioctl(kbd_fd, KIOCSLED, &led))
+ die("Couldn't set LEDs");
+#endif
+#ifdef KIOCCMD
+ click = KBD_CMD_NOCLICK;
+ if (ioctl(kbd_fd, KIOCCMD, &click))
+ die("Couldn't set click");
+#endif
+ if (ioctl(kbd_fd, KIOCTRANS, (caddr_t) &translate))
+ die("Couldn't set translation");
+ if (direct != -1 && ioctl(kbd_fd, KIOCSDIRECT, (caddr_t) &direct))
+ die("Couldn't set redirect");
+ return 0;
+}
+
+static void
+die(msg)
+ char *msg;
+{
+ fprintf(stderr, "%s\n", msg);
+ exit(1);
+}
+
+static void
+usage()
+{
+ int translate;
+
+ if (ioctl(kbd_fd, KIOCGTRANS, (caddr_t) &translate)) {
+ die("Couldn't inquire current translation");
+ }
+ fprintf(stderr, "kbd_mode {-a | -e | -n | -u }\n");
+ fprintf(stderr, "\tfor ascii, encoded (normal) SunView events,\n");
+ fprintf(stderr, " \tnon-encoded, or unencoded SunView events, resp.\n");
+ fprintf(stderr, "Current mode is %s.\n",
+ ( translate == 0 ? "n (non-translated bytes)" :
+ ( translate == 1 ? "a (ascii bytes)" :
+ ( translate == 2 ? "e (encoded events)" :
+ /* translate == 3 */ "u (unencoded events)"))));
+ exit(1);
+}
+
+
diff --git a/hw/xfree86/utils/kbd_mode/sun-kbd_mode.man.pre b/hw/xfree86/utils/kbd_mode/sun-kbd_mode.man.pre
new file mode 100644
index 000000000..88c4a89b4
--- /dev/null
+++ b/hw/xfree86/utils/kbd_mode/sun-kbd_mode.man.pre
@@ -0,0 +1,50 @@
+.\" $Xorg: kbd_mode.man,v 1.4 2001/02/09 02:04:43 xorgcvs Exp $
+.\" Copyright 1987 Sun Microsystems, Inc.
+.\" Copyright 1993, 1998 The Open Group
+.\"
+.\" Permission to use, copy, modify, distribute, and sell this software and its
+.\" documentation for any purpose is hereby granted without fee, provided that
+.\" the above copyright notice appear in all copies and that both that
+.\" copyright notice and this permission notice appear in supporting
+.\" documentation.
+.\"
+.\" The above copyright notice and this permission notice shall be included
+.\" in all copies or substantial portions of the Software.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+.\" OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+.\" MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+.\" IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR
+.\" OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+.\" ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+.\" OTHER DEALINGS IN THE SOFTWARE.
+.\"
+.\" Except as contained in this notice, the name of The Open Group shall
+.\" not be used in advertising or otherwise to promote the sale, use or
+.\" other dealings in this Software without prior written authorization
+.\" from The Open Group.
+.TH KBD_MODE 1 "Release 6.4" "X Version 11"
+.SH NAME
+kbd_mode \- recover the Sun console keyboard
+.SH SYNOPSIS
+.B kbd_mode
+[ -a -e -n -u ]
+.SH DESCRIPTION
+.I Kbd_mode
+resets the Sun console keyboard to a rational state.
+.SH OPTIONS
+The following options are supported, see \fIkb(4S)\fP for details:
+.TP 8
+.B \-a
+Causes ASCII to be reported.
+.TP 8
+.B \-e
+Causes \fIFirm_events\fP to be reported.
+.TP 8
+.B \-n
+Causes up/down key codes to be reported.
+.TP 8
+.B \-u
+Causes undecoded keyboard values to be reported.
+.SH SEE ALSO
+kb(4S)
diff --git a/hw/xfree86/utils/scanpci/scanpci.c b/hw/xfree86/utils/scanpci/scanpci.c
new file mode 100644
index 000000000..f3a142fba
--- /dev/null
+++ b/hw/xfree86/utils/scanpci/scanpci.c
@@ -0,0 +1,1790 @@
+/* $Xorg: scanpci.c,v 1.3 2000/08/17 19:51:10 cpqbld Exp $ */
+/*
+ * name: scanpci.c
+ *
+ * purpose: This program will scan for and print details of
+ * devices on the PCI bus.
+
+ * author: Robin Cutshaw (robin@xfree86.org)
+ *
+ * supported O/S's: SVR4, UnixWare, SCO, Solaris,
+ * FreeBSD, NetBSD, 386BSD, BSDI BSD/386,
+ * Linux, Mach/386, ISC
+ * DOS (WATCOM 9.5 compiler)
+ *
+ * compiling: [g]cc scanpci.c -o scanpci
+ * for SVR4 (not Solaris), UnixWare use:
+ * [g]cc -DSVR4 scanpci.c -o scanpci
+ * for DOS, watcom 9.5:
+ * wcc386p -zq -omaxet -7 -4s -s -w3 -d2 name.c
+ * and link with PharLap or other dos extender for exe
+ *
+ */
+
+/* $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.10 1998/02/27 17:13:22 robin Exp $ */
+
+/*
+ * Copyright 1995 by Robin Cutshaw <robin@XFree86.Org>
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the names of the above listed copyright holder(s)
+ * not be used in advertising or publicity pertaining to distribution of
+ * the software without specific, written prior permission. The above listed
+ * copyright holder(s) make(s) no representations about the suitability of this
+ * software for any purpose. It is provided "as is" without express or
+ * implied warranty.
+ *
+ * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
+ * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#if defined(__SVR4)
+#if !defined(SVR4)
+#define SVR4
+#endif
+#endif
+
+#ifdef __EMX__
+#define INCL_DOSFILEMGR
+#include <os2.h>
+#endif
+
+#include <stdio.h>
+#include <sys/types.h>
+#if defined(SVR4)
+#if defined(sun)
+#define __EXTENSIONS__
+#endif
+#include <sys/proc.h>
+#include <sys/tss.h>
+#if defined(NCR)
+#define __STDC
+#include <sys/sysi86.h>
+#undef __STDC
+#else
+#include <sys/sysi86.h>
+#endif
+#if defined(__SUNPRO_C) || defined(sun) || defined(__sun)
+#include <sys/psw.h>
+#else
+#include <sys/seg.h>
+#endif
+#include <sys/v86.h>
+#endif
+#if defined(__FreeBSD__) || defined(__386BSD__)
+#include <sys/file.h>
+#include <machine/console.h>
+#ifndef GCCUSESGAS
+#define GCCUSESGAS
+#endif
+#endif
+#if defined(__NetBSD__)
+#include <sys/param.h>
+#include <sys/file.h>
+#include <machine/sysarch.h>
+#ifndef GCCUSESGAS
+#define GCCUSESGAS
+#endif
+#endif
+#if defined(__bsdi__)
+#include <sys/file.h>
+#include <sys/ioctl.h>
+#include <i386/isa/pcconsioctl.h>
+#ifndef GCCUSESGAS
+#define GCCUSESGAS
+#endif
+#endif
+#if defined(SCO) || defined(ISC)
+#ifndef ISC
+#include <sys/console.h>
+#endif
+#include <sys/param.h>
+#include <sys/immu.h>
+#include <sys/region.h>
+#include <sys/proc.h>
+#include <sys/tss.h>
+#include <sys/sysi86.h>
+#include <sys/v86.h>
+#endif
+#if defined(Lynx_22)
+#ifndef GCCUSESGAS
+#define GCCUSESGAS
+#endif
+#endif
+
+
+#if defined(__WATCOMC__)
+
+#include <stdlib.h>
+void outl(unsigned port, unsigned data);
+#pragma aux outl = "out dx, eax" parm [dx] [eax];
+void outb(unsigned port, unsigned data);
+#pragma aux outb = "out dx, al" parm [dx] [eax];
+unsigned inl(unsigned port);
+#pragma aux inl = "in eax, dx" parm [dx];
+unsigned inb(unsigned port);
+#pragma aux inb = "xor eax,eax" "in al, dx" parm [dx];
+
+#else /* __WATCOMC__ */
+
+#if defined(__GNUC__)
+
+#if !defined(__alpha__) && !defined(__powerpc__)
+#if defined(GCCUSESGAS)
+#define OUTB_GCC "outb %0,%1"
+#define OUTL_GCC "outl %0,%1"
+#define INB_GCC "inb %1,%0"
+#define INL_GCC "inl %1,%0"
+#else
+#define OUTB_GCC "out%B0 (%1)"
+#define OUTL_GCC "out%L0 (%1)"
+#define INB_GCC "in%B0 (%1)"
+#define INL_GCC "in%L0 (%1)"
+#endif /* GCCUSESGAS */
+
+static void outb(unsigned short port, unsigned char val) {
+ __asm__ __volatile__(OUTB_GCC : :"a" (val), "d" (port)); }
+static void outl(unsigned short port, unsigned long val) {
+ __asm__ __volatile__(OUTL_GCC : :"a" (val), "d" (port)); }
+static unsigned char inb(unsigned short port) { unsigned char ret;
+ __asm__ __volatile__(INB_GCC : "=a" (ret) : "d" (port)); return ret; }
+static unsigned long inl(unsigned short port) { unsigned long ret;
+ __asm__ __volatile__(INL_GCC : "=a" (ret) : "d" (port)); return ret; }
+
+#endif /* !defined(__alpha__) && !defined(__powerpc__) */
+#else /* __GNUC__ */
+
+#if defined(__STDC__) && (__STDC__ == 1)
+# if !defined(NCR)
+# define asm __asm
+# endif
+#endif
+
+#if defined(__SUNPRO_C)
+/*
+ * This section is a gross hack in if you tell anyone that I wrote it,
+ * I'll deny it. :-)
+ * The leave/ret instructions are the big hack to leave %eax alone on return.
+ */
+ unsigned char inb(int port) {
+ asm(" movl 8(%esp),%edx");
+ asm(" subl %eax,%eax");
+ asm(" inb (%dx)");
+ asm(" leave");
+ asm(" ret");
+ }
+
+ unsigned short inw(int port) {
+ asm(" movl 8(%esp),%edx");
+ asm(" subl %eax,%eax");
+ asm(" inw (%dx)");
+ asm(" leave");
+ asm(" ret");
+ }
+
+ unsigned long inl(int port) {
+ asm(" movl 8(%esp),%edx");
+ asm(" inl (%dx)");
+ asm(" leave");
+ asm(" ret");
+ }
+
+ void outb(int port, unsigned char value) {
+ asm(" movl 8(%esp),%edx");
+ asm(" movl 12(%esp),%eax");
+ asm(" outb (%dx)");
+ }
+
+ void outw(int port, unsigned short value) {
+ asm(" movl 8(%esp),%edx");
+ asm(" movl 12(%esp),%eax");
+ asm(" outw (%dx)");
+ }
+
+ void outl(int port, unsigned long value) {
+ asm(" movl 8(%esp),%edx");
+ asm(" movl 12(%esp),%eax");
+ asm(" outl (%dx)");
+ }
+#else
+
+#if defined(SVR4)
+# if !defined(__USLC__)
+# define __USLC__
+# endif
+#endif
+
+#ifndef SCO325
+# include <sys/inline.h>
+#else
+# include "scoasm.h"
+#endif
+
+#endif /* SUNPRO_C */
+
+#endif /* __GNUC__ */
+#endif /* __WATCOMC__ */
+
+
+#if defined(__alpha__)
+#if defined(linux)
+#include <asm/unistd.h>
+#define BUS(tag) (((tag)>>16)&0xff)
+#define DFN(tag) (((tag)>>8)&0xff)
+int pciconfig_read(
+ unsigned char bus,
+ unsigned char dfn,
+ unsigned char off,
+ unsigned char len,
+ void * buf)
+{
+ return __syscall(__NR_pciconfig_read, bus, dfn, off, len, buf);
+}
+int pciconfig_write(
+ unsigned char bus,
+ unsigned char dfn,
+ unsigned char off,
+ unsigned char len,
+ void * buf)
+{
+ return __syscall(__NR_pciconfig_write, bus, dfn, off, len, buf);
+}
+#else
+Generate compiler error - scanpci unsupported on non-linux alpha platforms
+#endif /* linux */
+#endif /* __alpha__ */
+#if defined(Lynx) && defined(__powerpc__)
+/* let's mimick the Linux Alpha stuff for LynxOS so we don't have
+ * to change too much code
+ */
+#include <smem.h>
+
+unsigned char *pciConfBase;
+
+static __inline__ unsigned long
+swapl(unsigned long val)
+{
+ unsigned char *p = (unsigned char *)&val;
+ return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0] << 0));
+}
+
+
+#define BUS(tag) (((tag)>>16)&0xff)
+#define DFN(tag) (((tag)>>8)&0xff)
+
+#define PCIBIOS_DEVICE_NOT_FOUND 0x86
+#define PCIBIOS_SUCCESSFUL 0x00
+
+int pciconfig_read(
+ unsigned char bus,
+ unsigned char dev,
+ unsigned char offset,
+ int len, /* unused, alway 4 */
+ unsigned long *val)
+{
+ unsigned long _val;
+ unsigned long *ptr;
+
+ dev >>= 3;
+ if (bus || dev >= 16) {
+ *val = 0xFFFFFFFF;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ } else {
+ ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset));
+ _val = swapl(*ptr);
+ }
+ *val = _val;
+ return PCIBIOS_SUCCESSFUL;
+}
+
+int pciconfig_write(
+ unsigned char bus,
+ unsigned char dev,
+ unsigned char offset,
+ int len, /* unused, alway 4 */
+ unsigned long val)
+{
+ unsigned long _val;
+ unsigned long *ptr;
+
+ dev >>= 3;
+ _val = swapl(val);
+ if (bus || dev >= 16) {
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ } else {
+ ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset));
+ *ptr = _val;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+#endif
+
+#if !defined(__powerpc__)
+struct pci_config_reg {
+ /* start of official PCI config space header */
+ union {
+ unsigned long device_vendor;
+ struct {
+ unsigned short vendor;
+ unsigned short device;
+ } dv;
+ } dv_id;
+#define _device_vendor dv_id.device_vendor
+#define _vendor dv_id.dv.vendor
+#define _device dv_id.dv.device
+ union {
+ unsigned long status_command;
+ struct {
+ unsigned short command;
+ unsigned short status;
+ } sc;
+ } stat_cmd;
+#define _status_command stat_cmd.status_command
+#define _command stat_cmd.sc.command
+#define _status stat_cmd.sc.status
+ union {
+ unsigned long class_revision;
+ struct {
+ unsigned char rev_id;
+ unsigned char prog_if;
+ unsigned char sub_class;
+ unsigned char base_class;
+ } cr;
+ } class_rev;
+#define _class_revision class_rev.class_revision
+#define _rev_id class_rev.cr.rev_id
+#define _prog_if class_rev.cr.prog_if
+#define _sub_class class_rev.cr.sub_class
+#define _base_class class_rev.cr.base_class
+ union {
+ unsigned long bist_header_latency_cache;
+ struct {
+ unsigned char cache_line_size;
+ unsigned char latency_timer;
+ unsigned char header_type;
+ unsigned char bist;
+ } bhlc;
+ } bhlc;
+#define _bist_header_latency_cache bhlc.bist_header_latency_cache
+#define _cache_line_size bhlc.bhlc.cache_line_size
+#define _latency_timer bhlc.bhlc.latency_timer
+#define _header_type bhlc.bhlc.header_type
+#define _bist bhlc.bhlc.bist
+ union {
+ struct {
+ unsigned long dv_base0;
+ unsigned long dv_base1;
+ unsigned long dv_base2;
+ unsigned long dv_base3;
+ unsigned long dv_base4;
+ unsigned long dv_base5;
+ } dv;
+ struct {
+ unsigned long bg_rsrvd[2];
+ unsigned char primary_bus_number;
+ unsigned char secondary_bus_number;
+ unsigned char subordinate_bus_number;
+ unsigned char secondary_latency_timer;
+ unsigned char io_base;
+ unsigned char io_limit;
+ unsigned short secondary_status;
+ unsigned short mem_base;
+ unsigned short mem_limit;
+ unsigned short prefetch_mem_base;
+ unsigned short prefetch_mem_limit;
+ } bg;
+ } bc;
+#define _base0 bc.dv.dv_base0
+#define _base1 bc.dv.dv_base1
+#define _base2 bc.dv.dv_base2
+#define _base3 bc.dv.dv_base3
+#define _base4 bc.dv.dv_base4
+#define _base5 bc.dv.dv_base5
+#define _primary_bus_number bc.bg.primary_bus_number
+#define _secondary_bus_number bc.bg.secondary_bus_number
+#define _subordinate_bus_number bc.bg.subordinate_bus_number
+#define _secondary_latency_timer bc.bg.secondary_latency_timer
+#define _io_base bc.bg.io_base
+#define _io_limit bc.bg.io_limit
+#define _secondary_status bc.bg.secondary_status
+#define _mem_base bc.bg.mem_base
+#define _mem_limit bc.bg.mem_limit
+#define _prefetch_mem_base bc.bg.prefetch_mem_base
+#define _prefetch_mem_limit bc.bg.prefetch_mem_limit
+ unsigned long rsvd1;
+ unsigned long rsvd2;
+ unsigned long _baserom;
+ unsigned long rsvd3;
+ unsigned long rsvd4;
+ union {
+ unsigned long max_min_ipin_iline;
+ struct {
+ unsigned char int_line;
+ unsigned char int_pin;
+ unsigned char min_gnt;
+ unsigned char max_lat;
+ } mmii;
+ } mmii;
+#define _max_min_ipin_iline mmii.max_min_ipin_iline
+#define _int_line mmii.mmii.int_line
+#define _int_pin mmii.mmii.int_pin
+#define _min_gnt mmii.mmii.min_gnt
+#define _max_lat mmii.mmii.max_lat
+ /* I don't know how accurate or standard this is (DHD) */
+ union {
+ unsigned long user_config;
+ struct {
+ unsigned char user_config_0;
+ unsigned char user_config_1;
+ unsigned char user_config_2;
+ unsigned char user_config_3;
+ } uc;
+ } uc;
+#define _user_config uc.user_config
+#define _user_config_0 uc.uc.user_config_0
+#define _user_config_1 uc.uc.user_config_1
+#define _user_config_2 uc.uc.user_config_2
+#define _user_config_3 uc.uc.user_config_3
+ /* end of official PCI config space header */
+ unsigned long _pcibusidx;
+ unsigned long _pcinumbus;
+ unsigned long _pcibuses[16];
+ unsigned short _configtype; /* config type found */
+ unsigned short _ioaddr; /* config type 1 - private I/O addr */
+ unsigned long _cardnum; /* config type 2 - private card number */
+};
+#else
+/* ppc is big endian, swapping bytes is not quite enough
+ * to interpret the PCI config registers...
+ */
+struct pci_config_reg {
+ /* start of official PCI config space header */
+ union {
+ unsigned long device_vendor;
+ struct {
+ unsigned short device;
+ unsigned short vendor;
+ } dv;
+ } dv_id;
+#define _device_vendor dv_id.device_vendor
+#define _vendor dv_id.dv.vendor
+#define _device dv_id.dv.device
+ union {
+ unsigned long status_command;
+ struct {
+ unsigned short status;
+ unsigned short command;
+ } sc;
+ } stat_cmd;
+#define _status_command stat_cmd.status_command
+#define _command stat_cmd.sc.command
+#define _status stat_cmd.sc.status
+ union {
+ unsigned long class_revision;
+ struct {
+ unsigned char base_class;
+ unsigned char sub_class;
+ unsigned char prog_if;
+ unsigned char rev_id;
+ } cr;
+ } class_rev;
+#define _class_revision class_rev.class_revision
+#define _rev_id class_rev.cr.rev_id
+#define _prog_if class_rev.cr.prog_if
+#define _sub_class class_rev.cr.sub_class
+#define _base_class class_rev.cr.base_class
+ union {
+ unsigned long bist_header_latency_cache;
+ struct {
+ unsigned char bist;
+ unsigned char header_type;
+ unsigned char latency_timer;
+ unsigned char cache_line_size;
+ } bhlc;
+ } bhlc;
+#define _bist_header_latency_cache bhlc.bist_header_latency_cache
+#define _cache_line_size bhlc.bhlc.cache_line_size
+#define _latency_timer bhlc.bhlc.latency_timer
+#define _header_type bhlc.bhlc.header_type
+#define _bist bhlc.bhlc.bist
+ union {
+ struct {
+ unsigned long dv_base0;
+ unsigned long dv_base1;
+ unsigned long dv_base2;
+ unsigned long dv_base3;
+ unsigned long dv_base4;
+ unsigned long dv_base5;
+ } dv;
+/* ?? */
+ struct {
+ unsigned long bg_rsrvd[2];
+
+ unsigned char secondary_latency_timer;
+ unsigned char subordinate_bus_number;
+ unsigned char secondary_bus_number;
+ unsigned char primary_bus_number;
+
+ unsigned short secondary_status;
+ unsigned char io_limit;
+ unsigned char io_base;
+
+ unsigned short mem_limit;
+ unsigned short mem_base;
+
+ unsigned short prefetch_mem_limit;
+ unsigned short prefetch_mem_base;
+ } bg;
+ } bc;
+#define _base0 bc.dv.dv_base0
+#define _base1 bc.dv.dv_base1
+#define _base2 bc.dv.dv_base2
+#define _base3 bc.dv.dv_base3
+#define _base4 bc.dv.dv_base4
+#define _base5 bc.dv.dv_base5
+#define _primary_bus_number bc.bg.primary_bus_number
+#define _secondary_bus_number bc.bg.secondary_bus_number
+#define _subordinate_bus_number bc.bg.subordinate_bus_number
+#define _secondary_latency_timer bc.bg.secondary_latency_timer
+#define _io_base bc.bg.io_base
+#define _io_limit bc.bg.io_limit
+#define _secondary_status bc.bg.secondary_status
+#define _mem_base bc.bg.mem_base
+#define _mem_limit bc.bg.mem_limit
+#define _prefetch_mem_base bc.bg.prefetch_mem_base
+#define _prefetch_mem_limit bc.bg.prefetch_mem_limit
+ unsigned long rsvd1;
+ unsigned long rsvd2;
+ unsigned long _baserom;
+ unsigned long rsvd3;
+ unsigned long rsvd4;
+ union {
+ unsigned long max_min_ipin_iline;
+ struct {
+ unsigned char max_lat;
+ unsigned char min_gnt;
+ unsigned char int_pin;
+ unsigned char int_line;
+ } mmii;
+ } mmii;
+#define _max_min_ipin_iline mmii.max_min_ipin_iline
+#define _int_line mmii.mmii.int_line
+#define _int_pin mmii.mmii.int_pin
+#define _min_gnt mmii.mmii.min_gnt
+#define _max_lat mmii.mmii.max_lat
+ /* I don't know how accurate or standard this is (DHD) */
+ union {
+ unsigned long user_config;
+ struct {
+ unsigned char user_config_3;
+ unsigned char user_config_2;
+ unsigned char user_config_1;
+ unsigned char user_config_0;
+ } uc;
+ } uc;
+#define _user_config uc.user_config
+#define _user_config_0 uc.uc.user_config_0
+#define _user_config_1 uc.uc.user_config_1
+#define _user_config_2 uc.uc.user_config_2
+#define _user_config_3 uc.uc.user_config_3
+ /* end of official PCI config space header */
+ unsigned long _pcibusidx;
+ unsigned long _pcinumbus;
+ unsigned long _pcibuses[16];
+ unsigned short _ioaddr; /* config type 1 - private I/O addr */
+ unsigned short _configtype; /* config type found */
+ unsigned long _cardnum; /* config type 2 - private card number */
+};
+#endif
+
+extern void identify_card(struct pci_config_reg *, int);
+extern void print_i128(struct pci_config_reg *);
+extern void print_mach64(struct pci_config_reg *);
+extern void print_pcibridge(struct pci_config_reg *);
+extern void enable_os_io();
+extern void disable_os_io();
+
+#define MAX_DEV_PER_VENDOR_CFG1 32
+#define MAX_DEV_PER_VENDOR_CFG2 16
+#define MAX_PCI_DEVICES 64
+#define NF ((void (*)())NULL)
+#define PCI_MULTIFUNC_DEV 0x80
+#if defined(__alpha__) || defined(__powerpc__)
+#define PCI_ID_REG 0x00
+#define PCI_CMD_STAT_REG 0x04
+#define PCI_CLASS_REG 0x08
+#define PCI_HEADER_MISC 0x0C
+#define PCI_MAP_REG_START 0x10
+#define PCI_MAP_ROM_REG 0x30
+#define PCI_INTERRUPT_REG 0x3C
+#define PCI_REG_USERCONFIG 0x40
+#endif
+
+struct pci_vendor_device {
+ unsigned short vendor_id;
+ char *vendorname;
+ struct pci_device {
+ unsigned short device_id;
+ char *devicename;
+ void (*print_func)(struct pci_config_reg *);
+ } device[MAX_DEV_PER_VENDOR_CFG1];
+} pvd[] = {
+ { 0x0e11, "Compaq", {
+ { 0x3033, "QVision 1280/p", NF },
+ { 0xae10, "Smart-2/P RAID Controller", NF },
+ { 0xae32, "Netellignet 10/100", NF },
+ { 0xae34, "Netellignet 10", NF },
+ { 0xae35, "NetFlex 3", NF },
+ { 0xae40, "Netellignet 10/100 Dual", NF },
+ { 0xae43, "Netellignet 10/100 ProLiant", NF },
+ { 0xb011, "Netellignet 10/100 Integrated", NF },
+ { 0xf130, "ThunderLAN", NF },
+ { 0xf150, "NetFlex 3 BNC", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1000, "NCR", {
+ { 0x0001, "53C810", NF },
+ { 0x0002, "53C820", NF },
+ { 0x0003, "53C825", NF },
+ { 0x0004, "53C815", NF },
+ { 0x0005, "53C810AP", NF },
+ { 0x0006, "53C860", NF },
+ { 0x000B, "53C896", NF },
+ { 0x000C, "53C895", NF },
+ { 0x000D, "53C885", NF },
+ { 0x000F, "53C875", NF },
+ { 0x008F, "53C875J", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1002, "ATI", {
+ { 0x4158, "Mach32", NF },
+ { 0x4354, "Mach64 CT", print_mach64 },
+ { 0x4358, "Mach64 CX", print_mach64 },
+ { 0x4554, "Mach64 ET", print_mach64 },
+ { 0x4742, "Mach64 GB", print_mach64 },
+ { 0x4744, "Mach64 GD", print_mach64 },
+ { 0x4750, "Mach64 GP", print_mach64 },
+ { 0x4754, "Mach64 GT", print_mach64 },
+ { 0x4755, "Mach64 GT", print_mach64 },
+ { 0x4758, "Mach64 GX", print_mach64 },
+ { 0x4C47, "Mach64 LT", print_mach64 },
+ { 0x5654, "Mach64 VT", print_mach64 },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1004, "VLSI", {
+ { 0x0005, "82C592-FC1", NF },
+ { 0x0006, "82C593-FC1", NF },
+ { 0x0007, "82C594-AFC2", NF },
+ { 0x0009, "82C597-AFC2", NF },
+ { 0x000C, "82C541 Lynx", NF },
+ { 0x000D, "82C543 Lynx ISA", NF },
+ { 0x0702, "VAS96011", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1005, "Avance Logic", {
+ { 0x2301, "ALG2301", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x100B, "NS", {
+ { 0x0002, "87415", NF },
+ { 0xD001, "87410", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x100C, "Tseng Labs", {
+ { 0x3202, "ET4000w32p rev A", NF },
+ { 0x3205, "ET4000w32p rev B", NF },
+ { 0x3206, "ET4000w32p rev D", NF },
+ { 0x3207, "ET4000w32p rev C", NF },
+ { 0x3208, "ET6000/6100", NF },
+ { 0x4702, "ET6300", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x100E, "Weitek", {
+ { 0x9001, "P9000", NF },
+ { 0x9100, "P9100", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1011, "Digital Equipment Corporation", {
+ { 0x0001, "DC21050 PCI-PCI Bridge",print_pcibridge},
+ { 0x0002, "DC21040 10Mb/s Ethernet", NF },
+ { 0x0004, "TGA", NF },
+ { 0x0009, "DC21140 10/100 Mb/s Ethernet", NF },
+ { 0x000D, "TGA2", NF },
+ { 0x000F, "DEFPA (FDDI PCI)", NF },
+ { 0x0014, "DC21041 10Mb/s Ethernet Plus", NF },
+ { 0x0019, "DC21142 10/100 Mb/s Ethernet", NF },
+ { 0x0021, "DC21052", NF },
+ { 0x0024, "DC21152", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1013, "Cirrus Logic", {
+ { 0x0038, "GD 7548", NF },
+ { 0x00A0, "GD 5430", NF },
+ { 0x00A4, "GD 5434-4", NF },
+ { 0x00A8, "GD 5434-8", NF },
+ { 0x00AC, "GD 5436", NF },
+ { 0x00B8, "GD 5446", NF },
+ { 0x00BC, "GD 5480", NF },
+ { 0x00D0, "GD 5462", NF },
+ { 0x00D4, "GD 5464", NF },
+ { 0x1100, "CL 6729", NF },
+ { 0x1110, "CL 6832", NF },
+ { 0x1200, "GD 7542", NF },
+ { 0x1202, "GD 7543", NF },
+ { 0x1204, "GD 7541", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1014, "IBM", {
+ { 0x000A, "Fire Coral", NF },
+ { 0x0018, "Token Ring", NF },
+ { 0x001D, "82G2675", NF },
+ { 0x0022, "82351 pci-pci bridge", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x101A, "NCR", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x101C, "WD*", {
+ { 0x3296, "WD 7197", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1022, "AMD", {
+ { 0x2000, "79C970 Lance", NF },
+ { 0x2020, "53C974 SCSI", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1023, "Trident", {
+ { 0x9320, "TGUI 9320", NF },
+ { 0x9420, "TGUI 9420", NF },
+ { 0x9440, "TGUI 9440", NF },
+ { 0x9660, "TGUI 9660/9680/9682", NF },
+#if 0
+ { 0x9680, "TGUI 9680", NF },
+ { 0x9682, "TGUI 9682", NF },
+#endif
+ { 0x9750, "TGUI 9750", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1025, "ALI", {
+ { 0x1435, "M1435", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x102B, "Matrox", {
+ { 0x0518, "MGA-2 Atlas PX2085", NF },
+ { 0x0519, "MGA Millennium", NF },
+ { 0x051a, "MGA Mystique", NF },
+ { 0x051b, "MGA Millennium II", NF },
+ { 0x0D10, "MGA Impression", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x102C, "CT", {
+ { 0x00D8, "65545", NF },
+ { 0x00DC, "65548", NF },
+ { 0x00E0, "65550", NF },
+ { 0x00E4, "65554", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1031, "Miro", {
+ { 0x5601, "ZR36050", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1033, "NEC", {
+ { 0x0046, "PowerVR PCX2", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1036, "FD", {
+ { 0x0000, "TMC-18C30 (36C70)", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1039, "SIS", {
+ { 0x0001, "86C201", NF },
+ { 0x0002, "86C202", NF },
+ { 0x0008, "85C503", NF },
+ { 0x0205, "86C205", NF },
+ { 0x0406, "85C501", NF },
+ { 0x0496, "85C496", NF },
+ { 0x0601, "85C601", NF },
+ { 0x5107, "5107", NF },
+ { 0x5511, "85C5511", NF },
+ { 0x5513, "85C5513", NF },
+ { 0x5571, "5571", NF },
+ { 0x5597, "5597", NF },
+ { 0x7001, "7001", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x103C, "HP", {
+ { 0x1030, "J2585A", NF },
+ { 0x1031, "J2585B", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1042, "SMC/PCTECH", {
+ { 0x1000, "FDC 37C665/RZ1000", NF },
+ { 0x1001, "FDC /RZ1001", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1044, "DPT", {
+ { 0xA400, "SmartCache/Raid", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1045, "Opti", {
+ { 0xC178, "92C178", NF },
+ { 0xC557, "82C557 Viper-M", NF },
+ { 0xC558, "82C558 Viper-M ISA+IDE", NF },
+ { 0xC621, "82C621", NF },
+ { 0xC700, "82C700", NF },
+ { 0xC701, "82C701 FireStar Plus", NF },
+ { 0xC814, "82C814 Firebridge 1", NF },
+ { 0xC822, "82C822", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x104A, "SGS Thomson", {
+ { 0x0008, "STG2000", NF },
+ { 0x0009, "STG1764", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x104B, "BusLogic", {
+ { 0x0140, "946C 01", NF },
+ { 0x1040, "946C 10", NF },
+ { 0x8130, "FlashPoint", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x104C, "Texas Instruments", {
+ { 0x3d04, "3DLabs Permedia", NF },
+ { 0x3d07, "3DLabs Permedia 2", NF },
+ { 0xAC12, "PCI1130", NF },
+ { 0xAC15, "PCI1131", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x104E, "Oak", {
+ { 0x0107, "OTI107", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1050, "Windbond", {
+ { 0x0940, "89C940 NE2000-PCI", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1057, "Motorola", {
+ { 0x0001, "MPC105 Eagle", NF },
+ { 0x0002, "MPC105 Grackle", NF },
+ { 0x4801, "Raven", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x105A, "Promise", {
+ { 0x4D33, "IDE UltraDMA/33", NF },
+ { 0x5300, "DC5030", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x105D, "Number Nine", {
+ { 0x2309, "Imagine-128", print_i128 },
+ { 0x2339, "Imagine-128-II", print_i128 },
+ { 0x493D, "Imagine-128-T2R", print_i128 },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1060, "UMC", {
+ { 0x0101, "UM8673F", NF },
+ { 0x673A, "UM8886BF", NF },
+ { 0x886A, "UM8886A", NF },
+ { 0x8881, "UM8881F", NF },
+ { 0x8886, "UM8886F", NF },
+ { 0x8891, "UM8891A", NF },
+ { 0x9017, "UM9017F", NF },
+ { 0xE886, "UM8886N", NF },
+ { 0xE891, "UM8891N", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1061, "X", {
+ { 0x0001, "ITT AGX016", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1066, "PICOP", {
+ { 0x0001, "PT86C52x Vesuvius", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x106B, "Apple", {
+ { 0x0001, "Bandit", NF },
+ { 0x0002, "Grand Central", NF },
+ { 0x000E, "Hydra", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1074, "Nexgen", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1077, "QLogic", {
+ { 0x1020, "ISP1020", NF },
+ { 0x1022, "ISP1022", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1078, "Cyrix", {
+ { 0x0000, "5510", NF },
+ { 0x0001, "PCI Master", NF },
+ { 0x0002, "5520", NF },
+ { 0x0100, "5530 Kahlua Legacy", NF },
+ { 0x0101, "5530 Kahlua SMI", NF },
+ { 0x0102, "5530 Kahlua IDE", NF },
+ { 0x0103, "5530 Kahlua Audio", NF },
+ { 0x0104, "5530 Kahlua Video", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x107D, "Leadtek", {
+ { 0x0000, "S3 805", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1080, "Contaq", {
+ { 0x0600, "82C599", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1083, "FOREX", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x108D, "Olicom", {
+ { 0x0001, "OC-3136", NF },
+ { 0x0011, "OC-2315", NF },
+ { 0x0012, "OC-2325", NF },
+ { 0x0013, "OC-2183", NF },
+ { 0x0014, "OC-2326", NF },
+ { 0x0021, "OC-6151", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x108E, "Sun", {
+ { 0x1000, "EBUS", NF },
+ { 0x1001, "Happy Meal", NF },
+ { 0x8000, "PCI Bus Module", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1095, "CMD", {
+ { 0x0640, "640A", NF },
+ { 0x0643, "643", NF },
+ { 0x0646, "646", NF },
+ { 0x0670, "670", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1098, "Vision", {
+ { 0x0001, "QD 8500", NF },
+ { 0x0002, "QD 8580", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x109E, "Brooktree", {
+ { 0x0350, "Bt848", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10A8, "Sierra", {
+ { 0x0000, "STB Horizon 64", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10AA, "ACC", {
+ { 0x0000, "2056", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10AD, "Winbond", {
+ { 0x0001, "W83769F", NF },
+ { 0x0105, "SL82C105", NF },
+ { 0x0565, "W83C553", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10B3, "Databook", {
+ { 0xB106, "DB87144", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10B7, "3COM", {
+ { 0x5900, "3C590 10bT", NF },
+ { 0x5950, "3C595 100bTX", NF },
+ { 0x5951, "3C595 100bT4", NF },
+ { 0x5952, "3C595 10b-MII", NF },
+ { 0x9000, "3C900 10bTPO", NF },
+ { 0x9001, "3C900 10b Combo", NF },
+ { 0x9050, "3C905 100bTX", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10B8, "SMC", {
+ { 0x0005, "9432 TX", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10B9, "ALI", {
+ { 0x1445, "M1445", NF },
+ { 0x1449, "M1449", NF },
+ { 0x1451, "M1451", NF },
+ { 0x1461, "M1461", NF },
+ { 0x1489, "M1489", NF },
+ { 0x1511, "M1511", NF },
+ { 0x1513, "M1513", NF },
+ { 0x1521, "M1521", NF },
+ { 0x1523, "M1523", NF },
+ { 0x1531, "M1531 Aladdin IV", NF },
+ { 0x1533, "M1533 Aladdin IV", NF },
+ { 0x5215, "M4803", NF },
+ { 0x5219, "M5219", NF },
+ { 0x5229, "M5229 TXpro", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10BA, "Mitsubishi", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10BD, "Surecom", {
+ { 0x0E34, "NE-34PCI Lan", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10C8, "Neomagic", {
+ { 0x0001, "Magicgraph NM2070", NF },
+ { 0x0002, "Magicgraph 128V", NF },
+ { 0x0003, "Magicgraph 128ZV", NF },
+ { 0x0004, "Magicgraph NM2160", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10CD, "Advanced System Products", {
+ { 0x1200, "ABP940", NF },
+ { 0x1300, "ABP940U", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10DC, "CERN", {
+ { 0x0001, "STAR/RD24 SCI-PCI (PMC)", NF },
+ { 0x0002, "STAR/RD24 SCI-PCI (PMC)", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10DE, "NVidia", {
+ { 0x0008, "NV1", NF },
+ { 0x0009, "DAC64", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10E0, "IMS", {
+ { 0x8849, "8849", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10E1, "Tekram", {
+ { 0x690C, "DC690C", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10E3, "Tundra", {
+ { 0x0000, "CA91C042 Universe", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10E8, "AMCC", {
+ { 0x8043, "Myrinet PCI (M2-PCI-32)", NF },
+ { 0x807D, "S5933 PCI44", NF },
+ { 0x809C, "S5933 Traquair HEPC3", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10EA, "Intergraphics", {
+ { 0x1680, "IGA-1680", NF },
+ { 0x1682, "IGA-1682", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10EC, "Realtek", {
+ { 0x8029, "8029", NF },
+ { 0x8129, "8129", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x10FA, "Truevision", {
+ { 0x000C, "Targa 1000", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1101, "Initio Corp", {
+ { 0x9100, "320 P", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1106, "VIA", {
+ { 0x0505, "VT 82C505", NF },
+ { 0x0561, "VT 82C505", NF },
+ { 0x0576, "VT 82C576 3V", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1119, "Vortex", {
+ { 0x0001, "GDT 6000b", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x111A, "EF", {
+ { 0x0000, "155P-MF1", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1127, "Fore Systems", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x112F, "Imaging Technology", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x113C, "PLX", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1142, "Alliance", {
+ { 0x3210, "ProMotion 6410", NF },
+ { 0x6422, "ProMotion 6422", NF },
+ { 0x6424, "ProMotion AT24", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x114A, "VMIC", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x114F, "DIGI*", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1159, "Mutech", {
+ { 0x0001, "MV1000", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1163, "Rendition", {
+ { 0x0001, "V1000", NF },
+ { 0x2000, "V2100", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1179, "Toshiba", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1193, "Zeinet", {
+ { 0x0001, "1221", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x11CB, "Specialix", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x11FE, "Control", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x120E, "Cyclades", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x121A, "3Dfx Interactive", {
+ { 0x0001, "Voodoo Graphics", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1236, "Sigma Designs", {
+ { 0x6401, "REALmagic64/GX (SD 6425)", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1281, "YOKOGAWA", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1292, "TriTech Microelectronics", {
+ { 0xfc02, "Pyramid3D TR25202", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x12D2, "NVidia/SGS-Thomson", {
+ { 0x0018, "Riva128", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1C1C, "Symphony", {
+ { 0x0001, "82C101", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x1DE1, "Tekram", {
+ { 0xDC29, "DC290", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x3D3D, "3Dlabs", {
+ { 0x0001, "GLINT 300SX", NF },
+ { 0x0002, "GLINT 500TX", NF },
+ { 0x0003, "GLINT Delta", NF },
+ { 0x0004, "GLINT Permedia", NF },
+ { 0x0006, "GLINT MX", NF },
+ { 0x0007, "GLINT Permedia 2", NF },
+ { 0x0000, (char *)NULL, NF } } } ,
+ { 0x4005, "Avance", {
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x5333, "S3", {
+ { 0x0551, "Plato/PX", NF },
+ { 0x5631, "ViRGE", NF },
+ { 0x8811, "Trio32/64", NF },
+ { 0x8812, "Aurora64V+", NF },
+ { 0x8814, "Trio64UV+", NF },
+ { 0x883D, "ViRGE/VX", NF },
+ { 0x8880, "868", NF },
+ { 0x88B0, "928", NF },
+ { 0x88C0, "864-0", NF },
+ { 0x88C1, "864-1", NF },
+ { 0x88D0, "964-0", NF },
+ { 0x88D1, "964-1", NF },
+ { 0x88F0, "968", NF },
+ { 0x8901, "Trio64V2/DX or /GX", NF },
+ { 0x8902, "PLATO/PX", NF },
+ { 0x8A01, "ViRGE/DX or /GX", NF },
+ { 0x8A10, "ViRGE/GX2", NF },
+ { 0x8C01, "ViRGE/MX", NF },
+ { 0x8C02, "ViRGE/MX+", NF },
+ { 0x8C03, "ViRGE/MX+MV", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x8086, "Intel", {
+ { 0x0482, "82375EB pci-eisa bridge", NF },
+ { 0x0483, "82424ZX cache dram controller", NF },
+ { 0x0484, "82378IB/ZB pci-isa bridge", NF },
+ { 0x0486, "82430ZX Aries", NF },
+ { 0x04A3, "82434LX/NX pci cache mem controller", NF },
+ { 0x1230, "82371 bus-master IDE controller", NF },
+ { 0x1223, "SAA7116", NF },
+ { 0x1229, "82557 10/100MBit network controller",NF},
+ { 0x122D, "82437 Triton", NF },
+ { 0x122E, "82471 Triton", NF },
+ { 0x1230, "82438", NF },
+ { 0x1250, "82439", NF },
+ { 0x7000, "82371 pci-isa bridge", NF },
+ { 0x7010, "82371 bus-master IDE controller", NF },
+ { 0x7100, "82439 TX", NF },
+ { 0x7110, "82371AB PIIX4 ISA", NF },
+ { 0x7111, "82371AB PIIX4 IDE", NF },
+ { 0x7112, "82371AB PIIX4 USB", NF },
+ { 0x7113, "82371AB PIIX4 ACPI", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x9004, "Adaptec", {
+ { 0x5078, "7850", NF },
+ { 0x5578, "7855", NF },
+ { 0x6078, "7860", NF },
+ { 0x7078, "294x", NF },
+ { 0x7178, "2940", NF },
+ { 0x7278, "7872", NF },
+ { 0x7478, "2944", NF },
+ { 0x8178, "2940U", NF },
+ { 0x8278, "3940U", NF },
+ { 0x8478, "2944U", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x907F, "Atronics", {
+ { 0x2015, "IDE-2015PL", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0xEDD8, "ARK Logic", {
+ { 0xA091, "1000PV", NF },
+ { 0xA099, "2000PV", NF },
+ { 0xA0A1, "2000MT", NF },
+ { 0xA0A9, "2000MI", NF },
+ { 0x0000, (char *)NULL, NF } } },
+ { 0x0000, (char *)NULL, {
+ { 0x0000, (char *)NULL, NF } } }
+};
+
+#if defined(__alpha__)
+#define PCI_EN 0x00000000
+#else
+#define PCI_EN 0x80000000
+#endif
+
+#define PCI_MODE1_ADDRESS_REG 0xCF8
+#define PCI_MODE1_DATA_REG 0xCFC
+
+#define PCI_MODE2_ENABLE_REG 0xCF8
+#ifdef PC98
+#define PCI_MODE2_FORWARD_REG 0xCF9
+#else
+#define PCI_MODE2_FORWARD_REG 0xCFA
+#endif
+
+
+main(int argc, unsigned char *argv[])
+{
+ unsigned long tmplong1, tmplong2, config_cmd;
+ unsigned char tmp1, tmp2;
+ unsigned int idx;
+ struct pci_config_reg pcr;
+ int ch, verbose = 0, do_mode1_scan = 0, do_mode2_scan = 0;
+ int func;
+
+ while((ch = getopt(argc, argv, "v12")) != EOF) {
+ switch((char)ch) {
+ case '1':
+ do_mode1_scan = 1;
+ break;
+ case '2':
+ do_mode2_scan = 1;
+ break;
+ case 'v':
+ verbose = 1;
+ break;
+ default :
+ printf("Usage: %s [-v12] \n", argv[0]);
+ exit(1);
+ }
+ }
+#if !defined(MSDOS)
+ if (getuid()) {
+ printf("This program must be run as root\n");
+ exit(1);
+ }
+#endif
+
+ enable_os_io();
+
+#if !defined(__alpha__) && !defined(__powerpc__)
+ pcr._configtype = 0;
+
+ outb(PCI_MODE2_ENABLE_REG, 0x00);
+ outb(PCI_MODE2_FORWARD_REG, 0x00);
+ tmp1 = inb(PCI_MODE2_ENABLE_REG);
+ tmp2 = inb(PCI_MODE2_FORWARD_REG);
+ if ((tmp1 == 0x00) && (tmp2 == 0x00)) {
+ pcr._configtype = 2;
+ printf("PCI says configuration type 2\n");
+ } else {
+ tmplong1 = inl(PCI_MODE1_ADDRESS_REG);
+ outl(PCI_MODE1_ADDRESS_REG, PCI_EN);
+ tmplong2 = inl(PCI_MODE1_ADDRESS_REG);
+ outl(PCI_MODE1_ADDRESS_REG, tmplong1);
+ if (tmplong2 == PCI_EN) {
+ pcr._configtype = 1;
+ printf("PCI says configuration type 1\n");
+ } else {
+ printf("No PCI !\n");
+ disable_os_io();
+ exit(1);
+ }
+ }
+#else
+ pcr._configtype = 1;
+#endif
+
+ /* Try pci config 1 probe first */
+
+ if ((pcr._configtype == 1) || do_mode1_scan) {
+ printf("\nPCI probing configuration type 1\n");
+
+ pcr._ioaddr = 0xFFFF;
+
+ pcr._pcibuses[0] = 0;
+ pcr._pcinumbus = 1;
+ pcr._pcibusidx = 0;
+ idx = 0;
+
+ do {
+ printf("Probing for devices on PCI bus %d:\n\n", pcr._pcibusidx);
+
+ for (pcr._cardnum = 0x0; pcr._cardnum < MAX_DEV_PER_VENDOR_CFG1;
+ pcr._cardnum += 0x1) {
+ func = 0;
+ do { /* loop over the different functions, if present */
+#if !defined(__alpha__) && !defined(__powerpc__)
+ config_cmd = PCI_EN | (pcr._pcibuses[pcr._pcibusidx]<<16) |
+ (pcr._cardnum<<11) | (func<<8);
+
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd); /* ioreg 0 */
+ pcr._device_vendor = inl(PCI_MODE1_DATA_REG);
+#else
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_ID_REG, 4, &pcr._device_vendor);
+#endif
+
+ if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF))
+ break; /* nothing there */
+
+ printf("\npci bus 0x%x cardnum 0x%02x function 0x%04x: vendor 0x%04x device 0x%04x\n",
+ pcr._pcibuses[pcr._pcibusidx], pcr._cardnum, func,
+ pcr._vendor, pcr._device);
+
+#if !defined(__alpha__) && !defined(__powerpc__)
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x04);
+ pcr._status_command = inl(PCI_MODE1_DATA_REG);
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x08);
+ pcr._class_revision = inl(PCI_MODE1_DATA_REG);
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x0C);
+ pcr._bist_header_latency_cache = inl(PCI_MODE1_DATA_REG);
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x10);
+ pcr._base0 = inl(PCI_MODE1_DATA_REG);
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x14);
+ pcr._base1 = inl(PCI_MODE1_DATA_REG);
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x18);
+ pcr._base2 = inl(PCI_MODE1_DATA_REG);
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x1C);
+ pcr._base3 = inl(PCI_MODE1_DATA_REG);
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x20);
+ pcr._base4 = inl(PCI_MODE1_DATA_REG);
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x24);
+ pcr._base5 = inl(PCI_MODE1_DATA_REG);
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x30);
+ pcr._baserom = inl(PCI_MODE1_DATA_REG);
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x3C);
+ pcr._max_min_ipin_iline = inl(PCI_MODE1_DATA_REG);
+ outl(PCI_MODE1_ADDRESS_REG, config_cmd | 0x40);
+ pcr._user_config = inl(PCI_MODE1_DATA_REG);
+#else
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_CMD_STAT_REG, 4, &pcr._status_command);
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_CLASS_REG, 4, &pcr._class_revision);
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_HEADER_MISC, 4, &pcr._bist_header_latency_cache);
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_MAP_REG_START, 4, &pcr._base0);
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_MAP_REG_START + 0x04, 4, &pcr._base1);
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_MAP_REG_START + 0x08, 4, &pcr._base2);
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_MAP_REG_START + 0x0C, 4, &pcr._base3);
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_MAP_REG_START + 0x10, 4, &pcr._base4);
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_MAP_REG_START + 0x14, 4, &pcr._base5);
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_MAP_ROM_REG, 4, &pcr._baserom);
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_INTERRUPT_REG, 4, &pcr._max_min_ipin_iline);
+ pciconfig_read(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum<<3,
+ PCI_REG_USERCONFIG, 4, &pcr._user_config);
+#endif
+
+ /* check for pci-pci bridges */
+#define PCI_CLASS_MASK 0xff000000
+#define PCI_SUBCLASS_MASK 0x00ff0000
+#define PCI_CLASS_BRIDGE 0x06000000
+#define PCI_SUBCLASS_BRIDGE_PCI 0x00040000
+ switch(pcr._class_revision & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) {
+ case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI:
+ if (pcr._secondary_bus_number > 0) {
+ pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number;
+ }
+ break;
+ default:
+ break;
+ }
+ if((func==0) && ((pcr._header_type & PCI_MULTIFUNC_DEV) == 0)) {
+ /* not a multi function device */
+ func = 8;
+ } else {
+ func++;
+ }
+
+ if (idx++ >= MAX_PCI_DEVICES)
+ continue;
+
+ identify_card(&pcr, verbose);
+ } while( func < 8 );
+ }
+ } while (++pcr._pcibusidx < pcr._pcinumbus);
+ }
+
+#if !defined(__alpha__) && !defined(__powerpc__)
+ /* Now try pci config 2 probe (deprecated) */
+
+ if ((pcr._configtype == 2) || do_mode2_scan) {
+ outb(PCI_MODE2_ENABLE_REG, 0xF1);
+ outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
+
+ printf("\nPCI probing configuration type 2\n");
+
+ pcr._pcibuses[0] = 0;
+ pcr._pcinumbus = 1;
+ pcr._pcibusidx = 0;
+ idx = 0;
+
+ do {
+ for (pcr._ioaddr = 0xC000; pcr._ioaddr < 0xD000; pcr._ioaddr += 0x0100){
+ outb(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */
+ pcr._device_vendor = inl(pcr._ioaddr);
+ outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
+
+ if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF))
+ continue;
+ if ((pcr._vendor == 0xF0F0) || (pcr._device == 0xF0F0))
+ continue; /* catch ASUS P55TP4XE motherboards */
+
+ printf("\npci bus 0x%x slot at 0x%04x, vendor 0x%04x device 0x%04x\n",
+ pcr._pcibuses[pcr._pcibusidx], pcr._ioaddr, pcr._vendor,
+ pcr._device);
+
+ outb(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */
+ pcr._status_command = inl(pcr._ioaddr + 0x04);
+ pcr._class_revision = inl(pcr._ioaddr + 0x08);
+ pcr._bist_header_latency_cache = inl(pcr._ioaddr + 0x0C);
+ pcr._base0 = inl(pcr._ioaddr + 0x10);
+ pcr._base1 = inl(pcr._ioaddr + 0x14);
+ pcr._base2 = inl(pcr._ioaddr + 0x18);
+ pcr._base3 = inl(pcr._ioaddr + 0x1C);
+ pcr._base4 = inl(pcr._ioaddr + 0x20);
+ pcr._base5 = inl(pcr._ioaddr + 0x24);
+ pcr._baserom = inl(pcr._ioaddr + 0x30);
+ pcr._max_min_ipin_iline = inl(pcr._ioaddr + 0x3C);
+ pcr._user_config = inl(pcr._ioaddr + 0x40);
+ outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
+
+ /* check for pci-pci bridges (currently we only know Digital) */
+ if ((pcr._vendor == 0x1011) && (pcr._device == 0x0001))
+ if (pcr._secondary_bus_number > 0)
+ pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number;
+
+ if (idx++ >= MAX_PCI_DEVICES)
+ continue;
+
+ identify_card(&pcr, verbose);
+ }
+ } while (++pcr._pcibusidx < pcr._pcinumbus);
+
+ outb(PCI_MODE2_ENABLE_REG, 0x00);
+ }
+
+#endif /* __alpha__ */
+
+ disable_os_io();
+}
+
+
+void
+identify_card(struct pci_config_reg *pcr, int verbose)
+{
+
+ int i = 0, j, foundit = 0;
+
+ while (pvd[i].vendorname != (char *)NULL) {
+ if (pvd[i].vendor_id == pcr->_vendor) {
+ j = 0;
+ printf(" %s ", pvd[i].vendorname);
+ while (pvd[i].device[j].devicename != (char *)NULL) {
+ if (pvd[i].device[j].device_id == pcr->_device) {
+ printf("%s", pvd[i].device[j].devicename);
+ foundit = 1;
+ break;
+ }
+ j++;
+ }
+ }
+ if (foundit)
+ break;
+ i++;
+ }
+
+ if (!foundit)
+ printf(" Device unknown\n");
+ else {
+ printf("\n");
+ if (verbose) {
+ if (pvd[i].device[j].print_func != (void (*)())NULL) {
+ pvd[i].device[j].print_func(pcr);
+ return;
+ }
+ }
+ }
+
+ if (verbose) {
+ if (pcr->_status_command)
+ printf(" STATUS 0x%04x COMMAND 0x%04x\n",
+ pcr->_status, pcr->_command);
+ if (pcr->_class_revision)
+ printf(" CLASS 0x%02x 0x%02x 0x%02x REVISION 0x%02x\n",
+ pcr->_base_class, pcr->_sub_class, pcr->_prog_if,
+ pcr->_rev_id);
+ if (pcr->_bist_header_latency_cache)
+ printf(" BIST 0x%02x HEADER 0x%02x LATENCY 0x%02x CACHE 0x%02x\n",
+ pcr->_bist, pcr->_header_type, pcr->_latency_timer,
+ pcr->_cache_line_size);
+ if (pcr->_base0)
+ printf(" BASE0 0x%08x addr 0x%08x %s\n",
+ pcr->_base0, pcr->_base0 & (pcr->_base0 & 0x1 ?
+ 0xFFFFFFFC : 0xFFFFFFF0),
+ pcr->_base0 & 0x1 ? "I/O" : "MEM");
+ if (pcr->_base1)
+ printf(" BASE1 0x%08x addr 0x%08x %s\n",
+ pcr->_base1, pcr->_base1 & (pcr->_base1 & 0x1 ?
+ 0xFFFFFFFC : 0xFFFFFFF0),
+ pcr->_base1 & 0x1 ? "I/O" : "MEM");
+ if (pcr->_base2)
+ printf(" BASE2 0x%08x addr 0x%08x %s\n",
+ pcr->_base2, pcr->_base2 & (pcr->_base2 & 0x1 ?
+ 0xFFFFFFFC : 0xFFFFFFF0),
+ pcr->_base2 & 0x1 ? "I/O" : "MEM");
+ if (pcr->_base3)
+ printf(" BASE3 0x%08x addr 0x%08x %s\n",
+ pcr->_base3, pcr->_base3 & (pcr->_base3 & 0x1 ?
+ 0xFFFFFFFC : 0xFFFFFFF0),
+ pcr->_base3 & 0x1 ? "I/O" : "MEM");
+ if (pcr->_base4)
+ printf(" BASE4 0x%08x addr 0x%08x %s\n",
+ pcr->_base4, pcr->_base4 & (pcr->_base4 & 0x1 ?
+ 0xFFFFFFFC : 0xFFFFFFF0),
+ pcr->_base4 & 0x1 ? "I/O" : "MEM");
+ if (pcr->_base5)
+ printf(" BASE5 0x%08x addr 0x%08x %s\n",
+ pcr->_base5, pcr->_base5 & (pcr->_base5 & 0x1 ?
+ 0xFFFFFFFC : 0xFFFFFFF0),
+ pcr->_base5 & 0x1 ? "I/O" : "MEM");
+ if (pcr->_baserom)
+ printf(" BASEROM 0x%08x addr 0x%08x %sdecode-enabled\n",
+ pcr->_baserom, pcr->_baserom & 0xFFFF8000,
+ pcr->_baserom & 0x1 ? "" : "not-");
+ if (pcr->_max_min_ipin_iline)
+ printf(" MAX_LAT 0x%02x MIN_GNT 0x%02x INT_PIN 0x%02x INT_LINE 0x%02x\n",
+ pcr->_max_lat, pcr->_min_gnt,
+ pcr->_int_pin, pcr->_int_line);
+ if (pcr->_user_config)
+ printf(" BYTE_0 0x%02x BYTE_1 0x%02x BYTE_2 0x%02x BYTE_3 0x%02x\n",
+ pcr->_user_config_0, pcr->_user_config_1,
+ pcr->_user_config_2, pcr->_user_config_3);
+ }
+}
+
+
+void
+print_mach64(struct pci_config_reg *pcr)
+{
+ unsigned long sparse_io = 0;
+
+ if (pcr->_status_command)
+ printf(" STATUS 0x%04x COMMAND 0x%04x\n",
+ pcr->_status, pcr->_command);
+ if (pcr->_class_revision)
+ printf(" CLASS 0x%02x 0x%02x 0x%02x REVISION 0x%02x\n",
+ pcr->_base_class, pcr->_sub_class, pcr->_prog_if, pcr->_rev_id);
+ if (pcr->_bist_header_latency_cache)
+ printf(" BIST 0x%02x HEADER 0x%02x LATENCY 0x%02x CACHE 0x%02x\n",
+ pcr->_bist, pcr->_header_type, pcr->_latency_timer,
+ pcr->_cache_line_size);
+ if (pcr->_base0)
+ printf(" APBASE 0x%08x addr 0x%08x\n",
+ pcr->_base0, pcr->_base0 & (pcr->_base0 & 0x1 ?
+ 0xFFFFFFFC : 0xFFFFFFF0));
+ if (pcr->_base1)
+ printf(" BLOCKIO 0x%08x addr 0x%08x\n",
+ pcr->_base1, pcr->_base1 & (pcr->_base1 & 0x1 ?
+ 0xFFFFFFFC : 0xFFFFFFF0));
+ if (pcr->_baserom)
+ printf(" BASEROM 0x%08x addr 0x%08x %sdecode-enabled\n",
+ pcr->_baserom, pcr->_baserom & 0xFFFF8000,
+ pcr->_baserom & 0x1 ? "" : "not-");
+ if (pcr->_max_min_ipin_iline)
+ printf(" MAX_LAT 0x%02x MIN_GNT 0x%02x INT_PIN 0x%02x INT_LINE 0x%02x\n",
+ pcr->_max_lat, pcr->_min_gnt, pcr->_int_pin, pcr->_int_line);
+ switch (pcr->_user_config_0 & 0x03) {
+ case 0:
+ sparse_io = 0x2ec;
+ break;
+ case 1:
+ sparse_io = 0x1cc;
+ break;
+ case 2:
+ sparse_io = 0x1c8;
+ break;
+ }
+ printf(" SPARSEIO 0x%03x %s %s\n",
+ sparse_io, pcr->_user_config_0 & 0x04 ? "Block IO enabled" :
+ "Sparse IO enabled",
+ pcr->_user_config_0 & 0x08 ? "Disable 0x46E8" : "Enable 0x46E8");
+}
+
+void
+print_i128(struct pci_config_reg *pcr)
+{
+ if (pcr->_status_command)
+ printf(" STATUS 0x%04x COMMAND 0x%04x\n",
+ pcr->_status, pcr->_command);
+ if (pcr->_class_revision)
+ printf(" CLASS 0x%02x 0x%02x 0x%02x REVISION 0x%02x\n",
+ pcr->_base_class, pcr->_sub_class, pcr->_prog_if, pcr->_rev_id);
+ if (pcr->_bist_header_latency_cache)
+ printf(" BIST 0x%02x HEADER 0x%02x LATENCY 0x%02x CACHE 0x%02x\n",
+ pcr->_bist, pcr->_header_type, pcr->_latency_timer,
+ pcr->_cache_line_size);
+ printf(" MW0_AD 0x%08x addr 0x%08x %spre-fetchable\n",
+ pcr->_base0, pcr->_base0 & 0xFFC00000,
+ pcr->_base0 & 0x8 ? "" : "not-");
+ printf(" MW1_AD 0x%08x addr 0x%08x %spre-fetchable\n",
+ pcr->_base1, pcr->_base1 & 0xFFC00000,
+ pcr->_base1 & 0x8 ? "" : "not-");
+ printf(" XYW_AD(A) 0x%08x addr 0x%08x\n",
+ pcr->_base2, pcr->_base2 & 0xFFC00000);
+ printf(" XYW_AD(B) 0x%08x addr 0x%08x\n",
+ pcr->_base3, pcr->_base3 & 0xFFC00000);
+ printf(" RBASE_G 0x%08x addr 0x%08x\n",
+ pcr->_base4, pcr->_base4 & 0xFFFF0000);
+ printf(" IO 0x%08x addr 0x%08x\n",
+ pcr->_base5, pcr->_base5 & 0xFFFFFF00);
+ printf(" RBASE_E 0x%08x addr 0x%08x %sdecode-enabled\n",
+ pcr->_baserom, pcr->_baserom & 0xFFFF8000,
+ pcr->_baserom & 0x1 ? "" : "not-");
+ if (pcr->_max_min_ipin_iline)
+ printf(" MAX_LAT 0x%02x MIN_GNT 0x%02x INT_PIN 0x%02x INT_LINE 0x%02x\n",
+ pcr->_max_lat, pcr->_min_gnt, pcr->_int_pin, pcr->_int_line);
+}
+
+void
+print_pcibridge(struct pci_config_reg *pcr)
+{
+ if (pcr->_status_command)
+ printf(" STATUS 0x%04x COMMAND 0x%04x\n",
+ pcr->_status, pcr->_command);
+ if (pcr->_class_revision)
+ printf(" CLASS 0x%02x 0x%02x 0x%02x REVISION 0x%02x\n",
+ pcr->_base_class, pcr->_sub_class, pcr->_prog_if, pcr->_rev_id);
+ if (pcr->_bist_header_latency_cache)
+ printf(" BIST 0x%02x HEADER 0x%02x LATENCY 0x%02x CACHE 0x%02x\n",
+ pcr->_bist, pcr->_header_type, pcr->_latency_timer,
+ pcr->_cache_line_size);
+ printf(" PRIBUS 0x%02x SECBUS 0x%02x SUBBUS 0x%02x SECLT 0x%02x\n",
+ pcr->_primary_bus_number, pcr->_secondary_bus_number,
+ pcr->_subordinate_bus_number, pcr->_secondary_latency_timer);
+ printf(" IOBASE: 0x%02x00 IOLIM 0x%02x00 SECSTATUS 0x%04x\n",
+ pcr->_io_base, pcr->_io_limit, pcr->_secondary_status);
+ printf(" NOPREFETCH MEMBASE: 0x%08x MEMLIM 0x%08x\n",
+ pcr->_mem_base, pcr->_mem_limit);
+ printf(" PREFETCH MEMBASE: 0x%08x MEMLIM 0x%08x\n",
+ pcr->_prefetch_mem_base, pcr->_prefetch_mem_limit);
+ printf(" RBASE_E 0x%08x addr 0x%08x %sdecode-enabled\n",
+ pcr->_baserom, pcr->_baserom & 0xFFFF8000,
+ pcr->_baserom & 0x1 ? "" : "not-");
+ if (pcr->_max_min_ipin_iline)
+ printf(" MAX_LAT 0x%02x MIN_GNT 0x%02x INT_PIN 0x%02x INT_LINE 0x%02x\n",
+ pcr->_max_lat, pcr->_min_gnt, pcr->_int_pin, pcr->_int_line);
+}
+
+static int io_fd;
+#ifdef __EMX__
+USHORT callgate[3] = {0,0,0};
+#endif
+
+void
+enable_os_io()
+{
+#if defined(SVR4) || defined(SCO) || defined(ISC)
+#if defined(SI86IOPL)
+ sysi86(SI86IOPL, 3);
+#else
+ sysi86(SI86V86, V86SC_IOPL, PS_IOPL);
+#endif
+#endif
+#if defined(linux)
+ iopl(3);
+#endif
+#if defined(__FreeBSD__) || defined(__386BSD__) || defined(__bsdi__)
+ if ((io_fd = open("/dev/console", O_RDWR, 0)) < 0) {
+ perror("/dev/console");
+ exit(1);
+ }
+#if defined(__FreeBSD__) || defined(__386BSD__)
+ if (ioctl(io_fd, KDENABIO, 0) < 0) {
+ perror("ioctl(KDENABIO)");
+ exit(1);
+ }
+#endif
+#if defined(__bsdi__)
+ if (ioctl(io_fd, PCCONENABIOPL, 0) < 0) {
+ perror("ioctl(PCCONENABIOPL)");
+ exit(1);
+ }
+#endif
+#endif
+#if defined(__NetBSD__)
+#if !defined(USE_I386_IOPL)
+ if ((io_fd = open("/dev/io", O_RDWR, 0)) < 0) {
+ perror("/dev/io");
+ exit(1);
+ }
+#else
+ if (i386_iopl(1) < 0) {
+ perror("i386_iopl");
+ exit(1);
+ }
+#endif /* USE_I386_IOPL */
+#endif /* __NetBSD__ */
+#if defined(__OpenBSD__)
+ if (i386_iopl(1) < 0) {
+ perror("i386_iopl");
+ exit(1);
+ }
+#endif /* __OpenBSD__ */
+#if defined(MACH386)
+ if ((io_fd = open("/dev/iopl", O_RDWR, 0)) < 0) {
+ perror("/dev/iopl");
+ exit(1);
+ }
+#endif
+#ifdef __EMX__
+ {
+ HFILE hfd;
+ ULONG dlen,action;
+ APIRET rc;
+ static char *ioDrvPath = "/dev/fastio$";
+
+ if (DosOpen((PSZ)ioDrvPath, (PHFILE)&hfd, (PULONG)&action,
+ (ULONG)0, FILE_SYSTEM, FILE_OPEN,
+ OPEN_SHARE_DENYNONE|OPEN_FLAGS_NOINHERIT|OPEN_ACCESS_READONLY,
+ (ULONG)0) != 0) {
+ fprintf(stderr,"Error opening fastio$ driver...\n");
+ fprintf(stderr,"Please install xf86sup.sys in config.sys!\n");
+ exit(42);
+ }
+ callgate[0] = callgate[1] = 0;
+
+/* Get callgate from driver for fast io to ports and other stuff */
+
+ rc = DosDevIOCtl(hfd, (ULONG)0x76, (ULONG)0x64,
+ NULL, 0, NULL,
+ (ULONG*)&callgate[2], sizeof(USHORT), &dlen);
+ if (rc) {
+ fprintf(stderr,"xf86-OS/2: EnableIOPorts failed, rc=%d, dlen=%d; emergency exit\n",
+ rc,dlen);
+ DosClose(hfd);
+ exit(42);
+ }
+
+/* Calling callgate with function 13 sets IOPL for the program */
+
+ asm volatile ("movl $13,%%ebx;.byte 0xff,0x1d;.long _callgate"
+ : /*no outputs */
+ : /*no inputs */
+ : "eax","ebx","ecx","edx","cc");
+
+ DosClose(hfd);
+ }
+#endif
+#if defined(Lynx) && defined(__powerpc__)
+ pciConfBase = (unsigned char *) smem_create("PCI-CONF",
+ (char *)0x80800000, 64*1024, SM_READ|SM_WRITE);
+ if (pciConfBase == (void *) -1)
+ exit(1);
+#endif
+}
+
+
+void
+disable_os_io()
+{
+#if defined(SVR4) || defined(SCO) || defined(ISC)
+#if defined(SI86IOPL)
+ sysi86(SI86IOPL, 0);
+#else
+ sysi86(SI86V86, V86SC_IOPL, 0);
+#endif
+#endif
+#if defined(linux)
+ iopl(0);
+#endif
+#if defined(__FreeBSD__) || defined(__386BSD__)
+ if (ioctl(io_fd, KDDISABIO, 0) < 0) {
+ perror("ioctl(KDDISABIO)");
+ close(io_fd);
+ exit(1);
+ }
+ close(io_fd);
+#endif
+#if defined(__NetBSD__)
+#if !defined(USE_I386_IOPL)
+ close(io_fd);
+#else
+ if (i386_iopl(0) < 0) {
+ perror("i386_iopl");
+ exit(1);
+ }
+#endif /* NetBSD1_1 */
+#endif /* __NetBSD__ */
+#if defined(__bsdi__)
+ if (ioctl(io_fd, PCCONDISABIOPL, 0) < 0) {
+ perror("ioctl(PCCONDISABIOPL)");
+ close(io_fd);
+ exit(1);
+ }
+ close(io_fd);
+#endif
+#if defined(MACH386)
+ close(io_fd);
+#endif
+#if defined(Lynx) && defined(__powerpc__)
+ smem_create(NULL, (char *) pciConfBase, 0, SM_DETACH);
+ smem_remove("PCI-CONF");
+ pciConfBase = NULL;
+#endif
+}
diff --git a/hw/xfree86/utils/xorgconfig/Cards b/hw/xfree86/utils/xorgconfig/Cards
new file mode 100644
index 000000000..0412fdd61
--- /dev/null
+++ b/hw/xfree86/utils/xorgconfig/Cards
@@ -0,0 +1,2003 @@
+# $Xorg: Cards,v 1.3 2000/08/17 19:53:04 cpqbld Exp $
+# This is the database of card definitions used by xf86config.
+# Each definition should have a NAME entry, CHIPSET (descriptive) and
+# SERVER (one of Mono, VGA16, SVGA, S3, 8514, Mach8, Mach32, Mach64, AGX,
+# P9000, W32, I128).
+# A reference to another definition is made with SEE (already defined
+# entries are not overridden).
+# Optional entries are RAMDAC (identifier), CLOCKCHIP (identifier),
+# DACSPEED, NOCLOCKPROBE (advises never to probe clocks), UNSUPPORTED
+# (indicates card that is not yet properly supported by a dedicated
+# server). A LINE entry adds a line of text to be included in the
+# Device section (can include options or comments).
+# There's no CLOCKS option (although a Clocks line can be included
+# with LINE), as it is very undesirable to have a Clocks line that
+# is incorrect. The idea is that the Clocks are probed for to be
+# sure (a commented suggested Clocks line can be included).
+#
+# The majority of entries are just a binding of a model name to a
+# chipset/server and untested.
+#
+# $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/Cards,v 3.51.2.15 1998/02/27 15:28:57 dawes Exp $
+
+#Chips & Technologies
+
+#untested
+NAME Chips & Technologies CT65520
+CHIPSET ct65520
+SERVER SVGA
+LINE # Device section for C&T cards.
+LINE # Option "suspend_hack"
+LINE # Option "STN"
+LINE # Option "no_stretch"
+LINE # Option "no_center"
+LINE # Option "use_modeline"
+LINE # Option "fix_panel_size"
+LINE # videoram 512
+
+NAME Chips & Technologies CT65525
+CHIPSET ct65525
+LINE # Option "nolinear"
+LINE # MemBase 0x03b00000
+SEE Chips & Technologies CT65520
+
+NAME Chips & Technologies CT65530
+CHIPSET ct65530
+SEE Chips & Technologies CT65525
+
+NAME Chips & Technologies CT65535
+CHIPSET ct65535
+NOCLOCKPROBE
+LINE # Option "hw_clocks"
+LINE # Textclockfreq 25.175
+SEE Chips & Technologies CT65530
+
+NAME Chips & Technologies CT65540
+CHIPSET ct65540
+NOCLOCKPROBE
+LINE # Option "use_18bit_bus"
+SEE Chips & Technologies CT65535
+
+NAME Chips & Technologies CT65545
+CHIPSET ct65545
+NOCLOCKPROBE
+LINE # Option "noaccel"
+LINE # Option "no_bitblt"
+LINE # Option "xaa_no_color_exp"
+LINE # Option "xaa_benchmark"
+LINE # Option "sw_cursor"
+LINE # Option "mmio"
+SEE Chips & Technologies CT65540
+
+NAME Chips & Technologies CT65546
+CHIPSET ct65546
+SEE Chips & Technologies CT65545
+
+NAME Chips & Technologies CT65548
+CHIPSET ct65548
+SEE Chips & Technologies CT65545
+
+NAME Chips & Technologies CT65550
+CHIPSET ct65550
+NOCLOCKPROBE
+LINE # Option "noaccel"
+LINE # Option "no_bitblt"
+LINE # Option "xaa_no_color_exp"
+LINE # Option "xaa_benchmark"
+LINE # Option "sw_cursor"
+LINE # Option "sync_on_green"
+LINE # Option "fast_dram"
+LINE # Option "use_vclk1"
+LINE # Textclockfreq 25.175
+SEE Chips & Technologies CT65530
+
+NAME Chips & Technologies CT65554
+CHIPSET ct65554
+SEE Chips & Technologies CT65550
+
+NAME Chips & Technologies CT65555
+CHIPSET ct65555
+SEE Chips & Technologies CT65550
+
+NAME Chips & Technologies CT68554
+CHIPSET ct68554
+SEE Chips & Technologies CT65550
+
+NAME Chips & Technologies CT64200
+CHIPSET ct64200
+SERVER SVGA
+LINE # Device section for C&T cards.
+LINE # videoram 1024
+
+NAME Chips & Technologies CT64300
+CHIPSET ct64300
+SERVER SVGA
+LINE # Option "noaccel"
+LINE # Option "no_bitblt"
+LINE # Option "xaa_no_color_exp"
+LINE # Option "xaa_benchmark"
+LINE # Option "sw_cursor"
+LINE # Option "nolinear"
+LINE # MemBase 0x03b00000
+LINE # Option "hw_clocks"
+LINE # Textclockfreq 25.175
+SEE Chips & Technologies CT64200
+
+# Cirrus Logic
+
+#tested
+NAME Cirrus Logic GD542x
+CHIPSET CL-GD5420/2/4/6/8/9
+SERVER SVGA
+NOCLOCKPROBE
+LINE # Device section for Cirrus Logic GD5420/2/4/6/8/9-based cards.
+LINE #MemBase 0x00e00000
+LINE #MemBase 0x04e00000
+LINE #Option "linear"
+
+#tested
+NAME Cirrus Logic GD543x
+CHIPSET CL-GD5430/5434
+SERVER SVGA
+NOCLOCKPROBE
+LINE # Device section for Cirrus Logic GD5430/34-based cards.
+LINE #MemBase 0x00e00000 # ISA card that maps to 14Mb
+LINE #MemBase 0x04000000 # VLB card that maps to 64Mb
+LINE #MemBase 0x80000000 # VLB card that maps to 2048Mb
+LINE #MemBase 0x02000000 # VLB card that maps to 32Mb
+LINE #Option "linear"
+
+NAME Cirrus Logic GD544x
+CHIPSET CL-GD544x
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Creative Labs Graphics Blaster MA201
+SEE Cirrus Logic GD544x
+
+NAME Creative Labs Graphics Blaster MA202
+SEE Cirrus Logic GD544x
+
+#tested
+NAME Cirrus Logic GD5462
+CHIPSET CL-GD5462
+SERVER SVGA
+NOCLOCKPROBE
+
+#tested
+NAME Cirrus Logic GD5464
+CHIPSET CL-GD5464
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Creative Labs Graphics Blaster MA302
+CHIPSET CL-GD5462
+SEE Cirrus Logic GD5462
+
+NAME Creative Labs Graphics Blaster MA334
+CHIPSET CL-GD5464
+SEE Cirrus Logic GD5464
+
+NAME Creative Labs Graphics Blaster 3D
+CHIPSET CL-GD5464
+SEE Cirrus Logic GD5464
+
+#tested
+NAME Diamond SpeedStar 64
+CHIPSET CL-GD5434
+SEE Cirrus Logic GD543x
+
+NAME Diamond SpeedStar64 Graphics 2000/2200
+CHIPSET CL-GD5434
+SEE Cirrus Logic GD543x
+
+NAME Diamond SpeedStar Pro SE (CL-GD5430/5434)
+SEE Cirrus Logic GD543x
+
+NAME Diamond SpeedStar Pro 1100
+SEE Cirrus Logic GD542x
+
+NAME Orchid Kelvin 64 VLB Rev A
+CHIPSET CL-GD5434
+SERVER SVGA
+NOCLOCKPROBE
+LINE # Device section for Orchid Kelvin 64 VLB Rev A
+LINE # Linear framebuffer maps at 2048Mb. Some motherboards make linear addressing
+LINE # impossible. Some cards map at 32Mb.
+LINE #MemBase 0x02000000 # VLB card that maps to 32Mb
+LINE #MemBase 0x04000000 # VLB card that maps to 64Mb
+LINE MemBase 0x80000000 # VLB card that maps to 2048Mb
+LINE #Option "linear"
+
+NAME Orchid Kelvin 64 VLB Rev B
+CHIPSET CL-GD5434
+SERVER SVGA
+NOCLOCKPROBE
+LINE # Device section for Orchid Kelvin 64 VLB Rev B
+LINE # Linear framebuffer maps at 32Mb. Some motherboards make linear addressing
+LINE # impossible. Some cards map at 2048Mb.
+LINE MemBase 0x02000000 # VLB card that maps to 32Mb
+LINE #MemBase 0x04000000 # VLB card that maps to 64Mb
+LINE #MemBase 0x80000000 # VLB card that maps to 2048Mb
+LINE #Option "linear"
+
+NAME Orchid Kelvin 64
+CHIPSET CL-GD5434
+SEE Cirrus Logic GD543x
+
+NAME Intel 5430
+CHIPSET CL-GD5430
+SEE Cirrus Logic GD543x
+
+NAME STB Nitro (64)
+CHIPSET CL-GD5434
+SEE Cirrus Logic GD543x
+
+NAME STB Nitro 64 Video
+CHIPSET CL-GD5446
+SEE Cirrus Logic GD544x
+
+NAME STB Horizon
+CHIPSET CL-GD5426/28
+SEE Cirrus Logic GD542x
+
+NAME STB Horizon Video
+CHIPSET CL-GD5440
+SEE Cirrus Logic GD544x
+
+NAME Genoa 8500VL(-28)
+CHIPSET CL-GD5426/28
+SEE Cirrus Logic GD542x
+
+NAME Diamond SpeedStar Pro (not SE)
+CHIPSET CL-GD5426/28
+SEE Cirrus Logic GD542x
+
+NAME ALG-5434(E)
+CHIPSET CL-GD5434
+SEE Cirrus Logic GD543x
+
+NAME Actix ProStar
+CHIPSET CL-GD5426/5428
+SEE Cirrus Logic GD542x
+
+NAME Actix ProStar 64
+CHIPSET CL-GD5434
+SEE Cirrus Logic GD543x
+
+#tested
+NAME Acumos AVGA3
+SEE Cirrus Logic GD542x
+
+NAME DFI-WG1000
+SEE Cirrus Logic GD542x
+
+NAME Spider VLB Plus
+CHIPSET CL-GD5428
+SEE Cirrus Logic GD542x
+
+NAME VI720
+CHIPSET CL-GD5434
+SEE Cirrus Logic GD543x
+
+NAME Cirrus Logic GD62xx (laptop)
+CHIPSET CL-GD6205/15/25/35
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Cirrus Logic GD64xx (laptop)
+CHIPSET CL-GD6420/6440
+SERVER SVGA
+
+NAME Cirrus Logic GD754x (laptop)
+CHIPSET CL-GD7541/42/43/48
+SERVER SVGA
+NOCLOCKPROBE
+
+# S3 801/805
+
+NAME S3 801/805 (generic)
+CHIPSET S3 801/805
+SERVER S3
+
+NAME S3 86C801 (generic)
+SEE S3 801/805 (generic)
+
+NAME S3 86C805 (generic)
+SEE S3 801/805 (generic)
+
+#tested
+NAME S3 801/805 with ATT20c490 RAMDAC
+CHIPSET S3 801/805
+SERVER S3
+RAMDAC att20c490
+LINE #Option "dac_8_bit" # Not supported by some 20c490 clones
+
+NAME S3 801/805 with SC1148{2,3,4} RAMDAC
+CHIPSET S3 801/805
+SERVER S3
+RAMDAC sc11482
+
+NAME S3 801/805 with SC1148{5,7,9} RAMDAC
+CHIPSET S3 801/805
+SERVER S3
+RAMDAC sc11485
+
+NAME S3 801/805 with S3 GenDAC
+CHIPSET S3 801/805
+SERVER S3
+RAMDAC s3gendac
+CLOCKCHIP s3gendac
+
+NAME S3 801/805 with ATT20c490 RAMDAC and ICD2061A
+CHIPSET S3 801/805
+SERVER S3
+RAMDAC att20c490
+CLOCKCHIP icd2061a
+LINE #Option "dac_8_bit" # Not supported by some 20c490 clones
+
+NAME S3 801/805 with Chrontel 8391
+CHIPSET S3 801/805
+SERVER S3
+RAMDAC att20c490
+CLOCKCHIP ch8391
+LINE Option "dac_8_bit"
+
+#tested
+NAME Actix GE32+ 2MB
+CHIPSET S3 801/805
+SERVER S3
+RAMDAC att20c490
+LINE #Option "dac_8_bit"
+
+NAME Actix GE32i
+CHIPSET S3 805i
+SERVER S3
+
+NAME Orchid Fahrenheit VA
+CHIPSET S3 801/805
+SERVER S3
+RAMDAC att20c490
+
+NAME Orchid Fahrenheit 1280
+CHIPSET S3 801
+SERVER S3
+LINE #Probable clocks:
+LINE #Clocks 25.20 28.32 32.50 0.00 40.00 44.90 50.40 65.00
+LINE #Clocks 78.00 56.70 63.10 75.10 80.00 89.90 100.90 31.50
+
+NAME Orchid Fahrenheit-1280+
+CHIPSET S3 801/805
+SERVER S3
+RAMDAC att20C490
+LINE Dacspeed 110
+LINE Option "dac_8_bit"
+LINE #Option "nolinear" # VLB card may require this
+LINE #Probable clocks:
+LINE #Clocks 25.20 28.32 40.0 0.0 50.10 77.0 36.10 45.0
+LINE #Clocks 130.0 120.20 80.0 31.50 110.30 65.0 75.0 94.60
+
+NAME Diamond Stealth 24
+CHIPSET S3 801/805
+SERVER S3
+CLOCKCHIP icd2061a
+LINE #Option "nolinear"
+LINE #Ramdac "att20c490" # The Diamond RAMDAC is reportedly compatible for 15bpp
+
+NAME Miro Crystal 8S
+SEE S3 801/805 (generic)
+
+NAME Miro Crystal 10SD with GenDAC
+SEE S3 801/805 with S3 GenDAC
+
+NAME Dell S3 805
+SEE S3 801/805 (generic)
+
+NAME STB Powergraph X-24
+SEE S3 801/805 with ATT20c490 RAMDAC and ICD2061A
+
+NAME JAX 8241
+SEE S3 801/805 with Chrontel 8391
+
+NAME VL-41
+SEE S3 801/805 with Chrontel 8391
+
+NAME SPEA Mirage
+SEE S3 801/805 with Chrontel 8391
+
+# S3 864/Trio64/Trio32/868
+
+NAME S3 864 (generic)
+CHIPSET S3 864
+SERVER S3
+
+NAME S3 86C864 (generic)
+SEE S3 864 (generic)
+
+NAME S3 Vision864 (generic)
+SEE S3 864 (generic)
+
+NAME S3 864 with SDAC (86C716)
+CHIPSET S3 864
+SERVER S3
+RAMDAC s3_sdac
+CLOCKCHIP s3_sdac
+NOCLOCKPROBE
+
+NAME S3 864 with ATT 20C498 or 21C498
+CHIPSET S3 864
+SERVER S3
+RAMDAC att20c498
+
+NAME S3 864 with STG1703
+CHIPSET S3 864
+SERVER S3
+RAMDAC stg1703
+NOCLOCKPROBE
+
+NAME S3 868 (generic)
+CHIPSET S3 868
+SERVER S3
+
+NAME S3 86C868 (generic)
+SEE S3 868 (generic)
+
+NAME S3 Vision868 (generic)
+SEE S3 868 (generic)
+
+NAME S3 868 with SDAC (86C716)
+CHIPSET S3 868
+SERVER S3
+NOCLOCKPROBE
+
+NAME S3 868 with ATT 20C498 or 21C498
+CHIPSET S3 868
+SERVER S3
+RAMDAC att20c498
+
+NAME S3 868 with ATT 20C409
+CHIPSET S3 868
+SERVER S3
+RAMDAC att20c409
+NOCLOCKPROBE
+
+NAME Number Nine FX Motion 531
+CLOCKCHIP icd2061a
+SEE S3 868 with ATT 20C498 or 21C498
+
+NAME S3 Trio64 (generic)
+CHIPSET S3 Trio64
+SERVER S3
+NOCLOCKPROBE
+
+NAME S3 86C764 (generic)
+SEE S3 Trio64 (generic)
+
+NAME S3 Trio64V+ (generic)
+CHIPSET S3 Trio64V+
+SERVER S3
+NOCLOCKPROBE
+
+NAME S3 86C765 (generic)
+SEE S3 Trio64V+ (generic)
+
+NAME S3 Trio32 (generic)
+CHIPSET S3 Trio32
+SERVER S3
+NOCLOCKPROBE
+
+NAME Genoa Phantom 64i with S3 SDAC
+DACSPEED 135
+SEE S3 864 with SDAC (86C716)
+
+NAME Number Nine GXE64
+CHIPSET S3 864
+SERVER S3
+CLOCKCHIP icd2061a
+LINE Option "number_nine"
+
+NAME Number Nine GXE64 with S3 Trio64
+SEE S3 Trio64 (generic)
+
+NAME Diamond Stealth 64 DRAM with S3 SDAC
+DACSPEED 135
+SEE S3 864 with SDAC (86C716)
+
+NAME Diamond Stealth64 Graphics 2xx0 series (864 + SDAC)
+DACSPEED 135
+SEE S3 864 with SDAC (86C716)
+
+NAME Diamond Stealth 64 DRAM with S3 Trio64
+SEE S3 Trio64 (generic)
+
+NAME Diamond Stealth64 Graphics 2xx0 series (Trio64)
+SEE S3 Trio64 (generic)
+
+NAME Diamond Stealth 64 DRAM SE
+SEE S3 Trio32 (generic)
+
+NAME Diamond Stealth64 Video 2001 series (2121/2201)
+SEE S3 Trio64V+ (generic)
+
+NAME Actix GE64
+CLOCKCHIP icd2061a
+SEE S3 864 (generic)
+
+NAME ELSA Winner 1000PRO with S3 SDAC
+SEE S3 864 with SDAC (86C716)
+
+NAME ELSA Winner 1000PRO with STG1700 or AT&T RAMDAC
+CHIPSET S3 864
+SERVER S3
+CLOCKCHIP icd2061a
+
+NAME ELSA Winner 1000PRO/X
+SEE S3 868 with SDAC (86C716)
+
+NAME ELSA Winner 1000ISA
+CHIPSET S3 805i
+SERVER S3
+CLOCKCHIP icd2061a
+LINE Option "dac_8_bit"
+LINE # the following settings should be detected and set automatically by XF86_S3
+LINE # if the serial number of the ELSA card is printed correctly:
+LINE #ClockChip "icd2061a"
+
+NAME Cardex Trio64
+SEE S3 Trio64 (generic)
+
+NAME Cardex Trio64Pro
+SEE S3 Trio64 (generic)
+
+NAME Miro Crystal 12SD
+SEE S3 Trio32 (generic)
+
+NAME Miro Crystal 22SD
+SEE S3 Trio64 (generic)
+
+NAME Miro Crystal 20SD with ICS2494 (BIOS 1.xx)
+SEE S3 864 with ATT 20C498 or 21C498
+
+NAME Miro Crystal 20SD with ICD2061A (BIOS 2.xx)
+CLOCKCHIP icd2061a
+SEE S3 864 with ATT 20C498 or 21C498
+
+NAME Miro Crystal 20SD VLB with S3 SDAC (BIOS 3.xx)
+SEE S3 864 with SDAC (86C716)
+
+NAME Miro Crystal 20SD PCI with S3 SDAC
+SEE S3 868 with SDAC (86C716)
+
+NAME ELSA Winner 1000AVI (SDAC version)
+SEE S3 868 with SDAC (86C716)
+
+NAME ELSA Winner 1000AVI (AT&T 20C409 version)
+SEE S3 868 with ATT 20C409
+
+NAME Diamond Stealth Video DRAM
+SEE S3 868 with SDAC (86C716)
+
+NAME Diamond Stealth64 Video 2120/2200
+SEE S3 868 with SDAC (86C716)
+
+NAME SPEA/V7 Mirage P64
+CLOCKCHIP ics2595
+SEE S3 864 (generic)
+
+NAME SPEA/V7 Mirage P64 with S3 Trio64
+SEE S3 Trio64 (generic)
+
+NAME Number Nine FX Vision 330
+SEE S3 Trio64 (generic)
+
+NAME Number Nine FX Motion 331
+SEE S3 Trio64V+ (generic)
+
+NAME ASUS Video Magic PCI V864
+SEE S3 864 (generic)
+
+NAME ASUS Video Magic PCI VT64
+SEE S3 Trio64 (generic)
+
+NAME VidTech FastMax P20
+SEE S3 864 (generic)
+
+NAME VideoLogic GrafixStar 500
+SEE S3 868 with SDAC (86C716)
+
+NAME VideoLogic GrafixStar 400
+SEE S3 Trio64V+ (generic)
+
+NAME VideoLogic GrafixStar 300
+SEE S3 Trio64 (generic)
+
+NAME 2 the Max MAXColor S3 Trio64V+
+SEE S3 Trio64V+ (generic)
+
+NAME DataExpert DSV3365
+SEE S3 Trio64V+ (generic)
+
+NAME ExpertColor DSV3365
+SEE S3 Trio64V+ (generic)
+
+NAME DSV3326
+SEE S3 Trio64V+ (generic)
+
+# S3 Trio64V2
+
+NAME S3 Trio64V2 (generic)
+CHIPSET S3 Trio64V2
+SERVER S3
+NOCLOCKPROBE
+
+NAME S3 Trio64V2/DX (generic)
+SEE S3 Trio64V2 (generic)
+
+NAME S3 Trio64V2/GX (generic)
+SEE S3 Trio64V2 (generic)
+
+NAME S3 86C775 (generic)
+SEE S3 Trio64V2/DX (generic)
+
+NAME S3 86C785 (generic)
+SEE S3 Trio64V2/GX (generic)
+
+NAME ELSA WINNER 1000/T2D
+SEE S3 Trio64V2/DX (generic)
+
+
+# S3 Aurora64V+
+
+NAME S3 Aurora64V+ (generic)
+CHIPSET S3 Aurora64V+
+SERVER S3
+NOCLOCKPROBE
+LINE # Option "lcd_center"
+LINE # Set_LCDClk <pixel_clock_for_LCD>
+
+NAME S3 86CM65
+SEE S3 Aurora64V+ (generic)
+
+NAME SHARP 9080
+SEE S3 Aurora64V+ (generic)
+
+NAME SHARP 9090
+SEE S3 Aurora64V+ (generic)
+
+NAME COMPAQ Armada 7730MT
+SEE S3 Aurora64V+ (generic)
+
+NAME COMPAQ Armada 7380DMT
+SEE S3 Aurora64V+ (generic)
+
+
+# S3 964/968
+
+NAME S3 964 (generic)
+CHIPSET S3 964
+SERVER S3
+NOCLOCKPROBE
+
+NAME S3 86C964 (generic)
+SEE S3 964 (generic)
+
+NAME S3 Vision964 (generic)
+SEE S3 964 (generic)
+
+NAME S3 968 (generic)
+CHIPSET S3 968
+SERVER S3
+NOCLOCKPROBE
+
+NAME S3 86C968 (generic)
+SEE S3 968 (generic)
+
+NAME S3 Vision968 (generic)
+SEE S3 968 (generic)
+
+NAME Number Nine GXE64 Pro
+CHIPSET S3 964
+SERVER S3
+RAMDAC ti3025
+LINE Option "number_nine"
+
+NAME Diamond Stealth 64 VRAM
+CLOCKCHIP icd2061a
+LINE #Option "slow_vram"
+SEE S3 964 (generic)
+
+NAME Diamond Stealth64 Video 3200
+CHIPSET S3 968
+LINE #Option "slow_vram"
+SEE S3 968 (generic)
+
+NAME Diamond Stealth 64 Video VRAM (TI RAMDAC)
+CHIPSET S3 968
+LINE #Option "slow_vram"
+LINE #DacSpeed 220
+SEE S3 968 (generic)
+
+NAME Diamond Stealth64 Video 3240/3400 (TI RAMDAC)
+CHIPSET S3 968
+LINE #Option "slow_vram"
+LINE #DacSpeed 220
+SEE S3 968 (generic)
+
+NAME Diamond Stealth64 Video 3240/3400 (IBM RAMDAC)
+CHIPSET S3 968
+LINE #Option "slow_vram"
+RAMDAC ibm_rgb526
+LINE DacSpeed 220
+SEE S3 968 (generic)
+
+NAME Genoa VideoBlitz III AV
+CHIPSET S3 968
+LINE #s3RefClk 50
+LINE #DACspeed 170
+SEE S3 968 (generic)
+
+NAME STB Velocity 64 Video
+CHIPSET S3 968
+LINE #s3RefClk 24
+LINE #DACspeed 220
+SEE S3 968 (generic)
+
+NAME STB Powergraph 64 Video
+SEE S3 Trio64V+ (generic)
+
+NAME STB Powergraph 64
+SEE S3 Trio64 (generic)
+
+NAME ELSA Winner 1000TRIO
+SEE S3 Trio64 (generic)
+
+NAME ELSA Winner 1000TRIO/V
+SEE S3 Trio64V+ (generic)
+
+NAME Hercules Graphite Terminator 64
+LINE Option "slow_vram"
+LINE #s3RefClk 50
+LINE #DACspeed 170
+SEE S3 964 (generic)
+
+NAME Hercules Terminator 64/Video
+SEE S3 Trio64V+ (generic)
+
+NAME Hercules Graphite Terminator 64/DRAM
+SEE S3 Trio64 (generic)
+
+NAME Hercules Graphite Terminator Pro 64
+LINE #s3RefClk 16
+LINE #DACspeed 220
+SEE S3 968 (generic)
+
+NAME Number Nine FX Motion 771
+LINE #s3RefClk 16
+SEE S3 968 (generic)
+
+NAME Spider Tarantula 64
+SEE S3 964 (generic)
+
+NAME Miro Crystal 20SV
+CHIPSET S3 964
+SERVER S3
+CLOCKCHIP icd2061a
+
+NAME Miro Crystal 40SV
+CHIPSET S3 964
+SERVER S3
+CLOCKCHIP ti3025
+
+NAME Miro Crystal 80SV
+CHIPSET S3 968
+SERVER S3
+NOCLOCKPROBE
+
+NAME Miro Video 20SV
+CHIPSET S3 968
+SERVER S3
+RAMDAC att20c505
+LINE #DacSpeed 150
+CLOCKCHIP ics9161a
+
+NAME SPEA Mercury 64
+CHIPSET S3 964
+SERVER S3
+CLOCKCHIP ics9161a
+LINE #Option "spea_mercury"
+
+NAME ELSA Winner 2000PRO-2
+CHIPSET S3 964
+SERVER S3
+LINE #Option "ELSA_w2000pro"
+NOCLOCKPROBE
+
+NAME ELSA Winner 2000PRO-4
+CHIPSET S3 964
+SERVER S3
+LINE #Option "ELSA_w2000pro"
+NOCLOCKPROBE
+
+NAME ELSA Winner 2000PRO/X-2
+CHIPSET S3 968
+SERVER S3
+LINE #Option "sync_on_green"
+NOCLOCKPROBE
+
+NAME ELSA Winner 2000PRO/X-4
+CHIPSET S3 968
+SERVER S3
+LINE #Option "sync_on_green"
+NOCLOCKPROBE
+
+NAME ELSA Winner 2000PRO/X-8
+CHIPSET S3 968
+SERVER S3
+LINE #Option "sync_on_green"
+NOCLOCKPROBE
+
+NAME ELSA Winner 2000AVI
+CHIPSET S3 968
+SERVER S3
+LINE #Option "sync_on_green"
+NOCLOCKPROBE
+
+NAME ELSA Gloria-4
+CHIPSET S3 968
+SERVER S3
+LINE #Option "sync_on_green"
+NOCLOCKPROBE
+
+NAME ELSA Gloria-8
+CHIPSET S3 968
+SERVER S3
+LINE #Option "sync_on_green"
+NOCLOCKPROBE
+
+NAME VideoLogic GrafixStar 700
+CHIPSET S3 968
+SERVER S3
+NOCLOCKPROBE
+
+NAME LeadTek WinFast S430
+CHIPSET S3 968
+SERVER S3
+NOCLOCKPROBE
+
+NAME WinFast S430
+SEE LeadTek WinFast S430
+
+NAME LeadTek WinFast S510
+CHIPSET S3 968
+SERVER S3
+NOCLOCKPROBE
+
+NAME WinFast S510
+SEE LeadTek WinFast S510
+
+# S3 928
+
+NAME S3 928 (generic)
+CHIPSET S3 928
+SERVER S3
+
+NAME S3 86C928 (generic)
+SEE S3 928 (generic)
+
+NAME Actix Ultra
+CHIPSET S3 928
+SERVER S3
+RAMDAC att20c490
+LINE #Option "dac_8_bit"
+
+NAME Diamond Stealth Pro
+CHIPSET S3 928
+SERVER S3
+CLOCKCHIP icd2061a
+LINE #Ramdac "att20c490" # The Diamond RAMDAC is reportedly compatible for 15bpp
+LINE #Option "no_linear" # Some VLB machines may require this
+
+NAME ELSA Winner 1000VL
+CHIPSET S3 928
+SERVER S3
+LINE # the following settings should be detected and set automatically by XF86_S3
+LINE # if the serial number of the ELSA card is printed correctly:
+LINE #ClockChip "icd2061a"
+LINE #Membase 0xf8000000
+
+NAME ELSA Winner 1000TwinBus
+SEE ELSA Winner 1000VL
+
+NAME ELSA Winner 2000
+SEE S3 928 (generic)
+
+NAME Miro Crystal 16S
+SEE S3 928 (generic)
+
+NAME SPEA/V7 Mercury
+CHIPSET S3 928
+SERVER S3
+CLOCKCHIP sc11412
+LINE Option "spea_mercury"
+
+NAME STB Pegasus
+CHIPSET S3 928
+SERVER S3
+RAMDAC bt485
+CLOCKCHIP icd2061a
+LINE Option "stb_pegasus"
+LINE #Option "sync_on_green"
+
+NAME Number Nine GXE Level 14/16
+CHIPSET S3 928
+SERVER S3
+DACSPEED 200
+CLOCKCHIP icd2061a
+LINE Option "number_nine"
+LINE #Option "nolinear"
+LINE #Option "nomemaccess"
+
+NAME Number Nine GXE Level 10/11/12
+CHIPSET S3 928
+SERVER S3
+CLOCKCHIP icd2061a
+LINE Option "number_nine"
+
+NAME 928Movie
+CHIPSET S3 928
+SERVER S3
+CLOCKCHIP icd2595
+RAMDAC bt485
+LINE # pixel multiplexing not supported
+
+# S3 911/924
+
+NAME S3 911/924 (generic)
+CHIPSET S3 911/924
+SERVER S3
+
+NAME S3 86C911 (generic)
+SEE S3 911/924 (generic)
+
+NAME S3 86C924 (generic)
+SEE S3 911/924 (generic)
+
+NAME Diamond Stealth VRAM
+CHIPSET S3 911/924
+SERVER S3
+CLOCKCHIP icd2061a
+
+#NAME Orchid Fahrenheit 1280
+#SEE S3 911/924 (generic)
+
+NAME S3 924 with SC1148 DAC
+CHIPSET S3 924
+SERVER S3
+LINE #Probable clocks:
+LINE #Clocks 25.2 28.3 39.7 1.7 49.9 76.7 35.7 44
+LINE #Clocks 130.2 119.5 79.4 31.2 110.0 65.2 74.9 71.3
+
+# S3 ViRGE,/DX,/GX and ViRGE/VX
+
+NAME S3 ViRGE (old S3V server)
+CHIPSET S3 ViRGE
+SERVER S3V
+NOCLOCKPROBE
+
+NAME S3 ViRGE (generic)
+CHIPSET S3 ViRGE
+SERVER SVGA
+NOCLOCKPROBE
+LINE #Option "xaa_benchmark"
+LINE #Option "fifo_moderate"
+LINE #Option "pci_burst_on"
+LINE #Option "pci_retry"
+
+NAME S3 ViRGE/DX (generic)
+CHIPSET S3 ViRGE/DX
+SERVER SVGA
+NOCLOCKPROBE
+LINE #Option "xaa_benchmark"
+LINE #Option "fifo_moderate"
+LINE #Option "pci_burst_on"
+LINE #Option "pci_retry"
+
+NAME S3 ViRGE/GX (generic)
+CHIPSET S3 ViRGE/GX
+SERVER SVGA
+NOCLOCKPROBE
+LINE #Option "xaa_benchmark"
+LINE #Option "fifo_moderate"
+LINE #Option "pci_burst_on"
+LINE #Option "pci_retry"
+
+
+NAME S3 ViRGE/GX2 (generic)
+CHIPSET S3 ViRGE/GX2
+SERVER SVGA
+NOCLOCKPROBE
+LINE #Option "xaa_benchmark"
+LINE #Option "fifo_moderate"
+LINE #Option "pci_burst_on"
+LINE #Option "pci_retry"
+
+NAME S3 ViRGE/MX (generic)
+CHIPSET S3 ViRGE/MX
+SERVER SVGA
+NOCLOCKPROBE
+LINE #Option "lcd_center"
+LINE #Set_LCDClk <pixel_clock_for_LCD>
+LINE #Option "xaa_benchmark"
+LINE #Option "fifo_moderate"
+LINE #Option "pci_burst_on"
+LINE #Option "pci_retry"
+
+
+
+
+NAME S3 86C325 (generic)
+SEE S3 ViRGE (generic)
+
+NAME S3 86C375 (generic)
+SEE S3 ViRGE/DX (generic)
+
+NAME S3 86C385 (generic)
+SEE S3 ViRGE/GX (generic)
+
+NAME S3 86C357 (generic)
+SEE S3 ViRGE/GX2 (generic)
+
+NAME S3 86C260 (generic)
+SEE S3 ViRGE/MX (generic)
+
+
+NAME ELSA Victory 3D
+SEE S3 ViRGE (generic)
+
+NAME ELSA Victory 3DX
+SEE S3 ViRGE/DX (generic)
+
+NAME ELSA Winner 3000-S
+SEE S3 ViRGE (generic)
+
+NAME Number Nine Visual 9FX Reality 332
+SEE S3 ViRGE (generic)
+
+NAME Number Nine FX Motion 332
+SEE S3 ViRGE (generic)
+
+NAME Diamond Stealth 3D 2000
+SEE S3 ViRGE (generic)
+
+NAME Diamond Stealth 3D 2000 PRO
+SEE S3 ViRGE/DX (generic)
+
+NAME Diamond Multimedia Stealth 3D 2000
+SEE S3 ViRGE (generic)
+
+NAME Diamond Multimedia Stealth 3D 2000 PRO
+SEE S3 ViRGE/DX (generic)
+
+NAME Canopus Co. Power Window 3DV
+SEE S3 ViRGE (generic)
+
+NAME DataExpert DSV3325
+SEE S3 ViRGE (generic)
+
+NAME ExpertColor DSV3325
+SEE S3 ViRGE (generic)
+
+NAME DSV3325
+SEE S3 ViRGE (generic)
+
+NAME Hercules Terminator 64/3D
+SEE S3 ViRGE (generic)
+
+NAME Hercules Terminator 3D/DX
+SEE S3 ViRGE/DX (generic)
+
+NAME LeadTek WinFast 3D S600
+SEE S3 ViRGE (generic)
+
+NAME WinFast 3D S600
+SEE LeadTek WinFast 3D S600
+
+NAME LeadTek WinFast 3D S680
+SEE S3 ViRGE/GX2 (generic)
+
+NAME WinFast 3D S600
+SEE LeadTek WinFast 3D S680
+
+NAME miro miroMedia 3D
+SEE S3 ViRGE (generic)
+
+NAME Orchid Technology Fahrenheit Video 3D
+SEE S3 ViRGE (generic)
+
+NAME STB Systems Powergraph 3D
+SEE S3 ViRGE (generic)
+
+NAME STB Nitro 3D
+CHIPSET S3 ViRGE/GX
+SEE S3 ViRGE/GX (generic)
+
+NAME MELCO WGP-VG4S
+LINE #DACSpeed 191 162 111 83
+LINE #SetMClck 75
+SEE S3 ViRGE (generic)
+
+
+
+NAME S3 ViRGE/VX (generic)
+CHIPSET S3 ViRGE/VX
+SERVER SVGA
+NOCLOCKPROBE
+LINE #Option "xaa_benchmark"
+LINE #Option "fifo_moderate"
+LINE #Option "pci_burst_on"
+LINE #Option "pci_retry"
+
+
+NAME S3 86C988 (generic)
+SEE S3 ViRGE/VX (generic)
+
+NAME ELSA Winner 3000
+SEE S3 ViRGE/VX (generic)
+
+NAME ELSA Winner 3000-M-22
+SEE S3 ViRGE/VX (generic)
+
+NAME ELSA Winner 3000-L-42
+SEE S3 ViRGE/VX (generic)
+
+NAME ELSA Winner 2000AVI/3D
+SEE S3 ViRGE/VX (generic)
+
+NAME Diamond Stealth 3D 3000
+SEE S3 ViRGE/VX (generic)
+
+NAME STB Systems Velocity 3D
+SEE S3 ViRGE/VX (generic)
+
+NAME MELCO WGP-VX8
+SEE S3 ViRGE/VX (generic)
+
+
+NAME Toshiba Tecra 750CDT
+SEE S3 ViRGE/MX (generic)
+
+NAME Toshiba Tecra 750DVD
+SEE S3 ViRGE/MX (generic)
+
+NAME Toshiba Tecra 540CDT
+SEE S3 ViRGE/MX (generic)
+
+NAME Toshiba Tecra 550CDT
+SEE S3 ViRGE/MX (generic)
+
+
+
+
+
+# ET4000/ET6000
+
+NAME ET3000 (generic)
+CHIPSET ET3000
+SERVER SVGA
+
+NAME Genoa 5400
+SEE ET3000 (generic)
+
+NAME ET4000 (generic)
+CHIPSET ET4000
+SERVER SVGA
+
+NAME ET4000/W32 (generic)
+CHIPSET ET4000/W32
+SERVER W32
+
+NAME ET4000 W32i, W32p (generic)
+CHIPSET ET4000/W32(i/p)
+SERVER SVGA
+LINE #Option "linear" # for linear mode at 8bpp
+LINE #Option "noaccel" # when problems with accelerator
+LINE #Option "power_saver" # enable VESA DPMS
+LINE #Option "fast_dram"
+LINE #Option "pci_retry" # faster, but problematic for ISA DMA
+LINE #Option "hibit_high" # see README.tseng -- most cards need this
+LINE #Option "hibit_low" # see README.tseng -- mostly for older ET4000 cards
+LINE #MemBase 0x3C00000 # when automatic MemBase detection doesn't work
+LINE # -- see README.tseng for more (important) information on MemBase
+
+NAME ET6000 (generic)
+CHIPSET ET6000
+SERVER SVGA
+NOCLOCKPROBE
+LINE #videoram 2304 # 2.25 MB, when memory probe is incorrect
+LINE #Option "linear" # for linear mode at 8bpp
+LINE #Option "noaccel" # when problems with accelerator
+LINE #Option "power_saver" # enable VESA DPMS
+LINE #Option "pci_retry" # faster, but problematic for ISA DMA
+LINE #Option "hw_cursor" # Use hardware cursor (see docs for limitations)
+LINE #Option "xaa_no_color_exp" # When text (or bitmap) is not rendered correctly
+
+NAME ET6100 (generic)
+CHIPSET ET6100
+SERVER XSuSE_Tseng
+NOCLOCKPROBE
+
+NAME Diamond Stealth 32
+CLOCKCHIP icd2061a
+NOCLOCKPROBE
+SEE ET4000 W32i, W32p (generic)
+
+NAME Cardex Cobra
+SEE ET4000 W32i, W32p (generic)
+
+NAME Cardex Challenger (Pro)
+SEE ET4000 W32i, W32p (generic)
+
+NAME Colorgraphic Dual Lightning
+SEE ET4000 W32i, W32p (generic)
+
+NAME Dell onboard ET4000
+SEE ET4000 (generic)
+
+NAME DFI-WG5000
+SEE ET4000 W32i, W32p (generic)
+
+NAME Diamond SpeedStar (Plus)
+SEE ET4000 (generic)
+
+NAME Diamond SpeedStar 24
+SEE ET4000 (generic)
+
+NAME Diamond SpeedStar HiColor
+SEE ET4000 (generic)
+
+NAME Genoa 8900 Phantom 32i
+SEE ET4000 W32i, W32p (generic)
+
+NAME Hercules Dynamite
+SEE ET4000/W32 (generic)
+
+NAME Hercules Dynamite Power
+SEE ET4000 W32i, W32p (generic)
+
+NAME Hercules Dynamite Pro
+SEE ET4000 W32i, W32p (generic)
+
+NAME Integral FlashPoint
+SEE ET4000 W32i, W32p (generic)
+
+NAME LeadTek WinFast S200
+SEE ET4000 W32i, W32p (generic)
+
+NAME Matrox Comet
+SEE ET4000 W32i, W32p (generic)
+
+NAME Matrox Marvel II
+SEE ET4000 W32i, W32p (generic)
+
+NAME Miro MiroVideo 20TD
+SEE ET4000 W32i, W32p (generic)
+
+NAME WinFast S200
+SEE LeadTek WinFast S200
+
+NAME Sigma Concorde
+SEE ET4000/W32 (generic)
+
+NAME Sigma Legend
+SEE ET4000 (generic)
+
+NAME SPEA/V7 ShowTime Plus
+SEE ET4000 W32i, W32p (generic)
+
+NAME STB LightSpeed
+SEE ET4000 W32i, W32p (generic)
+
+NAME STB MVP-2
+SEE ET4000 (generic)
+
+NAME STB MVP-2 PCI
+SEE ET4000 W32i, W32p (generic)
+
+NAME STB MVP-2X
+SEE ET4000 W32i, W32p (generic)
+
+NAME STB MVP-4 PCI
+SEE ET4000 W32i, W32p (generic)
+
+NAME STB MVP-4X
+SEE ET4000 W32i, W32p (generic)
+
+NAME TechWorks Thunderbolt
+SEE ET4000/W32 (generic)
+
+NAME ViewTop PCI
+SEE ET4000 W32i, W32p (generic)
+
+NAME SNI PC5H W32
+CLOCKCHIP stg1703
+NOCLOCKPROBE
+SEE ET4000 W32i, W32p (generic)
+
+NAME SNI Scenic W32
+CLOCKCHIP stg1703
+NOCLOCKPROBE
+SEE ET4000 W32i, W32p (generic)
+
+NAME Hercules Dynamite 128/Video
+SEE ET6000 (generic)
+
+NAME STB LightSpeed 128
+SEE ET6000 (generic)
+
+NAME VideoLogic GrafixStar 600
+SEE ET6000 (generic)
+
+NAME Jazz Multimedia G-Force 128
+SEE ET6000 (generic)
+
+NAME Mirage Z-128
+SEE ET6000 (generic)
+
+NAME California Graphics SunTracer 6000
+SEE ET6000 (generic)
+
+NAME Binar Graphics AnyView
+SEE ET6000 (generic)
+
+NAME MediaVision Proaxcel 128
+SEE ET6000 (generic)
+
+NAME ATrend ATC-2165A
+SEE ET6000 (generic)
+
+NAME Interay PMC Viper
+SEE ET6000 (generic)
+
+2-the-Max MAXColor 6000
+SEE ET6000 (generic)
+
+Gainward Challenger EV
+SEE ET6000 (generic)
+
+MachSpeed VGA ET6000
+SEE ET6000 (generic)
+
+KouTech KeyVision 128 EV
+SEE ET6000 (generic)
+
+
+# ATI
+
+NAME ATI 8514 Ultra (no VGA)
+CHIPSET ATI-Mach8
+SERVER Mach8
+
+NAME ATI Graphics Ultra
+CHIPSET ATI-Mach8
+SERVER Mach8
+LINE #Probable clocks:
+LINE #Clocks 43 49 80 36 50 56 0 45 30 32 110 79 40 45 75 65
+LINE #Clocks 22 25 46 18 25 28 0 22 15 16 55 40 20 22 38 32
+
+NAME ATI Graphics Ultra Pro
+CHIPSET ATI-Mach32
+SERVER Mach32
+LINE #Probable clocks:
+LINE #Clocks 100 126 92 36 51 57 0 44 135 32 110 80 39
+LINE #Clocks 45 75 65 50 63 46 18 25 28 0 22 67 16 55 40 19 23 37 33
+LINE #Option "dac_8_bit"
+
+NAME ATI Wonder SVGA
+CHIPSET ATI vgawonder
+SERVER SVGA
+LINE #probable clocks:
+LINE #Clocks 30 32 11 80 42 48 92 36 40 45 75 65 50 56 0 0
+LINE #Clocks 15 16 55 0 21 24 46 18 20 22 37 32 25 28 0 0
+
+NAME ATI Ultra Plus
+CHIPSET ATI-Mach32
+SERVER Mach32
+
+NAME ATI Mach32
+CHIPSET ATI-Mach32
+SERVER Mach32
+
+NAME ATI Mach64
+CHIPSET ATI-Mach64
+SERVER Mach64
+NOCLOCKPROBE
+
+NAME ATI Mach64 with AT&T 20C408 RAMDAC
+CHIPSET ATI-Mach64
+SERVER Mach64
+LINE #Ramdac "att20c408"
+NOCLOCKPROBE
+
+NAME ATI Mach64 with CH8398 RAMDAC
+CHIPSET ATI-Mach64
+SERVER Mach64
+LINE #Ramdac "ch8398"
+NOCLOCKPROBE
+
+NAME ATI Mach64 with IBM RGB514 RAMDAC
+CHIPSET ATI-Mach64
+SERVER Mach64
+LINE #Ramdac "ibm_rgb514"
+NOCLOCKPROBE
+
+NAME ATI Mach64 CT (264CT), Internal RAMDAC
+CHIPSET ATI-Mach64
+SERVER Mach64
+NOCLOCKPROBE
+
+NAME ATI Mach64 VT (264VT), Internal RAMDAC
+CHIPSET ATI-Mach64
+SERVER Mach64
+NOCLOCKPROBE
+
+NAME ATI Mach64 GT (264GT), aka 3D RAGE, Internal RAMDAC
+CHIPSET ATI-Mach64
+SERVER Mach64
+NOCLOCKPROBE
+
+NAME ATI Mach64 3D RAGE II, Internal RAMDAC
+CHIPSET ATI-Mach64
+SERVER Mach64
+NOCLOCKPROBE
+
+NAME ATI Mach64 3D RAGE II+, Internal RAMDAC
+CHIPSET ATI-Mach64
+SERVER Mach64
+NOCLOCKPROBE
+
+NAME ATI Xpert@Play PCI and AGP, 3D Rage Pro
+CHIPSET ATI-Mach64
+SERVER Mach64
+NOCLOCKPROBE
+
+NAME ATI Xpert@Work, 3D Rage Pro
+CHIPSET ATI-Mach64
+SERVER Mach64
+NOCLOCKPROBE
+
+NAME ATI Pro Turbo+PC2TV, 3D Rage II+DVD
+CHIPSET ATI-Mach64
+SERVER Mach64
+NOCLOCKPROBE
+
+NAME ATI Graphics Xpression with STG1702 RAMDAC
+SEE ATI Mach64
+
+NAME ATI Graphics Xpression with 68875 RAMDAC
+SEE ATI Mach64
+
+NAME ATI Graphics Xpression with CH8398 RAMDAC
+SEE ATI Mach64 with CH8398 RAMDAC
+
+NAME ATI Graphics Xpression with AT&T 20C408 RAMDAC
+SEE ATI Mach64 with AT&T 20C408 RAMDAC
+
+NAME ATI Graphics Xpression with Mach64 CT (264CT)
+SEE ATI Mach64 CT (264CT), Internal RAMDAC
+
+NAME ATI Video Xpression
+SEE ATI Mach64 VT (264VT), Internal RAMDAC
+
+NAME ATI 3D Xpression
+SEE ATI Mach64 GT (264GT), aka 3D RAGE, Internal RAMDAC
+
+NAME ATI 3D Xpression+ PC2TV
+SEE ATI Mach64 3D RAGE II, Internal RAMDAC
+
+NAME ATI 3D Pro Turbo
+SEE ATI Mach64 3D RAGE II, Internal RAMDAC
+
+NAME ATI All-in-Wonder
+SEE ATI Mach64 3D RAGE II+, Internal RAMDAC
+
+NAME ATI Win Boost with STG1702 RAMDAC
+SEE ATI Mach64
+
+NAME ATI Win Boost with CH8398 RAMDAC
+SEE ATI Mach64 with CH8398 RAMDAC
+
+NAME ATI Win Boost with AT&T 20C408 RAMDAC
+SEE ATI Mach64 with AT&T 20C408 RAMDAC
+
+NAME ATI Win Boost with Mach64 CT (264CT)
+SEE ATI Mach64 CT (264CT), Internal RAMDAC
+
+NAME ATI Graphics Pro Turbo
+SEE ATI Mach64
+
+NAME ATI Graphics Pro Turbo 1600
+SEE ATI Mach64 with IBM RGB514 RAMDAC
+
+NAME ATI Win Turbo
+SEE ATI Mach64
+
+NAME ASUS PCI-V264CT
+SEE ATI Mach64 CT (264CT), Internal RAMDAC
+
+NAME ASUS PCI-AV264CT
+SEE ATI Mach64 CT (264CT), Internal RAMDAC
+
+# AGX
+
+NAME AGX (generic)
+CHIPSET AGX-014/15/16
+SERVER AGX
+
+NAME Boca Vortex (Sierra RAMDAC)
+CHIPSET AGX-015
+SERVER AGX
+RAMDAC sc15025
+LINE Option "dac_8_bit"
+LINE Option "no_wait_state"
+LINE #Option "fifo_moderate" # 2x bus bw - may result in random pixels
+
+NAME EIZO (VRAM)
+SEE AGX (generic)
+
+NAME Orchid Celsius (AT&T RAMDAC)
+CHIPSET AGX-015
+SERVER AGX
+RAMDAC att20c490
+LINE Option "dac_8_bit"
+LINE Option "no_wait_state"
+LINE #Option "fifo_moderate" # 2x bus bw - may result in random pixels
+
+NAME Orchid Celsius (Sierra RAMDAC)
+CHIPSET AGX-015
+SERVER AGX
+RAMDAC sc15025
+LINE Option "dac_8_bit"
+LINE Option "no_wait_state"
+LINE #Option "fifo_moderate" # 2x bus bw - may result in random pixels
+
+
+NAME Spider Black Widow
+CHIPSET AGX-015
+SERVER AGX
+RAMDAC sc15025
+LINE Option "dac_8_bit"
+LINE Option "no_wait_state"
+LINE #Option "fifo_moderate" # 2x bus bw - may result in random pixels
+
+
+NAME Spider Black Widow Plus
+CHIPSET AGX-016
+SERVER AGX
+RAMDAC sc15025
+LINE Option "dac_8_bit"
+LINE Option "no_wait_state"
+LINE #Option "fifo_moderate" # 2x bus bw - may result in random pixels
+LINE #Option "fifo_aggressive" # 3x bus bw - may result in random pixels
+LINE #Probable clocks:
+LINE #Clocks 25.2 28.3 39.9 72.2 50.0 76.9 36.1 44.8
+LINE #Clocks 89.0 119.8 79.9 31.5 110.0 64.9 74.9 94.9
+
+NAME Hercules Graphite HG210
+CHIPSET AGX-014
+SERVER AGX
+RAMDAC bt482
+DACSPEED 85
+LINE Chipset "AGX-014"
+LINE Option "dac_8_bit"
+LINE Option "no_wait_state"
+LINE #Probable clocks:
+LINE #Clocks 25.0 28.0 32.0 36.0 40.0 45.0 50.0 65.0
+LINE #Clocks 70.0 75.0 80.0 85.0 90.0 95.0 100.0 110.0
+
+NAME Hercules Graphite Pro
+CHIPSET AGX-015
+SERVER AGX
+# Card specific DAC, doesn't appear in ramdac menu
+LINE Ramdac "herc_dual_dac"
+LINE Chipset "AGX-015"
+LINE Option "dac_8_bit"
+LINE Option "no_wait_state"
+LINE #Option "fifo_moderate" # 2x bus bw - may result in random pixels
+LINE #Probable clocks:
+LINE #Clocks 25.0 28.0 32.0 36.0 40.0 45.0 50.0 65.0
+LINE #Clocks 70.0 75.0 80.0 85.0 90.0 95.0 100.0 110.0
+
+NAME Hercules Graphite Power
+CHIPSET AGX-016
+SERVER AGX
+# Card specific DAC, doesn't appear in ramdac menu
+# The glue logic state machine for RAMDAC switching doesn't work as
+# documented, for now we're stuck with the small RAMDAC
+LINE Ramdac "herc_small_dac"
+LINE Chipset "AGX-016"
+LINE Option "dac_8_bit"
+LINE Option "no_wait_state"
+LINE #Option "fifo_moderate" # 2x bus bw - may result in random pixels
+LINE #Option "fifo_aggressive" # 3x bus bw - may result in random pixels
+LINE #Probable clocks:
+LINE #Clocks 25.0 28.0 32.0 36.0 40.0 45.0 50.0 65.0
+LINE #Clocks 70.0 75.0 80.0 85.0 90.0 95.0 100.0 110.0
+
+NAME XGA-2 (ISA bus)
+CHIPSET XGA-2
+SERVER AGX
+NOCLOCKPROBE
+LINE #Instance 7 # XGA instance 0-7
+LINE #COPbase 0xC8F00 # XGA memory-mapped register address
+LINE #POSbase 0 # Disable probing if above are specified
+
+NAME XGA-1 (ISA bus)
+CHIPSET XGA-1
+SERVER AGX
+LINE #Instance 7 # XGA instance 0-7
+LINE #COPbase 0xC8F00 # XGA memory-mapped register address
+LINE #POSbase 0 # Disable probing if above are specified
+
+# WD
+
+NAME Paradise/WD 90CXX
+CHIPSET WD90CXX
+SERVER SVGA
+
+NAME DFI-WG6000
+CHIPSET WD90C33
+SERVER SVGA
+
+NAME Diamond SpeedStar 24X (not fully supported)
+CHIPSET WD90C31
+SERVER SVGA
+
+NAME WD 90C24 (laptop)
+CHIPSET WD90C24
+SERVER SVGA
+LINE #Chipset "wd90c24"
+LINE #Option "noaccel" # Use this if acceleration is causing problems
+LINE #Clocks 25.175 28.322 65 36 # These are not programmable
+LINE #Clocks 29.979 77.408 62.195 59.957 # These are programmable
+LINE #Clocks 31.5 35.501 75.166 50.114 # These are not programmable
+LINE #Clocks 39.822 72.038 44.744 80.092 # These are programmable
+LINE #Clocks 44.297 # Must match Mclk
+
+
+NAME WD 90C24A or 90C24A2 (laptop)
+CHIPSET WD90C24A
+SERVER SVGA
+LINE #Chipset "wd90c24"
+LINE #Clocks 25.175 28.322 65 36 # These are not programmable
+LINE #Clocks 29.979 77.408 62.195 59.957 # These are programmable
+LINE #Clocks 31.5 35.501 75.166 50.114 # These are not programmable
+LINE #Clocks 39.822 72.038 44.744 80.092 # These are programmable
+LINE #Clocks 44.297 # Must match Mclk
+
+# Avance Logic
+
+NAME Avance Logic 2101
+CHIPSET Avance Logic
+LINE #chipset "al2101"
+SERVER SVGA
+
+NAME Avance Logic 2228
+CHIPSET Avance Logic
+LINE #chipset "ali2228"
+SERVER SVGA
+
+NAME Avance Logic 2301
+CHIPSET Avance Logic
+LINE #chipset "ali2301"
+SERVER SVGA
+
+NAME Avance Logic 2302
+CHIPSET Avance Logic
+LINE #chipset "ali2302"
+SERVER SVGA
+
+NAME Avance Logic 2308
+CHIPSET Avance Logic
+LINE #chipset "ali2308"
+SERVER SVGA
+
+NAME Avance Logic 2401
+CHIPSET Avance Logic
+LINE #chipset "ali2401"
+SERVER SVGA
+
+NAME Hercules Stingray
+CHIPSET ALG-2228/2301/2302
+LINE #chipset "ali2228"
+SERVER SVGA
+
+NAME SPEA/V7 Mirage VEGA Plus
+CHIPSET ALG-2228
+LINE #chipset "ali2228"
+SERVER SVGA
+
+# ARK Logic
+
+NAME Ark Logic ARK1000PV (generic)
+CHIPSET ARK1000PV
+SERVER SVGA
+
+# For now, treat the VL as a PV. This may be changed later
+NAME Ark Logic ARK1000VL (generic)
+CHIPSET ARK1000VL
+LINE Chipset "ark1000pv"
+SERVER SVGA
+
+NAME Ark Logic ARK2000PV (generic)
+CHIPSET ARK1000PV
+SERVER SVGA
+
+NAME Ark Logic ARK2000MT (generic)
+CHIPSET ARK1000MT
+SERVER SVGA
+
+NAME Hercules Stingray Pro
+SEE Ark Logic ARK1000PV (generic)
+
+NAME Hercules Stingray Pro/V
+SEE Ark Logic ARK1000PV (generic)
+
+NAME Ocean (octek) VL-VGA-1000
+RAMDAC att20c490
+SEE Ark Logic ARK1000VL (generic)
+
+NAME Hercules Stingray 64/V with ZoomDAC
+SEE Ark Logic ARK2000PV (generic)
+
+NAME Hercules Stingray 64/V with ICS5342
+CHIPSET ARK2000MT
+RAMDAC ics5342
+SERVER SVGA
+
+NAME Diamond Stealth64 Graphics 2001 series
+CHIPSET ARK2000PV
+RAMDAC ics5342
+SERVER SVGA
+
+# Oak
+
+NAME Oak (generic)
+CHIPSET Oak-067/77/87
+SERVER SVGA
+
+NAME Paradise Accelerator Value
+CHIPSET Oak OTI-087
+SERVER SVGA
+
+# P9000
+
+NAME Diamond Viper VLB 2Mb
+CHIPSET Weitek 9000
+SERVER P9000
+LINE #Clocks must match the mode clocks (XFree86 3.1 P9000 server)
+LINE #Versions later than 3.1 do not require a clocks line
+LINE Chipset "vipervlb" # Required for some cards which autodetect as PCI
+LINE Videoram 2048 # Required
+LINE Membase 0x80000000 # Optional (0x80000000 is default)
+NOCLOCKPROBE
+
+NAME Diamond Viper PCI 2Mb
+CHIPSET Weitek 9000
+SERVER P9000
+LINE #Clocks must match the mode clocks (XFree86 3.1 P9000 server)
+LINE #Versions later than 3.1 do not require a clocks line
+LINE Videoram 2048 # Required
+LINE #Membase 0x80000000 # Use scanpci to get the correct Membase
+NOCLOCKPROBE
+
+NAME Orchid P9000 VLB
+CHIPSET Weitek 9000
+SERVER P9000
+LINE Chipset "orchid_p9000"
+LINE Membase 0xE0000000
+NOCLOCKPROBE
+
+# Trident
+
+NAME Trident 8900/9000 (generic)
+CHIPSET TVGA8900/9000
+SERVER SVGA
+
+NAME Trident 8900D (generic)
+CHIPSET TVGA8900D
+SERVER SVGA
+
+NAME Trident TVGA9200CXr (generic)
+CHIPSET TVGA9200CXr
+SERVER SVGA
+
+NAME Trident TGUI9400CXi (generic)
+CHIPSET TGUI9400CXi
+SERVER SVGA
+
+NAME Trident TGUI9420DGi (generic)
+CHIPSET TGUI9420DGi
+SERVER SVGA
+
+NAME Trident TGUI9430DGi (generic)
+CHIPSET TGUI9430DGi
+SERVER SVGA
+
+NAME Trident TGUI9440 (generic)
+CHIPSET TGUI9440
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Trident TGUI9660 (generic)
+CHIPSET TGUI9660
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Trident TGUI9680 (generic)
+CHIPSET TGUI9680
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Trident TGUI9682 (generic)
+CHIPSET TGUI9682
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Trident TGUI9685 (generic)
+CHIPSET TGUI9685
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Trident Cyber 9382 (generic)
+CHIPSET Cyber9382
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Trident Cyber 9385 (generic)
+CHIPSET Cyber9385
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Trident Cyber 9388 (generic)
+CHIPSET Cyber9388
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Trident Cyber 9397 (generic)
+CHIPSET Cyber9397
+SERVER SVGA
+NOCLOCKPROBE
+
+# SiS
+
+NAME SiS SG86C201
+CHIPSET SIS86C201
+SERVER SVGA
+
+# Alliance ProMotion
+
+NAME Alliance ProMotion 6422
+CHIPSET AP6422
+SERVER SVGA
+
+# VGA
+
+NAME Generic VGA compatible
+CHIPSET Generic VGA
+SERVER VGA16
+
+NAME Unsupported VGA compatible
+CHIPSET Generic VGA
+SERVER VGA16
+UNSUPPORTED
+
+# Number 9 I128
+
+NAME Number Nine Imagine I-128 (2-8MB)
+CHIPSET I128
+SERVER I128
+
+NAME Number Nine Imagine I-128 Series 2 (2-4MB)
+CHIPSET I128
+SERVER I128
+
+# Matrox
+
+NAME Matrox Millennium (MGA)
+CHIPSET mga2064w
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Matrox Millennium II
+CHIPSET mga2164w
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Matrox Millennium II AGP
+CHIPSET mga2164w AGP
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME Matrox Mystique
+CHIPSET mga1064sg
+SERVER SVGA
+NOCLOCKPROBE
+
+# NV1
+
+NAME Diamond Edge 3D
+CHIPSET nv1
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME RIVA128
+CHIPSET RIVA128
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME ELSA VICTORY ERAZOR
+SEE RIVA128
+
+NAME Diamond Viper 330
+SEE RIVA128
+
+NAME STB Velocity 128
+SEE RIVA128
+
+NAME ASUS 3Dexplorer
+SEE RIVA128
+
+# Alliance Semiconductor
+
+NAME Diamond Stealth Video 2500
+CHIPSET Alliance AT24
+SERVER SVGA
+NOCLOCKPROBE
+
+NAME AT3D
+CHIPSET Alliance AT3D
+SERVER SVGA
+NOCLOCKPROBE
+LINE #Option "no_accel"
+
+NAME AT25
+SEE AT3D
+
+NAME Hercules Stingray 128 3D
+SEE AT3D
+
+# Misc
+
+NAME Techworks Ultimate 3D
+CHIPSET CL-GD5464
+SEE Cirrus Logic GD5464
+
+NAME VideoLogic GrafixStar 550
+CHIPSET CL-GD5464
+SEE Cirrus Logic GD5464
+
+NAME Jaton Video-70P
+CHIPSET CL-GD5464
+SEE Cirrus Logic GD5464
+
+NAME Jaton Video-58P
+SEE ET6000 (generic)
+
+NAME Rendition Verite 1000
+CHIPSET Verite 1000
+SEE Unsupported VGA compatible
+
+NAME Creative Labs 3D Blaster PCI (Verite 1000)
+SEE Rendition Verite 1000
+
+NAME Canopus Total-3D
+SEE Rendition Verite 1000
+
+NAME Sierra Screaming 3D
+SEE Rendition Verite 1000
+
+NAME NeoMagic (laptop/notebook)
+CHIPSET NeoMagic 128/V/ZV
+SEE Unsupported VGA compatible
+
+END
diff --git a/hw/xfree86/utils/xorgconfig/cards.c b/hw/xfree86/utils/xorgconfig/cards.c
new file mode 100644
index 000000000..a714d04ca
--- /dev/null
+++ b/hw/xfree86/utils/xorgconfig/cards.c
@@ -0,0 +1,285 @@
+/* $Xorg: cards.c,v 1.3 2000/08/17 19:53:05 cpqbld Exp $ */
+
+
+
+
+
+/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/cards.c,v 3.11.2.1 1998/01/18 10:35:45 hohndel Exp $ */
+
+/*
+ * Functions to manipulate card database.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "cards.h"
+
+/*
+ * Database format:
+ *
+ * NAME <name of card>
+ * CHIPSET <chipset description>
+ * SERVER <server name>
+ *
+ * Optional keywords:
+ * RAMDAC <ramdac identifier>
+ * CLOCKCHIP <clockchip identifier>
+ * DACSPEED <dacspeed>
+ * NOCLOCKPROBE
+ * UNSUPPORTED
+ *
+ * SEE <name of card> refers to another card definition; parameters that
+ * are already defined are not overridden.
+ *
+ * <server name> is one of Mono, VGA16, SVGA, S3, Mach32, Mach8, 8514,
+ * P9000, AGX, W32.
+ *
+ * A useful additional keywords may be CLOCKS.
+ */
+
+
+
+/* Database vars. */
+
+int lastcard;
+
+Card card[MAX_CARDS];
+
+void sort_database();
+
+
+static int getline(f, l)
+FILE *f;
+char *l;
+{
+ if (fgets(l, 128, f) == NULL)
+ return -1;
+#ifdef __EMX__
+ {
+ char *p = strchr(l,'\r');
+ if (p) {
+ *p = '\n';
+ *(p+1) = '\0';
+ }
+ }
+#endif
+ return 0;
+}
+
+static void appendstring(destp, src)
+ char **destp;
+ char *src;
+{
+ char *newstr;
+ newstr = malloc(strlen(*destp) + strlen(src) + 1);
+ strcpy(newstr, *destp);
+ strcat(newstr, src);
+ if (strlen(*destp) > 0)
+ free(*destp);
+ *destp = newstr;
+}
+
+int lookupcard( char *name ) {
+ int i;
+ for (i = 0; i <= lastcard; i++)
+ if (strcmp(name, card[i].name) == 0)
+ return i;
+ return -1;
+}
+
+static char *s3_comment =
+"# Use Option \"nolinear\" if the server doesn't start up correctly\n"
+"# (this avoids the linear framebuffer probe). If that fails try\n"
+"# option \"nomemaccess\".\n"
+"#\n"
+"# Refer to /usr/X11R6/lib/doc/README.S3, and the XF86_S3 man page.\n";
+
+static char *cirrus_comment =
+"# Use Option \"no_bitblt\" if you have graphics problems. If that fails\n"
+"# try Option \"noaccel\".\n"
+"# Refer to /usr/X11R6/lib/doc/README.cirrus.\n"
+"# To allow linear addressing, uncomment the Option line and the\n"
+"# address that the card maps the framebuffer to.\n";
+
+int parse_database() {
+ FILE *f;
+ char buf[128];
+ int i, lineno;
+ char filename[128];
+
+#ifndef __EMX__
+ strcpy(filename, CARD_DATABASE_FILE);
+#else
+ strcpy(filename, (char*)__XOS2RedirRoot(CARD_DATABASE_FILE));
+#endif
+ f = fopen(filename, "r");
+ if (f == NULL)
+ return -1;
+
+ lastcard = -1;
+ lineno = 0;
+
+ for (;;) {
+ if (getline(f, buf))
+ break;
+ lineno++;
+ if (buf[0] == '#')
+ /* Comment. */
+ continue;
+ if (strncmp(buf, "END", 3) == 0)
+ /* End of database. */
+ break;
+ if (strncmp(buf, "LINE", 4) == 0 && lastcard>=0) {
+ /* Line of Device comment. */
+ char *lines;
+ /* Append to existing lines. */
+ appendstring(&card[lastcard].lines, buf + 5);
+ continue;
+ }
+ /*
+ * The following keywords require the trailing newline
+ * to be deleted.
+ */
+ i = strlen(buf);
+ buf[--i] = '\0';
+
+ /* remove trailing spaces or tabs */
+ for(--i; i>=0 && (buf[i] == ' ' || buf[i] == '\011'); i--) ;
+ if (i>=0)
+ buf[i+1] = '\0';
+ else
+ continue; /* skip empty lines */
+
+ if (strncmp(buf, "NAME", 4) == 0) {
+ /* New entry. */
+ lastcard++;
+ card[lastcard].name = malloc(strlen(buf + 5) + 1);
+ strcpy(card[lastcard].name, buf + 5);
+ card[lastcard].chipset = NULL;
+ card[lastcard].ramdac = NULL;
+ card[lastcard].clockchip = NULL;
+ card[lastcard].dacspeed = NULL;
+ card[lastcard].flags = 0;
+ card[lastcard].lines = "";
+ continue;
+ }
+ if (lastcard < 0) /* no NAME line found yet */
+ continue;
+ if (strncmp(buf, "SEE", 3) == 0) {
+ /* Reference to another entry. */
+ int i;
+ i = lookupcard(buf + 4);
+ if (i == -1) {
+ printf("Error in database, invalid reference: %s.\n",
+ buf + 4);
+ free(card[lastcard].name);
+ lastcard--;
+ continue;
+ }
+ if (card[lastcard].chipset == NULL)
+ card[lastcard].chipset = card[i].chipset;
+ if (card[lastcard].server == NULL)
+ card[lastcard].server = card[i].server;
+ if (card[lastcard].ramdac == NULL)
+ card[lastcard].ramdac = card[i].ramdac;
+ if (card[lastcard].clockchip == NULL)
+ card[lastcard].clockchip = card[i].clockchip;
+ if (card[lastcard].dacspeed == NULL)
+ card[lastcard].dacspeed = card[i].dacspeed;
+ card[lastcard].flags |= card[i].flags;
+ appendstring(&card[lastcard].lines, card[i].lines);
+ continue;
+ }
+ if (strncmp(buf, "CHIPSET", 7) == 0) {
+ /* Chipset description. */
+ card[lastcard].chipset = malloc(strlen(buf + 8) + 1);
+ strcpy(card[lastcard].chipset, buf + 8);
+ continue;
+ }
+ if (strncmp(buf, "SERVER", 6) == 0) {
+ /* Server identifier. */
+ card[lastcard].server = malloc(strlen(buf + 7) + 1);
+ strcpy(card[lastcard].server, buf + 7);
+ continue;
+ }
+ if (strncmp(buf, "RAMDAC", 6) == 0) {
+ /* Ramdac indentifier. */
+ card[lastcard].ramdac = malloc(strlen(buf + 7) + 1);
+ strcpy(card[lastcard].ramdac, buf + 7);
+ continue;
+ }
+ if (strncmp(buf, "CLOCKCHIP", 9) == 0) {
+ /* Clockchip indentifier. */
+ card[lastcard].clockchip = malloc(strlen(buf + 10) + 1);
+ strcpy(card[lastcard].clockchip, buf + 10);
+ card[lastcard].flags |= NOCLOCKPROBE;
+ continue;
+ }
+ if (strncmp(buf, "DACSPEED", 8) == 0) {
+ /* Clockchip indentifier. */
+ card[lastcard].dacspeed = malloc(strlen(buf + 9) + 1);
+ strcpy(card[lastcard].dacspeed, buf + 9);
+ continue;
+ }
+ if (strncmp(buf, "NOCLOCKPROBE", 12) == 0) {
+ card[lastcard].flags |= NOCLOCKPROBE;
+ continue;
+ }
+ if (strncmp(buf, "UNSUPPORTED", 12) == 0) {
+ card[lastcard].flags |= UNSUPPORTED;
+ continue;
+ }
+ /* test for missing required fields */
+ if (card[lastcard].server == NULL) {
+ fprintf(stderr, "Warning SERVER specification missing "
+ "in Card database entry %s (line %d).\n",
+ card[lastcard].name, lineno);
+ keypress();
+ card[lastcard].server = "unknown";
+ }
+ if (card[lastcard].chipset == NULL) {
+ fprintf(stderr, "Warning CHIPSET specification missing "
+ "in Card database entry %s (line %d).\n",
+ card[lastcard].name, lineno);
+ keypress();
+ card[lastcard].chipset = "unknown";
+ }
+ }
+
+ fclose(f);
+
+ /*
+ * Add general comments.
+ */
+ for (i = 0; i <= lastcard; i++) {
+ if (card[i].server && strcmp(card[i].server, "S3") == 0)
+ appendstring(&card[i].lines, s3_comment);
+ if (card[i].chipset &&
+ strncmp(card[i].chipset, "CL-GD", 5) == 0)
+ appendstring(&card[i].lines, cirrus_comment);
+ }
+
+ sort_database();
+
+ return 0;
+}
+
+#ifdef __STDC__
+#define CONST const
+#else
+#define CONST
+#endif
+
+static int compare_card(e1, e2)
+ CONST void *e1;
+ CONST void *e2;
+{
+ return strcmp(((Card *)e1)->name, ((Card *)e2)->name);
+}
+
+void sort_database() {
+ /* Each element is a bunch of words, but nothing too bad. */
+ qsort(card, lastcard + 1, sizeof(Card), compare_card);
+}
diff --git a/hw/xfree86/utils/xorgconfig/cards.h b/hw/xfree86/utils/xorgconfig/cards.h
new file mode 100644
index 000000000..11976d978
--- /dev/null
+++ b/hw/xfree86/utils/xorgconfig/cards.h
@@ -0,0 +1,36 @@
+/* $XFree86: xc/programs/Xserver/hw/xfree86/xf86config/cards.h,v 3.3 1996/12/23 07:04:44 dawes Exp $ */
+
+
+
+
+
+/* $Xorg: cards.h,v 1.3 2000/08/17 19:53:05 cpqbld Exp $ */
+
+#ifndef CARD_DATABASE_FILE
+#define CARD_DATABASE_FILE "Cards"
+#endif
+
+#define MAX_CARDS 1000
+
+typedef struct {
+ char *name; /* Name of the card. */
+ char *chipset; /* Chipset (decriptive). */
+ char *server; /* Server identifier. */
+ char *ramdac; /* Ramdac identifier. */
+ char *clockchip; /* Clockchip identifier. */
+ char *dacspeed; /* DAC speed rating. */
+ int flags;
+ char *lines; /* Additional Device section lines. */
+} Card;
+
+/* Flags: */
+#define NOCLOCKPROBE 0x1 /* Never probe clocks of the card. */
+#define UNSUPPORTED 0x2 /* Card is not supported (only VGA). */
+
+extern int lastcard;
+
+extern Card card[MAX_CARDS];
+
+
+int parse_database();
+
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-24 12:47:54 +0000