diff options
| author | Xing Zheng <zhengxing@rock-chips.com> | 2016-10-21 12:03:40 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-10-21 09:34:19 +0200 |
| commit | 5c1c63f6345b9e1600875f3122166c0af434158e (patch) | |
| tree | 80e6471ee2c5dfebca74bbb7d4f90624cc03de00 /drivers/clk/rockchip | |
| parent | 1001354ca34179f3db924eb66672442a173147dc (diff) | |
clk: rockchip: add 533.25MHz to rk3399 clock rates table
We need to get the accurate 533.25MHz for the DP display.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3399.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 8387c7a40bda..a5a3f412d09a 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -93,6 +93,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), + RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), |