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2018-04-12broadcom/vc5: Drop the finished_seqno optimization.Eric Anholt2-11/+0
With the DRM scheduler changes, I'm about to remove all seqnos from the UABI.
2018-04-12broadcom/vc5: Drop the throttling code.Eric Anholt1-9/+0
Since I'll be using the DRM scheduler, we won't run into the problem of a runaway client starving other clients of GPU time.
2018-04-12broadcom/vc5: Move flush_last_load into load_general, like for stores.Eric Anholt1-28/+29
This should avoid mistakes with not flushing as we change the series of loads. Already, it fixes a hopefully unreachable case where we were emitting just the TILE_COORDINATES and not the dummy store that needs to go with it.
2018-04-12broadcom/vc5: Rename read_but_not_cleared to loads_pending.Eric Anholt1-13/+13
This is a more obvious name for what the variable means, and matches what it's called for stores.
2018-04-12broadcom/vc5: Refactor the implicit coords/stores_pending logic.Eric Anholt1-23/+13
Since I just fixed a bug due to forgetting to do these right, do it once in the helper func.
2018-04-12broadcom/vc5: Emit missing TILE_COORDINATES_IMPLICIT in separate z/s stores.Eric Anholt1-5/+16
Fixes a simulator assertion failure in KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8
2018-04-12broadcom/vc5: Add checks that we don't try to do raw Z+S load/stores.Eric Anholt1-0/+8
This was dying in the simulator on GTF-GLES3.gtf.GL3Tests.packed_depth_stencil.packed_depth_stencil_blit. We'll need to do basically the same thing as Z32F/S8 does in the MSAA Z24S8 case.
2018-04-12broadcom/vc5: Fix MSAA depth/stencil size setup.Eric Anholt1-2/+4
The v3dX(get_internal_type_bpp_for_output_format)() call only handles color output formats (which overlap in enum numbers with depth output formats), so for depth we just need to take the normal cpp times the number of samples.
2018-04-12st/va: add VP9 config to enable profile2Leo Liu2-1/+5
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radeonsi: use PIPE_FORMAT_P016 format for VP9 profile2Leo Liu1-1/+2
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radeon/vcn: add VP9 profile2 supportLeo Liu1-0/+16
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12vl: add VP9 profile2 supportLeo Liu2-1/+3
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12st/va: add VP9 config to enable profile0Leo Liu2-1/+5
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12st/va: parse VP9 uncompressed frame headerLeo Liu3-1/+239
To get some of UVD required parameters. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12st/va: add slice parameter handling for VP9Leo Liu1-1/+24
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12st/va: add picture parameter handling for VP9Leo Liu1-1/+51
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12st/va: add handles for VP9 buffersLeo Liu5-2/+54
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12st/va: add VP9 picture to contextLeo Liu2-0/+5
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radeonsi: cap VP9 support to progressive bufferLeo Liu1-0/+2
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radeonsi: cap VP9 support to RavenLeo Liu1-0/+4
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radeon/vcn: add VP9 context bufferLeo Liu1-0/+26
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radeon/vcn: get VP9 msg bufferLeo Liu2-1/+176
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radeon/vcn: fill probability table to prob buffersLeo Liu1-0/+38
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radeon/vcn: add VP9 message buffer interfaceLeo Liu1-0/+134
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radeon/vcn: add VP9 prob table bufferLeo Liu2-18/+37
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12vl: add VP9 probability tablesLeo Liu3-1/+588
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radeon/vcn: add VP9 dpb buffer sizeLeo Liu1-0/+6
The current FW has restricted the size to the worse case, and the new dynamic dpb buffer support is on the way from firmware side, we will change accordingly. Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radeon/vcn: add VP9 stream type for decoderLeo Liu2-0/+4
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12vl: add VP9 picture descriptionLeo Liu1-0/+94
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12vl: add VP9 profile0 and formatLeo Liu2-2/+7
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
2018-04-12radv: fix radv_layout_dcc_compressed() when image doesn't have DCCSamuel Pitoiset1-1/+1
num_dcc_levels means that DCC is supported, but this doesn't mean that it's enabled by the driver. Instead, we should rely on radv_image_has_dcc(). This fixes some multisample regressions since 0babc8e5d66 ("radv: fix picking the method for resolve subpass") on Vega. This is because the resolve method changed from HW to FS, but those fails are totally unexpected, so there might some differences between Polaris and Vega here. Fixes: 44fcf587445 ("radv: Disable DCC for GENERAL layout and compute transfer dest.") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-12radv: add radv_decompress_resolve_{subpass}_src() helpersSamuel Pitoiset4-54/+73
This helper shares common code before resolving using either a fragment or a compute shader. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-12radv: add radv_init_dcc_control_reg() helperSamuel Pitoiset1-32/+52
And add some comments. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-12glsl: fix compat shaders in GLSL 1.40Timothy Arceri1-0/+2
The compatibility and core tokens were not added until GLSL 1.50, for GLSL 1.40 just assume all shaders built with a compat profile are compat shaders. Fixes rendering issues in Dawn of War II on radeonsi which has enabled OpenGL 3.1 compat support. Fixes: a0c8b49284ef "mesa: enable OpenGL 3.1 with ARB_compatibility" Reviewed-by: Marek Olšák <marek.olsak@amd.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105807
2018-04-11mesa: Silence remaining unused parameter warnings in teximage.cIan Romanick1-21/+21
src/mesa/main/teximage.c: In function ‘_mesa_test_proxy_teximage’: src/mesa/main/teximage.c:1301:51: warning: unused parameter ‘level’ [-Wunused-parameter] GLuint numLevels, GLint level, ^~~~~ src/mesa/main/teximage.c: In function ‘texsubimage_error_check’: src/mesa/main/teximage.c:2186:30: warning: unused parameter ‘dsa’ [-Wunused-parameter] bool dsa, const char *callerName) ^~~ src/mesa/main/teximage.c: In function ‘copytexture_error_check’: src/mesa/main/teximage.c:2297:32: warning: unused parameter ‘width’ [-Wunused-parameter] GLint width, GLint height, GLint border ) ^~~~~ src/mesa/main/teximage.c:2297:45: warning: unused parameter ‘height’ [-Wunused-parameter] GLint width, GLint height, GLint border ) ^~~~~~ src/mesa/main/teximage.c: In function ‘check_rtt_cb’: src/mesa/main/teximage.c:2679:21: warning: unused parameter ‘key’ [-Wunused-parameter] check_rtt_cb(GLuint key, void *data, void *userData) ^~~ src/mesa/main/teximage.c: In function ‘override_internal_format’: src/mesa/main/teximage.c:2756:55: warning: unused parameter ‘width’ [-Wunused-parameter] override_internal_format(GLenum internalFormat, GLint width, GLint height) ^~~~~ src/mesa/main/teximage.c:2756:68: warning: unused parameter ‘height’ [-Wunused-parameter] override_internal_format(GLenum internalFormat, GLint width, GLint height) ^~~~~~ src/mesa/main/teximage.c: In function ‘texture_sub_image’: src/mesa/main/teximage.c:3293:24: warning: unused parameter ‘dsa’ [-Wunused-parameter] bool dsa) ^~~ src/mesa/main/teximage.c: In function ‘can_avoid_reallocation’: src/mesa/main/teximage.c:3788:53: warning: unused parameter ‘x’ [-Wunused-parameter] mesa_format texFormat, GLint x, GLint y, GLsizei width, ^ src/mesa/main/teximage.c:3788:62: warning: unused parameter ‘y’ [-Wunused-parameter] mesa_format texFormat, GLint x, GLint y, GLsizei width, ^ src/mesa/main/teximage.c: In function ‘valid_texstorage_ms_parameters’: src/mesa/main/teximage.c:5987:40: warning: unused parameter ‘samples’ [-Wunused-parameter] GLsizei samples, unsigned dims) ^~~~~~~ Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Brian Paul <brianp@vmware.com>
2018-04-11mesa: Silence unused parameter warning in compressedteximage_only_formatIan Romanick3-10/+10
Passing ctx to compressedteximage_only_format was the only use of the ctx parameter in _mesa_format_no_online_compression, so that parameter had to go too. ../../SOURCE/master/src/mesa/main/teximage.c: In function ‘compressedteximage_only_format’: ../../SOURCE/master/src/mesa/main/teximage.c:1355:57: warning: unused parameter ‘ctx’ [-Wunused-parameter] compressedteximage_only_format(const struct gl_context *ctx, GLenum format) ^~~ Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Brian Paul <brianp@vmware.com>
2018-04-11blorp: Silence unused function warningsNanley Chery3-4/+4
vulkan/genX_blorp_exec.c:69:1: warning: ‘blorp_get_surface_base_address’ defined but not used [-Wunused-function] blorp_get_surface_base_address(struct blorp_batch *batch) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from vulkan/genX_blorp_exec.c:35:0: ./blorp/blorp_genX_exec.h:1249:1: warning: ‘blorp_emit_memcpy’ defined but not used [-Wunused-function] blorp_emit_memcpy(struct blorp_batch *batch, ^~~~~~~~~~~~~~~~~ genX_blorp_exec.c:99:1: warning: ‘blorp_get_surface_base_address’ defined but not used [-Wunused-function] blorp_get_surface_base_address(struct blorp_batch *batch) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from genX_blorp_exec.c:33:0: ../../../../../src/intel/blorp/blorp_genX_exec.h:1249:1: warning: ‘blorp_emit_memcpy’ defined but not used [-Wunused-function] blorp_emit_memcpy(struct blorp_batch *batch, ^~~~~~~~~~~~~~~~~ Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-04-11nir/vars_to_ssa: Simplify node matching codeCaio Marcelo de Oliveira Filho1-36/+31
The matching code doesn't make real use of the return value. The main function return value is ignored, and while the worker function propagate its return value, the actual callback never returns false. v2: Style fixes. (Jason) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-11nir/vars_to_ssa: Remove an unnecessary deref_arry_type checkCaio Marcelo de Oliveira Filho1-4/+5
Only fully-qualified direct derefs, collected in direct_deref_nodes, are checked for aliasing, so it is already known up front that they have only array derefs of type direct. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-11nir/vars_to_ssa: Rework register_variable_uses()Caio Marcelo de Oliveira Filho1-28/+23
The return value was needed to make use of the old nir_foreach_block helper, but not needed anymore with the macro version. Then go one step further and move the foreach directly into the register variable uses function. v2: Move foreach to register_variable_uses(). (Jason) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-11nir: Use nir_builder in lower_io_to_temporariesJason Ekstrand1-19/+16
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-04-11radv: Enable RB+ on Raven.Bas Nieuwenhuizen1-1/+2
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-04-11vulkan: fix build issue on android (both anv/radv)Tapani Pälli2-5/+5
Fixes linking errors against: anv_GetPhysicalDeviceImageFormatProperties2KHR radv_GetPhysicalDeviceImageFormatProperties2KHR Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-04-11radeonsi: correctly parse disassembly with labelsNicolai Hähnle1-31/+32
LLVM now emits labels as part of the disassembly string, which is very useful but breaks the old parsing approach. Use the semicolon to detect the boundary of instructions instead of going by line breaks. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-04-11radeonsi: pass -O halt_waves to umr for hang debuggingNicolai Hähnle2-3/+3
This will give us meaningful wave information in the case of a hang where shaders are still running in an infinite loop. Note that we call umr multiple times for different sections of the ddebug hang dump, and so the wave information will not necessarily match up between sections. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-04-10vulkan: Drop vk_android_native_buffer.xmlJason Ekstrand12-109/+26
All the information in vk_android_native_buffer.xml is now in vk.xml. The only exception is the extension type attribute which we can work around in the generators while we wait for the XML to be fixed. Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-04-10nir/lower_atomics: Rework the main walker loop a bitJason Ekstrand1-8/+16
This replaces some "if (...} { }" with "if (...) continue;" to reduce nesting depth and makes nir_metadata_preserve conditional on progress for the given impl. Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-04-11radv: Enable RB+ where possible.Bas Nieuwenhuizen3-6/+151
According to Marek, not enabling it on Stoney has a significant negative performance impact. (And I guess this might impact performance on Raven as well) The register settings are pretty much copied from radeonsi. I did not put this in the pipeline as that would make the pipeline more dependent on the format which mean we would have to have more pipelines for the meta shaders. v2: Don't clear RB+ regs if not enabled as the CLEAR_STATE packet does already. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-04-11nir: Check if u_vector_init() succeedsTopi Pohjolainen1-2/+9
However, it only fails when running out of memory. Now, if we are about to check that, we should be consistent and check the allocation of the worklist as well. CID: 1433512 Fixes: edb18564c7 nir: Initial implementation of a nir_instr_worklist Reviewed-by: Thomas Helland <thomashelland90@gmail.com> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-04-11mesa: Assert base format before truncating to unsigned shortTopi Pohjolainen1-2/+3
CID: 1433709 Fixes: ca721b3d8: mesa: use GLenum16 in a few more places Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Brian Paul <brianp@vmware.com> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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