diff options
| author | Mika Kuoppala <mika.kuoppala@intel.com> | 2016-03-22 15:08:24 +0200 |
|---|---|---|
| committer | Mika Kuoppala <mika.kuoppala@intel.com> | 2016-04-01 14:01:42 +0300 |
| commit | 72aeabb4add23318f009a8eb79e242903f3587df (patch) | |
| tree | 8a3525332b07c0f72e589e7a3a59fb5ac6356bf5 | |
| parent | 22f140806d6f036e8036d04cba75fda79668c179 (diff) | |
drm/i915: Use wait_until_reg macros in intel_dsi
Use wait_until_reg macros in this file where appropriate.
Note that we can still use reg_set|clr variant in fifo
stat checkup as the masks have only one bit set.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dsi.c | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 3ca9a19cbe6d..2f8468babe04 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -125,7 +125,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, /* note: this is never true for reads */ if (packet.payload_length) { - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) + if (wait_until_reg_clr(MIPI_GEN_FIFO_STAT(port), data_mask, 50)) DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); write_data(dev_priv, data_reg, packet.payload, @@ -136,16 +136,15 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); } - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { + if (wait_until_reg_clr(MIPI_GEN_FIFO_STAT(port), ctrl_mask, 50)) DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); - } I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); /* ->rx_len is set only for reads */ if (msg->rx_len) { - data_mask = GEN_READ_DATA_AVAIL; - if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) + if (wait_until_reg_set(MIPI_INTR_STAT(port), + GEN_READ_DATA_AVAIL, 50)) DRM_ERROR("Timeout waiting for read data.\n"); read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); @@ -217,7 +216,6 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, struct drm_encoder *encoder = &intel_dsi->base.base; struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; - u32 mask; /* XXX: pipe, hs */ if (hs) @@ -234,8 +232,8 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, I915_WRITE(MIPI_DPI_CONTROL(port), cmd); - mask = SPL_PKT_SENT_INTERRUPT; - if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) + if (wait_until_reg_set(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT, + 100)) DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); return 0; @@ -623,8 +621,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) /* Wait till Clock lanes are in LP-00 state for MIPI Port A * only. MIPI Port C has no similar bit for checking */ - if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT) - == 0x00000), 30)) + if (wait_until_reg_clr(port_ctrl, AFE_LATCHOUT, 30)) DRM_ERROR("DSI LP not going Low\n"); /* Disable MIPI PHY transparent latch */ |