From 042f16e6afbfdeb2174d1b6b4e9ae3e225319f63 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Wed, 27 Feb 2019 08:50:31 -0800 Subject: b32csel squash! WIP: intel/compiler: Import Gen8 / Gen9 ALU machine description --- src/intel/compiler/gen8_md.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/intel/compiler/gen8_md.py b/src/intel/compiler/gen8_md.py index 8b0161a82286..c993c993196e 100644 --- a/src/intel/compiler/gen8_md.py +++ b/src/intel/compiler/gen8_md.py @@ -566,6 +566,23 @@ gen8_md = [ (('extract_i16', a, 1), Instruction('MOV', r, subscript(a, W, 1))), (('extract_i16', a, 2), Instruction('MOV', r, subscript(a, W, 2))), (('extract_i16', a, 3), Instruction('MOV', r, subscript(a, W, 3))), + + # Select + (('b32csel', 'a(front_face)', 1.0, -1.0), InstructionList([(t0, D), ], + (Instruction('OR', + subscript(t0, W, 1), + retype(grf(0, 0, 1), W), + imm(0x3f80, W)), + Instruction('AND', retype(r, UD), retype(t0, UD), imm(0xbf800000, UD)))) + ), + (('b32csel', 'a(front_face)', -1.0, 1.0), InstructionList([(t0, D), ], + (Instruction('OR', subscript(t0, W, 1), neg(retype(grf(0, 0, 1), W)), imm(0x3f80, W)), + Instruction('AND', retype(r, UD), retype(t0, UD), imm(0xbf800000, UD)))) + ), + (('b32csel', a, b, c), InstructionList([], + (Instruction('CMP', null(D), a, imm(0, D)).cmod('NZ'), + Instruction('SEL', r, b, c).predicate())) + ), ] gen8_unsupported = [ -- cgit v1.2.3