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2017-04-26svga: Set the surface dirty bit for the right surface viewCharmaine Lee1-5/+19
For VGPU10, we will render to a backed surface view when the same resource is used for rendering and sampling. In this case, we will mark the dirty bit for the backed surface view. Reviewed-by: Brian Paul <brianp@vmware.com>
2017-04-26svga: Move rendertarget view related fields to hw_clear stateCharmaine Lee4-17/+18
This patch moves the rendertarget view related fields from svga_hw_draw_state to svga_hw_clear_state where all the hw framebuffer related state resides. Reviewed-by: Brian Paul <brianp@vmware.com>
2017-04-26svga: Move setting the rendered_to flags to framebuffer emit timeCharmaine Lee2-18/+28
Instead of setting the rendered_to flags at set time, this patch moves the setting of the flags to framebuffer emit time. Reviewed-by: Brian Paul <brianp@vmware.com>
2017-04-26svga: add const qualifiers on svga_check_sampler_view_resource_collision()Brian Paul2-4/+4
We don't change any of the argument objects. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-04-26svga: improve surface view debug messagesBrian Paul1-4/+5
The old ones were somewhat cryptic. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-04-26svga: add DEBUG_SAMPLERSBrian Paul3-1/+4
The debug output in svga_create_sampler_state() was controlled by DEBUG_VIEWS but that's not consistent with the other debug output for sampler views. Create/use a new debug flag just for this. Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-04-26svga: fail screen creation if HW version is too oldBrian Paul1-0/+7
Tested by verifying 3D acceleration works with HWv8 but not earlier. For HWv7 and older we get the GDI Generic renderer. Reviewed-by: Neha Bhende<bhenden@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-04-26winsys/svga: fix error path when kernel is not able to create surfaceDeepak Rawat1-15/+18
If for some reason kernel is not able to create surface, when no buffer was provided the function vmw_svga_winsys_surface_create should return NULL. This patch fixes the issue where the code was not following the clean up path in case of error, which used to cause SIGSEGV. Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2017-04-26draw: whitespace fixes in draw_pipe_vbuf.cBrian Paul1-104/+89
Remove trailing whitespace, fix formatting, etc. Trivial.
2017-04-26st/mesa: minor clean-ups in st_update_renderbuffer_surface()Brian Paul1-9/+8
Remove unneeded parens. Add const qualifiers. Move var decls closer to where they're used. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Neha Bhende<bhenden@vmware.com>
2017-04-26nv50,nvc0: disable the TGSI merge registers passSamuel Pitoiset2-2/+4
shader-db results on GK106 (Thanks Karol): total instructions in shared programs : 3931608 -> 3929463 (-0.05%) total gprs used in shared programs : 481255 -> 479014 (-0.47%) total local used in shared programs : 27481 -> 27381 (-0.36%) total bytes used in shared programs : 36031256 -> 36011120 (-0.06%) local gpr inst bytes helped 14 1471 1309 1309 hurt 1 88 384 384 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-04-26radeonsi: disable the TGSI merge registers passSamuel Pitoiset1-1/+1
47109 shaders in 29632 tests Totals: SGPRS: 1917364 -> 1916620 (-0.04 %) VGPRS: 1165802 -> 1165202 (-0.05 %) Spilled SGPRs: 1880 -> 1843 (-1.97 %) Spilled VGPRs: 70 -> 65 (-7.14 %) Private memory VGPRs: 1184 -> 1184 (0.00 %) Scratch size: 1312 -> 1308 (-0.30 %) dwords per thread Code Size: 60211356 -> 60192268 (-0.03 %) bytes LDS: 1077 -> 1077 (0.00 %) blocks Max Waves: 428597 -> 428674 (0.02 %) Wait states: 0 -> 0 (0.00 %) Totals from affected shaders: SGPRS: 238173 -> 237429 (-0.31 %) VGPRS: 149556 -> 148956 (-0.40 %) Spilled SGPRs: 1263 -> 1226 (-2.93 %) Spilled VGPRs: 25 -> 20 (-20.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 20 -> 16 (-20.00 %) dwords per thread Code Size: 10457904 -> 10438816 (-0.18 %) bytes LDS: 50 -> 50 (0.00 %) blocks Max Waves: 41283 -> 41360 (0.19 %) Wait states: 0 -> 0 (0.00 %) Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-26st/glsl_to_tgsi: disable the merge registers pass conditionallySamuel Pitoiset1-1/+6
The main goal of this pass to merge temporary registers in order to reduce the total number of registers and also to produce optimal TGSI code. In fact, compilers seem to be confused when temporary variables are already merged, maybe because it's done too early in the process. Skipping the pass, reduce both the register pressure and the code size, at least for Nouveau and RadeonSI because they have a real backend compiler. Found by luck while fixing an issue in the TGSI dead code elimination pass which affects tex instructions with bindless samplers. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-26gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERSSamuel Pitoiset15-0/+21
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-26radeonsi: use unsynchronized transfers for shader binary uploadsSamuel Pitoiset1-1/+2
Because the buffer is new, it can't be referenced by any CS. This can save few CPU cycles by skipping the whole PIPE_TRANSFER_UNSYNCHRONIZED if in amdgpu_bo_map(). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-26radeonsi: turn si_shader_key::mono into a non-unionMarek Olšák3-15/+11
A merged LS-HS shader needs both fix_fetch and inputs_to_copy for compilation. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi: adjust ESGS ring buffer size computation on VIMarek Olšák1-1/+4
Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: don't set deprecated field PARTIAL_ES_WAVE_ONMarek Olšák1-2/+3
Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: set MAX_PRIMGRP_IN_WAVE in the correct registerMarek Olšák2-1/+5
Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: add a workaround for viewing a slice of 3D as a 2D imageMarek Olšák1-8/+22
Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: fix 1D array shader imagesMarek Olšák1-0/+1
Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: fix most things wrong with shader imagesMarek Olšák2-12/+24
There are 2 major hw changes: - The address must always point to the address of level 0. GFX9 tiling modes don't allow binding to a non-0 level. - 3D must always be bound as 3D, because 2D and 3D use entirely different tiling modes, and the texture target determines which set of modes is used. Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radeonsi/gfx9: fix texture buffer objects and image buffers with IDXEN==0Marek Olšák1-1/+34
Cc: 17.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26mesa: tidy up left over APPLE_vertex_array_object semanticsTimothy Arceri4-43/+9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26mesa: inline bind_vertex_array() helperTimothy Arceri1-17/+6
The previous commit removed the only other user of this function. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26mesa: drop APPLE_vertex_array_object supportTimothy Arceri11-100/+19
Shared context support for VAOs was dropped in 0b2750620b65. From the ARB_vertex_array_object spec: "This extension differs from GL_APPLE_vertex_array_object in that client memory cannot be accessed through a non-zero vertex array object. It also differs in that vertex array objects are explicitly not sharable between contexts." Nobody should be using this extension over ARB_vertex_array_object anymore so just drop it rather than adding locking back just for VAOs created from these functions. For reference the Nvidia blob doesn't expose this extension. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-26radv: Enable userspace fence checking.Bas Nieuwenhuizen3-3/+36
v2: - Added some error handling. - memset the buffer to 0. v3: Added assert for buffer size. Signed-off-by: Bas Nieuwenhuizen <basni@google.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-04-25i965: Remove unused variable 'options'Matt Turner1-2/+0
Should have been removed in commit ad55b1a7701a
2017-04-25glsl: Initialize current_varMatt Turner1-1/+1
CID: 1324644 (Uninitialized pointer field)
2017-04-25radv/ac: setup mrt exports then export them in one go. (v2)Dave Airlie1-15/+19
Noticed while looking at Sascha Willems deferred shaders. This is a bit of an llvm workaround, llvm was producing this: v_cvt_pkrtz_f16_f32_e64 v4, v7, v8 ; D2960004 00021107 v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0 ; D2960006 0001E509 s_waitcnt vmcnt(0) ; BF8C0F70 exp mrt0 v4, v4, v6, v6 compr ; C400040F 00000604 s_waitcnt expcnt(0) ; BF8C0F0F v_cvt_pkrtz_f16_f32_e64 v4, v12, v5 ; D2960004 00020B0C v_cvt_pkrtz_f16_f32_e64 v5, v14, 1.0 ; D2960005 0001E50E exp mrt1 v4, v4, v5, v5 compr ; C400041F 00000504 s_waitcnt expcnt(0) ; BF8C0F0F v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp mrt2 v0, v0, v1, v1 done compr vm ; C4001C2F 00000100 After this change: v_cvt_pkrtz_f16_f32_e64 v4, v7, v8 ; D2960004 00021107 s_waitcnt vmcnt(0) ; BF8C0F70 v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300 v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0 ; D2960006 0001E509 v_cvt_pkrtz_f16_f32_e64 v5, v12, v5 ; D2960005 00020B0C v_cvt_pkrtz_f16_f32_e64 v7, v14, 1.0 ; D2960007 0001E50E exp mrt0 v4, v4, v6, v6 compr ; C400040F 00000604 v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702 exp mrt1 v5, v5, v7, v7 compr ; C400041F 00000705 exp mrt2 v0, v0, v1, v1 done compr vm ; C4001C2F 00000100 No waitcnt for exports are emitted. v2: fixup index->mrt mapping (Bas). Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-25radv/ac: overhaul vs output/ps input routingDave Airlie3-37/+55
In order to cleanly eliminate exports rewrite the code first to mirror how radeonsi works for now. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-25radv/ac: move point coord after layer/viewport.Dave Airlie1-6/+7
These need to be ordered as per shader enum ordering, I'll rewrite this soon, but this is a bug fix. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-25gallium: remove u_caps.c/h interfaceSamuel Pitoiset3-340/+0
No longer used. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-25ddebug: implement get_query_result_resourceMarek Olšák1-0/+16
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-25trace: don't trace resource_destroyMarek Olšák1-7/+4
due to the lack of pipe_resource wrapping, we can get this call from inside of driver calls, which would try to lock an already-locked mutex. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-25gallium/util: add debugging helpers printing pipeline statisticsMarek Olšák2-0/+59
typically useful for hw bring-up Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-25Android: fix r300g only buildRob Herring1-3/+5
If r300g is the only radeon driver built, the Android build fails to build: ninja: error: 'out/target/product/linaro_x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeon_intermediates/export_includes', needed by 'out/target/product/linaro_x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/import_includes', missing and no known rule to make it This is because the path to build libmesa_pipe_radeon was only getting added for r600g and radeonsi, but the library dependency was added for all radeon drivers. As libmesa_pipe_radeon is not needed for r300g, drop the library dependency. Cc: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Emil Velikov <emil.velikov@collabora.com>
2017-04-25mesa: use locked version of HashWalk for xfb objectsTimothy Arceri1-2/+2
From Chapter 5 'Shared Objects and Multiple Contexts' of the OpenGL 4.5 spec: "Objects which contain references to other objects include framebuffer, program pipeline, query, transform feedback, and vertex array objects. Such objects are called container objects and are not shared" Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-25mesa: create locked version of HashWalkTimothy Arceri2-8/+31
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-04-24genxml: Fix gen_pack_header.py crash when field type is invalid.Rafael Antognolli1-2/+2
Just return earlier in that case. Also set prefix to an empty string, so we don't get to use it undefined. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-24genxml: Make BLEND_STATE command support variable length array.Rafael Antognolli7-48/+74
We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers dwords (on gen8+), but the BLEND_STATE struct length is always 17. By marking it size 1, which is actually the size of the struct minus the BLEND_STATE_ENTRY's, we can emit a BLEND_STATE of variable number of entries. For gen6 and gen7 we set length to 0, since it only contains BLEND_STATE_ENTRY's, and no other data. With this change, we also change the code for blorp and anv to emit only the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on gen6-7 and 17 dwords on gen8+. v2: - Use designated initializers on blorp and remove 0 from initialization (Jason) - Default entries to disabled on Vulkan (Jason) - Rebase code. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-24genxml: Fix python crash when no dwords are found.Rafael Antognolli1-5/+12
If the 'dwords' dict is empty, max(dwords.keys()) throws an exception. This case could happen when we have an instruction that is only an array of other structs, with variable length. v2: - Add another clause for empty dwords and make it work with python 3 (Dylan) - Set the length to 0 if dwords is empty, and do not declare dw Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-24genxml: Remove unused parameter.Rafael Antognolli1-2/+2
'start' parameter from Group.emit_pack_function() is useless. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-24intel/aubinator: Correctly read variable length structs.Rafael Antognolli3-6/+54
Before this commit, when a group with count="0" is found, only one field is added to the struct representing the instruction. This causes only one entry to be printed by aubinator, for variable length groups. With this commit we "detect" that there's a variable length group (count="0") and store the offset of the last entry added to the struct when reading the xml. When finally reading the aubdump file, we check the size of the group and whether we have variable number of elements, and in that case, reuse the last field to add the remaining elements. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Tested-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-24isl/format: Update the R16G16B16X16_FLOAT entryNanley Chery1-1/+1
The section of the PRM mentioned in the code comment above this table says that this format supports the render target write message. Internal documentation says that this format also supports alpha blending. As a side effect, this allows CCS_D buffers to be created for images with this format. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2017-04-24anv/pass: Delete anv_pass::subpass_attachmentsNanley Chery1-1/+0
This field has no users. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2017-04-24intel/fs: Take into account amount of data read in spilling cost heuristic.Francisco Jerez1-1/+1
Until now the spilling cost calculation was neglecting the amount of data read from the register during the spilling cost calculation. This caused it to make suboptimal decisions in some cases leading to higher memory bandwidth usage than necessary. Improves Unigine Heaven performance by ~4% on BDW, reversing an unintended FPS regression from my previous commit 147e71242ce539ff28e282f009c332818c35f5ac with n=12 and statistical significance 5%. In addition SynMark2 OglCSDof performance is improved by an additional ~5% on SKL, and a Kerbal Space Program apitrace around the Moho planet I can provide on request improves by ~20%. Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Plamena Manolova <plamena.manolova@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-24intel/fs: Use regs_written() in spilling cost heuristic for improved accuracy.Francisco Jerez1-2/+1
This is what we use later on to compute the number of registers that will actually get spilled to memory, so it's more likely to match reality than the current open-coded approximation. Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Plamena Manolova <plamena.manolova@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-04-24i965/vec4: Use reads_accumulator_implicitly(), not MACH checks.Kenneth Graunke1-4/+4
Curro pointed out that I should not just check for MACH, but use the reads_accumulator_implicitly() helper, which would also prevent the same bug with MAC and SADA2 (if we ever decide to use them). Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2017-04-24android: radv/ac: Fix nir.h includeMauro Rossi1-0/+2
Fixes following building errors due to missing include paths: external/mesa/src/amd/common/ac_shader_info.c:23:10: fatal error: 'nir/nir.h' file not found ^ external/mesa/src/compiler/nir/nir.h:48:10: fatal error: 'nir_opcodes.h' file not found ^ Fixes: 224cf29 "radv/ac: add initial pre-pass for shader info gathering" Acked-by: Dave Airlie <Airlied@redhat.com> Acked-by: Emil Velikov <emil.velikov@collabora.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 09:46:09 +0000