i965: track number of basic blocks and cfg calculationstag/oct-18-2013

11 files changed, 27 insertions, 15 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp b/src/mesa/drivers/dri/i965/brw_cfg.cpp
index 33097ebff4f..4d2cd68d007 100644
--- a/src/mesa/drivers/dri/i965/brw_cfg.cpp
+++ b/src/mesa/drivers/dri/i965/brw_cfg.cpp
@@ -70,6 +70,7 @@ bblock_t::make_list(void *mem_ctx)
 cfg_t::cfg_t(backend_visitor *v)
 {
    create(v->mem_ctx, &v->instructions);
+   v->num_cfg++;
 }
 
 cfg_t::cfg_t(void *mem_ctx, exec_list *instructions)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index fcff060623b..2bde55d14f1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3207,6 +3207,7 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
    fs_generator g(brw, c, prog, fp, v.dual_src_output.file != BAD_FILE);
    const unsigned *generated = g.generate_assembly(&v.instructions,
                                                    simd16_instructions,
+                                                   v.num_cfg, v2.num_cfg,
                                                    final_assembly_size);
 
    if (unlikely(brw->perf_debug) && shader) {
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index b5aed23951b..c0e6bbc15ed 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -487,10 +487,11 @@ public:
 
    const unsigned *generate_assembly(exec_list *simd8_instructions,
                                      exec_list *simd16_instructions,
+                                     int simd8_num_cfg, int simd16_num_cfg,
                                      unsigned *assembly_size);
 
 private:
-   void generate_code(exec_list *instructions);
+   void generate_code(exec_list *instructions, int num_cfg);
    void generate_fb_write(fs_inst *inst);
    void generate_pixel_xy(struct brw_reg dst, bool is_x);
    void generate_linterp(fs_inst *inst, struct brw_reg dst,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 7c75187c245..e6ef4c8eb19 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1152,7 +1152,7 @@ fs_generator::generate_shader_time_add(fs_inst *inst,
 }
 
 void
-fs_generator::generate_code(exec_list *instructions)
+fs_generator::generate_code(exec_list *instructions, int num_cfg)
 {
    int last_native_insn_offset = p->next_insn_offset;
    int beginning_offset = p->next_insn_offset;
@@ -1570,8 +1570,8 @@ fs_generator::generate_code(exec_list *instructions)
    }
 
    if (!shader || prog->Name != 0) {
-      fprintf(stderr, "SIMD%d shader: %d instructions. %d loops.\n",
-                      dispatch_width, (last_native_insn_offset - beginning_offset) / 16, loops);
+      fprintf(stderr, "SIMD%d shader: %d instructions. %d loops. %d BB. %d CFG calculations\n",
+                      dispatch_width, (last_native_insn_offset - beginning_offset) / 16, loops, cfg->num_blocks, num_cfg);
    }
 
    brw_set_uip_jip(p);
@@ -1589,10 +1589,11 @@ fs_generator::generate_code(exec_list *instructions)
 const unsigned *
 fs_generator::generate_assembly(exec_list *simd8_instructions,
                                 exec_list *simd16_instructions,
+                                int simd8_num_cfg, int simd16_num_cfg,
                                 unsigned *assembly_size)
 {
    dispatch_width = 8;
-   generate_code(simd8_instructions);
+   generate_code(simd8_instructions, simd8_num_cfg);
 
    if (simd16_instructions) {
       /* We have to do a compaction pass now, or the one at the end of
@@ -1612,7 +1613,7 @@ fs_generator::generate_assembly(exec_list *simd8_instructions,
       brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
 
       dispatch_width = 16;
-      generate_code(simd16_instructions);
+      generate_code(simd16_instructions, simd16_num_cfg);
    }
 
    return brw_get_program(p, assembly_size);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 9f37013bddf..41e9a79c4c7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2666,6 +2666,7 @@ fs_visitor::fs_visitor(struct brw_context *brw,
                        unsigned dispatch_width)
    : dispatch_width(dispatch_width)
 {
+   this->num_cfg = 0;
    this->c = c;
    this->brw = brw;
    this->fp = fp;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index 7cebf1ffdd1..eddbbc519ba 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -65,6 +65,8 @@ public:
    /** ralloc context for temporary data used during compile */
    void *mem_ctx;
 
+   int num_cfg;
+
    /**
     * List of either fs_inst or vec4_instruction (inheriting from
     * backend_instruction)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index d3ee9a1f4c9..c8e5bb6ae79 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1575,6 +1575,7 @@ brw_vs_emit(struct brw_context *brw,
    vec4_generator g(brw, prog, &c->vp->program.Base, &prog_data->base, mem_ctx,
                     INTEL_DEBUG & DEBUG_VS);
    const unsigned *generated =g.generate_assembly(&v.instructions,
+                                                  v.num_cfg,
                                                   final_assembly_size);
 
    if (unlikely(brw->perf_debug) && shader) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 6261494b333..14613566278 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -549,10 +549,10 @@ public:
                   bool debug_flag);
    ~vec4_generator();
 
-   const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
+   const unsigned *generate_assembly(exec_list *insts, int num_cfg, unsigned *asm_size);
 
 private:
-   void generate_code(exec_list *instructions);
+   void generate_code(exec_list *instructions, int num_cfg);
    void generate_vec4_instruction(vec4_instruction *inst,
                                   struct brw_reg dst,
                                   struct brw_reg *src,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 892327bd0e8..a42cc5b21b4 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -21,6 +21,7 @@
  */
 
 #include "brw_vec4.h"
+#include "brw_cfg.h"
 
 extern "C" {
 #include "brw_eu.h"
@@ -1146,7 +1147,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
 }
 
 void
-vec4_generator::generate_code(exec_list *instructions)
+vec4_generator::generate_code(exec_list *instructions, int num_cfg)
 {
    int last_native_insn_offset = 0;
    int loops = 0;
@@ -1206,17 +1207,18 @@ vec4_generator::generate_code(exec_list *instructions)
    }
 
    if (unlikely(debug_flag)) {
+      cfg_t *cfg = new(mem_ctx) cfg_t(mem_ctx, instructions);
       if (shader) {
          printf("Native code for vertex shader %d:\n", shader_prog->Name);
          if (shader_prog->Name != 0) {
-            fprintf(stderr, "vec4 shader: %d instructions. %d loops.\n",
-                            last_native_insn_offset / 16, loops);
+            fprintf(stderr, "vec4 shader: %d instructions. %d loops. %d BB. %d CFG calculations\n",
+                            last_native_insn_offset / 16, loops, cfg->num_blocks, num_cfg);
          }
       } else {
          printf("Native code for vertex program %d:\n", prog->Id);
          if (prog->Id != 0) {
-            fprintf(stderr, "vec4 shader: %d instructions. %d loops.\n",
-                            last_native_insn_offset / 16, loops);
+            fprintf(stderr, "vec4 shader: %d instructions. %d loops. %d BB. %d CFG calculations\n",
+                            last_native_insn_offset / 16, loops, cfg->num_blocks, num_cfg);
          }
       }
    }
@@ -1235,10 +1237,11 @@ vec4_generator::generate_code(exec_list *instructions)
 
 const unsigned *
 vec4_generator::generate_assembly(exec_list *instructions,
+                                  int num_cfg,
                                   unsigned *assembly_size)
 {
    brw_set_access_mode(p, BRW_ALIGN_16);
-   generate_code(instructions);
+   generate_code(instructions, num_cfg);
    return brw_get_program(p, assembly_size);
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 96636e8838b..3b0b8acf4c7 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -542,7 +542,7 @@ brw_gs_emit(struct brw_context *brw,
    vec4_generator g(brw, prog, &c->gp->program.Base, &c->prog_data.base,
                     mem_ctx, INTEL_DEBUG & DEBUG_GS);
    const unsigned *generated =
-      g.generate_assembly(&v.instructions, final_assembly_size);
+      g.generate_assembly(&v.instructions, v.num_cfg, final_assembly_size);
 
    return generated;
 }
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 231815f12d4..9e0e9bef695 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -3146,6 +3146,7 @@ vec4_visitor::vec4_visitor(struct brw_context *brw,
                            bool debug_flag)
    : debug_flag(debug_flag)
 {
+   this->num_cfg = 0;
    this->brw = brw;
    this->ctx = &brw->ctx;
    this->shader_prog = shader_prog;