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authorIan Romanick <ian.d.romanick@intel.com>2019-03-25 16:31:51 -0700
committerIan Romanick <ian.d.romanick@intel.com>2019-03-26 10:29:22 -0700
commitf7a4275a5c51c6d54ef19a4a60062ec71afb553d (patch)
tree0c3a4aa3ac51fe11e61b73ddb4c638e30c58cefb
parent74164bc7eb6f1d4febb41d7a9c8d1fc18af9cb12 (diff)
squash! WIP: intel/compiler: Begin using code generator generator for Gen8 and Gen9
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 4eaebc945c45..bcd15dbfe3d4 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -878,6 +878,13 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
break;
}
+ assert((devinfo->gen != 9 && devinfo->gen != 8) ||
+ instr->op == nir_op_imov ||
+ instr->op == nir_op_fmov ||
+ instr->op == nir_op_vec2 ||
+ instr->op == nir_op_vec3 ||
+ instr->op == nir_op_vec4);
+
fs_reg op[4];
fs_reg result = prepare_alu_destination_and_sources(bld, instr, op, true);