diff options
author | Ian Romanick <ian.d.romanick@intel.com> | 2019-02-19 20:55:59 -0800 |
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committer | Ian Romanick <ian.d.romanick@intel.com> | 2019-03-26 10:29:22 -0700 |
commit | 2aeb95135e88bccb1be15f3e86d4de0e5202d811 (patch) | |
tree | 369266f0d7b21a039051694a525c6a6210504812 | |
parent | d1a9aba61bd7f4c8a6d61821fe98df5faaa5a488 (diff) |
WIP: intel/compiler: Import Gen8 / Gen9 ALU machine description
-rw-r--r-- | src/intel/compiler/gen8_md.py | 169 | ||||
-rw-r--r-- | src/intel/compiler/meson.build | 11 |
2 files changed, 179 insertions, 1 deletions
diff --git a/src/intel/compiler/gen8_md.py b/src/intel/compiler/gen8_md.py new file mode 100644 index 000000000000..30cd05cc3ce9 --- /dev/null +++ b/src/intel/compiler/gen8_md.py @@ -0,0 +1,169 @@ +# +# Copyright (C) 2019 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. + +import gen_gen_codegen +from math import ldexp +from gen_gen_codegen import retype, abs, grf, imm, neg, null, subscript, Instruction, InstructionList + +# Convenience variables +a = 'a' +b = 'b' +c = 'c' +d = 'd' +r = 'r' + +t0 = 't0' +t1 = 't1' +zero = 'zero' + +B = 'B' +UB = 'UB' +W = 'W' +UW = 'UW' +D = 'D' +UD = 'UD' +Q = 'Q' +UQ = 'UQ' +F = 'F' +DF = 'DF' +HF = 'HF' +result_type = 'VF' + +gen8_md = [ + # General arithmetic + (('fadd', a, b), Instruction('ADD', r, a, b)), + (('iadd', a, b), Instruction('ADD', r, a, b)), + (('uadd_sat', a, b), Instruction('ADD', r, a, b).saturate()), + (('fmul', a, b), Instruction('MUL', r, a, b)), + (('imul_2x32_64', a, b), Instruction('MUL', r, a, b)), + (('umul_2x32_64', a, b), Instruction('MUL', r, a, b)), + (('imul', a, b), Instruction('MUL', r, a, b)), + (('imul_high', a, b), Instruction('SHADER_OPCODE_MULH', r, a, b)), + (('umul_high', a, b), Instruction('SHADER_OPCODE_MULH', r, a, b)), + (('idiv', a, b), Instruction('SHADER_OPCODE_INT_QUOTIENT', r, a, b)), + (('udiv', a, b), Instruction('SHADER_OPCODE_INT_QUOTIENT', r, a, b)), + (('irem', a, b), Instruction('SHADER_OPCODE_INT_REMAINDER', r, a, b)), + (('umod', a, b), Instruction('SHADER_OPCODE_INT_REMAINDER', r, a, b)), + + (('imod', a, b), InstructionList([(t0, D), ], + (# Get a regular C-style remainder. If a % b == 0, set the predicate. + Instruction('SHADER_OPCODE_INT_REMAINDER', r, a, b), + + # Math instructions don't support conditional mod + Instruction('MOV', null(D), r).cmod('NZ'), + + # Now, we need to determine if signs of the sources are different. + # When we XOR the sources, the top bit is 0 if they are the same and 1 + # if they are different. We can then use a conditional modifier to + # turn that into a predicate. This leads us to an XOR.l instruction. + # + # Technically, according to the PRM, you're not allowed to use .l on a + # XOR instruction. However, emperical experiments and Curro's reading + # of the simulator source both indicate that it's safe. + Instruction('XOR', t0, a, b).predicate().cmod('L'), + + # If the result of the initial remainder operation is non-zero and the + # two sources have different signs, add in a copy of op[1] to get the + # final integer modulus value. + Instruction('ADD', r, r, b).predicate())) + ), + + # 3-source arithmetic + (('ffma', a, b, c), Instruction('MAD', r, c, b, a)), + (('flrp', a, b, c), Instruction('LRP', r, c, b, a)), + + # Trig / exponent / log / etc. + (('frcp', a), Instruction('SHADER_OPCODE_RCP', r, a)), + (('fpow', a, b), Instruction('SHADER_OPCODE_POW', r, a, b)), + (('fexp2', a), Instruction('SHADER_OPCODE_EXP2', r, a)), + (('flog2', a), Instruction('SHADER_OPCODE_LOG2', r, a)), + (('fsin', a), Instruction('SHADER_OPCODE_SIN', r, a)), + (('fcos', a), Instruction('SHADER_OPCODE_COS', r, a)), + (('fsqrt', a), Instruction('SHADER_OPCODE_SQRT', r, a)), + (('frsq', a), Instruction('SHADER_OPCODE_RSQ', r, a)), + + # Rounding + (('ftrunc', a), Instruction('RNDZ', r, a)), + (('fceil', a), InstructionList([(t0, F)], + (Instruction('RNDD', t0, neg(a)), + Instruction('MOV', r, neg(t0)))) + ), + (('ffloor', a), Instruction('RNDD', r, a)), + (('ffract', a), Instruction('FRC', r, a)), + (('fround_even', a), Instruction('RNDE', r, a)), +] + +gen8_unsupported = [ + ('uadd_carry', "Should have been lowered by carry_to_arith()."), + ('usub_borrow', "Should have been lowered by borrow_to_arith()."), + (['fdot2', + 'fdot3', + 'fdot4', + 'b32all_fequal2', + 'b32all_iequal2', + 'b32all_fequal3', + 'b32all_iequal3', + 'b32all_fequal4', + 'b32all_iequal4', + 'b32any_fnequal2', + 'b32any_inequal2', + 'b32any_fnequal3', + 'b32any_inequal3', + 'b32any_fnequal4', + 'b32any_inequal4'], + "Lowered by nir_lower_alu_reductions"), + (['fnoise1_1', + 'fnoise1_2', + 'fnoise1_3', + 'fnoise1_4', + 'fnoise2_1', + 'fnoise2_2', + 'fnoise2_3', + 'fnoise2_4', + 'fnoise3_1', + 'fnoise3_2', + 'fnoise3_3', + 'fnoise3_4', + 'fnoise4_1', + 'fnoise4_2', + 'fnoise4_3', + 'fnoise4_4'], + "not reached: should be handled by lower_noise"), + ('ldexp', "not reached: should be handled by ldexp_to_arith()"), + (['pack_snorm_2x16', + 'pack_snorm_4x8', + 'pack_unorm_2x16', + 'pack_unorm_4x8', + 'unpack_snorm_2x16', + 'unpack_snorm_4x8', + 'unpack_unorm_2x16', + 'unpack_unorm_4x8', + 'unpack_half_2x16', + 'pack_half_2x16'], + "not reached: should be handled by lower_packing_builtins"), + (['ubitfield_extract', + 'ibitfield_extract'], + "should have been lowered"), + ('bitfield_insert', "not reached: should have been lowered"), +] + +print(gen_gen_codegen.CodeGeneratorGenerator("gen8", gen8_md, gen8_unsupported).render()) diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build index d0bec0fccf28..8866631557c1 100644 --- a/src/intel/compiler/meson.build +++ b/src/intel/compiler/meson.build @@ -131,9 +131,18 @@ brw_nir_trig = custom_target( capture : true, ) +gen8_md = custom_target( + 'gen8_md.h', + input : 'gen8_md.py', + output : 'gen8_md.h', + command : [ prog_python, '@INPUT@' ], + depend_files : ['gen_gen_codegen.py'], + capture : true, +) + libintel_compiler = static_library( 'intel_compiler', - [libintel_compiler_files, brw_nir_trig, ir_expression_operation_h], + [libintel_compiler_files, brw_nir_trig, gen8_md, ir_expression_operation_h], include_directories : [inc_common, inc_intel], c_args : [c_vis_args, no_override_init_args], cpp_args : [cpp_vis_args], |