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| author | Ian Romanick <ian.d.romanick@intel.com> | 2019-02-25 15:42:35 -0800 |
|---|---|---|
| committer | Ian Romanick <ian.d.romanick@intel.com> | 2019-03-26 10:29:22 -0700 |
| commit | 25d4436a07f8bb6665a1e3fdb6a556555c5b5007 (patch) | |
| tree | 2897cdff147dfe562daad312affae2a8aa1a6f7d | |
| parent | 7bdd85581b77608e6c64a99f2534bb250fc65785 (diff) | |
fsign
squash! WIP: intel/compiler: Import Gen8 / Gen9 ALU machine description
| -rw-r--r-- | src/intel/compiler/gen8_md.py | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/intel/compiler/gen8_md.py b/src/intel/compiler/gen8_md.py index 7ba80f3d1127..b1173baf1e94 100644 --- a/src/intel/compiler/gen8_md.py +++ b/src/intel/compiler/gen8_md.py @@ -306,6 +306,29 @@ gen8_md = [ (('fsqrt', a), Instruction('SHADER_OPCODE_SQRT', r, a)), (('frsq', a), Instruction('SHADER_OPCODE_RSQ', r, a)), + # Straightforward since the source can be assumed to be strictly >= 0 + (('fsign', 'a(abs_src_mod)'), InstructionList([], + (Instruction('MOV', r, a).cmod('NZ'), + Instruction('MOV', r, imm(1.0, F)).predicate())) + ), + # Straightforward since the source can be assumed to be strictly <= 0 + (('fsign', 'a(neg_abs_src_mod)'), InstructionList([], + (Instruction('MOV', r, a).cmod('NZ'), + Instruction('MOV', r, imm(-1.0, F)).predicate())) + ), + (('fsign', 'a@32'), InstructionList([], + (Instruction('CMP', null(F), a, imm(0.0, F)).cmod('NZ'), + Instruction('AND', retype(r, UD), retype(a, UD), imm(0x80000000, UD)), + Instruction('OR', retype(r, UD), retype(r, UD), imm(0x3f800000, UD)).predicate())) + ), + (('fsign', 'a@64'), InstructionList([(zero, DF), ], + (Instruction('MOV', zero, imm(0.0, DF)), + Instruction('CMP', null(DF), a, zero).cmod('NZ'), + Instruction('MOV', r, zero), + Instruction('AND', subscript(r, UD, 1), subscript(a, UD, 1), imm(0x80000000, UD)), + Instruction('OR', subscript(r, UD, 1), subscript(r, UD, 1), imm(0x3f800000, UD)).predicate())) + ), + # Rounding (('ftrunc', a), Instruction('RNDZ', r, a)), (('fceil', a), InstructionList([(t0, F)], |