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2017-03-03Merge tag 'armsoc-late' of ↵Linus Torvalds1-0/+6
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late DT updates from Arnd Bergmann: "These updates have been kept in a separate branch mostly because they rely on updates to the respective clk drivers to keep the shared header files in sync. This includes two branches for arm64 dt updates, both following up on earlier changes for the same platforms that are already merged: Samsung: - add USB3 support in Exynos7 - minor PM related updates Amlogic: - new machines: WeTek Set-top-boxes - various devices added to DT There are also a couple of bugfixes that trickled in since the start of the merge window: - The moxart_defconfig was not building the intended platform - CPU-hotplug was broken on ux500 - Coresight was broken on Juno (never worked)" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits) ARM: deconfig: fix the moxart defconfig ARM: ux500: resume the second core properly arm64: dts: juno: update definition for programmable replicator arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7 pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ...
2017-03-02Merge branch 'next/late' with mainlineArnd Bergmann2-1/+10
* next/late: (25 commits) arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7 pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ARM64: dts: meson-gxbb-vega-s95: Add LED ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-02-25Merge tag 'clk-for-linus' of ↵Linus Torvalds20-364/+1201
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The usual collection of new drivers, non-critical fixes, and updates to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits) clk: renesas: mstp: ensure register writes complete clk: qcom: Do not drop device node twice clk: mvebu: adjust clock handling for the CP110 system controller clk: mvebu: Expand mv98dx3236-core-clock support clk: zte: add i2s clocks for zx296718 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i clk: sunxi-ng: Check kzalloc() for errors and cleanup error path clk: tegra: Add BPMP clock driver clk: uniphier: add eMMC clock for LD11 and LD20 SoCs clk: uniphier: add NAND clock for all UniPhier SoCs ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: qcom: SDHCI enablement on Nexus 5X / 6P ...
2017-02-16Merge tag 'amlogic-dt64-2' of ↵Arnd Bergmann1-0/+6
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/late Pull "Amlogic DT updates for v4.11, round 2" from Kevin Hilman: - add SAR ADC driver - add ADC laddered keys to meson-gxbb-p200 board * tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ARM64: dts: meson-gxbb-vega-s95: Add LED ARM64: dts: meson-gx: add the serial CTS and RTS pin groups ARM64: dts: meson-gx: add the missing uart_AO_B clk: meson-gxbb: Export HDMI clocks ARM64: dts: meson-gxm: add SCPI configuration for GXM ARM64: dts: meson-gx: move the SCPI and SRAM nodes to meson-gx
2017-02-03Merge tag 'v4.11-rockchip-clk2' of ↵Stephen Boyd1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: "Non-critical fix for the pclk_edp divider on rk3399, one new clock-id and making niu (interconnect) clocks critical on rk3288, as CLK_IGNORE_UNUSED is not enough to keep them running all the time when more users access particular clock subtrees." * tag 'v4.11-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3288: make all niu clocks critical clk: rockchip: use rk3288 vip_out clock ids clk: rockchip: add rk3288 vip_out clock id clk: rockchip: fix the incorrect pclk_edp div width for RK3399
2017-02-03Merge tag 'sunxi-clk-for-4.11' of ↵Stephen Boyd5-0/+511
https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock updates from Maxime Ripard: - Support for one new SoC, the V3s - Conversion of two old SoCs to the new framework, the old sun5i family and the A80 - A bunch of fixes * tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits) ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU clk: sunxi-ng: Call divider_round_rate if we only have a single parent ARM: gr8: Convert to CCU ARM: sun5i: Convert to CCU clk: sunxi-ng: Add sun5i CCU driver clk: sunxi-ng: Implement global pre-divider clk: sunxi-ng: Implement multiplier maximum clk: sunxi-ng: mult: Fix minimum in round rate clk: sunxi-ng: Implement factors offsets clk: sunxi-ng: multiplier: Add fractional support clk: sunxi-ng: add support for V3s CCU dt-bindings: add device binding for the CCU of Allwinner V3s ...
2017-01-30clk: sunxi-ng: Add A80 Display Engine CCUChen-Yu Tsai1-0/+80
With the A80 SoC, Allwinner grouped and moved some subsystem specific clock controls to a separate address space, and possibly separate hardware block. One such subsystem is the display engine. The main clock control unit now only has 1 set of bus gate, dram gate, module clock, and reset control for the entire display subsystem. These feed into a secondary clock control unit, which has controls for each individual module of the display pipeline. This block is not documented in the user manual. Allwinner's kernel was used as the reference. Add support for the display engine clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30clk: sunxi-ng: Add A80 USB CCUChen-Yu Tsai1-0/+59
Add support for the USB clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30clk: sunxi-ng: Add A80 CCUChen-Yu Tsai1-0/+162
Add support for the main clock unit found in the A80. Some clocks were not documented in the released user manual, but were found in the official kernel from Allwinner. These include controls for the I2S, SPDIF, SATA, and eDP blocks. Note that on the A80, some subsystems have separate clock controllers downstream of the main clock unit. These include the MMC, USB, and display engine subsystems. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-29Merge tag 'renesas-dt2-for-v4.11' of ↵Olof Johansson1-0/+4
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Second Round of Renesas ARM Based SoC DT Updates for v4.11 Enhancements: - Add power-domains to mmcif on r7s72100 SoC - Add OSTM to rskrza1/r7s72100 - Link ARM GIC to clock and clock domain on r8a774[35] SoCs Clean-up: - Correct SATA device status on r8a7779/marzen * tag 'renesas-dt2-for-v4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: dts: r7s72100: add power-domains to mmcif ARM: dts: rskrza1: add ostm DT support ARM: dts: r7s72100: add ostm to device tree ARM: dts: r7s72100: add ostm clock to device tree ARM: dts: r8a7745: Link ARM GIC to clock and clock domain ARM: dts: r8a7743: Link ARM GIC to clock and clock domain ARM: dts: r8a7779, marzen: Fix sata device status Signed-off-by: Olof Johansson <olof@lixom.net>
2017-01-27dt-bindings: qcom: clk: Add missing binding for SDCHI enablement on Nexus 5X/6PJeremy McNicoll1-0/+1
AHB clock branch is needed in order to enable SDHCI on msm899(2/4). Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-27Merge tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung into ↵Stephen Boyd1-1/+4
clk-next Pull Samsung clk driver updates from Sylwester Nawrocki: - Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY - Exynos PLL code updates and overall minor clean-ups * tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung: clk: samsung: mark s3c...._clk_sleep_init() as __init clk: samsung: Add enable/disable support for PLL35XX clocks clk: samsung: exynos5433: Correct typos in SoC name clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
2017-01-27clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocksMarek Szyprowski1-1/+4
Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed to setup initial clock configuration for display subsystem in device tree in order to avoid dependency on the configuration left by the bootloader. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-26Merge branch 'clk-ux500' into clk-nextStephen Boyd1-0/+11
* clk-ux500: clk: ux500: Convert ABx500 clocks to use OF probing clk: ux500: Add device tree bindings for ABx500 clocks clk: ux500: move AB8500 sysclk over to PRCMU clk driver
2017-01-26clk: ux500: Convert ABx500 clocks to use OF probingLinus Walleij1-0/+11
These clocks have been broken for a long time unfortunately, a hurdle of misc problems made them stop working at some point breaking USB and audio on Ux500. The platform as such and all "regular" clocks are migrated to OF/device tree, so let's migrate also this driver. With this patch and the corresponding DTS fixes, and a bunch of probe deferral fixes, audio starts working again on Ux500. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26Merge branch 'clk-stm32f4' into clk-nextStephen Boyd1-0/+20
* clk-stm32f4: clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boards
2017-01-26Merge branch 'clk-imx7', 'clk-bcm2835' into clk-nextStephen Boyd2-1/+4
* clk-imx7: clk: imx7d: Add the OCOTP clock * clk-bcm2835: clk: bcm2835: Add leaf clock measurement support, disabled by default clk: bcm2835: Register the DSI0/DSI1 pixel clocks. clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.
2017-01-24ARM: dts: r7s72100: add ostm clock to device treeChris Brandt1-0/+4
Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-01-23clk: gxbb: add the SAR ADC clocks and expose themMartin Blumenstingl1-0/+4
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-23clk: sunxi-ng: Add sun5i CCU driverMaxime Ripard1-0/+103
The Allwinner A10s, A13, R8 and NextThing GR8 are all based on the same silicon, and all share the same clocks. However, they're not packaged in the same way, and therefore not all the controllers are actually available on all these SoCs. Introduce a clock controller driver for all these SoCs with different compatibles to take that into account. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-22clk: rockchip: add rk3288 vip_out clock idJacob Chen1-0/+1
Add clock-ids for the vip block of the rk3288 Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-20clk: stm32f7: Add stm32f7 clock DT bindings for STM32F746 boardsGabriel Fernandez1-0/+20
This patch introduces the stm32f7 clock DT bindings. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: imx7d: Add the OCOTP clockFabio Estevam1-1/+2
Add the OCOTP so that this hardware block can be used. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20clk: bcm2835: Register the DSI0/DSI1 pixel clocks.Eric Anholt1-0/+2
The DSI pixel clocks are muxed from clocks generated in the analog phy by the DSI driver. In order to set them as parents, we need to do the same name lookup dance on them as we do for our root oscillator. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20Merge tag 'v4.11-rockchip-clk1' of ↵Stephen Boyd3-0/+403
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: A new clock-type for the 1-2 muxes per soc that are for whatever reason controlled through the General Register Files, support for the rk3328 clock-controller (including a new pll-type) and the usual clock ids and some fixes. * tag 'v4.11-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: clk: add rockchip,grf property for RK3399 clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: use rk3288 isp_in clock ids clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188 clk: rockchip: add rk3288 isp_in clock ids clk: rockchip: Remove useless init of "grf" to -EPROBE_DEFER clk: rockchip: add clock controller for rk3328 dt-bindings: add bindings for rk3328 clock controller clk: rockchip: add dt-binding header for rk3328 clk: rockchip: add new pll-type for rk3328 clk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288 clk: rockchip: add a clock-type for muxes based in the grf
2017-01-20Merge tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung into ↵Stephen Boyd1-360/+0
clk-next Pull Samsung clk updates from Sylwester Nawrocki: - addition of the CPU clock configuration data for Exynos4412 Prime SoC variant, - removal of driver for deprecated Exynos4415 SoC, - switching from the syscore to regular system sleep PM ops in the audio subsystem clocks controller driver, - updates of the definitions of some "Network On Chip" related clocks. * tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung: clk: samsung: Remove Exynos4415 driver (SoC not supported anymore) clk: samsung: exynos-audss: Replace syscore PM with platform device PM clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
2017-01-20clk: sunxi-ng: add support for V3s CCUIcenowy Zheng1-0/+107
V3s has a similar but cut-down CCU to H3. Some muxes, especially clocks about CSI, are different, which makes it to need a new CCU driver. Add such a new driver for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-18clk: meson-gxbb: Export HDMI clocksNeil Armstrong1-0/+2
Export HDMI clock from internal to dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-16clk: samsung: Remove Exynos4415 driver (SoC not supported anymore)Krzysztof Kozlowski1-360/+0
Support for Exynos4415 is going away because there are no internal nor external users. Since commit 46dcf0ff0de3 ("ARM: dts: exynos: Remove exynos4415.dtsi"), the platform cannot be instantiated so remove also the drivers. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Kukjin Kim <kgene@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-13clk: rockchip: add clock ids for memory controller parts on rk3066/rk3188Heiko Stuebner1-0/+2
Add clock ids for the upctl and publ controllers used for ddr control. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13clk: rockchip: add rk3288 isp_in clock idsJacob Chen1-0/+1
Add clock-ids for the isp block of the rk3288. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-10clk: stm32f4: Update DT bindings documentationGabriel Fernandez1-0/+39
Creation of dt include file for specific stm32f4 clocks. These specific clocks are not derived from system clock (SYSCLOCK) We should use index 1 to use these clocks in DT. e.g. <&rcc 1 CLK_LSI> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org>
2017-01-09clk: mdm9615: Add EBI2 clockZoran Markovic1-0/+2
Add definition of EBI2 clock used by MDM9615 NAND controller. Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> [sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09Merge branch 'clk-hi3660' into clk-nextStephen Boyd1-0/+194
* clk-hi3660: clk: hisilicon: Add clock driver for hi3660 SoC dt-bindings: Document the hi3660 clock bindings
2017-01-09clk: hisilicon: Add clock driver for hi3660 SoCZhangfei Gao1-0/+194
Add clock drivers for hi3660 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Simplify probe with function pointer] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: qcom: Add GCC_MSS_RESET supportAvaneesh Kumar Dwivedi1-0/+1
Add support to use reset control framework for resetting MSS with hexagon v56 1.5.0. Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09Merge branches 'clk-qcom-rpm8974', 'clk-stm32f4', 'clk-ipq4019' and ↵Stephen Boyd3-2/+88
'clk-fixes' into clk-next * clk-qcom-rpm8974: clk: qcom: smd-rpmcc: Add msm8974 clocks * clk-stm32f4: clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board clk: stm32f4: Add SAI clocks clk: stm32f4: Add I2S clock clk: stm32f4: Add lcd-tft clock clk: stm32f4: Add post divisor for I2S & SAI PLLs clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards clk: stm32f4: Update DT bindings documentation * clk-ipq4019: clk: qcom: ipq4019: Add the cpu clock frequency change notifier clk: qcom: ipq4019: Add all the frequencies for apss cpu clk: qcom: ipq4019: correct sdcc frequency and parent name clk: qcom: ipq4019: Add the nodes for pcnoc clk: qcom: ipq4019: Add the apss cpu pll divider clock node clk: qcom: ipq4019: remove fixed clocks and add pll clocks * clk-fixes: clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method clk: renesas: mstp: Support 8-bit registers for r7s72100
2017-01-05clk: rockchip: add dt-binding header for rk3328Elaine Zhang1-0/+400
Add the dt-bindings header for the rk3328, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3328. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-12-21clk: stm32f4: Update DT bindings documentationGabriel Fernandez1-0/+39
Creation of dt include file for specific stm32f4 clocks. These specific clocks are not derived from system clock (SYSCLOCK) We should use index 1 to use these clocks in DT. e.g. <&rcc 1 CLK_LSI> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: smd-rpmcc: Add msm8974 clocksBjorn Andersson1-2/+38
This adds all RPM based clocks for msm8974, except cxo and gfx3d_clk_src. Tested-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: Add the nodes for pcnocAbhishek Sahu1-0/+1
The current ipq4019 clock driver does not have the node for PCNOC so this patch adds and registers the PCNOC clock nodes. This PCNOC clock is critical and should not be turned off so setting CRITICAL flag also. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: Add the apss cpu pll divider clock nodeAbhishek Sahu1-0/+1
The current ipq4019 clock driver does not have support for all the frequency supported by APSS CPU. APSS CPU frequency is provided with APSS CPU PLL divider which divides down the VCO frequency. This divider is nonlinear and specific to IPQ4019 so the standard divider code cannot be used for this. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-21clk: qcom: ipq4019: remove fixed clocks and add pll clocksAbhishek Sahu1-0/+9
The current ipq4019 clock driver registered the PLL clocks and dividers as fixed clock. These fixed clock needs to be removed from driver probe function and same need to be registered with clock framework. These PLL clocks should be programmed only once and the same are being programmed already by the boot loader so the set rate operation is not required for these clocks. Only the rate can be calculated by clock operations in clock driver file so this patch adds the same. The PLL takes the reference clock from XO and generates the intermediate VCO frequency. This VCO frequency will be divided down by different PLL internal dividers. Some of the PLL internal dividers are fixed while other are programmable. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-12-15Merge tag 'armsoc-drivers' of ↵Linus Torvalds1-0/+940
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, including a couple of newly added drivers: - A new driver for the power management controller on TI Keystone - Support for the prerelease "SCPI" firmware protocol that ended up being shipped by Amlogic in their GXBB SoC. - A soc_device can now be matched using a glob from inside the kernel, when another driver wants to know the specific chip it is running on and cannot find out from DT, firmware or hardware. - Renesas SoCs now support identification through the soc_device interface, both in user space and kernel. - Renesas r8a7743 and r8a7745 gain support for their system controller - A new checking module for the ARM "PSCI" (not to be confused with "SCPI" mentioned above) firmware interface. - A new driver for the Tegra GMI memory interface - Support for the Tegra firmware interfaces with their power management controllers As usual, the updates for the reset controller framework are merged here, as they tend to touch multiple SoCs as well, including a new driver for the Oxford (now Broadcom) OX820 chip and the Tegra bpmp interface. The existing drivers for Atmel, Qualcomm, NVIDIA, TI Davinci, and Rockchips SoCs see some further updates" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (76 commits) misc: sram: remove useless #ifdef drivers: psci: Allow PSCI node to be disabled drivers: psci: PSCI checker module soc: renesas: Identify SoC and register with the SoC bus firmware: qcom: scm: Return PTR_ERR when devm_clk_get fails firmware: qcom: scm: Remove core, iface and bus clocks dependency dt-bindings: firmware: scm: Add MSM8996 DT bindings memory: da8xx-ddrctl: drop the call to of_flat_dt_get_machine_name() bus: da8xx-mstpri: drop the call to of_flat_dt_get_machine_name() ARM: shmobile: Document DT bindings for Product Register soc: renesas: rcar-sysc: add R8A7745 support reset: Add Tegra BPMP reset driver dt-bindings: firmware: Allow child nodes inside the Tegra BPMP dt-bindings: Add power domains to Tegra BPMP firmware firmware: tegra: Add BPMP support firmware: tegra: Add IVC library dt-bindings: firmware: Add bindings for Tegra BPMP mailbox: tegra-hsp: Use after free in tegra_hsp_remove_doorbells() mailbox: Add Tegra HSP driver firmware: arm_scpi: add support for pre-v1.0 SCPI compatible ...
2016-12-15Merge tag 'armsoc-dt' of ↵Linus Torvalds3-18/+8
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together. We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board: - Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors These are commercially available consumer platforms we now support: - Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385 And a couple of new boards targeted at developers, makers or industrial integration: - Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module Other changes: - added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq - Continued fixes for W=1 dtc warnings - The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST - The exynos4415 dtsi file is removed as nothing uses it. - Intel PXA25x can now be booted using devicetree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...
2016-12-06Merge tag 'v4.10-rockchip-clk2' of ↵Stephen Boyd1-0/+269
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: A new clock controller for the rk1108 soc (single-core Cortex-A7+DSP), a fix making sure the cpuclk rate is actually valid, before trying to set it and a copy-paste fix for the rk3399's testclk. * tag 'v4.10-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add clock controller for rk1108 dt-bindings: add documentation for rk1108 cru clk: rockchip: add dt-binding header for rk1108 clk: rockchip: fix copy-paste error in rk3399 testclk clk: rockchip: validity should be checked prior to cpu clock rate change
2016-11-30Merge tag 'v4.10-rockchip-dts32-2' of ↵Arnd Bergmann1-0/+269
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Pull "Rockchip dts32 changes for 4.10" from Heiko Stübner: A bit of attention for the rk3066, fixed tsadc reset node as well as enabling the dma for uart and mmc controllers. And one new soc, the rk1108 combining a single-core Cortex-A7 with a separate DSP core. * tag 'v4.10-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: add the sdmmc pinctrl for rk1108 ARM: dts: rockchip: add rockchip RK1108 Evaluation board ARM: dts: rockchip: add basic support for RK1108 SOC clk: rockchip: add dt-binding header for rk1108 dt-bindings: rockchip-dw-mshc: add RK1108 dw-mshc description ARM: dts: rockchip: enable dma for uart and mmc on rk3066a ARM: dts: rockchip: fix TSADC reset node for rk3066a
2016-11-30Merge tag 'rzg-clock-defs-tag1' of ↵Arnd Bergmann2-0/+87
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into next/dt Pull "Renesas RZ/G1M and RZ/G1E CPG Core Clock Definitions" from Geert Uytterhoeven: Shared by clock drivers, and DTS files. * tag 'rzg-clock-defs-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: Add r8a7745 CPG Core Clock Definitions clk: renesas: Add r8a7743 CPG Core Clock Definitions
2016-11-18dt-bindings: firmware: Add bindings for Tegra BPMPJoseph Lo1-0/+940
The Boot and Power Management Processor (BPMP) is a co-processor found in Tegra SoCs. It is designed to handle the early stages of the boot process as well as to offload power management tasks (such as clocks, resets, powergates, ...). The binding document defines the resources that are used by the BPMP firmware, which implements the interprocessor communication (IPC) between the CPU and the BPMP. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-17Merge tag 'v4.10-rockchip-dts32-1' of ↵Olof Johansson1-1/+7
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt 32bit devicetree changes for Rockchip including removal of skeleton.dtsi inclusion, missing unit names for memory nodes, various frequency optimizations allowing for better performance on rk3066, the usage of pin constants to bridge between the two numbering schemes used (gpio controllers using 0-31 and pins being labeled A0-A7,..., D0-D7) and UHS/HS modes for the mmc controllers on the popmetal board. Two new boards, the PX3-based evaluation board, with the PX3 being an industrial variant of the rk3188 soc and the Rikomagic MK808 board based around the rk3066 are also added. * tag 'v4.10-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (21 commits) ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max" ARM: dts: rockchip: Set sdmmc frequency at boot time for rk3066a ARM: dts: rockchip: use pin constants to describe gpios on Popmetal-RK3288 include: dt-bindings: Add GPIO pin index definition for rockchip pinctrl ARM: dts: rockchip: Add rk3066 MK808 board devicetree: Add vendor prefix for Rikomagic ARM: dts: rockchip: initialize rk3066 PLL clock rate clk: rockchip: Add binding ids for cpu and peri clocks on rk3066 ARM: dts: rockchip: enable HS200/DDR52 mode for emmc on rk3288-popmetal ARM: dts: rockchip: Support UHS mode for SD card on PopMetal-RK3288 board ARM: dts: rockchip: remove always-on and boot-on from vcc_sd for px3-evb ARM: dts: rockchip: update compatible strings for Rockchip efuse ARM: dts: rockchip: add rockchip PX3 Evaluation board ARM: dts: rockchip: Add missing unit name to memory nodes in rk3xxx boards ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards ARM: dts: rockchip: Add missing unit name to memory nodes in rk322x boards ARM: dts: rockchip: Add missing unit name to memory nodes in rk3036 boards ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3xxx.dtsi ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3288.dtsi ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk322x.dtsi ... Signed-off-by: Olof Johansson <olof@lixom.net>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-25 07:24:46 +0000