~lostgoat/linux - Work in progress for my drm linux changes

Age	Commit message (Expand)	Author	Files	Lines
2014-01-07	agp/intel: Use pci_bus_address() to get GTTADR bus address	Bjorn Helgaas	1	-1/+1
2014-01-07	agp/intel: Use pci_bus_address() to get MMADR bus address	Bjorn Helgaas	1	-2/+2
2014-01-07	agp/intel: Support 64-bit GMADR	Yinghai Lu	1	-2/+2
2012-11-11	drm/i915: Kill off now unused gen6+ AGP code	Ben Widawsky	1	-91/+0
2012-08-17	drm/i915: fix hsw uncached pte	Daniel Vetter	1	-0/+1
2012-08-07	drm/i915: add more Haswell PCI IDs	Paulo Zanoni	1	-5/+34
2012-06-25	Merge tag 'v3.5-rc4' into drm-intel-next-queued	Daniel Vetter	1	-0/+1
2012-06-12	drm/i915 + agp/intel-gtt: prep work for direct setup	Daniel Vetter	1	-3/+0
2012-06-06	char/agp: add another Ironlake host bridge	Eugeni Dodonov	1	-0/+1
2012-04-12	Merge branch 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-int...	Dave Airlie	1	-0/+14
2012-04-09	drm/i915: add Haswell devices and their PCI IDs	Eugeni Dodonov	1	-0/+11
2012-04-02	drm/i915: add Ivy Bridge GT2 Server entries	Eugeni Dodonov	1	-0/+1
2012-03-29	agp/intel: add ValleyView AGP driver	Jesse Barnes	1	-0/+3
2011-07-13	agp/intel: Fix typo in G4x_GMCH_SIZE_VT_2M	Chris Wilson	1	-3/+4
2011-05-13	agp/intel: add Ivy Bridge support	Jesse Barnes	1	-0/+8
2011-02-22	agp/intel: Experiment with a 855GM GWB bit	Chris Wilson	1	-0/+1
2011-01-11	agp/intel: Flush the chipset write buffers when changing GTT base	Chris Wilson	1	-0/+2
2010-10-27	intel-gtt: maximize ggtt size on platforms that support this	Daniel Vetter	1	-3/+11
2010-09-21	Merge branch 'drm-intel-fixes' into HEAD	Chris Wilson	1	-0/+2
2010-09-17	drm/i915,agp/intel: Add second set of PCI-IDs for B43	Chris Wilson	1	-0/+2
2010-09-08	intel-gtt: introduce intel_gtt_driver	Daniel Vetter	1	-40/+0
2010-09-08	agp/intel: make intel-gtt.c into a real source file	Daniel Vetter	1	-0/+3
2010-09-07	intel_agp,i915: Add more sandybridge graphics device ids	Zhenyu Wang	1	-6/+12
2010-09-07	agp/intel: use #ifdef idiom for intel-agp.h	Zhenyu Wang	1	-0/+4
2010-08-21	drm/i915,intel_agp: Add support for Sandybridge D0	Zhenyu Wang	1	-0/+1
2010-08-01	agp/intel: Add actual definitions of the Sandybridge PTE caching bits.	Zhenyu Wang	1	-0/+6
2010-04-18	agp/intel: introduce intel-agp.h header file	Daniel Vetter	1	-0/+239