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2015-03-05bcma: prepare Kconfig symbol for PCI driverRafał Miłecki2-2/+19
Driver for PCIe core requires PCI to be enabled, however we shouldn't require it for the whole bus. Someone may be not interested in extra PCI devices and what's more there are SoCs without any PCI at all (like BCM5356C0, BCM5357*, BCM47186B0). For more details see Kconfig "help". Please note this patch doesn't allow disabling PCI drivers yet, as it requires more work on calls to bcma_core_pci_* functions. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-05bcma: move internal function declarations to private headerRafał Miłecki1-0/+41
These functions are not exported nor used anywhere, so there is no reason to put them in public headers. Also drop unused bcma_chipco_(suspend|resume). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-05bcma: Kconfig: Let it depend on PCIChen Gang1-1/+1
bcma also needs PCI, just like IOMEM and DMA, so let it depend on PCI, or will cause building break for allmodconfig under c6x: CC [M] drivers/bcma/driver_pcie2.o drivers/bcma/driver_pcie2.c: In function 'bcma_core_pcie2_up': drivers/bcma/driver_pcie2.c:196:8: error: implicit declaration of function 'pcie_set_readrq' [-Werror=implicit-function-declaration] err = pcie_set_readrq(dev, pcie2->reqsize); ^ Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-03bcma: gpio: enable GPIO IRQ domain on BCM5301XRafał Miłecki1-2/+2
Just like on BCM47XX arch, BCM5301X also has ChipCommon with IRQ for GPIOs. Now we have interrupts working on BCM5301X we can finally make use of it. This has been successfully tested on 5 different devices (Buffalo, Luxul, Netgear). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-03bcma: add missing includesRafał Miłecki2-0/+2
kbuild found out that commit 804e27dee49e ("bcma: support bringing up bus hosted on PCIe Gen 2") broke the build on m68k: drivers/bcma/driver_pcie2.c: In function 'bcma_core_pcie2_up': >> drivers/bcma/driver_pcie2.c:196:2: error: implicit declaration of function 'pcie_set_readrq' [-Werror\ =implicit-function-declaration] err = pcie_set_readrq(dev, pcie2->reqsize); ^ cc1: some warnings being treated as errors Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-02bcma: enable support for PCIe Gen 2 host devicesRafał Miłecki3-2/+16
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-02bcma: support bringing up bus hosted on PCIe Gen 2Rafał Miłecki3-3/+30
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-02bcma: change IRQ control function to accept bus as an argumentRafał Miłecki1-3/+3
It doesn't operate on PCI core, but PCI host device, so there is no point of passing core related struct. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-02bcma: add helpers bringing PCIe hosted bus up / downRafał Miłecki3-18/+32
Bringing PCIe hosted bus up requires operating on host-related core. Since we plan to support PCIe Gen 2 devices we should provide a helper picking the correct one (PCIE or PCIE2). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29bcma: implement host code support for PCIe Gen 2 devicesRafał Miłecki1-2/+4
This is stil incomplete, so we don't add PCI IDs of new devices yet. Purpose of this patch is to allow testing & adjusting rest of the code. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29bcma: add early_init function for PCIe core and move some fix into itRafał Miłecki2-22/+51
There are some PCIe core fixes that need to be applied before accessing SPROM, otherwise reading it may fail. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29bcma: add empty PCIe hostmode functions if support is disabledRafał Miłecki2-2/+8
This allows us to drop some #ifdef magic (mess). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29bcma: detect SPROM revision 11Rafał Miłecki1-1/+2
Extracting values from it is still unsupported, but at least we'll display some meaningful error now. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29bcma: simplify freeing cores (internal devices structs)Rafał Miłecki1-11/+9
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29bcma: fix watchdog on some ARM chipsetsRafał Miłecki1-3/+7
These chipsets don't need changing clock mode. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-23bcma: use standard bus scanning during early registerRafał Miłecki4-89/+15
Starting with kernel 3.19-rc1 early registration of bcma on MIPS is done a bit later, with memory allocator available. This allows us to simplify code by using standard bus scanning method. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-23bcma: clean bus initialization codeRafał Miłecki3-9/+15
This moves main bus init code to the main.c and renames old function to make its purpose clear. Thanks to this change we'll also be able to separate scanning from registration (and support PCIe Gen 2 devices) in the future. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-15bcma: fix three coding style issues, more than 80 characters per lineOscar Forner Martinez1-3/+7
Three lines with more than 80 characters per line have been split in several lines. Signed-off-by: Oscar Forner Martinez <oscar.forner.martinez@gmail.com> Acked-by: Rafa? Mi?ecki <zajec5@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2014-12-11Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-2/+11
Pull MIPS updates from Ralf Baechle: "This is an unusually large pull request for MIPS - in parts because lots of patches missed the 3.18 deadline but primarily because some folks opened the flood gates. - Retire the MIPS-specific phys_t with the generic phys_addr_t. - Improvments for the backtrace code used by oprofile. - Better backtraces on SMP systems. - Cleanups for the Octeon platform code. - Cleanups and fixes for the Loongson platform code. - Cleanups and fixes to the firmware library. - Switch ATH79 platform to use the firmware library. - Grand overhault to the SEAD3 and Malta interrupt code. - Move the GIC interrupt code to drivers/irqchip - Lots of GIC cleanups and updates to the GIC code to use modern IRQ infrastructures and features of the kernel. - OF documentation updates for the GIC bindings - Move GIC clocksource driver to drivers/clocksource - Merge GIC clocksource driver with clockevent driver. - Further updates to bring the GIC clocksource driver up to date. - R3000 TLB code cleanups - Improvments to the Loongson 3 platform code. - Convert pr_warning to pr_warn. - Merge a bunch of small lantiq and ralink fixes that have been staged/lingering inside the openwrt tree for a while. - Update archhelp for IP22/IP32 - Fix a number of issues for Loongson 1B. - New clocksource and clockevent driver for Loongson 1B. - Further work on clk handling for Loongson 1B. - Platform work for Broadcom BMIPS. - Error handling cleanups for TurboChannel. - Fixes and optimization to the microMIPS support. - Option to disable the FTLB. - Dump more relevant information on machine check exception - Change binfmt to allow arch to examine PT_*PROC headers - Support for new style FPU register model in O32 - VDSO randomization. - BCM47xx cleanups - BCM47xx reimplement the way the kernel accesses NVRAM information. - Random cleanups - Add support for ATH25 platforms - Remove pointless locking code in some PCI platforms. - Some improvments to EVA support - Minor Alchemy cleanup" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (185 commits) MIPS: Add MFHC0 and MTHC0 instructions to uasm. MIPS: Cosmetic cleanups of page table headers. MIPS: Add CP0 macros for extended EntryLo registers MIPS: Remove now unused definition of phys_t. MIPS: Replace use of phys_t with phys_addr_t. MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT PCMCIA: Alchemy Don't select 64BIT_PHYS_ADDR in Kconfig. MIPS: lib: memset: Clean up some MIPS{EL,EB} ifdefery MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIO MIPS: <asm/types.h> fix indentation. MAINTAINERS: Add entry for BMIPS multiplatform kernel MIPS: Enable VDSO randomization MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration MIPS: Remove declaration of obsolete arch_init_clk_ops() MIPS: atomic.h: Reformat to fit in 79 columns MIPS: Apply `.insn' to fixup labels throughout MIPS: Fix microMIPS LL/SC immediate offsets MIPS: Kconfig: Only allow 32-bit microMIPS builds MIPS: signal.c: Fix an invalid cast in ISA mode bit handling MIPS: mm: Only build one microassembler that is suitable ...
2014-11-24MIPS: BCM47XX: Make bcma init NVRAM instead of bcm47xx polling itRafał Miłecki1-2/+11
This drops ssb/bcma dependency and will allow us to make it a standalone driver. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/8233/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19Merge commit '4e6ce4dc7ce71d0886908d55129d5d6482a27ff9' of ↵John W. Linville2-3/+4
git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless
2014-11-11bcma: get IRQ numbers from dtHauke Mehrtens1-1/+51
It is not possible to auto detect the irq numbers used by the cores on an arm SoC. If bcma was registered with device tree it will search for some device tree nodes with the irq number and add it to the core configuration. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-11-11bcma: make it possible to specify a IRQ num in bcma_core_irq()Hauke Mehrtens5-14/+29
This moves bcma_core_irq() to main.c and add a extra parameter with a number so that we can return different irq number for devices with more than one. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-10-27bcma: fill core details for every deviceRafał Miłecki3-3/+8
We were setting things like dma_dev, IRQ, etc. during core registration only. We need such info for cores handled internally (e.g. ChipCommon) as well. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-10-23bcma: add another PCI ID of device with BCM43228Rafał Miłecki1-2/+3
It was found attached to the BCM47081A0 SoC. Log: bcma: bus0: Found chip with id 43228, rev 0x00 and package 0x08 Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-10-23bcma: fix build when CONFIG_OF_ADDRESS is not setHauke Mehrtens1-1/+1
Commit 2101e533f41a ("bcma: register bcma as device tree driver") introduces a hard dependency on OF_ADDRESS into the bcma driver. OF_ADDRESS is specifically disabled for the sparc architecture. This results in the following error when building sparc64:allmodconfig. drivers/bcma/main.c: In function 'bcma_of_find_child_device': drivers/bcma/main.c:150:3: error: implicit declaration of function 'of_translate_address' Fixes: 2101e533f41a ("bcma: register bcma as device tree driver") Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-10-09Merge tag 'gpio-v3.18-1' of ↵Linus Torvalds1-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO changes from Linus Walleij: "This is the bulk of GPIO changes for the v3.18 development cycle: - Increase the default ARCH_NR_GPIO from 256 to 512. This was done to avoid having a custom <asm/gpio.h> header for the x86 architecture - GPIO is custom and complicated enough as it is already! We want to move to a radix to store the descriptors going forward, and finally get rid of this fixed array size altogether. - Endgame patching of the gpio_remove() semantics initiated by Abdoulaye Berthe. It is not accepted by the system that the removal of a GPIO chip fails during eg reboot or shutdown, and therefore the return value has now painfully been refactored away. For special cases like GPIO expanders on a hot-pluggable bus like USB, we may later add some gpiochip_try_remove() call, but for the cases we have now, return values are moot. - Some incremental refactoring of the gpiolib core and ACPI GPIO library for more descriptor usage. - Refactor the chained IRQ handler set-up method to handle also threaded, nested interrupts and set up the parent IRQ correctly. Switch STMPE and TC3589x drivers to use this registration method. - Add a .irq_not_threaded flag to the struct gpio_chip, so that also GPIO expanders that block but are still not using threaded IRQ handlers. - New drivers for the ARM64 X-Gene SoC GPIO controller. - The syscon GPIO driver has been improved to handle the "DSP GPIO" found on the TI Keystone 2 SoC:s. - ADNP driver switched to use gpiolib irqchip helpers. - Refactor the DWAPB driver to support being instantiated from and MFD cell (platform device). - Incremental feature improvement in the Zynq, MCP23S08, DWAPB, OMAP, Xilinx and Crystalcove drivers. - Various minor fixes" * tag 'gpio-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (52 commits) gpio: pch: Build context save/restore only for PM pinctrl: abx500: get rid of unused variable gpio: ks8695: fix 'else should follow close brace '}'' gpio: stmpe: add verbose debug code gpio: stmpe: fix up interrupt enable logic gpio: staticize xway_stp_init() gpio: handle also nested irqchips in the chained handler set-up gpio: set parent irq on chained handlers gpiolib: irqchip: use irq_find_mapping while removing irqchip gpio: crystalcove: support virtual GPIO pinctrl: bcm281xx: make Kconfig dependency more strict gpio: kona: enable only on BCM_MOBILE or for compile testing gpio, bcm-kona, LLVMLinux: Remove use of __initconst gpio: Fix ngpio in gpio-xilinx driver gpio: dwapb: fix pointer to integer cast gpio: xgene: Remove unneeded #ifdef CONFIG_OF guard gpio: xgene: Remove unneeded forward declation for struct xgene_gpio gpio: xgene: Fix missing spin_lock_init() gpio: ks8695: fix switch case indentation gpiolib: add irq_not_threaded flag to gpio_chip ...
2014-09-30bcma: use chipcommon node from DT for SoC GPIO chipRafał Miłecki1-0/+4
This will allow us to define GPIO-attached devices (LEDs, buttons) in the the device tree. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-09-30bcma: register bcma as device tree driverHauke Mehrtens3-1/+146
This driver is used by the bcm53xx ARM SoC code. Now it is possible to give the address of the chipcommon core in device tree and bcma will search for all the other cores. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-09-26bcma: gpio: use ChipCommon GPIO IRQ on BCM47XX arch onlyRafał Miłecki1-2/+2
GPIOs can be also used on bcm53xx, however this arch requires different implementation of IRQ support. It uses different IRQ number (117) and different masks & acking. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-09-26bcma: print chip ID in a more user-friendly formRafał Miłecki1-2/+6
Some chip IDs are easier to read/understand when printed in a decimal form. For example on my bcm53xx arch router this patch replaces: Found chip with id 0xCF12, rev 0x00 and package 0x02 with a: Found chip with id 53010, rev 0x00 and package 0x02 Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-09-18driver:gpio remove all usage of gpio_remove retval in driverabdoulaye berthe1-1/+2
this remove all reference to gpio_remove retval in all driver except pinctrl and gpio. the same thing is done for gpio and pinctrl in two different patches. Signed-off-by: Abdoulaye Berthe <berthe.ab@gmail.com> Acked-by: Michael Büsch <m@bues.ch> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Mauro Carvalho Chehab <m.chehab@samsung.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-09-09bcma: add support for chipcommon B coreHauke Mehrtens5-0/+77
This core is used on BCM4708 to configure the PCIe and USB3 PHYs and it contains the addresses to the Device Management unit. This will be used by the PCIe driver first. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-09-09bcma: store more alternative addressesHauke Mehrtens1-4/+5
Each core could have more than one alternative address. There are cores with 8 alternative addresses for different functions. The PHY control in the Chip common B core is done through the 2. alternative address and not the first one. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> CC: linux-usb@vger.kernel.org Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-09-09bcma: register NAND and QSPI cores earlyRafał Miłecki1-0/+21
On Northstar (ARM arch) we will use MTD subsystem to access NVRAM and SPROM. To get access to flash device we need to register these cores first. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-09-09bcma: move code for core registration into separate functionRafał Miłecki1-31/+36
This cleans code a bit and will us to register cores in other places as well. The only difference with this patch is using "core_index" for setting device name. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-09-09bcma: use separated function to initialize bus on SoCRafał Miłecki1-2/+9
This is required to split SoC bus init into two phases. The later one (which includes scanning) should be called when kalloc is available. Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-09-09bcma: move bus struct setup into early part of host specific codeRafał Miłecki4-9/+6
This change is important for SoC host. In future we will want to know chip ID (needed for early MIPS boot) before doing cores scanning. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-09-08Merge branch 'master' of ↵John W. Linville1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless
2014-09-04bcma: get info about flash type SoC booted fromRafał Miłecki1-0/+62
There is an ongoing work on cleaning MIPS's nvram support so it could be re-used on other platforms (bcm53xx to say precisely). This will require a bit of extra logic in bcma this patch implements. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-08-28bcma: only map wrapper if its address is availableHauke Mehrtens2-4/+11
The Chipcommon B core does not have a wrap address and it would fail here. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-08-25bcma: add PCI ID for spromless BCM43217Hauke Mehrtens1-0/+1
This adds the PCI ID a BCM43217 without a sprom. This devices was found on a Netgear R6250 attached to a BCM4708 ARM SoC. bcma: bus1: Found chip with id 0xA8D1, rev 0x00 and package 0x08 bcma: bus1: Core 0 found: ChipCommon (manuf 0x4BF, id 0x800, rev 0x27, class 0x0) bcma: bus1: Core 1 found: IEEE 802.11 (manuf 0x4BF, id 0x812, rev 0x1E, class 0x0) bcma: bus1: Core 2 found: PCIe (manuf 0x4BF, id 0x820, rev 0x14, class 0x0) b43-phy0: Broadcom 43217 WLAN found (core revision 30) b43-phy0: Found PHY: Analog 9, Type 4 (N), Revision 17 b43-phy0: Found Radio: Manuf 0x17F, ID 0x2057, Revision 14, Version 1 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-07-31bcma: use NS prefix for names of Northstar specific coresRafał Miłecki1-11/+11
It's cleaner and we don't have quite identical names like BCMA_CORE_PCIEG2 and BCMA_CORE_PCIE2. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-07-29bcma: add support for BCM43131 that was found in Tenda W311ERafał Miłecki3-0/+3
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-07-18bcma: add support for BCM43217 found in Tenda W322E (14e4:43a9)Rafał Miłecki3-0/+3
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-07-18bcma: extract antenna gains from SPROM correctlyRafał Miłecki1-8/+33
Just like in case of SSB SPROMs they are encoded in a bit tricky way. SPROM struct already uses s8 type and it's supposed to store decoded values. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-07-07bcma: add driver for PCIe Gen 2 coreRafał Miłecki3-0/+184
New Broadcom PCIe devices (802.11ac ones?) use Gen2 and have to be initialized differently. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-06-19bcma: gpio: register all 32 GPIOs on BCM53572Rafał Miłecki1-0/+1
I've here a device detected as: bcma: bus0: Found chip with id 0xD144, rev 0x01 and package 0x08 I couldn't find GPIO handling hw button until trying GPIO 20. It seems BCM53572 also has 32 GPIOs. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-03-27bcma: gpio: register 32 GPIOs on BCM5357Rafał Miłecki1-1/+8
Some Broadcom boards have more GPIOs available. For example Linksys E3200 home router is based on SoC id 0x5357, package 0x0A and uses GPIO 23 to reset internal USB WiFi (gpio23=wombo_reset). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
2014-01-30Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2-2/+136
Pull MIPS updates from Ralf Baechle: "The most notable new addition inside this pull request is the support for MIPS's latest and greatest core called "inter/proAptiv". The patch series describes this core as follows. "The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit." The platform specific patches touch all 3 Broadcom families. It adds support for the new Broadcom/Netlogix XLP9xx Soc, building a common BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count and full gpio button/led descriptions for BCM47xx. The rest of the series are cleanups and bug fixes that are MIPS generic and consist largely of changes that Imgtec/MIPS had published in their linux-mti-3.10.git stable tree. Random other cleanups and patches preparing code to be merged in 3.15" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) mips: select ARCH_MIGHT_HAVE_PC_SERIO mips: delete non-required instances of include <linux/init.h> MIPS: KVM: remove shadow_tlb code MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI mips/ide: flush dcache also if icache does not snoop dcache MIPS: BCM47XX: fix position of cpu_wait disabling MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N> MIPS: introduce MIPS_L1_CACHE_SHIFT_<N> MIPS: ZBOOT: gather string functions into string.c arch/mips/pci: don't check resource with devm_ioremap_resource arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource bcma: gpio: don't cast u32 to unsigned long ssb: gpio: add own IRQ domain MIPS: BCM47XX: fix sparse warnings in board.c MIPS: BCM47XX: add board detection for Linksys WRT54GS V1 MIPS: BCM47XX: fix detection for some boards MIPS: BCM47XX: Enable buttons support on SSB MIPS: BCM47XX: Convert WNDR4500 to new syntax MIPS: BCM47XX: Use "timer" trigger for status LEDs ...
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