summaryrefslogtreecommitdiff
path: root/src/radeon.h
diff options
context:
space:
mode:
Diffstat (limited to 'src/radeon.h')
-rw-r--r--src/radeon.h100
1 files changed, 46 insertions, 54 deletions
diff --git a/src/radeon.h b/src/radeon.h
index fd91e3d..81e0db7 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1,4 +1,4 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.43 2003/11/06 18:38:00 tsi Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.37 2003/02/23 23:28:48 dawes Exp $ */
/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
@@ -72,8 +72,8 @@
#define RADEON_MMIOSIZE 0x80000
#define RADEON_VBIOS_SIZE 0x00010000
-#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX
- * Need to comfirm this is not used
+#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX
+ * Need to comfirm this is not used
* for something else.
*/
@@ -94,6 +94,20 @@ do { \
#define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate)
typedef struct {
+ /* All values in XCLKS */
+ int ML; /* Memory Read Latency */
+ int MB; /* Memory Burst Length */
+ int Trcd; /* RAS to CAS delay */
+ int Trp; /* RAS percentage */
+ int Twr; /* Write Recovery */
+ int CL; /* CAS Latency */
+ int Tr2w; /* Read to Write Delay */
+ int Rloop; /* Loop Latency */
+ int Rloop_fudge; /* Add to ML to get Rloop */
+ char *name;
+} RADEONRAMRec, *RADEONRAMPtr;
+
+typedef struct {
/* Common registers */
CARD32 ovr_clr;
CARD32 ovr_wid_left_right;
@@ -109,7 +123,7 @@ typedef struct {
CARD32 cap1_trig_cntl;
CARD32 bus_cntl;
CARD32 surface_cntl;
- CARD32 bios_5_scratch;
+
/* Other registers to save for VT switches */
CARD32 dp_datatype;
CARD32 rbbm_soft_reset;
@@ -128,9 +142,6 @@ typedef struct {
CARD32 crtc_offset;
CARD32 crtc_offset_cntl;
CARD32 crtc_pitch;
- CARD32 disp_merge_cntl;
- CARD32 grph_buffer_cntl;
- CARD32 crtc_more_cntl;
/* CRTC2 registers */
CARD32 crtc2_gen_cntl;
@@ -138,8 +149,6 @@ typedef struct {
CARD32 dac2_cntl;
CARD32 disp_output_cntl;
CARD32 disp_hw_debug;
- CARD32 disp2_merge_cntl;
- CARD32 grph2_buffer_cntl;
CARD32 crtc2_h_total_disp;
CARD32 crtc2_h_sync_strt_wid;
CARD32 crtc2_v_total_disp;
@@ -162,7 +171,6 @@ typedef struct {
CARD32 lvds_gen_cntl;
CARD32 lvds_pll_cntl;
CARD32 tmds_pll_cntl;
- CARD32 tmds_transmitter_cntl;
/* Computed values for PLL */
CARD32 dot_clock_freq;
@@ -171,8 +179,8 @@ typedef struct {
int post_div;
/* PLL registers */
- unsigned ppll_ref_div;
- unsigned ppll_div_3;
+ CARD32 ppll_ref_div;
+ CARD32 ppll_div_3;
CARD32 htotal_cntl;
/* Computed values for PLL2 */
@@ -237,27 +245,20 @@ typedef enum {
typedef enum {
CHIP_FAMILY_UNKNOW,
CHIP_FAMILY_LEGACY,
+ CHIP_FAMILY_R128,
+ CHIP_FAMILY_M3,
CHIP_FAMILY_RADEON,
- CHIP_FAMILY_RV100,
- CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
+ CHIP_FAMILY_VE,
+ CHIP_FAMILY_M6,
CHIP_FAMILY_RV200,
- CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
+ CHIP_FAMILY_M7,
CHIP_FAMILY_R200,
CHIP_FAMILY_RV250,
- CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
- CHIP_FAMILY_RV280,
- CHIP_FAMILY_R300,
- CHIP_FAMILY_R350,
- CHIP_FAMILY_RV350,
- CHIP_FAMILY_LAST
+ CHIP_FAMILY_M9,
+ CHIP_FAMILY_R300
} RADEONChipFamily;
typedef struct {
- CARD32 freq;
- CARD32 value;
-}RADEONTMDSPll;
-
-typedef struct {
EntityInfoPtr pEnt;
pciVideoPtr PciInfo;
PCITAG PciTag;
@@ -284,10 +285,10 @@ typedef struct {
RADEONDDCType DDCType;
RADEONConnectorType ConnectorType;
Bool HasCRTC2; /* All cards except original Radeon */
- Bool IsMobility; /* Mobile chips for laptops */
- Bool IsIGP; /* IGP chips */
Bool IsSecondary; /* Second Screen */
Bool IsSwitching; /* Flag for switching mode */
+ Bool IsDell; /* Dell OEM VE card */
+ int DellType;
Bool Clone; /* Force second head to clone primary*/
RADEONMonitorType CloneType;
RADEONDDCType CloneDDCType;
@@ -298,7 +299,7 @@ typedef struct {
Bool OverlayOnCRTC2;
Bool PanelOff; /* Force panel (LCD/DFP) off */
int FPBIOSstart; /* Start of the flat panel info */
- Bool ddc_mode; /* Validate mode by matching exactly
+ Bool ddc_mode; /* Validate mode by matching exactly
* the modes supported in DDC data
*/
Bool R300CGWorkaround;
@@ -314,10 +315,7 @@ typedef struct {
int VBlank;
int PanelPwrDly;
int DotClock;
- int RefDivider;
- int FeedbackDivider;
- int PostDivider;
- Bool UseBiosDividers;
+
/* EDID data using DDC interface */
Bool ddc_bios;
Bool ddc1;
@@ -326,12 +324,7 @@ typedef struct {
CARD32 DDCReg;
RADEONPLLRec pll;
- RADEONTMDSPll tmds_pll[4];
- int RamWidth;
- float sclk; /* in MHz */
- float mclk; /* in MHz */
- Bool IsDDR;
- int DispPriority;
+ RADEONRAMPtr ram;
RADEONSaveRec SavedReg; /* Original (text) mode */
RADEONSaveRec ModeReg; /* Current mode */
@@ -427,9 +420,9 @@ typedef struct {
Bool have3DWindows; /* Are there any 3d clients? */
int drmMinor;
- drmSize gartSize;
+ drmSize agpSize;
drmHandle agpMemHandle; /* Handle from drmAgpAlloc */
- unsigned long gartOffset;
+ unsigned long agpOffset;
unsigned char *AGP; /* Map */
int agpMode;
int agpFastWrite;
@@ -444,20 +437,20 @@ typedef struct {
int CPusecTimeout; /* CP timeout in usecs */
/* CP ring buffer data */
- unsigned long ringStart; /* Offset into GART space */
+ unsigned long ringStart; /* Offset into AGP space */
drmHandle ringHandle; /* Handle from drmAddMap */
drmSize ringMapSize; /* Size of map */
int ringSize; /* Size of ring (in MB) */
unsigned char *ring; /* Map */
int ringSizeLog2QW;
- unsigned long ringReadOffset; /* Offset into GART space */
+ unsigned long ringReadOffset; /* Offset into AGP space */
drmHandle ringReadPtrHandle; /* Handle from drmAddMap */
drmSize ringReadMapSize; /* Size of map */
unsigned char *ringReadPtr; /* Map */
/* CP vertex/indirect buffer data */
- unsigned long bufStart; /* Offset into GART space */
+ unsigned long bufStart; /* Offset into AGP space */
drmHandle bufHandle; /* Handle from drmAddMap */
drmSize bufMapSize; /* Size of map */
int bufSize; /* Size of buffers (in MB) */
@@ -465,13 +458,13 @@ typedef struct {
int bufNumBufs; /* Number of buffers */
drmBufMapPtr buffers; /* Buffer map */
- /* CP GART Texture data */
- unsigned long gartTexStart; /* Offset into GART space */
- drmHandle gartTexHandle; /* Handle from drmAddMap */
- drmSize gartTexMapSize; /* Size of map */
- int gartTexSize; /* Size of GART tex space (in MB) */
- unsigned char *gartTex; /* Map */
- int log2GARTTexGran;
+ /* CP AGP Texture data */
+ unsigned long agpTexStart; /* Offset into AGP space */
+ drmHandle agpTexHandle; /* Handle from drmAddMap */
+ drmSize agpTexMapSize; /* Size of map */
+ int agpTexSize; /* Size of AGP tex space (in MB) */
+ unsigned char *agpTex; /* Map */
+ int log2AGPTexGran;
/* CP accleration */
drmBufPtr indirectBuffer;
@@ -573,13 +566,12 @@ extern Bool RADEONDGAInit(ScreenPtr pScreen);
extern int RADEONMinBits(int val);
extern void RADEONInitVideo(ScreenPtr pScreen);
-extern void RADEONResetVideo(ScrnInfoPtr pScrn);
+
extern void R300CGWorkaround(ScrnInfoPtr pScrn);
#ifdef XF86DRI
extern Bool RADEONDRIScreenInit(ScreenPtr pScreen);
extern void RADEONDRICloseScreen(ScreenPtr pScreen);
-extern void RADEONDRIResume(ScreenPtr pScreen);
extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen);
extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn);
@@ -675,7 +667,7 @@ do { \
"ADVANCE_RING() start: %d used: %d count: %d\n", \
info->indirectStart, \
info->indirectBuffer->used, \
- __count * (int)sizeof(CARD32)); \
+ __count * sizeof(CARD32)); \
} \
info->indirectBuffer->used += __count * (int)sizeof(CARD32); \
} while (0)
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-25 20:47:38 +0000