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authorAlex Deucher <agd5f@yahoo.com>2004-12-12 17:29:45 +0000
committerAlex Deucher <agd5f@yahoo.com>2004-12-12 17:29:45 +0000
commit33d07d426adb5d6b88c9af5fb4bff7b8f25f26fb (patch)
tree730d6570f30e0a9de0e2cdf8244d4a4e5df0d174
parent4c276644ec1bbe565f2abb182ec188e0d5475105 (diff)
- missing diff from agp 8x support
-rw-r--r--src/radeon_dri.c31
1 files changed, 23 insertions, 8 deletions
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index e99a6fe..fc32fd9 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -721,23 +721,38 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
unsigned int device = drmAgpDeviceId(info->drmFD);
mode &= ~RADEON_AGP_MODE_MASK;
- switch (info->agpMode) {
- case 4: mode |= RADEON_AGP_4X_MODE;
- case 2: mode |= RADEON_AGP_2X_MODE;
- case 1: default: mode |= RADEON_AGP_1X_MODE;
+ if ((mode & RADEON_AGPv3_MODE) &&
+ (INREG(RADEON_AGP_STATUS) & RADEON_AGPv3_MODE)) {
+ switch (info->agpMode) {
+ case 8: mode |= RADEON_AGPv3_8X_MODE;
+ case 4: default: mode |= RADEON_AGPv3_4X_MODE;
+ }
+ /*TODO: need to take care of other bits valid for v3 mode
+ * currently these bits are not used in all tested cards.
+ */
+ } else {
+ switch (info->agpMode) {
+ case 4: mode |= RADEON_AGP_4X_MODE;
+ case 2: mode |= RADEON_AGP_2X_MODE;
+ case 1: default: mode |= RADEON_AGP_1X_MODE;
+ }
}
- if (info->agpFastWrite) mode |= RADEON_AGP_FW_MODE;
-
- if ((vendor == PCI_VENDOR_AMD) &&
+ if (info->agpFastWrite &&
+ (vendor == PCI_VENDOR_AMD) &&
(device == PCI_CHIP_AMD761)) {
/* Disable fast write for AMD 761 chipset, since they cause
* lockups when enabled.
*/
- mode &= ~0x10; /* FIXME: Magic number */
+ info->agpFastWrite = FALSE;
+ xf86DrvMsg(pScreen->myNum, X_WARNING,
+ "[agp] Not enabling Fast Writes on AMD 761 chipset to avoid "
+ "lockups");
}
+ if (info->agpFastWrite) mode |= RADEON_AGP_FW_MODE;
+
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] Mode 0x%08lx [AGP 0x%04x/0x%04x; Card 0x%04x/0x%04x]\n",
mode, vendor, device,