Age | Commit message (Collapse) | Author | Files | Lines |
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Mmap from /sys/devices/pci* on linux forces the cache-disable and
write-through bits, which turns our write-combining map into an
uncached-map, seriously impacting performance. It turns out that a bug in
mprotect allows us to fix this by disabling access to those pages and then
immediately re-enabling them.
(cherry picked from commit c3fb62df4e60b63295f94c99b3c5de70dbf94e1c)
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2D pitch limit applys to all chips. Pre-965 chip has
8KB pitch limit for 3D. 965 supports max pitch by current
exa (128KB).
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This reverts commit 602613e397bdf0cf701a6a7748f9343875864466.
Pre-965 chipset actually have different pitch limit for 2d and 3d
engine. For 2D blit, it's 32KB max. For 3D, it's 8KB max. Don't
limit it to minimal which fallback 2D operations (noteable copy
slow).
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pI830 may point to NULL if I830PreInit fails
(cherry picked from commit 0ae283582d21776d3317d5fc1c25751d50d562c7)
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i8xx currently only works in FULL mode.
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2.3-rc3
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Fix distcheck
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This reverts commit f47486fab3dffcbb03e7ad89f777abba1e887299.
Sorry for failing to push the #line processing changes to intel-gen4asm;
those are now pushed, so this change should no longer be necessary. Having
correct file name and line numbers in the error messages is awfully nice
though.
(cherry picked from commit da85d1b822dcb31698e9c5ab85a7bb27ad745eee)
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intel-gen4asm doesn't allow '#' line
(cherry picked from commit f47486fab3dffcbb03e7ad89f777abba1e887299)
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(cherry picked from commit 5c9cde37e769287fb7bf4e08c3600a33c2e92dce)
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(cherry picked from commit 152a50703aa5e9ebaa9abbe448518742734a5eb7)
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(cherry picked from commit d5a80e1e3ab5724d34b20f9ee6f830efd0f5b076)
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(cherry picked from commit f270456e5612cb88933e6aabcd9a816c5c292229)
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The hardware has been marked as needing a sync, so the next video put will
block waiting for the previous one to complete. Adding a sync here just
stalls the video playback for no good reason.
(cherry picked from commit 3fc3d1a701bae257b70aa7b7654c722f30e71399)
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(cherry picked from commit b68d9f4245d0ebe3371c179401ff145f1a4d101b)
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(cherry picked from commit 781be9d47289713b0a8fcd95c769a9c6241d62e9)
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The Intel driver appears to be coded to only work with displays
expecting 18 bit pixels. However I have an application using a LCD
display that expects pixel data in 24 bit format. The difference is
only 2 bits in a single GPU register. This patch implements that
change, controlled by a new driver option, "LVDS24Bit". The default
value is false, which is the previous behavior. When set to true,
then 24 bit panels should work (at least the one I'm testing here
does).
Fd.o bug #15201
Signed-off-by: Mike Isely <isely@pobox.com>
(cherry picked from commit e031cc02e65acfbafb48136dad414751e04425c5)
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(cherry picked from commit 79b18980ac9f60b1978abe421352df965aed1681)
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Disable panel fitting on 855GM, and fix dither setting.
(cherry picked from commit 2b720262e1235f1c9da860ba3e9181f0c377aa5e)
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Using the updated factors even when BT709 conversion isn't available
(non-965) should still give us better color reproduction. Tested on a
945GM, examining the +/-5% of black bars of videotestsrc.
(cherry picked from commit af92f4f885c8eae2211d09080b2289aa5bab9ec1)
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FD bug #15353. Launchpad bug ID is available for reference.
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(cherry picked from commit 0147c1c84872f7a109721a53d88a539932d9be81)
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(cherry picked from commit 90886f9a602d58b754e9a8d0f1a9c40803d34fa2)
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(cherry picked from commit 0836373dc6e2f8612f120074980561f7ac11f6f7)
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Saving registers means we can run more in parallel.
(cherry picked from commit bfd803e085e938866efb45c67a79facef78ec399)
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Clean up register allocation to never overlap
Always write 4 values for each texture vertex.
(cherry picked from commit a6492661ae07310128eb73c3ef037c42ce7ab184)
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(cherry picked from commit f8081178eb6fda0e405967cbacad532561619262)
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(cherry picked from commit 879f8717b09f79156b218ee9cc2107700190d586)
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(cherry picked from commit 6db8faeb754897b21af045d00f50db9640b080bb)
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(cherry picked from commit 6bb92213374f278387c539bbe05b773e87e11b90)
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(cherry picked from commit 05710145b6fc4ed2c528128b2e6022591a53d050)
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Use macros for register names, modularize functions into separate files.
(cherry picked from commit 08500507284f13ad7084eb231b43e117e9728129)
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(cherry picked from commit 949d73271d7100c1f028fd60f185f4929461304e)
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sf_mask is the same as sf except that it must compute both src and mask uvw
cooefficients, which are conveniently adjacent in the same registers, and so
need only an extended execution width
(cherry picked from commit 492ff1494f782240e6ca68919b2d0b9aa400fc53)
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This involves correctly computing u/v locations based on x/y vectors and
line constants computed in new sf program.
Also, use fewer instructions to make this go a bit faster (2X for 500x500
composite).
(cherry picked from commit 6304b38423f99190a5e54f1a7dcaa75adfad4f2a)
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(cherry picked from commit 771a56b1ed0df69345c723cb62a73b6842cd8227)
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(cherry picked from commit 4f469189fed541549e5d470b2529275a29cc2f20)
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2.3-rc2
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(cherry picked from commit 7dcb6e627449c80cea9812462ce6a3e125bd1240)
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(cherry picked from commit d50264fc7c4e0f80d9cc68dfdf322f68520a0f1e)
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If the legacy bit is set, use both the BLC_PWM_CTL and LBB regs to control the
backlight, rather than just LBB. Looks like more platforms want that than what
the current code does. Note that kernel provided interfaces will always be
used if available, so this shouldn't affect users with /sys/class/backlight
interfaces at all.
Fixes #14721.
(cherry picked from commit 1450acd046d47e1739a3ffbd146c73ad2974a935)
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(cherry picked from commit 3414313ac9d0faa95797ee18cc33afa231ec7581)
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(cherry picked from commit c40f195f2dc3467259b4588e087aac9741003ebf)
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(cherry picked from commit 7bba2c13310ed5ac22a355a3cc0ec8b7afaa79cf)
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It's gone, really.
(cherry picked from commit b1f358ba97473b792ec2b7ed5170152faebe7262)
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They should be listed as lower case, since that's what you'd pass to xrandr.
(cherry picked from commit 52d6ced652059989e6d9780a149488ccd16e3a22)
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