diff options
Diffstat (limited to 'hw/xfree86/os-support/bus')
| -rw-r--r-- | hw/xfree86/os-support/bus/Pci.c | 1171 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/Pci.h | 127 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/axpPci.c | 47 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/freebsdPci.c | 4 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/ix86Pci.c | 19 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/linuxPci.c | 955 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/netbsdPci.c | 2 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/sparcPci.c | 28 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/xf86Pci.h | 547 | ||||
| -rw-r--r-- | hw/xfree86/os-support/bus/zx1PCI.c | 8 |
10 files changed, 301 insertions, 2607 deletions
diff --git a/hw/xfree86/os-support/bus/Pci.c b/hw/xfree86/os-support/bus/Pci.c index 30f7667fa..31e9023f0 100644 --- a/hw/xfree86/os-support/bus/Pci.c +++ b/hw/xfree86/os-support/bus/Pci.c @@ -8,8 +8,6 @@ * All of the public PCI access functions exported to the other parts of * the server are declared in Pci.h and defined herein. These include: * pciInit() - Initialize PCI access functions - * pciFindFirst() - Find a PCI device by dev/vend id - * pciFindNext() - Find another PCI device by dev/vend id * pciReadLong() - Read a 32 bit value from a device's cfg space * pciReadWord() - Read a 16 bit value from a device's cfg space * pciReadByte() - Read an 8 bit value from a device's cfg space @@ -20,24 +18,11 @@ * pciSetBitsByte() - Write an 8 bit value against a mask * pciTag() - Return tag for a given PCI bus, device, & * function - * pciDomTag() - Return tag for a given PCI domain, bus, - * device & function * pciBusAddrToHostAddr() - Convert a PCI address to a host address - * pciHostAddrToBusAddr() - Convert a host address to a PCI address - * pciGetBaseSize() - Returns the number of bits in a PCI base - * addr mapping - * xf86MapPciMem() - Like xf86MapVidMem() except function expects - * a PCI address and a PCITAG that identifies - * a PCI device - * xf86ReadPciBIOS() - Like xf86ReadBIOS() but can handle PCI/host - * address translation and BIOS decode enabling * xf86scanpci() - Return info about all PCI devices - * xf86GetPciDomain() - Return domain number from a PCITAG * xf86MapDomainMemory() - Like xf86MapPciMem() but can handle * domain/host address translation - * xf86MapDomainIO() - Maps PCI I/O spaces - * xf86ReadDomainMemory() - Like xf86ReadPciBIOS() but can handle - * domain/host address translation + * xf86MapLegacyIO() - Maps PCI I/O spaces * * The actual PCI backend driver is selected by the pciInit() function * (see below) using either compile time definitions, run-time checks, @@ -210,269 +195,50 @@ #include "xf86_OSproc.h" #include "Pci.h" +#include <pciaccess.h> + +#if 0 +#include <stdio.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#endif + #define PCI_MFDEV_SUPPORT 1 /* Include PCI multifunction device support */ #define PCI_BRIDGE_SUPPORT 1 /* Include support for PCI-to-PCI bridges */ /* * Global data */ -static int pciInitialized = 0; - -CARD32 pciDevid; /* Requested device/vendor ID (after mask) */ -CARD32 pciDevidMask; /* Bit mask applied (AND) before comparison */ - /* of real devid's with requested */ - -int pciBusNum; /* Bus Number of current device */ -int pciDevNum; /* Device number of current device */ -int pciFuncNum; /* Function number of current device */ -PCITAG pciDeviceTag; /* Tag for current device */ pciBusInfo_t *pciBusInfo[MAX_PCI_BUSES] = { NULL, }; _X_EXPORT int pciNumBuses = 0; /* Actual number of PCI buses */ int pciMaxBusNum = MAX_PCI_BUSES; -static Bool inProbe = FALSE; -static pciConfigPtr *pci_devp = NULL; - -static int readPciBios( PCITAG Tag, CARD8* tmp, ADDRESS hostbase, - unsigned char * buf, int len, PciBiosType BiosType ); - -static int (*pciOSHandleBIOS)(PCITAG Tag, int basereg, unsigned char *buf, int len); - -int xf86MaxPciDevs = 0; - -/* - * Platform specific PCI function pointers. - * - * NOTE: A platform/OS specific pci init procedure can override these defaults - * by setting them to the appropriate platform dependent functions. - */ -PCITAG (*pciFindFirstFP)(void) = pciGenFindFirst; -PCITAG (*pciFindNextFP)(void) = pciGenFindNext; /* * pciInit - choose correct platform/OS specific PCI init routine */ -void -pciInit() +static void +pciInit(void) { - if (pciInitialized) - return; + static int pciInitialized = 0; + if (!pciInitialized) { pciInitialized = 1; /* XXX */ #if defined(DEBUGPCI) - if (DEBUGPCI >= xf86Verbose) - xf86Verbose = DEBUGPCI; -#endif - - ARCH_PCI_INIT(); -#if defined(ARCH_PCI_OS_INIT) - if (pciNumBuses <= 0) - ARCH_PCI_OS_INIT(); -#endif - if (xf86MaxPciDevs == 0) { - xf86Msg(X_WARNING, - "OS did not count PCI devices, guessing wildly\n"); - xf86MaxPciDevs = MAX_PCI_DEVICES; + if (DEBUGPCI >= xf86Verbose) { + xf86Verbose = DEBUGPCI; } - if (pci_devp) - xfree(pci_devp); - pci_devp = xnfcalloc(xf86MaxPciDevs + 1, sizeof(pciConfigPtr)); -} - -void pciSetOSBIOSPtr(int (*bios_fn)(PCITAG Tag, int basereg, unsigned char * buf, int len)) -{ - pciOSHandleBIOS = bios_fn; -} - -_X_EXPORT PCITAG -pciFindFirst(CARD32 id, CARD32 mask) -{ -#ifdef DEBUGPCI - ErrorF("pciFindFirst(0x%lx, 0x%lx), pciInit = %d\n", id, mask, pciInitialized); -#endif - pciInit(); - - pciDevid = id & mask; - pciDevidMask = mask; - - return((*pciFindFirstFP)()); -} - -_X_EXPORT PCITAG -pciFindNext(void) -{ -#ifdef DEBUGPCI - ErrorF("pciFindNext(), pciInit = %d\n", pciInitialized); -#endif - pciInit(); - - return((*pciFindNextFP)()); -} - -_X_EXPORT CARD32 -pciReadLong(PCITAG tag, int offset) -{ - int bus = PCI_BUS_FROM_TAG(tag); - -#ifdef DEBUGPCI - ErrorF("pciReadLong(0x%lx, %d)\n", tag, offset); #endif - pciInit(); - if ((bus >= 0) && ((bus < pciNumBuses) || inProbe) && pciBusInfo[bus] && - pciBusInfo[bus]->funcs->pciReadLong) { - CARD32 rv = (*pciBusInfo[bus]->funcs->pciReadLong)(tag, offset); - - PCITRACE(1, ("pciReadLong: tag=0x%x [b=%d,d=%d,f=%d] returns 0x%08x\n", - tag, bus, PCI_DEV_FROM_TAG(tag), PCI_FUNC_FROM_TAG(tag), rv)); - return(rv); - } - - return(PCI_NOT_FOUND); -} - -_X_EXPORT CARD16 -pciReadWord(PCITAG tag, int offset) -{ - CARD32 tmp; - int shift = (offset & 3) * 8; - int aligned_offset = offset & ~3; - int bus = PCI_BUS_FROM_TAG(tag); - - if (shift != 0 && shift != 16) - FatalError("pciReadWord: Alignment error: Cannot read 16 bits " - "at offset %d\n", offset); - - pciInit(); - - if ((bus >= 0) && ((bus < pciNumBuses) || inProbe) && pciBusInfo[bus] && - pciBusInfo[bus]->funcs->pciReadWord) { - CARD32 rv = (*pciBusInfo[bus]->funcs->pciReadWord)(tag, offset); - - return(rv); - } else { - tmp = pciReadLong(tag, aligned_offset); - - return((CARD16)((tmp >> shift) & 0xffff)); - } -} - -_X_EXPORT CARD8 -pciReadByte(PCITAG tag, int offset) -{ - CARD32 tmp; - int shift = (offset & 3) * 8; - int aligned_offset = offset & ~3; - int bus = PCI_BUS_FROM_TAG(tag); - - pciInit(); - - if ((bus >= 0) && ((bus < pciNumBuses) || inProbe) && pciBusInfo[bus] && - pciBusInfo[bus]->funcs->pciReadByte) { - CARD8 rv = (*pciBusInfo[bus]->funcs->pciReadByte)(tag, offset); - - return(rv); - } else { - tmp = pciReadLong(tag, aligned_offset); - - return((CARD8)((tmp >> shift) & 0xff)); - } -} - -_X_EXPORT void -pciWriteLong(PCITAG tag, int offset, CARD32 val) -{ - int bus = PCI_BUS_FROM_TAG(tag); - - pciInit(); - - if ((bus >= 0) && (bus < pciNumBuses) && pciBusInfo[bus] && - pciBusInfo[bus]->funcs->pciWriteLong) - (*pciBusInfo[bus]->funcs->pciWriteLong)(tag, offset, val); -} - -_X_EXPORT void -pciWriteWord(PCITAG tag, int offset, CARD16 val) -{ - CARD32 tmp; - int aligned_offset = offset & ~3; - int shift = (offset & 3) * 8; - int bus = PCI_BUS_FROM_TAG(tag); - - if (shift != 0 && shift != 16) - FatalError("pciWriteWord: Alignment Error: Cannot read 16 bits " - "from offset %d\n", offset); - - pciInit(); - - if ((bus >= 0) && (bus < pciNumBuses) && pciBusInfo[bus] && - pciBusInfo[bus]->funcs->pciWriteWord) { - (*pciBusInfo[bus]->funcs->pciWriteWord)(tag, offset, val); - } else { - tmp = pciReadLong(tag, aligned_offset); - - tmp &= ~(0xffffL << shift); - tmp |= (((CARD32)val) << shift); - - pciWriteLong(tag, aligned_offset, tmp); - } -} - -_X_EXPORT void -pciWriteByte(PCITAG tag, int offset, CARD8 val) -{ - CARD32 tmp; - int aligned_offset = offset & ~3; - int shift = (offset & 3) *8 ; - int bus = PCI_BUS_FROM_TAG(tag); - - pciInit(); - - if ((bus >= 0) && (bus < pciNumBuses) && pciBusInfo[bus] && - pciBusInfo[bus]->funcs->pciWriteByte) { - (*pciBusInfo[bus]->funcs->pciWriteByte)(tag, offset, val); - } else { - - tmp = pciReadLong(tag, aligned_offset); - - tmp &= ~(0xffL << shift); - tmp |= (((CARD32)val) << shift); - - pciWriteLong(tag, aligned_offset, tmp); - } -} - -_X_EXPORT void -pciSetBitsLong(PCITAG tag, int offset, CARD32 mask, CARD32 val) -{ - int bus = PCI_BUS_FROM_TAG(tag); - -#ifdef DEBUGPCI - ErrorF("pciReadLong(0x%lx, %d)\n", tag, offset); -#endif - pciInit(); - - if ((bus >= 0) && (bus < pciNumBuses) && pciBusInfo[bus] && - pciBusInfo[bus]->funcs->pciSetBitsLong) { - (*pciBusInfo[bus]->funcs->pciSetBitsLong)(tag, offset, mask, val); + ARCH_PCI_INIT(); } } -void -pciSetBitsByte(PCITAG tag, int offset, CARD8 mask, CARD8 val) -{ - CARD32 tmp_mask, tmp_val; - int aligned_offset = offset & ~3; - int shift = (offset & 3) *8 ; - - tmp_mask = mask << shift; - tmp_val = val << shift; - pciSetBitsLong(tag, aligned_offset, tmp_mask, tmp_val); -} - _X_EXPORT ADDRESS pciBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr) { @@ -487,931 +253,54 @@ pciBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr) return(addr); } -_X_EXPORT ADDRESS -pciHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr) -{ - int bus = PCI_BUS_FROM_TAG(tag); - - pciInit(); - - if ((bus >= 0) && (bus < pciNumBuses) && pciBusInfo[bus] && - pciBusInfo[bus]->funcs->pciAddrHostToBus) - return (*pciBusInfo[bus]->funcs->pciAddrHostToBus)(tag, type, addr); - else - return(addr); -} - -/* - * pciGetBaseSize() returns the size of a PCI base address mapping in bits. - * The index identifies the base register: 0-5 are the six standard registers, - * and 6 is the ROM base register. If destructive is TRUE, it will write - * to the base address register to get an accurate result. Otherwise it - * makes a conservative guess based on the alignment of the already allocated - * address. If the result is accurate (ie, not an over-estimate), this is - * indicated by setting *min to TRUE (when min is non-NULL). This happens - * when either the destructive flag is set, the information is supplied by - * the OS if the OS supports this. - */ - -int -pciGetBaseSize(PCITAG tag, int index, Bool destructive, Bool *min) -{ - int offset; - CARD32 addr1; - CARD32 addr2; - CARD32 mask1; - CARD32 mask2; - int bits = 0; - - /* - * Eventually a function for this should be added to pciBusFuncs_t, but for - * now we'll just use a simple method based on the alignment of the already - * allocated address. - */ - - /* - * silently ignore bogus index values. Valid values are 0-6. 0-5 are - * the 6 base address registers, and 6 is the ROM base address register. - */ - if (index < 0 || index > 6) - return 0; - - pciInit(); - - if (xf86GetPciSizeFromOS(tag, index, &bits)) { - if (min) - *min = TRUE; - return bits; - } - - if (min) - *min = destructive; - - /* Get the PCI offset */ - if (index == 6) - offset = PCI_MAP_ROM_REG; - else - offset = PCI_MAP_REG_START + (index << 2); - - addr1 = pciReadLong(tag, offset); - /* - * Check if this is the second part of a 64 bit address. - * XXX need to check how endianness affects 64 bit addresses. - */ - if (index > 0 && index < 6) { - addr2 = pciReadLong(tag, offset - 4); - if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2)) - return 0; - } - - if (destructive) { - pciWriteLong(tag, offset, 0xffffffff); - mask1 = pciReadLong(tag, offset); - pciWriteLong(tag, offset, addr1); - } else { - mask1 = addr1; - } - - /* Check if this is the first part of a 64 bit address. */ - if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1)) { - if (PCIGETMEMORY(mask1) == 0) { - addr2 = pciReadLong(tag, offset + 4); - if (destructive) { - pciWriteLong(tag, offset + 4, 0xffffffff); - mask2 = pciReadLong(tag, offset + 4); - pciWriteLong(tag, offset + 4, addr2); - } else { - mask2 = addr2; - } - if (mask2 == 0) - return 0; - bits = 32; - while ((mask2 & 1) == 0) { - bits++; - mask2 >>= 1; - } - if (bits > 32) - return bits; - } - } - if (index < 6) - if (PCI_MAP_IS_MEM(mask1)) - mask1 = PCIGETMEMORY(mask1); - else - mask1 = PCIGETIO(mask1); - else - mask1 = PCIGETROM(mask1); - if (mask1 == 0) - return 0; - bits = 0; - while ((mask1 & 1) == 0) { - bits++; - mask1 >>= 1; - } - /* I/O maps can be no larger than 8 bits */ - - if ((index < 6) && PCI_MAP_IS_IO(addr1) && bits > 8) - bits = 8; - /* ROM maps can be no larger than 24 bits */ - if (index == 6 && bits > 24) - bits = 24; - return bits; -} - _X_EXPORT PCITAG pciTag(int busnum, int devnum, int funcnum) { return(PCI_MAKE_TAG(busnum,devnum,funcnum)); } -_X_EXPORT PCITAG -pciDomTag(int domnum, int busnum, int devnum, int funcnum) -{ - return(PCI_MAKE_TAG(PCI_MAKE_BUS(domnum,busnum),devnum,funcnum)); -} - -#if defined(PCI_MFDEV_SUPPORT) - -Bool -pciMfDev(int busnum, int devnum) -{ - PCITAG tag0, tag1; - CARD32 id0, id1, val; - - /* Detect a multi-function device that complies to the PCI 2.0 spec */ - - tag0 = PCI_MAKE_TAG(busnum, devnum, 0); - id0 = pciReadLong(tag0, PCI_ID_REG); - if ((CARD16)(id0 + 1) <= (CARD16)1UL) - return FALSE; - - val = pciReadLong(tag0, PCI_HEADER_MISC) & 0x00ff0000; - if ((val != 0x00ff0000) && (val & PCI_HEADER_MULTIFUNCTION)) - return TRUE; - - /* - * Now, to find non-compliant devices... - * If there is a valid ID for function 1 and the ID for func 0 and 1 - * are different, or the base0 values of func 0 and 1 are differend, - * then assume there is a multi-function device. - */ - tag1 = PCI_MAKE_TAG(busnum, devnum, 1); - id1 = pciReadLong(tag1, PCI_ID_REG); - if ((CARD16)(id1 + 1) <= (CARD16)1UL) - return FALSE; - - /* Vendor IDs should match */ - if ((id0 ^ id1) & 0x0000ffff) - return FALSE; - - if ((id0 != id1) || - /* Note the following test is valid for header types 0, 1 and 2 */ - (pciReadLong(tag0, PCI_MAP_REG_START) != - pciReadLong(tag1, PCI_MAP_REG_START))) - return TRUE; - - return FALSE; -} - -#endif - -/* - * Generic find/read/write functions - */ -PCITAG -pciGenFindNext(void) -{ - CARD32 devid, tmp; - int sec_bus, pri_bus; - static int previousBus = 0; - Bool speculativeProbe = FALSE; - unsigned char base_class, sub_class; - -#ifdef DEBUGPCI - ErrorF("pciGenFindNext\n"); -#endif - - for (;;) { - -#ifdef DEBUGPCI - ErrorF("pciGenFindNext: pciBusNum %d\n", pciBusNum); -#endif - if (pciBusNum == -1) { - /* - * Start at top of the order - */ - if (pciNumBuses <= 0) - return(PCI_NOT_FOUND); - - /* Skip ahead to the first bus defined by pciInit() */ - for (pciBusNum = 0; !pciBusInfo[pciBusNum]; ++pciBusNum); - pciFuncNum = 0; - pciDevNum = 0; - previousBus = pciBusNum; /* make sure previousBus exists */ - } else { -#ifdef PCI_MFDEV_SUPPORT -#ifdef DEBUGPCI - ErrorF("pciGenFindNext: pciFuncNum %d\n", pciFuncNum); -#endif - /* - * Somewhere in middle of order. Determine who's - * next up - */ - if (pciFuncNum == 0) { - /* - * Is current dev a multifunction device? - */ - if (!speculativeProbe && pciMfDev(pciBusNum, pciDevNum)) - /* Probe for other functions */ - pciFuncNum = 1; - else - /* - * No more functions this device. Next - * device please - */ - pciDevNum ++; - } else if (++pciFuncNum >= 8) { - /* No more functions for this device. Next device please */ - pciFuncNum = 0; - pciDevNum ++; - } -#else - pciDevNum ++; -#endif - if (pciDevNum >= 32 || - !pciBusInfo[pciBusNum] || - pciDevNum >= pciBusInfo[pciBusNum]->numDevices) { -#ifdef DEBUGPCI - ErrorF("pciGenFindNext: next bus\n"); -#endif - /* - * No more devices for this bus. Next bus please - */ - if (speculativeProbe) { - NextSpeculativeBus: - xfree(pciBusInfo[pciBusNum]); - pciBusInfo[pciBusNum] = NULL; - speculativeProbe = FALSE; - } - - if (++pciBusNum >= pciMaxBusNum) { -#ifdef DEBUGPCI - ErrorF("pciGenFindNext: out of buses\n"); -#endif - /* No more buses. All done for now */ - return(PCI_NOT_FOUND); - } - - pciDevNum = 0; - } - } - -#ifdef DEBUGPCI - ErrorF("pciGenFindNext: pciBusInfo[%d] = 0x%lx\n", pciBusNum, pciBusInfo[pciBusNum]); -#endif - if (!pciBusInfo[pciBusNum]) { - pciBusInfo[pciBusNum] = xnfalloc(sizeof(pciBusInfo_t)); - *pciBusInfo[pciBusNum] = *pciBusInfo[previousBus]; - - speculativeProbe = TRUE; - } - - /* - * At this point, pciBusNum, pciDevNum, and pciFuncNum have been - * advanced to the next device. Compute the tag, and read the - * device/vendor ID field. - */ -#ifdef DEBUGPCI - ErrorF("pciGenFindNext: [%d, %d, %d]\n", pciBusNum, pciDevNum, pciFuncNum); -#endif - pciDeviceTag = PCI_MAKE_TAG(pciBusNum, pciDevNum, pciFuncNum); - inProbe = TRUE; - devid = pciReadLong(pciDeviceTag, PCI_ID_REG); - inProbe = FALSE; -#ifdef DEBUGPCI - ErrorF("pciGenFindNext: pciDeviceTag = 0x%lx, devid = 0x%lx\n", pciDeviceTag, devid); -#endif - if ((CARD16)(devid + 1U) <= (CARD16)1UL) - continue; /* Nobody home. Next device please */ - - /* - * Some devices mis-decode configuration cycles in such a way as to - * create phantom buses. - */ - if (speculativeProbe && (pciDevNum == 0) && (pciFuncNum == 0) && - (PCI_BUS_NO_DOMAIN(pciBusNum) > 0)) { - for (;;) { - if (++pciDevNum >= pciBusInfo[pciBusNum]->numDevices) - goto NextSpeculativeBus; - if (devid != - pciReadLong(PCI_MAKE_TAG(pciBusNum, pciDevNum, 0), - PCI_ID_REG)) - break; - } - - pciDevNum = 0; - } - - if (pciNumBuses <= pciBusNum) - pciNumBuses = pciBusNum + 1; - - speculativeProbe = FALSE; - previousBus = pciBusNum; - -#ifdef PCI_BRIDGE_SUPPORT - /* - * Before checking for a specific devid, look for enabled - * PCI to PCI bridge devices. If one is found, create and - * initialize a bus info record (if one does not already exist). - */ - tmp = pciReadLong(pciDeviceTag, PCI_CLASS_REG); - base_class = PCI_CLASS_EXTRACT(tmp); - sub_class = PCI_SUBCLASS_EXTRACT(tmp); - if ((base_class == PCI_CLASS_BRIDGE) && - ((sub_class == PCI_SUBCLASS_BRIDGE_PCI) || - (sub_class == PCI_SUBCLASS_BRIDGE_CARDBUS))) { - tmp = pciReadLong(pciDeviceTag, PCI_PCI_BRIDGE_BUS_REG); - sec_bus = PCI_SECONDARY_BUS_EXTRACT(tmp, pciDeviceTag); - pri_bus = PCI_PRIMARY_BUS_EXTRACT(tmp, pciDeviceTag); -#ifdef DEBUGPCI - ErrorF("pciGenFindNext: pri_bus %d sec_bus %d\n", - pri_bus, sec_bus); -#endif - if (pciBusNum != pri_bus) { - /* Some bridges do not implement the primary bus register */ - if ((PCI_BUS_NO_DOMAIN(pri_bus) != 0) || - (sub_class != PCI_SUBCLASS_BRIDGE_CARDBUS)) - xf86Msg(X_WARNING, - "pciGenFindNext: primary bus mismatch on PCI" - " bridge 0x%08lx (0x%02x, 0x%02x)\n", - pciDeviceTag, pciBusNum, pri_bus); - pri_bus = pciBusNum; - } - if ((pri_bus < sec_bus) && (sec_bus < pciMaxBusNum) && - pciBusInfo[pri_bus]) { - /* - * Found a secondary PCI bus - */ - if (!pciBusInfo[sec_bus]) { - pciBusInfo[sec_bus] = xnfalloc(sizeof(pciBusInfo_t)); - - /* Copy parents settings... */ - *pciBusInfo[sec_bus] = *pciBusInfo[pri_bus]; - } - - /* ...but not everything same as parent */ - pciBusInfo[sec_bus]->primary_bus = pri_bus; - pciBusInfo[sec_bus]->secondary = TRUE; - pciBusInfo[sec_bus]->numDevices = 32; - - if (pciNumBuses <= sec_bus) - pciNumBuses = sec_bus + 1; - } - } -#endif - - /* - * Does this device match the requested devid after - * applying mask? - */ -#ifdef DEBUGPCI - ErrorF("pciGenFindNext: pciDevidMask = 0x%lx, pciDevid = 0x%lx\n", pciDevidMask, pciDevid); -#endif - if ((devid & pciDevidMask) == pciDevid) - /* Yes - Return it. Otherwise, next device */ - return(pciDeviceTag); /* got a match */ - - } /* for */ - /*NOTREACHED*/ -} - -PCITAG -pciGenFindFirst(void) -{ - /* Reset PCI bus number to start from top */ - pciBusNum = -1; - - return pciGenFindNext(); -} - -CARD32 -pciByteSwap(CARD32 u) -{ -#if X_BYTE_ORDER == X_BIG_ENDIAN - - return lswapl(u); - -#else /* !BIG_ENDIAN */ - - return(u); - -#endif -} - ADDRESS pciAddrNOOP(PCITAG tag, PciAddrType type, ADDRESS addr) { return(addr); } -_X_EXPORT pciConfigPtr * -xf86scanpci(int flags) +_X_EXPORT Bool +xf86scanpci(void) { - pciConfigPtr devp; - pciBusInfo_t *busp; - int idx = 0, i; - PCITAG tag; static Bool done = FALSE; + static Bool success = FALSE; /* * if we haven't found PCI devices checking for pci_devp may * result in an endless recursion if platform/OS specific PCI * bus probing code calls this function from with in it. */ - if (done || pci_devp) - return pci_devp; + if (done) + return success; done = TRUE; + success = (pci_system_init() == 0); pciInit(); -#ifdef XF86SCANPCI_WRAPPER - XF86SCANPCI_WRAPPER(SCANPCI_INIT); -#endif - - tag = pciFindFirst(0,0); /* 0 mask means match any valid device */ - /* Check if no devices, return now */ - if (tag == PCI_NOT_FOUND) { -#ifdef XF86SCANPCI_WRAPPER - XF86SCANPCI_WRAPPER(SCANPCI_TERM); -#endif - return NULL; - } - -#ifdef DEBUGPCI - ErrorF("xf86scanpci: tag = 0x%lx\n", tag); -#endif -#ifndef OLD_FORMAT - xf86MsgVerb(X_INFO, 2, "PCI: PCI scan (all values are in hex)\n"); -#endif - - while (idx < xf86MaxPciDevs && tag != PCI_NOT_FOUND) { - devp = xcalloc(1, sizeof(pciDevice)); - if (!devp) { - xf86Msg(X_ERROR, - "xf86scanpci: Out of memory after %d devices!!\n", idx); - return (pciConfigPtr *)NULL; - } - - /* Identify pci device by bus, dev, func, and tag */ - devp->tag = tag; - devp->busnum = PCI_BUS_FROM_TAG(tag); - devp->devnum = PCI_DEV_FROM_TAG(tag); - devp->funcnum = PCI_FUNC_FROM_TAG(tag); - - /* Read config space for this device */ - for (i = 0; i < 17; i++) /* PCI hdr plus 1st dev spec dword */ - devp->cfgspc.dwords[i] = pciReadLong(tag, i * sizeof(CARD32)); - - /* Some broken devices don't implement this field... */ - if (devp->pci_header_type == 0xff) - devp->pci_header_type = 0; - - switch (devp->pci_header_type & 0x7f) { - case 0: - /* Get base address sizes for type 0 headers */ - for (i = 0; i < 7; i++) - devp->basesize[i] = - pciGetBaseSize(tag, i, FALSE, &devp->minBasesize); - break; - - case 1: - case 2: - /* Allow master aborts to complete normally on secondary buses */ - if (!(devp->pci_bridge_control & PCI_PCI_BRIDGE_MASTER_ABORT_EN)) - break; - pciWriteByte(tag, PCI_PCI_BRIDGE_CONTROL_REG, - devp->pci_bridge_control & - ~(PCI_PCI_BRIDGE_MASTER_ABORT_EN | - PCI_PCI_BRIDGE_SECONDARY_RESET)); - break; - - default: - break; - } - -#ifdef OLD_FORMAT - xf86MsgVerb(X_INFO, 2, "PCI: BusID 0x%.2x,0x%02x,0x%1x " - "ID 0x%04x,0x%04x Rev 0x%02x Class 0x%02x,0x%02x\n", - devp->busnum, devp->devnum, devp->funcnum, - devp->pci_vendor, devp->pci_device, devp->pci_rev_id, - devp->pci_base_class, devp->pci_sub_class); -#else - xf86MsgVerb(X_INFO, 2, "PCI: %.2x:%02x:%1x: chip %04x,%04x" - " card %04x,%04x rev %02x class %02x,%02x,%02x hdr %02x\n", - devp->busnum, devp->devnum, devp->funcnum, - devp->pci_vendor, devp->pci_device, - devp->pci_subsys_vendor, devp->pci_subsys_card, - devp->pci_rev_id, devp->pci_base_class, - devp->pci_sub_class, devp->pci_prog_if, - devp->pci_header_type); -#endif - - pci_devp[idx++] = devp; - if (idx == xf86MaxPciDevs) - break; - tag = pciFindNext(); - -#ifdef DEBUGPCI - ErrorF("xf86scanpci: tag = pciFindNext = 0x%lx\n", tag); -#endif - } - - /* Restore modified data (in reverse order), and link buses */ - while (--idx >= 0) { - devp = pci_devp[idx]; - switch (devp->pci_header_type & 0x7f) { - case 0: - if ((devp->pci_base_class != PCI_CLASS_BRIDGE) || - (devp->pci_sub_class != PCI_SUBCLASS_BRIDGE_HOST)) - break; - pciBusInfo[devp->busnum]->bridge = devp; - pciBusInfo[devp->busnum]->primary_bus = devp->busnum; - break; - - case 1: - case 2: - i = PCI_SECONDARY_BUS_EXTRACT(devp->pci_pp_bus_register, devp->tag); - if (i > devp->busnum) { - if (pciBusInfo[i]) { - pciBusInfo[i]->bridge = devp; - /* - * The back link needs to be set here, and is unlikely to - * change. - */ - devp->businfo = pciBusInfo[i]; - } -#ifdef ARCH_PCI_PCI_BRIDGE - ARCH_PCI_PCI_BRIDGE(devp); -#endif - } - if (!(devp->pci_bridge_control & PCI_PCI_BRIDGE_MASTER_ABORT_EN)) - break; - pciWriteByte(devp->tag, PCI_PCI_BRIDGE_CONTROL_REG, - devp->pci_bridge_control & ~PCI_PCI_BRIDGE_SECONDARY_RESET); - break; - - default: - break; - } - } - -#ifdef XF86SCANPCI_WRAPPER - XF86SCANPCI_WRAPPER(SCANPCI_TERM); -#endif - - /* - * Lastly, link bridges to their secondary bus, after the architecture has - * had a chance to modify these assignments. - */ - for (idx = 0; idx < pciNumBuses; idx++) { - if (!(busp = pciBusInfo[idx]) || !(devp = busp->bridge)) - continue; - devp->businfo = busp; - } - -#ifndef OLD_FORMAT - xf86MsgVerb(X_INFO, 2, "PCI: End of PCI scan\n"); -#endif - - return pci_devp; -} - -pciConfigPtr -xf86GetPciConfigFromTag(PCITAG Tag) -{ - pciConfigPtr pDev; - int i = 0; - - for (i = 0 ; (pDev = pci_devp[i]) && i <= xf86MaxPciDevs; i++) { - if (Tag == pDev->tag) - return pDev; - } - - return NULL; /* Bad data */ + return success; } -CARD32 -pciCheckForBrokenBase(PCITAG Tag,int basereg) -{ - pciWriteLong(Tag, PCI_MAP_REG_START + (basereg << 2), 0xffffffff); - return pciReadLong(Tag, PCI_MAP_REG_START + (basereg << 2)); -} - -#if defined(INCLUDE_XF86_MAP_PCI_MEM) - -_X_EXPORT pointer -xf86MapPciMem(int ScreenNum, int Flags, PCITAG Tag, ADDRESS Base, - unsigned long Size) -{ - ADDRESS hostbase = pciBusAddrToHostAddr(Tag, PCI_MEM,Base); - pointer base; - CARD32 save = 0; - - /* - * If there are possible read side-effects, disable memory while - * doing the mapping. - */ - if (Flags & VIDMEM_READSIDEEFFECT) { - save = pciReadLong(Tag, PCI_CMD_STAT_REG); - pciWriteLong(Tag, PCI_CMD_STAT_REG, - save & ~PCI_CMD_MEM_ENABLE); - } - base = xf86MapDomainMemory(ScreenNum, Flags, Tag, hostbase, Size); - if (!base) { - FatalError("xf86MapPciMem: Could not mmap PCI memory " - "[base=0x%lx,hostbase=0x%lx,size=%lx] (%s)\n", - Base, hostbase, Size, strerror(errno)); - } - /* - * If read side-effects, do whatever might be needed to prevent - * unintended reads, then restore PCI_CMD_STAT_REG. - */ - if (Flags & VIDMEM_READSIDEEFFECT) { - xf86MapReadSideEffects(ScreenNum, Flags, base, Size); - pciWriteLong(Tag, PCI_CMD_STAT_REG, save); - } - return((pointer)base); -} - -static int -handlePciBIOS( PCITAG Tag, int basereg, unsigned char * buf, int len ) -{ - CARD32 romsave = 0; - int i; - romBaseSource b_reg; - ADDRESS hostbase; - CARD8 tmp[64]; - int ret = 0; - - romsave = pciReadLong(Tag, PCI_MAP_ROM_REG); - - for (i = ROM_BASE_PRESET; i <= ROM_BASE_FIND; i++) { - memType savebase = 0, newbase, romaddr; - - switch (i) { - case ROM_BASE_PRESET: - /* Does the driver have a preference? */ - if (basereg > ROM_BASE_PRESET && basereg <= ROM_BASE_FIND) - b_reg = basereg; - else - b_reg = ++i; - break; - case ROM_BASE_FIND: - /* - * If we have something that looks like a valid address - * in romsave, it's probably not going to help to try - * to guess a new address and reprogram it. - */ - if (PCIGETROM(romsave)) { - pciWriteLong(Tag, PCI_MAP_ROM_REG, PCI_MAP_ROM_ADDRESS_MASK); - if (romsave != pciReadLong(Tag, PCI_MAP_ROM_REG)) { - pciWriteLong(Tag, PCI_MAP_ROM_REG, romsave); - continue; - } - } - default: - b_reg = i; - } - - if (!(newbase = getValidBIOSBase(Tag, b_reg))) - continue; /* no valid address found */ - - romaddr = PCIGETROM(newbase); - - /* if we use a mem base save it and move it out of the way */ - if (b_reg >= 0 && b_reg <= 5) { - memType emptybase; - savebase = pciReadLong(Tag, PCI_MAP_REG_START+(b_reg<<2)); - xf86MsgVerb(X_INFO,5,"xf86ReadPciBios: modifying membase[%i]" - " for device %i:%i:%i\n", basereg, - (int)PCI_BUS_FROM_TAG(Tag), (int)PCI_DEV_FROM_TAG(Tag), - (int)PCI_FUNC_FROM_TAG(Tag)); - if (!(emptybase = getEmptyPciRange(Tag,b_reg))) { - xf86Msg(X_ERROR,"Cannot find empty range to map base to\n"); - return 0; - } - pciWriteLong(Tag, PCI_MAP_REG_START + (b_reg << 2), - emptybase); - } - /* Set ROM base address and enable ROM address decoding */ - pciWriteLong(Tag, PCI_MAP_ROM_REG, romaddr - | PCI_MAP_ROM_DECODE_ENABLE); - - hostbase = pciBusAddrToHostAddr(Tag, PCI_MEM, PCIGETROM(romaddr)); - - if ((xf86ReadDomainMemory(Tag, hostbase, sizeof(tmp), tmp) != - sizeof(tmp)) || - (tmp[0] != 0x55) || (tmp[1] != 0xaa) || !tmp[2] ) { - /* Restore the base registers if they were changed. */ - pciWriteLong(Tag, PCI_MAP_ROM_REG, romsave); - if (savebase) pciWriteLong(Tag, PCI_MAP_REG_START + (b_reg << 2), - (CARD32) savebase); - - /* No BIOS found: try another address */ - continue; - } - - ret = readPciBios( Tag, tmp, hostbase, buf, len, PCI_BIOS_PC ); - - /* Restore the base register if it was changed. */ - if (savebase) pciWriteLong(Tag, PCI_MAP_REG_START + (b_reg << 2), - (CARD32) savebase); - /* Restore ROM address decoding */ - pciWriteLong(Tag, PCI_MAP_ROM_REG, romsave); - - return ret; - } - /* Restore ROM address decoding */ - pciWriteLong(Tag, PCI_MAP_ROM_REG, romsave); - return 0; -} - - -static int -readPciBios(PCITAG Tag, CARD8* tmp, ADDRESS hostbase, unsigned char * buf, - int len, PciBiosType bios_type ) -{ - unsigned int image_length = 0; - int ret; - - /* We found a PCI BIOS Image. Now we look for the correct type */ - while ((tmp[0] == 0x55) && (tmp[1] == 0xAA)) { - unsigned short data_off = tmp[0x18] | (tmp[0x19] << 8); - unsigned char data[0x18]; - unsigned char type; - - if ((xf86ReadDomainMemory(Tag, hostbase + data_off, sizeof(data), data) - != sizeof(data)) || - (data[0] != 'P') || - (data[1] != 'C') || - (data[2] != 'I') || - (data[3] != 'R')) - break; - - type = data[0x14]; -#ifdef PRINT_PCI - ErrorF("data segment in BIOS: 0x%x, type: 0x%x\n", data_off, type); -#endif - if (type != bios_type) { /* not correct image: find next one */ - const unsigned char indicator = data[0x15]; - unsigned int i_length; - - if (indicator & 0x80) /* last image */ - break; - - i_length = (data[0x10] | (data[0x11] << 8)) << 9; - -#ifdef PRINT_PCI - ErrorF( "data image length: 0x%x, ind: 0x%x\n", i_length, indicator ); -#endif - hostbase += i_length; - if (xf86ReadDomainMemory(Tag, hostbase, sizeof(tmp), tmp) - != sizeof(tmp)) - break; - continue; - } - /* OK, we have a PCI BIOS Image of the correct type */ - - if ( bios_type == PCI_BIOS_PC ) - image_length = tmp[2] << 9; - else - image_length = (data[0x10] | (data[0x11] << 8)) << 9; -#ifdef PRINT_PCI - ErrorF("BIOS length: 0x%x\n", image_length); -#endif - break; - } - - ret = 0; - if (image_length) { - - /* If no length is given return the full length. Beware: Area pointed to - * by Buf must be large enough! - */ - if (len == 0) { - len = image_length; - } - else if ( len > image_length ) { - len = image_length; - xf86MsgVerb( X_INFO, 3, "Truncating PCI BIOS Length to %i\n", - len ); - } - - /* Read BIOS */ - ret = xf86ReadDomainMemory( Tag, hostbase, len, buf ); - } - - return ret; -} - - -static int -HandlePciBios(PCITAG Tag, int basereg, unsigned char * buf, int len) -{ - int n, num; - CARD32 Acc1, Acc2; - PCITAG *pTag; - int i; - - /* fall back to the old code if the OS code fails */ - if (pciOSHandleBIOS) { - n = pciOSHandleBIOS(Tag, basereg, buf, len); - if (n) - return n; - } - - n = handlePciBIOS( Tag, basereg, buf, len ); - if (n) - return n; - - num = pciTestMultiDeviceCard(PCI_BUS_FROM_TAG(Tag), - PCI_DEV_FROM_TAG(Tag), - PCI_FUNC_FROM_TAG(Tag),&pTag); - - if (!num) return 0; - -#define PCI_ENA (PCI_CMD_MEM_ENABLE | PCI_CMD_IO_ENABLE) - Acc1 = pciReadLong(Tag, PCI_CMD_STAT_REG); - pciWriteLong(Tag, PCI_CMD_STAT_REG, (Acc1 & ~PCI_ENA)); - - for (i = 0; i < num; i++) { - Acc2 = pciReadLong(pTag[i], PCI_CMD_STAT_REG); - pciWriteLong(pTag[i], PCI_CMD_STAT_REG, (Acc2 | PCI_ENA)); - - n = handlePciBIOS( pTag[i], 0, buf, len ); - - pciWriteLong(pTag[i], PCI_CMD_STAT_REG, Acc2); - if (n) - break; - } - pciWriteLong(Tag, PCI_CMD_STAT_REG, Acc1); - return n; -} - -_X_EXPORT int -xf86ReadPciBIOS(unsigned long Offset, PCITAG Tag, int basereg, - unsigned char *Buf, int Len) -{ - return HandlePciBios(Tag, basereg, Buf, Len); -} - -#endif /* INCLUDE_XF86_MAP_PCI_MEM */ - #ifdef INCLUDE_XF86_NO_DOMAIN -_X_EXPORT int -xf86GetPciDomain(PCITAG Tag) -{ - return 0; -} - _X_EXPORT pointer -xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag, +xf86MapDomainMemory(int ScreenNum, int Flags, struct pci_device *dev, ADDRESS Base, unsigned long Size) { return xf86MapVidMem(ScreenNum, Flags, Base, Size); } -_X_EXPORT IOADDRESS -xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, - IOADDRESS Base, unsigned long Size) -{ - return Base; -} - -_X_EXPORT int -xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len, unsigned char *Buf) +IOADDRESS +xf86MapLegacyIO(struct pci_device *dev) { - int ret, length, rlength; - - /* Read in 64kB chunks */ - ret = 0; - while ((length = Len) > 0) { - if (length > 0x010000) length = 0x010000; - rlength = xf86ReadBIOS(Base, 0, Buf, length); - if (rlength < 0) { - ret = rlength; - break; - } - ret += rlength; - if (rlength < length) break; - Base += rlength; - Buf += rlength; - Len -= rlength; - } - - return ret; + (void) dev; + return 0; } #endif /* INCLUDE_XF86_NO_DOMAIN */ diff --git a/hw/xfree86/os-support/bus/Pci.h b/hw/xfree86/os-support/bus/Pci.h index f0cb916da..632a7a048 100644 --- a/hw/xfree86/os-support/bus/Pci.h +++ b/hw/xfree86/os-support/bus/Pci.h @@ -157,50 +157,6 @@ #define PCI_TAG_NO_DOMAIN(tag) ((tag) & 0x00ffff00u) /* - * Macros for bus numbers found in P2P headers. - */ -#define PCI_PRIMARY_BUS_EXTRACT(x, tag) \ - ((((x) & PCI_PRIMARY_BUS_MASK ) >> 0) | (PCI_DOM_FROM_TAG(tag) << 8)) -#define PCI_SECONDARY_BUS_EXTRACT(x, tag) \ - ((((x) & PCI_SECONDARY_BUS_MASK ) >> 8) | (PCI_DOM_FROM_TAG(tag) << 8)) -#define PCI_SUBORDINATE_BUS_EXTRACT(x, tag) \ - ((((x) & PCI_SUBORDINATE_BUS_MASK) >> 16) | (PCI_DOM_FROM_TAG(tag) << 8)) - -#define PCI_PRIMARY_BUS_INSERT(x, y) \ - (((x) & ~PCI_PRIMARY_BUS_MASK ) | (((y) & 0xffu) << 0)) -#define PCI_SECONDARY_BUS_INSERT(x, y) \ - (((x) & ~PCI_SECONDARY_BUS_MASK ) | (((y) & 0xffu) << 8)) -#define PCI_SUBORDINATE_BUS_INSERT(x, y) \ - (((x) & ~PCI_SUBORDINATE_BUS_MASK) | (((y) & 0xffu) << 16)) - -/* Ditto for CardBus bridges */ -#define PCI_CB_PRIMARY_BUS_EXTRACT(x, tag) \ - PCI_PRIMARY_BUS_EXTRACT(x, tag) -#define PCI_CB_CARDBUS_BUS_EXTRACT(x, tag) \ - PCI_SECONDARY_BUS_EXTRACT(x, tag) -#define PCI_CB_SUBORDINATE_BUS_EXTRACT(x, tag) \ - PCI_SUBORDINATE_BUS_EXTRACT(x, tag) - -#define PCI_CB_PRIMARY_BUS_INSERT(x, tag) \ - PCI_PRIMARY_BUS_INSERT(x, tag) -#define PCI_CB_CARDBUS_BUS_INSERT(x, tag) \ - PCI_SECONDARY_BUS_INSERT(x, tag) -#define PCI_CB_SUBORDINATE_BUS_INSERT(x, tag) \ - PCI_SUBORDINATE_BUS_INSERT(x, tag) - -#if X_BYTE_ORDER == X_BIG_ENDIAN -#define PCI_CPU(val) (((val >> 24) & 0x000000ff) | \ - ((val >> 8) & 0x0000ff00) | \ - ((val << 8) & 0x00ff0000) | \ - ((val << 24) & 0xff000000)) -#define PCI_CPU16(val) (((val >> 8) & 0x000000ff) | \ - ((val << 8) & 0x0000ff00)) -#else -#define PCI_CPU(val) (val) -#define PCI_CPU16(val) (val) -#endif - -/* * Debug Macros/Definitions */ /* #define DEBUGPCI 2 */ /* Disable/enable trace in PCI code */ @@ -234,97 +190,79 @@ #if defined(__alpha__) # if defined(linux) # define ARCH_PCI_INIT axpPciInit -# define INCLUDE_XF86_MAP_PCI_MEM -# elif defined(__FreeBSD__) || defined(__OpenBSD__) +# elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) # define ARCH_PCI_INIT freebsdPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # elif defined(__NetBSD__) # define ARCH_PCI_INIT netbsdPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # endif #elif defined(__arm__) # if defined(linux) # define ARCH_PCI_INIT linuxPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # endif #elif defined(__hppa__) # if defined(linux) # define ARCH_PCI_INIT linuxPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # endif #elif defined(__ia64__) # if defined(linux) # define ARCH_PCI_INIT ia64linuxPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # elif defined(FreeBSD) # define ARCH_PCI_INIT freebsdPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # endif # define XF86SCANPCI_WRAPPER ia64ScanPCIWrapper #elif defined(__i386__) || defined(i386) -# define ARCH_PCI_INIT ix86PciInit -# define INCLUDE_XF86_MAP_PCI_MEM -# define INCLUDE_XF86_NO_DOMAIN # if defined(linux) -# define ARCH_PCI_OS_INIT linuxPciInit +# define ARCH_PCI_INIT linuxPciInit +# else +# define ARCH_PCI_INIT ix86PciInit # endif +# define INCLUDE_XF86_NO_DOMAIN #elif defined(__mc68000__) # if defined(linux) # define ARCH_PCI_INIT linuxPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # endif #elif defined(__mips__) # if defined(linux) # define ARCH_PCI_INIT linuxPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # endif #elif defined(__powerpc__) || defined(__powerpc64__) # if defined(linux) # define ARCH_PCI_INIT linuxPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN /* Needs kernel work to remove */ # elif defined(__FreeBSD__) || defined(__OpenBSD__) # define ARCH_PCI_INIT freebsdPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # elif defined(__NetBSD__) # define ARCH_PCI_INIT netbsdPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # else # define ARCH_PCI_INIT ppcPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # endif #elif defined(__s390__) # if defined(linux) # define ARCH_PCI_INIT linuxPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # endif #elif defined(__sh__) # if defined(linux) # define ARCH_PCI_INIT linuxPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # endif #elif defined(__sparc__) || defined(sparc) # if defined(linux) # define ARCH_PCI_INIT linuxPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # elif defined(sun) # define ARCH_PCI_INIT sparcPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # elif (defined(__OpenBSD__) || defined(__FreeBSD__)) && defined(__sparc64__) # define ARCH_PCI_INIT freebsdPciInit -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN # endif # if !defined(__FreeBSD__) && !defined(linux) @@ -333,28 +271,21 @@ #elif defined(__amd64__) || defined(__amd64) # if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) # define ARCH_PCI_INIT freebsdPciInit +# elif defined(linux) +# define ARCH_PCI_INIT linuxPciInit # else # define ARCH_PCI_INIT ix86PciInit # endif -# define INCLUDE_XF86_MAP_PCI_MEM # define INCLUDE_XF86_NO_DOMAIN -# if defined(linux) -# define ARCH_PCI_OS_INIT linuxPciInit -# endif #endif #ifndef ARCH_PCI_INIT #error No PCI support available for this architecture/OS combination #endif -extern void ARCH_PCI_INIT(void); -#if defined(ARCH_PCI_OS_INIT) -extern void ARCH_PCI_OS_INIT(void); -#endif +#undef INCLUDE_XF86_NO_DOMAIN -#if defined(ARCH_PCI_PCI_BRIDGE) -extern void ARCH_PCI_PCI_BRIDGE(pciConfigPtr pPCI); -#endif +extern void ARCH_PCI_INIT(void); #if defined(XF86SCANPCI_WRAPPER) typedef enum { @@ -369,27 +300,7 @@ extern void XF86SCANPCI_WRAPPER(scanpciWrapperOpt flags); * (e.g. a primary PCI bus and all of its secondaries) */ typedef struct pci_bus_funcs { - CARD32 (*pciReadLong)(PCITAG, int); - void (*pciWriteLong)(PCITAG, int, CARD32); - void (*pciSetBitsLong)(PCITAG, int, CARD32, CARD32); - ADDRESS (*pciAddrHostToBus)(PCITAG, PciAddrType, ADDRESS); ADDRESS (*pciAddrBusToHost)(PCITAG, PciAddrType, ADDRESS); - /* - * The next three are optional. If NULL, the corresponding function is - * to be performed generically. - */ - CARD16 (*pciControlBridge)(int, CARD16, CARD16); - void (*pciGetBridgeBuses)(int, int *, int *, int *); - /* Use pointer's to avoid #include recursion */ - void (*pciGetBridgeResources)(int, pointer *, pointer *, pointer *); - - /* These are optional and will be implemented using read long - * if not present. */ - CARD8 (*pciReadByte)(PCITAG, int); - void (*pciWriteByte)(PCITAG, int, CARD8); - CARD16 (*pciReadWord)(PCITAG, int); - void (*pciWriteWord)(PCITAG, int, CARD16); - } pciBusFuncs_t, *pciBusFuncs_p; /* @@ -402,7 +313,7 @@ typedef struct pci_bus_info { int primary_bus; /* Parent bus */ pciBusFuncs_p funcs; /* PCI access functions */ void *pciBusPriv; /* Implementation private data */ - pciConfigPtr bridge; /* bridge that opens this bus */ + struct pci_device *bridge; /* bridge that opens this bus */ } pciBusInfo_t; #define HOST_NO_BUS ((pciBusInfo_t *)(-1)) @@ -414,32 +325,14 @@ typedef struct pci_bus_info { #define PCI_CFG_MECH_OTHER 3 /* Something else */ /* Generic PCI service functions and helpers */ -PCITAG pciGenFindFirst(void); -PCITAG pciGenFindNext(void); CARD32 pciCfgMech1Read(PCITAG tag, int offset); void pciCfgMech1Write(PCITAG tag, int offset, CARD32 val); void pciCfgMech1SetBits(PCITAG tag, int offset, CARD32 mask, CARD32 val); -CARD32 pciByteSwap(CARD32); -Bool pciMfDev(int, int); ADDRESS pciAddrNOOP(PCITAG tag, PciAddrType type, ADDRESS); -extern void pciSetOSBIOSPtr(int (*bios_fn)(PCITAG Tag, int basereg, unsigned char * buf, int len)); -extern PCITAG (*pciFindFirstFP)(void); -extern PCITAG (*pciFindNextFP)(void); - -extern CARD32 pciDevid; -extern CARD32 pciDevidMask; - extern int pciMaxBusNum; -extern int pciBusNum; -extern int pciDevNum; -extern int pciFuncNum; -extern PCITAG pciDeviceTag; - -extern int xf86MaxPciDevs; - extern pciBusInfo_t *pciBusInfo[]; #endif /* _PCI_H */ diff --git a/hw/xfree86/os-support/bus/axpPci.c b/hw/xfree86/os-support/bus/axpPci.c index fc16a512e..e2f086c53 100644 --- a/hw/xfree86/os-support/bus/axpPci.c +++ b/hw/xfree86/os-support/bus/axpPci.c @@ -229,9 +229,6 @@ axpPciInit() pciNumBuses = bus + 1; } - - pciFindFirstFP = pciGenFindFirst; - pciFindNextFP = pciGenFindNext; } /* @@ -330,12 +327,11 @@ xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag, pDomain->dense_mem + Base - _bus_base(), Size); } -_X_EXPORT IOADDRESS -xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, - IOADDRESS Base, unsigned long Size) +IOADDRESS +xf86MapLegacyIO(struct pci_device *dev) { axpDomainPtr pDomain; - int domain = PCI_DOM_FROM_TAG(Tag); + const int domain = dev->domain; if ((domain < 0) || (domain >= pciNumDomains) || !(pDomain = xf86DomainInfo[domain])) @@ -346,7 +342,7 @@ xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, * base [this is ok since we also constrain sparse I/O systems to * a single domain in axpSetupDomains()] */ - if (pDomain->sparse_io) return Base; + if (pDomain->sparse_io) return 0; /* * I/O addresses on Alpha are really just different physical memory @@ -359,42 +355,11 @@ xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, * Map the entire I/O space (64kB) at once and only once. */ if (!pDomain->mapped_io) - pDomain->mapped_io = (IOADDRESS)xf86MapVidMem(ScreenNum, Flags, + pDomain->mapped_io = (IOADDRESS)xf86MapVidMem(-1, VIDMEM_MMIO, pDomain->dense_io - _bus_base(), 0x10000); - return pDomain->mapped_io + Base; -} - -_X_EXPORT int -xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len, unsigned char *Buf) -{ - static unsigned long pagemask = 0; - unsigned char *MappedAddr; - unsigned long MapSize; - ADDRESS MapBase; - int i; - - if (!pagemask) pagemask = xf86getpagesize() - 1; - - /* Ensure page boundaries */ - MapBase = Base & ~pagemask; - MapSize = ((Base + Len + pagemask) & ~pagemask) - MapBase; - - /* - * VIDMEM_MMIO in order to get sparse mapping on sparse memory systems - * so we can use mmio functions to read (that way we can really get byte - * at a time reads on dense memory systems with byte/word instructions. - */ - MappedAddr = xf86MapDomainMemory(-1, VIDMEM_READONLY | VIDMEM_MMIO, - Tag, MapBase, MapSize); - - for (i = 0; i < Len; i++) { - *Buf++ = xf86ReadMmio8(MappedAddr, Base - MapBase + i); - } - - xf86UnMapVidMem(-1, MappedAddr, MapSize); - return Len; + return pDomain->mapped_io; } resPtr diff --git a/hw/xfree86/os-support/bus/freebsdPci.c b/hw/xfree86/os-support/bus/freebsdPci.c index 61cb405a8..ff11c72f4 100644 --- a/hw/xfree86/os-support/bus/freebsdPci.c +++ b/hw/xfree86/os-support/bus/freebsdPci.c @@ -83,7 +83,7 @@ static pciBusInfo_t freebsdPci0 = { /* bridge */ NULL }; -#if !defined(__OpenBSD__) && !defined(__FreeBSD__) +#if !defined(__OpenBSD__) && !defined(__FreeBSD__) && !defined(__DragonFly__) #if X_BYTE_ORDER == X_BIG_ENDIAN #ifdef __sparc__ #ifndef ASI_PL @@ -124,8 +124,6 @@ freebsdPciInit() pciNumBuses = 1; pciBusInfo[0] = &freebsdPci0; - pciFindFirstFP = pciGenFindFirst; - pciFindNextFP = pciGenFindNext; } static CARD32 diff --git a/hw/xfree86/os-support/bus/ix86Pci.c b/hw/xfree86/os-support/bus/ix86Pci.c index fd7bdf6c8..3ed4f1422 100644 --- a/hw/xfree86/os-support/bus/ix86Pci.c +++ b/hw/xfree86/os-support/bus/ix86Pci.c @@ -171,6 +171,7 @@ /* * Intel x86 platform specific PCI access functions */ +#if 0 static CARD32 ix86PciReadLongSetup(PCITAG tag, int off); static void ix86PciWriteLongSetup(PCITAG, int off, CARD32 val); static void ix86PciSetBitsLongSetup(PCITAG, int off, CARD32 mask, CARD32 val); @@ -180,27 +181,34 @@ static void ix86PciSetBitsLongCFG1(PCITAG, int off, CARD32 mask, CARD32 val); static CARD32 ix86PciReadLongCFG2(PCITAG tag, int off); static void ix86PciWriteLongCFG2(PCITAG, int off, CARD32 val); static void ix86PciSetBitsLongCFG2(PCITAG, int off, CARD32 mask, CARD32 val); +#endif static pciBusFuncs_t ix86Funcs0 = { +#if 0 /* pciReadLong */ ix86PciReadLongSetup, /* pciWriteLong */ ix86PciWriteLongSetup, /* pciSetBitsLong */ ix86PciSetBitsLongSetup, +#endif /* pciAddrHostToBus */ pciAddrNOOP, /* pciAddrBusToHost */ pciAddrNOOP }; static pciBusFuncs_t ix86Funcs1 = { +#if 0 /* pciReadLong */ ix86PciReadLongCFG1, /* pciWriteLong */ ix86PciWriteLongCFG1, /* pciSetBitsLong */ ix86PciSetBitsLongCFG1, +#endif /* pciAddrHostToBus */ pciAddrNOOP, /* pciAddrBusToHost */ pciAddrNOOP }; static pciBusFuncs_t ix86Funcs2 = { +#if 0 /* pciReadLong */ ix86PciReadLongCFG2, /* pciWriteLong */ ix86PciWriteLongCFG2, /* pciSetBitsLong */ ix86PciSetBitsLongCFG2, +#endif /* pciAddrHostToBus */ pciAddrNOOP, /* pciAddrBusToHost */ pciAddrNOOP }; @@ -218,6 +226,7 @@ static pciBusInfo_t ix86Pci0 = { static Bool ix86PciBusCheck(void) { +#if 0 PCITAG tag; CARD32 id, class; CARD8 device; @@ -250,6 +259,7 @@ ix86PciBusCheck(void) break; } } +#endif return FALSE; } @@ -271,12 +281,7 @@ void ix86PciSelectCfgmech(void) * We rely on xf86Info.pciFlags to tell which mechanisms to try.... */ switch (xf86Info.pciFlags) { - case PCIOsConfig: -#ifdef ARCH_PCI_OS_INIT - return; -#endif - case PCIProbe1: if (!xf86EnableIO()) return; @@ -544,6 +549,7 @@ ix86PcibusTag(CARD8 bus, CARD8 cardnum, CARD8 func) } #endif +#if 0 static CARD32 ix86PciReadLongSetup(PCITAG Tag, int reg) { @@ -680,6 +686,7 @@ ix86PciSetBitsLongCFG2(PCITAG Tag, int reg, CARD32 mask, CARD32 val) outb(PCI_CFGMECH2_ENABLE_REG, 0); outb(PCI_CFGMECH2_FORWARD_REG, 0); } +#endif void ix86PciInit() @@ -687,8 +694,6 @@ ix86PciInit() /* Initialize pciBusInfo[] array and function pointers */ pciNumBuses = 1; pciBusInfo[0] = &ix86Pci0; - pciFindFirstFP = pciGenFindFirst; - pciFindNextFP = pciGenFindNext; /* Make sure that there is a PCI bus present. */ ix86PciSelectCfgmech(); diff --git a/hw/xfree86/os-support/bus/linuxPci.c b/hw/xfree86/os-support/bus/linuxPci.c index 9a9a99d49..b88fae6c7 100644 --- a/hw/xfree86/os-support/bus/linuxPci.c +++ b/hw/xfree86/os-support/bus/linuxPci.c @@ -60,31 +60,15 @@ * linux platform specific PCI access functions -- using /proc/bus/pci * needs kernel version 2.2.x */ -static CARD32 linuxPciCfgRead(PCITAG tag, int off); -static void linuxPciCfgWrite(PCITAG, int off, CARD32 val); -static void linuxPciCfgSetBits(PCITAG tag, int off, CARD32 mask, CARD32 bits); static ADDRESS linuxTransAddrBusToHost(PCITAG tag, PciAddrType type, ADDRESS addr); #if defined(__powerpc__) static ADDRESS linuxPpcBusAddrToHostAddr(PCITAG, PciAddrType, ADDRESS); -static ADDRESS linuxPpcHostAddrToBusAddr(PCITAG, PciAddrType, ADDRESS); #endif -static CARD8 linuxPciCfgReadByte(PCITAG tag, int off); -static void linuxPciCfgWriteByte(PCITAG tag, int off, CARD8 val); -static CARD16 linuxPciCfgReadWord(PCITAG tag, int off); -static void linuxPciCfgWriteWord(PCITAG tag, int off, CARD16 val); -static int linuxPciHandleBIOS(PCITAG Tag, int basereg, unsigned char *buf, int len); -static Bool linuxDomainSupport(void); - static pciBusFuncs_t linuxFuncs0 = { -/* pciReadLong */ linuxPciCfgRead, -/* pciWriteLong */ linuxPciCfgWrite, -/* pciSetBitsLong */ linuxPciCfgSetBits, #if defined(__powerpc__) -/* pciAddrHostToBus */ linuxPpcHostAddrToBusAddr, /* pciAddrBusToHost */ linuxPpcBusAddrToHostAddr, #else -/* pciAddrHostToBus */ pciAddrNOOP, /* linuxTransAddrBusToHost is busted on sparc64 but the PCI rework tree * makes it all moot, so we kludge it for now */ #if defined(__sparc__) @@ -93,16 +77,6 @@ static pciBusFuncs_t linuxFuncs0 = { /* pciAddrBusToHost */ linuxTransAddrBusToHost, #endif /* __sparc64__ */ #endif - -/* pciControlBridge */ NULL, -/* pciGetBridgeBuses */ NULL, -/* pciGetBridgeResources */ NULL, - -/* pciReadByte */ linuxPciCfgReadByte, -/* pciWriteByte */ linuxPciCfgWriteByte, - -/* pciReadWord */ linuxPciCfgReadWord, -/* pciWriteWord */ linuxPciCfgWriteWord, }; static pciBusInfo_t linuxPci0 = { @@ -115,150 +89,108 @@ static pciBusInfo_t linuxPci0 = { /* bridge */ NULL }; -/* from lnx_pci.c. */ -extern int lnxPciInit(void); +static const struct pci_id_match match_host_bridge = { + PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, + (PCI_CLASS_BRIDGE << 16) | (PCI_SUBCLASS_BRIDGE_HOST << 8), + 0x0000ffff00, 0 +}; -static Bool domain_support = FALSE; +#ifndef INCLUDE_XF86_NO_DOMAIN +#define MAX_DOMAINS 257 +static pointer DomainMmappedIO[MAX_DOMAINS]; +#endif void -linuxPciInit() +linuxPciInit(void) { struct stat st; + +#ifndef INCLUDE_XF86_NO_DOMAIN + (void) memset(DomainMmappedIO, 0, sizeof(DomainMmappedIO)); +#endif + if ((xf86Info.pciFlags == PCIForceNone) || (-1 == stat("/proc/bus/pci", &st))) { /* when using this as default for all linux architectures, we'll need a fallback for 2.0 kernels here */ return; } -#ifndef INCLUDE_XF86_NO_DOMAIN - domain_support = linuxDomainSupport(); -#endif pciNumBuses = 1; pciBusInfo[0] = &linuxPci0; - pciFindFirstFP = pciGenFindFirst; - pciFindNextFP = pciGenFindNext; - pciSetOSBIOSPtr(linuxPciHandleBIOS); - xf86MaxPciDevs = lnxPciInit(); } +/** + * \bug + * The generation of the procfs file name for the domain != 0 case may not be + * correct. + */ static int -linuxPciOpenFile(PCITAG tag, Bool write) +linuxPciOpenFile(struct pci_device *dev, Bool write) { - static int ldomain, lbus,ldev,lfunc,fd = -1,is_write = 0; - int domain, bus, dev, func; - char file[64]; - struct stat ignored; - static int is26 = -1; - - domain = PCI_DOM_FROM_TAG(tag); - bus = PCI_BUS_NO_DOMAIN(PCI_BUS_FROM_TAG(tag)); - dev = PCI_DEV_FROM_TAG(tag); - func = PCI_FUNC_FROM_TAG(tag); - if (is26 == -1) { - if (stat("/sys/bus/pci",&ignored) < 0) - is26 = 0; - else - is26 = 1; - } + static struct pci_device *last_dev = NULL; + static int fd = -1,is_write = 0; + char file[64]; + struct stat ignored; + static int is26 = -1; + + if (dev == NULL) { + return -1; + } + + if (is26 == -1) { + is26 = (stat("/sys/bus/pci", &ignored) < 0) ? 0 : 1; + } - if (!domain_support && domain > 0) - return -1; - - if (fd == -1 || (write && (!is_write)) || domain != ldomain - || bus != lbus || dev != ldev || func != lfunc) { - if (fd != -1) { - close(fd); - fd = -1; - } - if (is26) - sprintf(file,"/sys/bus/pci/devices/%04x:%02x:%02x.%01x/config", - domain, bus, dev, func); - else { - if (bus < 256) { - sprintf(file, "/proc/bus/pci/%04x:%02x", domain, bus); - if (stat(file, &ignored) < 0) { - if (domain == 0) - sprintf(file, "/proc/bus/pci/%02x/%02x.%1x", - bus, dev, func); - else - goto bail; - } else - sprintf(file, "/proc/bus/pci/%04x:%02x/%02x.%1x", - domain, bus, dev, func); - } else { - sprintf(file, "/proc/bus/pci/%04x:%04x", domain, bus); - if (stat(file, &ignored) < 0) { - if (domain == 0) - sprintf(file, "/proc/bus/pci/%04x/%02x.%1x", - bus, dev, func); - else - goto bail; - } else - sprintf(file, "/proc/bus/pci/%04x:%04x/%02x.%1x", - domain, bus, dev, func); - } + if (fd == -1 || (write && (!is_write)) || (last_dev != dev)) { + if (fd != -1) { + close(fd); + fd = -1; + } + + if (is26) { + sprintf(file,"/sys/bus/pci/devices/%04u:%02x:%02x.%01x/config", + dev->domain, dev->bus, dev->dev, dev->func); + } else { + if (dev->domain == 0) { + sprintf(file,"/proc/bus/pci/%02x", dev->bus); + if (stat(file, &ignored) < 0) { + sprintf(file, "/proc/bus/pci/0000:%02x/%02x.%1x", + dev->bus, dev->dev, dev->func); + } else { + sprintf(file, "/proc/bus/pci/%02x/%02x.%1x", + dev->bus, dev->dev, dev->func); } - if (write) { - fd = open(file,O_RDWR); - if (fd != -1) is_write = TRUE; - } else switch (is_write) { - case TRUE: - fd = open(file,O_RDWR); - if (fd > -1) - break; - default: - fd = open(file,O_RDONLY); - is_write = FALSE; + } else { + sprintf(file,"/proc/bus/pci/%02x%02x", dev->domain, dev->bus); + if (stat(file, &ignored) < 0) { + sprintf(file, "/proc/bus/pci/%04x:%04x/%02x.%1x", + dev->domain, dev->bus, dev->dev, dev->func); + } else { + sprintf(file, "/proc/bus/pci/%02x%02x/%02x.%1x", + dev->domain, dev->bus, dev->dev, dev->func); } - bail: - ldomain = domain; - lbus = bus; - ldev = dev; - lfunc = func; + } } - return fd; -} - -static CARD32 -linuxPciCfgRead(PCITAG tag, int off) -{ - int fd; - CARD32 val = 0xffffffff; - if (-1 != (fd = linuxPciOpenFile(tag,FALSE))) { - lseek(fd,off,SEEK_SET); - read(fd,&val,4); + if (write) { + fd = open(file,O_RDWR); + if (fd != -1) is_write = TRUE; + } else { + switch (is_write) { + case TRUE: + fd = open(file,O_RDWR); + if (fd > -1) + break; + default: + fd = open(file,O_RDONLY); + is_write = FALSE; + } } - return PCI_CPU(val); -} - -static void -linuxPciCfgWrite(PCITAG tag, int off, CARD32 val) -{ - int fd; - if (-1 != (fd = linuxPciOpenFile(tag,TRUE))) { - lseek(fd,off,SEEK_SET); - val = PCI_CPU(val); - write(fd,&val,4); - } -} + last_dev = dev; + } -static void -linuxPciCfgSetBits(PCITAG tag, int off, CARD32 mask, CARD32 bits) -{ - int fd; - CARD32 val = 0xffffffff; - - if (-1 != (fd = linuxPciOpenFile(tag,TRUE))) { - lseek(fd,off,SEEK_SET); - read(fd,&val,4); - val = PCI_CPU(val); - val = (val & ~mask) | (bits & mask); - val = PCI_CPU(val); - lseek(fd,off,SEEK_SET); - write(fd,&val,4); - } + return fd; } /* @@ -305,77 +237,8 @@ linuxPpcBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr) else return addr; } -static ADDRESS -linuxPpcHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr) -{ - if (type == PCI_MEM) - { - ADDRESS membase = syscall(__NR_pciconfig_iobase, 1, - PCI_BUS_FROM_TAG(tag), PCI_DFN_FROM_TAG(tag)); - return (addr - membase); - } - else if (type == PCI_IO) - { - ADDRESS iobase = syscall(__NR_pciconfig_iobase, 2, - PCI_BUS_FROM_TAG(tag), PCI_DFN_FROM_TAG(tag)); - return (addr - iobase); - } - else return addr; -} - #endif /* __powerpc__ */ -static CARD8 -linuxPciCfgReadByte(PCITAG tag, int off) -{ - int fd; - CARD8 val = 0xff; - - if (-1 != (fd = linuxPciOpenFile(tag,FALSE))) { - lseek(fd,off,SEEK_SET); - read(fd,&val,1); - } - - return val; -} - -static void -linuxPciCfgWriteByte(PCITAG tag, int off, CARD8 val) -{ - int fd; - - if (-1 != (fd = linuxPciOpenFile(tag,TRUE))) { - lseek(fd,off,SEEK_SET); - write(fd, &val, 1); - } -} - -static CARD16 -linuxPciCfgReadWord(PCITAG tag, int off) -{ - int fd; - CARD16 val = 0xff; - - if (-1 != (fd = linuxPciOpenFile(tag,FALSE))) { - lseek(fd, off, SEEK_SET); - read(fd, &val, 2); - } - - return PCI_CPU16(val); -} - -static void -linuxPciCfgWriteWord(PCITAG tag, int off, CARD16 val) -{ - int fd; - - if (-1 != (fd = linuxPciOpenFile(tag,TRUE))) { - lseek(fd, off, SEEK_SET); - val = PCI_CPU16(val); - write(fd, &val, 2); - } -} - #ifndef INCLUDE_XF86_NO_DOMAIN /* @@ -422,19 +285,42 @@ linuxPciCfgWriteWord(PCITAG tag, int off, CARD16 val) #endif /* This probably shouldn't be Linux-specific */ -static pciConfigPtr -xf86GetPciHostConfigFromTag(PCITAG Tag) +static struct pci_device * +get_parent_bridge(struct pci_device *dev) { - int bus = PCI_BUS_FROM_TAG(Tag); - pciBusInfo_t *pBusInfo; + struct pci_id_match bridge_match = { + PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, + (PCI_CLASS_BRIDGE << 16) | (PCI_SUBCLASS_BRIDGE_PCI << 8), + 0 + }; + struct pci_device *bridge; + struct pci_device_iterator *iter; - while ((bus < pciNumBuses) && (pBusInfo = pciBusInfo[bus])) { - if (bus == pBusInfo->primary_bus) - return pBusInfo->bridge; - bus = pBusInfo->primary_bus; + if (dev == NULL) { + return NULL; } - return NULL; /* Bad data */ + iter = pci_id_match_iterator_create(& bridge_match); + if (iter == NULL) { + return NULL; + } + + while ((bridge = pci_device_next(iter)) != NULL) { + if (bridge->domain == dev->domain) { + const struct pci_bridge_info *info = + pci_device_get_bridge_info(bridge); + + if (info != NULL) { + if (info->secondary_bus == dev->bus) { + break; + } + } + } + } + + pci_iterator_destroy(iter); + + return bridge; } /* @@ -470,20 +356,18 @@ static const struct pciSizes { #define NUM_SIZES (sizeof(pciControllerSizes) / sizeof(pciControllerSizes[0])) static const struct pciSizes * -linuxGetSizesStruct(PCITAG Tag) +linuxGetSizesStruct(const struct pci_device *dev) { static const struct pciSizes default_size = { 0, 0, 1U << 16, (unsigned long)(1ULL << 32) }; - pciConfigPtr pPCI; int i; - /* Find host bridge */ - if ((pPCI = xf86GetPciHostConfigFromTag(Tag))) { - /* Look up vendor/device */ + /* Look up vendor/device */ + if (dev != NULL) { for (i = 0; i < NUM_SIZES; i++) { - if ((pPCI->pci_vendor == pciControllerSizes[i].vendor) - && (pPCI->pci_device == pciControllerSizes[i].device)) { + if ((dev->vendor_id == pciControllerSizes[i].vendor) + && (dev->device_id == pciControllerSizes[i].device)) { return & pciControllerSizes[i]; } } @@ -494,84 +378,31 @@ linuxGetSizesStruct(PCITAG Tag) } static __inline__ unsigned long -linuxGetIOSize(PCITAG Tag) +linuxGetIOSize(const struct pci_device *dev) { - const struct pciSizes * const sizes = linuxGetSizesStruct(Tag); + const struct pciSizes * const sizes = linuxGetSizesStruct(dev); return sizes->io_size; } -static __inline__ void -linuxGetSizes(PCITAG Tag, unsigned long *io_size, unsigned long *mem_size) -{ - const struct pciSizes * const sizes = linuxGetSizesStruct(Tag); - - *io_size = sizes->io_size; - *mem_size = sizes->mem_size; -} - -static Bool -linuxDomainSupport(void) -{ - DIR *dir; - struct dirent *dirent; - char *end; - - if (!(dir = opendir("/proc/bus/pci"))) - return FALSE; - while (1) { - if (!(dirent = readdir(dir))) - return FALSE; - strtol(dirent->d_name,&end,16); - /* entry of the form xx or xxxx : x=[0..f] no domain */ - if (*end == '\0') - return FALSE; - else if (*end == ':') { - /* ':' found immediately after: verify for xxxx:xx or xxxx:xxxx */ - strtol(end + 1,&end,16); - if (*end == '\0') - return TRUE; - } - } - return FALSE; -} - -_X_EXPORT int -xf86GetPciDomain(PCITAG Tag) -{ - pciConfigPtr pPCI; - int fd, result; - - pPCI = xf86GetPciHostConfigFromTag(Tag); - - if (pPCI && (result = PCI_DOM_FROM_BUS(pPCI->busnum))) - return result + 1; - - if (!pPCI || pPCI->fakeDevice) - return 1; /* Domain 0 is reserved */ - - if ((fd = linuxPciOpenFile(pPCI ? pPCI->tag : 0,FALSE)) < 0) - return 0; - - if ((result = ioctl(fd, PCIIOC_CONTROLLER, 0)) < 0) - return 0; - - return result + 1; /* Domain 0 is reserved */ -} - static pointer -linuxMapPci(int ScreenNum, int Flags, PCITAG Tag, +linuxMapPci(int ScreenNum, int Flags, struct pci_device *dev, ADDRESS Base, unsigned long Size, int mmap_ioctl) { + /* Align to page boundary */ + const ADDRESS realBase = Base & ~(getpagesize() - 1); + const ADDRESS Offset = Base - realBase; + do { - pciConfigPtr pPCI; unsigned char *result; - ADDRESS realBase, Offset; int fd, mmapflags, prot; xf86InitVidMem(); - prot = ((Flags & VIDMEM_READONLY) == 0); - if (((fd = linuxPciOpenFile(Tag, prot)) < 0) || + /* If dev is NULL, linuxPciOpenFile will return -1, and this routine + * will fail gracefully. + */ + prot = ((Flags & VIDMEM_READONLY) == 0); + if (((fd = linuxPciOpenFile(dev, prot)) < 0) || (ioctl(fd, mmap_ioctl, 0) < 0)) break; @@ -601,9 +432,6 @@ linuxMapPci(int ScreenNum, int Flags, PCITAG Tag, #endif /* ?__ia64__ */ - /* Align to page boundary */ - realBase = Base & ~(getpagesize() - 1); - Offset = Base - realBase; if (Flags & VIDMEM_READONLY) prot = PROT_READ; @@ -626,49 +454,23 @@ linuxMapPci(int ScreenNum, int Flags, PCITAG Tag, return NULL; } -#define MAX_DOMAINS 257 -static pointer DomainMmappedIO[MAX_DOMAINS]; - static int -linuxOpenLegacy(PCITAG Tag, char *name) +linuxOpenLegacy(struct pci_device *dev, char *name) { -#define PREFIX "/sys/class/pci_bus/%04x:%02x/%s" - char *path; - int domain, bus; - pciBusInfo_t *pBusInfo; - pciConfigPtr bridge = NULL; - int fd; - - path = xalloc(strlen(PREFIX) + strlen(name)); - if (!path) - return -1; - - for (;;) { - domain = xf86GetPciDomain(Tag); - bus = PCI_BUS_NO_DOMAIN(PCI_BUS_FROM_TAG(Tag)); - - /* Domain 0 is reserved -- see xf86GetPciDomain() */ - if ((domain <= 0) || (domain >= MAX_DOMAINS)) - FatalError("linuxOpenLegacy(): domain out of range\n"); + static const char PREFIX[] = "/sys/class/pci_bus/%04x:%02x/%s"; + char path[sizeof(PREFIX) + 10]; + int fd = -1; - sprintf(path, PREFIX, domain - 1, bus, name); + while (dev != NULL) { + snprintf(path, sizeof(path) - 1, PREFIX, dev->domain, dev->bus, name); fd = open(path, O_RDWR); if (fd >= 0) { - xfree(path); return fd; } - pBusInfo = pciBusInfo[PCI_BUS_FROM_TAG(Tag)]; - if (!pBusInfo || (bridge == pBusInfo->bridge) || - !(bridge = pBusInfo->bridge)) { - xfree(path); - return -1; - } - - Tag = bridge->tag; + dev = get_parent_bridge(dev); } - xfree(path); return fd; } @@ -680,10 +482,9 @@ linuxOpenLegacy(PCITAG Tag, char *name) * the legacy ISA memory space (memory in a domain between 0 and 1MB). */ _X_EXPORT pointer -xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag, +xf86MapDomainMemory(int ScreenNum, int Flags, struct pci_device *dev, ADDRESS Base, unsigned long Size) { - int domain = xf86GetPciDomain(Tag); int fd = -1; pointer addr; @@ -691,11 +492,8 @@ xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag, * We use /proc/bus/pci on non-legacy addresses or if the Linux sysfs * legacy_mem interface is unavailable. */ - if (Base >= 1024*1024) - addr = linuxMapPci(ScreenNum, Flags, Tag, Base, Size, - PCIIOC_MMAP_IS_MEM); - else if ((fd = linuxOpenLegacy(Tag, "legacy_mem")) < 0) - addr = linuxMapPci(ScreenNum, Flags, Tag, Base, Size, + if ((Base > 1024*1024) || ((fd = linuxOpenLegacy(dev, "legacy_mem")) < 0)) + return linuxMapPci(ScreenNum, Flags, dev, Base, Size, PCIIOC_MMAP_IS_MEM); else addr = mmap(NULL, Size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, Base); @@ -709,434 +507,143 @@ xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag, return addr; } -/* - * xf86MapDomainIO - map I/O space in this domain +/** + * Map I/O space in this domain * * Each domain has a legacy ISA I/O space. This routine will try to * map it using the Linux sysfs legacy_io interface. If that fails, * it'll fall back to using /proc/bus/pci. * - * If the legacy_io interface *does* exist, the file descriptor (fd below) - * will be saved in the DomainMmappedIO array in the upper bits of the + * If the legacy_io interface \b does exist, the file descriptor (\c fd below) + * will be saved in the \c DomainMmappedIO array in the upper bits of the * pointer. Callers will do I/O with small port numbers (<64k values), so - * the platform I/O code can extract the port number and the fd, lseek to - * the port number in the legacy_io file, and issue the read or write. + * the platform I/O code can extract the port number and the \c fd, \c lseek + * to the port number in the legacy_io file, and issue the read or write. * * This has no means of returning failure, so all errors are fatal */ -_X_EXPORT IOADDRESS -xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, - IOADDRESS Base, unsigned long Size) +IOADDRESS +xf86MapLegacyIO(struct pci_device *dev) { - int domain = xf86GetPciDomain(Tag); + const int domain = dev->domain; + struct pci_device *bridge = get_parent_bridge(dev); int fd; - if ((domain <= 0) || (domain >= MAX_DOMAINS)) - FatalError("xf86MapDomainIO(): domain out of range\n"); + if (domain >= MAX_DOMAINS) + FatalError("xf86MapLegacyIO(): domain out of range\n"); - if (DomainMmappedIO[domain]) - return (IOADDRESS)DomainMmappedIO[domain] + Base; - - /* Permanently map all of I/O space */ - if ((fd = linuxOpenLegacy(Tag, "legacy_io")) < 0) { - DomainMmappedIO[domain] = linuxMapPci(ScreenNum, Flags, Tag, - 0, linuxGetIOSize(Tag), + if (DomainMmappedIO[domain] == NULL) { + /* Permanently map all of I/O space */ + fd = linuxOpenLegacy(bridge, "legacy_io"); + if (fd < 0) { + DomainMmappedIO[domain] = linuxMapPci(-1, VIDMEM_MMIO, bridge, + 0, linuxGetIOSize(bridge), PCIIOC_MMAP_IS_IO); - /* ia64 can't mmap legacy IO port space */ - if (!DomainMmappedIO[domain]) - return Base; - } - else { /* legacy_io file exists, encode fd */ - DomainMmappedIO[domain] = (pointer)(fd << 24); - } - - return (IOADDRESS)DomainMmappedIO[domain] + Base; -} - -/* - * xf86ReadDomainMemory - copy from domain memory into a caller supplied buffer - */ -_X_EXPORT int -xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len, unsigned char *Buf) -{ - unsigned char *ptr, *src; - ADDRESS offset; - unsigned long size; - int len, pagemask = getpagesize() - 1; - - unsigned int i, dom, bus, dev, func; - unsigned int fd; - char file[256]; - struct stat st; - - dom = PCI_DOM_FROM_TAG(Tag); - bus = PCI_BUS_NO_DOMAIN(PCI_BUS_FROM_TAG(Tag)); - dev = PCI_DEV_FROM_TAG(Tag); - func = PCI_FUNC_FROM_TAG(Tag); - sprintf(file, "/sys/bus/pci/devices/%04x:%02x:%02x.%1x/rom", - dom, bus, dev, func); - - /* - * If the caller wants the ROM and the sysfs rom interface exists, - * try to use it instead of reading it from /proc/bus/pci. - */ - if (((Base & 0xfffff) == 0xC0000) && (stat(file, &st) == 0)) { - if ((fd = open(file, O_RDWR))) - Base = 0x0; - - /* enable the ROM first */ - write(fd, "1", 2); - lseek(fd, 0, SEEK_SET); - - len = min(Len, st.st_size); - - /* copy the ROM until we hit Len, EOF or read error */ - for (; len && (size = read(fd, Buf, len)) > 0 ; Buf+=size, len-=size) - ; - - write(fd, "0", 2); - close(fd); - - return Len; + } + else { /* legacy_io file exists, encode fd */ + DomainMmappedIO[domain] = (pointer)(fd << 24); + } } - /* Ensure page boundaries */ - offset = Base & ~pagemask; - size = ((Base + Len + pagemask) & ~pagemask) - offset; - - ptr = xf86MapDomainMemory(-1, VIDMEM_READONLY, Tag, offset, size); - - if (!ptr) - return -1; - - /* Using memcpy() here can hang the system */ - src = ptr + (Base - offset); - for (len = Len; len-- > 0;) - *Buf++ = *src++; - - xf86UnMapVidMem(-1, ptr, size); - - return Len; + return (IOADDRESS)DomainMmappedIO[domain]; } resPtr xf86BusAccWindowsFromOS(void) { - pciConfigPtr *ppPCI, pPCI; + struct pci_device *dev; + struct pci_device_iterator *iter; resPtr pRes = NULL; resRange range; - unsigned long io_size, mem_size; - int domain; - - if ((ppPCI = xf86scanpci(0))) { - for (; (pPCI = *ppPCI); ppPCI++) { - if ((pPCI->pci_base_class != PCI_CLASS_BRIDGE) || - (pPCI->pci_sub_class != PCI_SUBCLASS_BRIDGE_HOST)) - continue; - - domain = xf86GetPciDomain(pPCI->tag); - linuxGetSizes(pPCI->tag, &io_size, &mem_size); - - RANGE(range, 0, (ADDRESS)(mem_size - 1), - RANGE_TYPE(ResExcMemBlock, domain)); - pRes = xf86AddResToList(pRes, &range, -1); - RANGE(range, 0, (IOADDRESS)(io_size - 1), - RANGE_TYPE(ResExcIoBlock, domain)); - pRes = xf86AddResToList(pRes, &range, -1); - - if (domain <= 0) - break; - } + iter = pci_id_match_iterator_create(& match_host_bridge); + while ((dev = pci_device_next(iter)) != NULL) { + const int domain = dev->domain; + const struct pciSizes * const sizes = linuxGetSizesStruct(dev); + + RANGE(range, 0, (ADDRESS)(sizes->mem_size - 1), + RANGE_TYPE(ResExcMemBlock, domain)); + pRes = xf86AddResToList(pRes, &range, -1); + + RANGE(range, 0, (IOADDRESS)(sizes->io_size - 1), + RANGE_TYPE(ResExcIoBlock, domain)); + pRes = xf86AddResToList(pRes, &range, -1); + + /* FIXME: The old code reserved domain 0 for a special purpose. The + * FIXME: new code just uses whatever domains the kernel tells it, + * FIXME: but there is no way to get a domain < 0. What should + * FIXME: happen here? + * + if (domain <= 0) + break; + */ } + pci_iterator_destroy(iter); + return pRes; } resPtr xf86PciBusAccWindowsFromOS(void) { - pciConfigPtr *ppPCI, pPCI; - resPtr pRes = NULL; - resRange range; - unsigned long io_size, mem_size; - int domain; - - if ((ppPCI = xf86scanpci(0))) { - for (; (pPCI = *ppPCI); ppPCI++) { - if ((pPCI->pci_base_class != PCI_CLASS_BRIDGE) || - (pPCI->pci_sub_class != PCI_SUBCLASS_BRIDGE_HOST)) - continue; - - domain = xf86GetPciDomain(pPCI->tag); - linuxGetSizes(pPCI->tag, &io_size, &mem_size); - - RANGE(range, 0, (ADDRESS)(mem_size - 1), - RANGE_TYPE(ResExcMemBlock, domain)); - pRes = xf86AddResToList(pRes, &range, -1); - - RANGE(range, 0, (IOADDRESS)(io_size - 1), - RANGE_TYPE(ResExcIoBlock, domain)); - pRes = xf86AddResToList(pRes, &range, -1); - - if (domain <= 0) - break; - } - } - - return pRes; + return xf86BusAccWindowsFromOS(); } resPtr xf86AccResFromOS(resPtr pRes) { - pciConfigPtr *ppPCI, pPCI; + struct pci_device *dev; + struct pci_device_iterator *iter; resRange range; - unsigned long io_size, mem_size; - int domain; - - if ((ppPCI = xf86scanpci(0))) { - for (; (pPCI = *ppPCI); ppPCI++) { - if ((pPCI->pci_base_class != PCI_CLASS_BRIDGE) || - (pPCI->pci_sub_class != PCI_SUBCLASS_BRIDGE_HOST)) - continue; - - domain = xf86GetPciDomain(pPCI->tag); - linuxGetSizes(pPCI->tag, &io_size, &mem_size); - - /* - * At minimum, the top and bottom resources must be claimed, so - * that resources that are (or appear to be) unallocated can be - * relocated. - */ - RANGE(range, 0x00000000u, 0x0009ffffu, - RANGE_TYPE(ResExcMemBlock, domain)); - pRes = xf86AddResToList(pRes, &range, -1); - RANGE(range, 0x000c0000u, 0x000effffu, - RANGE_TYPE(ResExcMemBlock, domain)); - pRes = xf86AddResToList(pRes, &range, -1); - RANGE(range, 0x000f0000u, 0x000fffffu, - RANGE_TYPE(ResExcMemBlock, domain)); - pRes = xf86AddResToList(pRes, &range, -1); - - RANGE(range, (ADDRESS)(mem_size - 1), (ADDRESS)(mem_size - 1), - RANGE_TYPE(ResExcMemBlock, domain)); - pRes = xf86AddResToList(pRes, &range, -1); - - RANGE(range, 0x00000000u, 0x00000000u, - RANGE_TYPE(ResExcIoBlock, domain)); - pRes = xf86AddResToList(pRes, &range, -1); - RANGE(range, (IOADDRESS)(io_size - 1), (IOADDRESS)(io_size - 1), - RANGE_TYPE(ResExcIoBlock, domain)); - pRes = xf86AddResToList(pRes, &range, -1); - - if (domain <= 0) - break; - } - } - - return pRes; -} - -#endif /* !INCLUDE_XF86_NO_DOMAIN */ - -int linuxPciHandleBIOS(PCITAG Tag, int basereg, unsigned char *buf, int len) -{ - unsigned int dom, bus, dev, func; - unsigned int fd; - char file[256]; - struct stat st; - int ret; - int sofar = 0; - - dom = PCI_DOM_FROM_TAG(Tag); - bus = PCI_BUS_NO_DOMAIN(PCI_BUS_FROM_TAG(Tag)); - dev = PCI_DEV_FROM_TAG(Tag); - func = PCI_FUNC_FROM_TAG(Tag); - sprintf(file, "/sys/bus/pci/devices/%04x:%02x:%02x.%1x/rom", - dom, bus, dev, func); - - if (stat(file, &st) == 0) - { - if ((fd = open(file, O_RDWR))) - basereg = 0x0; - - /* enable the ROM first */ - write(fd, "1", 2); - lseek(fd, 0, SEEK_SET); - do { - /* copy the ROM until we hit Len, EOF or read error */ - ret = read(fd, buf+sofar, len-sofar); - if (ret <= 0) - break; - sofar += ret; - } while (sofar < len); - - write(fd, "0", 2); - close(fd); - if (sofar < len) - xf86MsgVerb(X_INFO, 3, "Attempted to read BIOS %dKB from %s: got %dKB\n", len/1024, file, sofar/1024); - return sofar; - } - return 0; -} - -#ifdef __ia64__ -static PCITAG ia64linuxPciFindFirst(void); -static PCITAG ia64linuxPciFindNext(void); - -void -ia64linuxPciInit() -{ - struct stat st; - - linuxPciInit(); - - if (!stat("/proc/sgi_sn/licenseID", &st) && pciNumBuses) { - /* Be a little paranoid here and only use this code for Altix systems. - * It is generic, so it should work on any system, but depends on - * /proc/bus/pci entries for each domain/bus combination. Altix is - * guaranteed a recent enough kernel to have them. - */ - pciFindFirstFP = ia64linuxPciFindFirst; - pciFindNextFP = ia64linuxPciFindNext; - } -} - -static DIR *busdomdir; -static DIR *devdir; - -static PCITAG -ia64linuxPciFindFirst(void) -{ - busdomdir = opendir("/proc/bus/pci"); - devdir = NULL; - - return ia64linuxPciFindNext(); -} -static struct dirent *getnextbus(int *domain, int *bus) -{ - struct dirent *entry; - int dombus; - - for (;;) { - entry = readdir(busdomdir); - if (entry == NULL) { - *domain = 0; - *bus = 0; - closedir(busdomdir); - return NULL; - } - if (sscanf(entry->d_name, "%04x:%02x", domain, bus) != 2) - continue; - dombus = PCI_MAKE_BUS(*domain, *bus); - - if (pciNumBuses <= dombus) - pciNumBuses = dombus + 1; - if (!pciBusInfo[dombus]) { - pciBusInfo[dombus] = xnfalloc(sizeof(pciBusInfo_t)); - *pciBusInfo[dombus] = *pciBusInfo[0]; - } - - return entry; + iter = pci_id_match_iterator_create(& match_host_bridge); + while ((dev = pci_device_next(iter)) != NULL) { + const int domain = dev->domain; + const struct pciSizes * const sizes = linuxGetSizesStruct(dev); + + /* + * At minimum, the top and bottom resources must be claimed, so + * that resources that are (or appear to be) unallocated can be + * relocated. + */ + RANGE(range, 0x00000000u, 0x0009ffffu, + RANGE_TYPE(ResExcMemBlock, domain)); + pRes = xf86AddResToList(pRes, &range, -1); + RANGE(range, 0x000c0000u, 0x000effffu, + RANGE_TYPE(ResExcMemBlock, domain)); + pRes = xf86AddResToList(pRes, &range, -1); + RANGE(range, 0x000f0000u, 0x000fffffu, + RANGE_TYPE(ResExcMemBlock, domain)); + pRes = xf86AddResToList(pRes, &range, -1); + + RANGE(range, (ADDRESS)(sizes->mem_size - 1), + (ADDRESS)(sizes->mem_size - 1), + RANGE_TYPE(ResExcMemBlock, domain)); + pRes = xf86AddResToList(pRes, &range, -1); + + RANGE(range, 0x00000000u, 0x00000000u, + RANGE_TYPE(ResExcIoBlock, domain)); + pRes = xf86AddResToList(pRes, &range, -1); + RANGE(range, (IOADDRESS)(sizes->io_size - 1), + (IOADDRESS)(sizes->io_size - 1), + RANGE_TYPE(ResExcIoBlock, domain)); + pRes = xf86AddResToList(pRes, &range, -1); + + /* FIXME: The old code reserved domain 0 for a special purpose. The + * FIXME: new code just uses whatever domains the kernel tells it, + * FIXME: but there is no way to get a domain < 0. What should + * FIXME: happen here? + * + if (domain <= 0) + break; + */ } -} -static PCITAG -ia64linuxPciFindNext(void) -{ - struct dirent *entry; - char file[40]; - static int bus, dev, func, domain; - PCITAG pciDeviceTag; - CARD32 devid; - - for (;;) { - if (devdir == NULL) { - entry = getnextbus(&domain, &bus); - if (!entry) - return PCI_NOT_FOUND; - snprintf(file, 40, "/proc/bus/pci/%s", entry->d_name); - devdir = opendir(file); - if (!devdir) - return PCI_NOT_FOUND; - - } + pci_iterator_destroy(iter); - entry = readdir(devdir); - - if (entry == NULL) { - closedir(devdir); - devdir = NULL; - continue; - } - - if (sscanf(entry->d_name, "%02x . %01x", &dev, &func) == 2) { - CARD32 tmp; - int sec_bus, pri_bus; - unsigned char base_class, sub_class; - - int pciBusNum = PCI_MAKE_BUS(domain, bus); - pciDeviceTag = PCI_MAKE_TAG(pciBusNum, dev, func); - - /* - * Before checking for a specific devid, look for enabled - * PCI to PCI bridge devices. If one is found, create and - * initialize a bus info record (if one does not already exist). - */ - tmp = pciReadLong(pciDeviceTag, PCI_CLASS_REG); - base_class = PCI_CLASS_EXTRACT(tmp); - sub_class = PCI_SUBCLASS_EXTRACT(tmp); - if ((base_class == PCI_CLASS_BRIDGE) && - ((sub_class == PCI_SUBCLASS_BRIDGE_PCI) || - (sub_class == PCI_SUBCLASS_BRIDGE_CARDBUS))) { - tmp = pciReadLong(pciDeviceTag, PCI_PCI_BRIDGE_BUS_REG); - sec_bus = PCI_SECONDARY_BUS_EXTRACT(tmp, pciDeviceTag); - pri_bus = PCI_PRIMARY_BUS_EXTRACT(tmp, pciDeviceTag); -#ifdef DEBUGPCI - ErrorF("ia64linuxPciFindNext: pri_bus %d sec_bus %d\n", - pri_bus, sec_bus); -#endif - if (pciBusNum != pri_bus) { - /* Some bridges do not implement the primary bus register */ - if ((PCI_BUS_NO_DOMAIN(pri_bus) != 0) || - (sub_class != PCI_SUBCLASS_BRIDGE_CARDBUS)) - xf86Msg(X_WARNING, - "ia64linuxPciFindNext: primary bus mismatch on PCI" - " bridge 0x%08lx (0x%02x, 0x%02x)\n", - pciDeviceTag, pciBusNum, pri_bus); - pri_bus = pciBusNum; - } - if ((pri_bus < sec_bus) && (sec_bus < pciMaxBusNum) && - pciBusInfo[pri_bus]) { - /* - * Found a secondary PCI bus - */ - if (!pciBusInfo[sec_bus]) { - pciBusInfo[sec_bus] = xnfalloc(sizeof(pciBusInfo_t)); - - /* Copy parents settings... */ - *pciBusInfo[sec_bus] = *pciBusInfo[pri_bus]; - } - - /* ...but not everything same as parent */ - pciBusInfo[sec_bus]->primary_bus = pri_bus; - pciBusInfo[sec_bus]->secondary = TRUE; - pciBusInfo[sec_bus]->numDevices = 32; - - if (pciNumBuses <= sec_bus) - pciNumBuses = sec_bus + 1; - } - } - - devid = pciReadLong(pciDeviceTag, PCI_ID_REG); - if ((devid & pciDevidMask) == pciDevid) - /* Yes - Return it. Otherwise, next device */ - return pciDeviceTag; - } - } + return pRes; } -#endif +#endif /* !INCLUDE_XF86_NO_DOMAIN */ diff --git a/hw/xfree86/os-support/bus/netbsdPci.c b/hw/xfree86/os-support/bus/netbsdPci.c index ee52c89cc..760302752 100644 --- a/hw/xfree86/os-support/bus/netbsdPci.c +++ b/hw/xfree86/os-support/bus/netbsdPci.c @@ -79,8 +79,6 @@ netbsdPciInit() pciNumBuses = 1; pciBusInfo[0] = &netbsdPci0; - pciFindFirstFP = pciGenFindFirst; - pciFindNextFP = pciGenFindNext; /* use businfo to get the number of devs */ if (ioctl(devpci, PCI_IOC_BUSINFO, &pci_businfo) != 0) FatalError("netbsdPciInit: not a PCI bus device"); diff --git a/hw/xfree86/os-support/bus/sparcPci.c b/hw/xfree86/os-support/bus/sparcPci.c index 5dd6b9369..82b1d89b9 100644 --- a/hw/xfree86/os-support/bus/sparcPci.c +++ b/hw/xfree86/os-support/bus/sparcPci.c @@ -622,7 +622,7 @@ xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag, } _X_EXPORT IOADDRESS -xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, +xf86MapLegacyIO(int ScreenNum, int Flags, PCITAG Tag, IOADDRESS Base, unsigned long Size) { sparcDomainPtr pDomain; @@ -632,7 +632,7 @@ xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, !(pDomain = xf86DomainInfo[domain]) || (((unsigned long long)Base + (unsigned long long)Size) > pDomain->io_size)) - FatalError("xf86MapDomainIO() called with invalid parameters.\n"); + FatalError("xf86MapLegacyIO() called with invalid parameters.\n"); /* Permanently map all of I/O space */ if (!pDomain->io) { @@ -648,30 +648,6 @@ xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, return (IOADDRESS)pDomain->io + Base; } -_X_EXPORT int -xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len, unsigned char *Buf) -{ - unsigned char *ptr, *src; - ADDRESS offset; - unsigned long size; - int len; - - /* Ensure page boundaries */ - offset = Base & ~pagemask; - size = ((Base + Len + pagemask) & ~pagemask) - offset; - - ptr = xf86MapDomainMemory(-1, VIDMEM_READONLY, Tag, offset, size); - - /* Using memcpy() here hangs the system */ - src = ptr + (Base - offset); - for (len = Len; len-- > 0;) - *Buf++ = *src++; - - xf86UnMapVidMem(-1, ptr, size); - - return Len; -} - resPtr xf86BusAccWindowsFromOS(void) { diff --git a/hw/xfree86/os-support/bus/xf86Pci.h b/hw/xfree86/os-support/bus/xf86Pci.h index c444a0cd1..2b8a4f76b 100644 --- a/hw/xfree86/os-support/bus/xf86Pci.h +++ b/hw/xfree86/os-support/bus/xf86Pci.h @@ -106,8 +106,7 @@ #include <X11/Xarch.h> #include <X11/Xfuncproto.h> #include "misc.h" - -#define PCI_NOT_FOUND 0xFFFFFFFFU +#include <pciaccess.h> /* * PCI cfg space definitions (e.g. stuff right out of the PCI spec) @@ -172,19 +171,6 @@ #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 -/* 0x01 mass storage subclasses */ -#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 -#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 -#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 -#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 -#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 - -/* 0x02 network subclasses */ -#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00 -#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01 -#define PCI_SUBCLASS_NETWORK_FDDI 0x02 -#define PCI_SUBCLASS_NETWORK_MISC 0x80 - /* 0x03 display subclasses */ #define PCI_SUBCLASS_DISPLAY_VGA 0x00 #define PCI_SUBCLASS_DISPLAY_XGA 0x01 @@ -195,11 +181,6 @@ #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 -/* 0x05 memory subclasses */ -#define PCI_SUBCLASS_MEMORY_RAM 0x00 -#define PCI_SUBCLASS_MEMORY_FLASH 0x01 -#define PCI_SUBCLASS_MEMORY_MISC 0x80 - /* 0x06 bridge subclasses */ #define PCI_SUBCLASS_BRIDGE_HOST 0x00 #define PCI_SUBCLASS_BRIDGE_ISA 0x01 @@ -213,33 +194,6 @@ #define PCI_SUBCLASS_BRIDGE_MISC 0x80 #define PCI_IF_BRIDGE_PCI_SUBTRACTIVE 0x01 -/* 0x07 communications controller subclasses */ -#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 -#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 -#define PCI_SUBCLASS_COMMUNICATIONS_MULTISERIAL 0x02 -#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 -#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 - -/* 0x08 generic system peripherals subclasses */ -#define PCI_SUBCLASS_SYSPERIPH_PIC 0x00 -#define PCI_SUBCLASS_SYSPERIPH_DMA 0x01 -#define PCI_SUBCLASS_SYSPERIPH_TIMER 0x02 -#define PCI_SUBCLASS_SYSPERIPH_RTC 0x03 -#define PCI_SUBCLASS_SYSPERIPH_HOTPCI 0x04 -#define PCI_SUBCLASS_SYSPERIPH_MISC 0x80 - -/* 0x09 input device subclasses */ -#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00 -#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01 -#define PCI_SUBCLASS_INPUT_MOUSE 0x02 -#define PCI_SUBCLASS_INPUT_SCANNER 0x03 -#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04 -#define PCI_SUBCLASS_INPUT_MISC 0x80 - -/* 0x0a docking station subclasses */ -#define PCI_SUBCLASS_DOCKING_GENERIC 0x00 -#define PCI_SUBCLASS_DOCKING_MISC 0x80 - /* 0x0b processor subclasses */ #define PCI_SUBCLASS_PROCESSOR_386 0x00 #define PCI_SUBCLASS_PROCESSOR_486 0x01 @@ -249,101 +203,6 @@ #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40 -/* 0x0c serial bus controller subclasses */ -#define PCI_SUBCLASS_SERIAL_FIREWIRE 0x00 -#define PCI_SUBCLASS_SERIAL_ACCESS 0x01 -#define PCI_SUBCLASS_SERIAL_SSA 0x02 -#define PCI_SUBCLASS_SERIAL_USB 0x03 -#define PCI_SUBCLASS_SERIAL_FIBRECHANNEL 0x04 -#define PCI_SUBCLASS_SERIAL_SMBUS 0x05 - -/* 0x0d wireless controller subclasses */ -#define PCI_SUBCLASS_WIRELESS_IRDA 0x00 -#define PCI_SUBCLASS_WIRELESS_CONSUMER_IR 0x01 -#define PCI_SUBCLASS_WIRELESS_RF 0x02 -#define PCI_SUBCLASS_WIRELESS_MISC 0x80 - -/* 0x0e intelligent I/O controller subclasses */ -#define PCI_SUBCLASS_I2O_I2O 0x00 - -/* 0x0f satellite communications controller subclasses */ -#define PCI_SUBCLASS_SATELLITE_TV 0x01 -#define PCI_SUBCLASS_SATELLITE_AUDIO 0x02 -#define PCI_SUBCLASS_SATELLITE_VOICE 0x03 -#define PCI_SUBCLASS_SATELLITE_DATA 0x04 - -/* 0x10 encryption/decryption controller subclasses */ -#define PCI_SUBCLASS_CRYPT_NET_COMPUTING 0x00 -#define PCI_SUBCLASS_CRYPT_ENTERTAINMENT 0x10 -#define PCI_SUBCLASS_CRYPT_MISC 0x80 - -/* 0x11 data acquisition and signal processing controller subclasses */ -#define PCI_SUBCLASS_DATAACQ_DPIO 0x00 -#define PCI_SUBCLASS_DATAACQ_MISC 0x80 - - -/* Header */ -#define PCI_HEADER_MISC 0x0c -#define PCI_HEADER_MULTIFUNCTION 0x00800000 - -/* Interrupt configration register */ -#define PCI_INTERRUPT_REG 0x3c -#define PCI_INTERRUPT_PIN_MASK 0x0000ff00 -#define PCI_INTERRUPT_PIN_EXTRACT(x) \ - ((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff) -#define PCI_INTERRUPT_PIN_NONE 0x00 -#define PCI_INTERRUPT_PIN_A 0x01 -#define PCI_INTERRUPT_PIN_B 0x02 -#define PCI_INTERRUPT_PIN_C 0x03 -#define PCI_INTERRUPT_PIN_D 0x04 - -#define PCI_INTERRUPT_LINE_MASK 0x000000ff -#define PCI_INTERRUPT_LINE_EXTRACT(x) \ - ((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff) -#define PCI_INTERRUPT_LINE_INSERT(x,v) \ - (((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0)) - -/* Base registers */ -#define PCI_MAP_REG_START 0x10 -#define PCI_MAP_REG_END 0x28 -#define PCI_MAP_ROM_REG 0x30 - -#define PCI_MAP_MEMORY 0x00000000 -#define PCI_MAP_IO 0x00000001 - -#define PCI_MAP_MEMORY_TYPE 0x00000007 -#define PCI_MAP_IO_TYPE 0x00000003 - -#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 -#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 -#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 -#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 -#define PCI_MAP_MEMORY_CACHABLE 0x00000008 -#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e -#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 - -#define PCI_MAP_IO_ATTR_MASK 0x00000003 - -#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) -#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) - -#define PCI_MAP_IS64BITMEM(b) \ - (((b) & PCI_MAP_MEMORY_TYPE) == PCI_MAP_MEMORY_TYPE_64BIT) - -#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) -#define PCIGETMEMORY64HIGH(b) (*((CARD32*)&(b) + 1)) -#define PCIGETMEMORY64(b) \ - (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) - -#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc - -#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) - -#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 -#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 - -#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) - /* PCI-PCI bridge mapping registers */ #define PCI_PCI_BRIDGE_BUS_REG 0x18 #define PCI_SUBORDINATE_BUS_MASK 0x00ff0000 @@ -354,12 +213,6 @@ #define PCI_PCI_BRIDGE_MEM_REG 0x20 #define PCI_PCI_BRIDGE_PMEM_REG 0x24 -#define PCI_PPB_IOBASE_EXTRACT(x) (((x) << 8) & 0xFF00) -#define PCI_PPB_IOLIMIT_EXTRACT(x) (((x) << 0) & 0xFF00) - -#define PCI_PPB_MEMBASE_EXTRACT(x) (((x) << 16) & 0xFFFF0000) -#define PCI_PPB_MEMLIMIT_EXTRACT(x) (((x) << 0) & 0xFFFF0000) - #define PCI_PCI_BRIDGE_CONTROL_REG 0x3E #define PCI_PCI_BRIDGE_PARITY_EN 0x01 #define PCI_PCI_BRIDGE_SERR_EN 0x02 @@ -368,31 +221,6 @@ #define PCI_PCI_BRIDGE_MASTER_ABORT_EN 0x20 #define PCI_PCI_BRIDGE_SECONDARY_RESET 0x40 #define PCI_PCI_BRIDGE_FAST_B2B_EN 0x80 -/* header type 2 extensions */ -#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ -#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ -#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 -#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 -#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 - -#define PCI_CB_SEC_STATUS_REG 0x16 /* Secondary status */ -#define PCI_CB_PRIMARY_BUS_REG 0x18 /* PCI bus number */ -#define PCI_CB_CARD_BUS_REG 0x19 /* CardBus bus number */ -#define PCI_CB_SUBORDINATE_BUS_REG 0x1a /* Subordinate bus number */ -#define PCI_CB_LATENCY_TIMER_REG 0x1b /* CardBus latency timer */ -#define PCI_CB_MEM_BASE_0_REG 0x1c -#define PCI_CB_MEM_LIMIT_0_REG 0x20 -#define PCI_CB_MEM_BASE_1_REG 0x24 -#define PCI_CB_MEM_LIMIT_1_REG 0x28 -#define PCI_CB_IO_BASE_0_REG 0x2c -#define PCI_CB_IO_LIMIT_0_REG 0x30 -#define PCI_CB_IO_BASE_1_REG 0x34 -#define PCI_CB_IO_LIMIT_1_REG 0x38 -#define PCI_CB_BRIDGE_CONTROL_REG 0x3E - -#define PCI_CB_IO_RANGE_MASK ~0x03 -#define PCI_CB_IOBASE(x) (x & PCI_CB_IO_RANGE_MASK) -#define PCI_CB_IOLIMIT(x) ((x & PCI_CB_IO_RANGE_MASK) + 3) /* Subsystem identification register */ #define PCI_SUBSYSTEM_ID_REG 0x2c @@ -410,258 +238,6 @@ typedef unsigned long ADDRESS; /* Memory/PCI address */ typedef unsigned long IOADDRESS; /* Must be large enough for a pointer */ typedef unsigned long PCITAG; -/* - * PCI configuration space - */ -typedef struct pci_cfg_regs { - /* start of official PCI config space header */ - union { /* Offset 0x0 - 0x3 */ - CARD32 device_vendor; - struct { -#if X_BYTE_ORDER == X_BIG_ENDIAN - CARD16 device; - CARD16 vendor; -#else - CARD16 vendor; - CARD16 device; -#endif - } dv; - } dv_id; - - union { /* Offset 0x4 - 0x8 */ - CARD32 status_command; - struct { -#if X_BYTE_ORDER == X_BIG_ENDIAN - CARD16 status; - CARD16 command; -#else - CARD16 command; - CARD16 status; -#endif - } sc; - } stat_cmd; - - union { /* Offset 0x8 - 0xb */ - CARD32 class_revision; - struct { -#if X_BYTE_ORDER == X_BIG_ENDIAN - CARD8 base_class; - CARD8 sub_class; - CARD8 prog_if; - CARD8 rev_id; -#else - CARD8 rev_id; - CARD8 prog_if; - CARD8 sub_class; - CARD8 base_class; -#endif - } cr; - } class_rev; - - union { /* Offset 0xc - 0xf */ - CARD32 bist_header_latency_cache; - struct { -#if X_BYTE_ORDER == X_BIG_ENDIAN - CARD8 bist; - CARD8 header_type; - CARD8 latency_timer; - CARD8 cache_line_size; -#else - CARD8 cache_line_size; - CARD8 latency_timer; - CARD8 header_type; - CARD8 bist; -#endif - } bhlc; - } bhlc; - union { /* Offset 0x10 - 0x3b */ - struct { /* header type 2 */ - CARD32 cg_rsrvd1; /* 0x10 */ -#if X_BYTE_ORDER == X_BIG_ENDIAN - CARD16 secondary_status; /* 0x16 */ - CARD16 cg_rsrvd2; /* 0x14 */ - - union { - CARD32 cg_bus_reg; - struct { - CARD8 latency_timer; /* 0x1b */ - CARD8 subordinate_bus_number; /* 0x1a */ - CARD8 cardbus_bus_number; /* 0x19 */ - CARD8 primary_bus_number; /* 0x18 */ - } cgbr; - } cgbr; -#else - CARD16 cg_rsrvd2; /* 0x14 */ - CARD16 secondary_status; /* 0x16 */ - - union { - CARD32 cg_bus_reg; - struct { - CARD8 primary_bus_number; /* 0x18 */ - CARD8 cardbus_bus_number; /* 0x19 */ - CARD8 subordinate_bus_number; /* 0x1a */ - CARD8 latency_timer; /* 0x1b */ - } cgbr; - } cgbr; -#endif - CARD32 mem_base0; /* 0x1c */ - CARD32 mem_limit0; /* 0x20 */ - CARD32 mem_base1; /* 0x24 */ - CARD32 mem_limit1; /* 0x28 */ - CARD32 io_base0; /* 0x2c */ - CARD32 io_limit0; /* 0x30 */ - CARD32 io_base1; /* 0x34 */ - CARD32 io_limit1; /* 0x38 */ - } cg; - struct { - union { /* Offset 0x10 - 0x27 */ - struct { /* header type 0 */ - CARD32 dv_base0; - CARD32 dv_base1; - CARD32 dv_base2; - CARD32 dv_base3; - CARD32 dv_base4; - CARD32 dv_base5; - } dv; - struct { /* header type 1 */ - CARD32 bg_rsrvd[2]; -#if X_BYTE_ORDER == X_BIG_ENDIAN - union { - CARD32 pp_bus_reg; - struct { - CARD8 secondary_latency_timer; - CARD8 subordinate_bus_number; - CARD8 secondary_bus_number; - CARD8 primary_bus_number; - } ppbr; - } ppbr; - - CARD16 secondary_status; - CARD8 io_limit; - CARD8 io_base; - - CARD16 mem_limit; - CARD16 mem_base; - - CARD16 prefetch_mem_limit; - CARD16 prefetch_mem_base; -#else - union { - CARD32 pp_bus_reg; - struct { - CARD8 primary_bus_number; - CARD8 secondary_bus_number; - CARD8 subordinate_bus_number; - CARD8 secondary_latency_timer; - } ppbr; - } ppbr; - - CARD8 io_base; - CARD8 io_limit; - CARD16 secondary_status; - - CARD16 mem_base; - CARD16 mem_limit; - - CARD16 prefetch_mem_base; - CARD16 prefetch_mem_limit; -#endif - } bg; - } bc; - union { /* Offset 0x28 - 0x2b */ - CARD32 rsvd1; - CARD32 pftch_umem_base; - CARD32 cardbus_cis_ptr; - } um_c_cis; - union { /* Offset 0x2c - 0x2f */ - CARD32 subsys_card_vendor; - CARD32 pftch_umem_limit; - CARD32 rsvd2; - struct { -#if X_BYTE_ORDER == X_BIG_ENDIAN - CARD16 subsys_card; - CARD16 subsys_vendor; -#else - CARD16 subsys_vendor; - CARD16 subsys_card; -#endif - } ssys; - } um_ssys_id; - union { /* Offset 0x30 - 0x33 */ - CARD32 baserom; - struct { -#if X_BYTE_ORDER == X_BIG_ENDIAN - CARD16 io_ulimit; - CARD16 io_ubase; -#else - CARD16 io_ubase; - CARD16 io_ulimit; -#endif - } b_u_io; - } uio_rom; - struct { - CARD32 rsvd3; /* Offset 0x34 - 0x37 */ - CARD32 rsvd4; /* Offset 0x38 - 0x3b */ - } rsvd; - } cd; - } cx; - union { /* Offset 0x3c - 0x3f */ - union { /* header type 0 */ - CARD32 max_min_ipin_iline; - struct { -#if X_BYTE_ORDER == X_BIG_ENDIAN - CARD8 max_lat; - CARD8 min_gnt; - CARD8 int_pin; - CARD8 int_line; -#else - CARD8 int_line; - CARD8 int_pin; - CARD8 min_gnt; - CARD8 max_lat; -#endif - } mmii; - } mmii; - struct { /* header type 1 */ -#if X_BYTE_ORDER == X_BIG_ENDIAN - CARD16 bridge_control; /* upper 8 bits reserved */ - CARD8 rsvd2; - CARD8 rsvd1; -#else - CARD8 rsvd1; - CARD8 rsvd2; - CARD16 bridge_control; /* upper 8 bits reserved */ -#endif - } bctrl; - } bm; - union { /* Offset 0x40 - 0xff */ - CARD32 dwords[48]; - CARD8 bytes[192]; - } devspf; -} pciCfgRegs; - -typedef union pci_cfg_spc { - pciCfgRegs regs; - CARD32 dwords[256/sizeof(CARD32)]; - CARD8 bytes[256/sizeof(CARD8)]; -} pciCfgSpc; - -/* - * Data structure returned by xf86scanpci including contents of - * PCI config space header - */ -typedef struct pci_device { - PCITAG tag; - int busnum; - int devnum; - int funcnum; - pciCfgSpc cfgspc; - int basesize[7]; /* number of bits in base addr allocations */ - Bool minBasesize; - pointer businfo; /* pointer to secondary's bus info structure */ - Bool fakeDevice; /* Device added by system chipset support */ -} pciDevice, *pciConfigPtr; - typedef enum { PCI_MEM, PCI_MEM_SIZE, @@ -673,130 +249,17 @@ typedef enum { PCI_IO_SPARSE_MASK } PciAddrType; -#define pci_device_vendor cfgspc.regs.dv_id.device_vendor -#define pci_vendor cfgspc.regs.dv_id.dv.vendor -#define pci_device cfgspc.regs.dv_id.dv.device -#define pci_status_command cfgspc.regs.stat_cmd.status_command -#define pci_command cfgspc.regs.stat_cmd.sc.command -#define pci_status cfgspc.regs.stat_cmd.sc.status -#define pci_class_revision cfgspc.regs.class_rev.class_revision -#define pci_rev_id cfgspc.regs.class_rev.cr.rev_id -#define pci_prog_if cfgspc.regs.class_rev.cr.prog_if -#define pci_sub_class cfgspc.regs.class_rev.cr.sub_class -#define pci_base_class cfgspc.regs.class_rev.cr.base_class -#define pci_bist_header_latency_cache cfgspc.regs.bhlc.bist_header_latency_cache -#define pci_cache_line_size cfgspc.regs.bhlc.bhlc.cache_line_size -#define pci_latency_timer cfgspc.regs.bhlc.bhlc.latency_timer -#define pci_header_type cfgspc.regs.bhlc.bhlc.header_type -#define pci_bist cfgspc.regs.bhlc.bhlc.bist -#define pci_cb_secondary_status cfgspc.regs.cx.cg.secondary_status -#define pci_cb_bus_register cfgspc.regs.cx.cg.cgbr.cg_bus_reg -#define pci_cb_primary_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.primary_bus_number -#define pci_cb_cardbus_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.cardbus_bus_number -#define pci_cb_subordinate_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.subordinate_bus_number -#define pci_cb_latency_timer cfgspc.regs.cx.cg.cgbr.cgbr.latency_timer -#define pci_cb_membase0 cfgspc.regs.cx.cg.mem_base0 -#define pci_cb_memlimit0 cfgspc.regs.cx.cg.mem_limit0 -#define pci_cb_membase1 cfgspc.regs.cx.cg.mem_base1 -#define pci_cb_memlimit1 cfgspc.regs.cx.cg.mem_limit1 -#define pci_cb_iobase0 cfgspc.regs.cx.cg.io_base0 -#define pci_cb_iolimit0 cfgspc.regs.cx.cg.io_limit0 -#define pci_cb_iobase1 cfgspc.regs.cx.cg.io_base1 -#define pci_cb_iolimit1 cfgspc.regs.cx.cg.io_limit1 -#define pci_base0 cfgspc.regs.cx.cd.bc.dv.dv_base0 -#define pci_base1 cfgspc.regs.cx.cd.bc.dv.dv_base1 -#define pci_base2 cfgspc.regs.cx.cd.bc.dv.dv_base2 -#define pci_base3 cfgspc.regs.cx.cd.bc.dv.dv_base3 -#define pci_base4 cfgspc.regs.cx.cd.bc.dv.dv_base4 -#define pci_base5 cfgspc.regs.cx.cd.bc.dv.dv_base5 -#define pci_cardbus_cis_ptr cfgspc.regs.cx.cd.umem_c_cis.cardbus_cis_ptr -#define pci_subsys_card_vendor cfgspc.regs.cx.cd.um_ssys_id.subsys_card_vendor -#define pci_subsys_vendor cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_vendor -#define pci_subsys_card cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_card -#define pci_baserom cfgspc.regs.cx.cd.uio_rom.baserom -#define pci_pp_bus_register cfgspc.regs.cx.cd.bc.bg.ppbr.pp_bus_reg -#define pci_primary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.primary_bus_number -#define pci_secondary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_bus_number -#define pci_subordinate_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.subordinate_bus_number -#define pci_secondary_latency_timer cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_latency_timer -#define pci_io_base cfgspc.regs.cx.cd.bc.bg.io_base -#define pci_io_limit cfgspc.regs.cx.cd.bc.bg.io_limit -#define pci_secondary_status cfgspc.regs.cx.cd.bc.bg.secondary_status -#define pci_mem_base cfgspc.regs.cx.cd.bc.bg.mem_base -#define pci_mem_limit cfgspc.regs.cx.cd.bc.bg.mem_limit -#define pci_prefetch_mem_base cfgspc.regs.cx.cd.bc.bg.prefetch_mem_base -#define pci_prefetch_mem_limit cfgspc.regs.cx.cd.bc.bg.prefetch_mem_limit -#define pci_rsvd1 cfgspc.regs.cx.cd.um_c_cis.rsvd1 -#define pci_rsvd2 cfgspc.regs.cx.cd.um_ssys_id.rsvd2 -#define pci_prefetch_upper_mem_base cfgspc.regs.cx.cd.um_c_cis.pftch_umem_base -#define pci_prefetch_upper_mem_limit cfgspc.regs.cx.cd.um_ssys_id.pftch_umem_limit -#define pci_upper_io_base cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ubase -#define pci_upper_io_limit cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ulimit -#define pci_int_line cfgspc.regs.bm.mmii.mmii.int_line -#define pci_int_pin cfgspc.regs.bm.mmii.mmii.int_pin -#define pci_min_gnt cfgspc.regs.bm.mmii.mmii.min_gnt -#define pci_max_lat cfgspc.regs.bm.mmii.mmii.max_lat -#define pci_max_min_ipin_iline cfgspc.regs.bm.mmii.max_min_ipin_iline -#define pci_bridge_control cfgspc.regs.bm.bctrl.bridge_control -#define pci_user_config cfgspc.regs.devspf.dwords[0] -#define pci_user_config_0 cfgspc.regs.devspf.bytes[0] -#define pci_user_config_1 cfgspc.regs.devspf.bytes[1] -#define pci_user_config_2 cfgspc.regs.devspf.bytes[2] -#define pci_user_config_3 cfgspc.regs.devspf.bytes[3] - -typedef enum { - PCI_BIOS_PC = 0, - PCI_BIOS_OPEN_FIRMWARE, - PCI_BIOS_HP_PA_RISC, - PCI_BIOS_OTHER -} PciBiosType; /* Public PCI access functions */ -void pciInit(void); -PCITAG pciFindFirst(CARD32 id, CARD32 mask); -PCITAG pciFindNext(void); -CARD32 pciReadLong(PCITAG tag, int offset); -CARD16 pciReadWord(PCITAG tag, int offset); -CARD8 pciReadByte(PCITAG tag, int offset); -void pciWriteLong(PCITAG tag, int offset, CARD32 val); -void pciWriteWord(PCITAG tag, int offset, CARD16 val); -void pciWriteByte(PCITAG tag, int offset, CARD8 val); -void pciSetBitsLong(PCITAG tag, int offset, CARD32 mask, CARD32 val); -void pciSetBitsByte(PCITAG tag, int offset, CARD8 mask, CARD8 val); ADDRESS pciBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr); -ADDRESS pciHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr); PCITAG pciTag(int busnum, int devnum, int funcnum); -PCITAG pciDomTag(int domnum, int busnum, int devnum, int funcnum); -int pciGetBaseSize(PCITAG tag, int indx, Bool destructive, Bool *min); -CARD32 pciCheckForBrokenBase(PCITAG tag,int basereg); -pointer xf86MapPciMem(int ScreenNum, int Flags, PCITAG Tag, - ADDRESS Base, unsigned long Size); -int xf86ReadPciBIOS(unsigned long Offset, PCITAG Tag, int basereg, - unsigned char *Buf, int Len); -pciConfigPtr *xf86scanpci(int flags); -pciConfigPtr xf86GetPciConfigFromTag(PCITAG Tag); +Bool xf86scanpci(void); extern int pciNumBuses; /* Domain access functions. Some of these probably shouldn't be public */ -int xf86GetPciDomain(PCITAG tag); -pointer xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag, - ADDRESS Base, unsigned long Size); -IOADDRESS xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag, - IOADDRESS Base, unsigned long Size); -int xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len, - unsigned char *Buf); - -typedef enum { - ROM_BASE_PRESET = -2, - ROM_BASE_BIOS, - ROM_BASE_MEM0 = 0, - ROM_BASE_MEM1, - ROM_BASE_MEM2, - ROM_BASE_MEM3, - ROM_BASE_MEM4, - ROM_BASE_MEM5, - ROM_BASE_FIND -} romBaseSource; +pointer xf86MapDomainMemory(int ScreenNum, int Flags, struct pci_device *dev, + ADDRESS Base, unsigned long Size); +IOADDRESS xf86MapLegacyIO(struct pci_device *dev); #endif /* _XF86PCI_H */ diff --git a/hw/xfree86/os-support/bus/zx1PCI.c b/hw/xfree86/os-support/bus/zx1PCI.c index d83bc9116..561fbd9f7 100644 --- a/hw/xfree86/os-support/bus/zx1PCI.c +++ b/hw/xfree86/os-support/bus/zx1PCI.c @@ -1073,13 +1073,13 @@ xf86PostScanZX1(void) xf86MsgVerb(X_INFO, 2, "PCI: BusID 0x%.2x,0x%02x,0x%1x " "ID 0x%04x,0x%04x Rev 0x%02x Class 0x%02x,0x%02x\n", pPCI->busnum, pPCI->devnum, pPCI->funcnum, - pPCI->pci_vendor, pPCI->pci_device, pPCI->pci_rev_id, + pPCI->pci_vendor, pPCI->_pci_device, pPCI->pci_rev_id, pPCI->pci_base_class, pPCI->pci_sub_class); #else xf86MsgVerb(X_INFO, 2, "PCI: %.2x:%02x:%1x: chip %04x,%04x" " card %04x,%04x rev %02x class %02x,%02x,%02x hdr %02x\n", pPCI->busnum, pPCI->devnum, pPCI->funcnum, - pPCI->pci_vendor, pPCI->pci_device, + pPCI->pci_vendor, pPCI->_pci_device, pPCI->pci_subsys_vendor, pPCI->pci_subsys_card, pPCI->pci_rev_id, pPCI->pci_base_class, pPCI->pci_sub_class, pPCI->pci_prog_if, @@ -1122,13 +1122,13 @@ xf86PostScanZX1(void) xf86MsgVerb(X_INFO, 2, "PCI: BusID 0x%.2x,0x%02x,0x%1x " "ID 0x%04x,0x%04x Rev 0x%02x Class 0x%02x,0x%02x\n", pPCI->busnum, pPCI->devnum, pPCI->funcnum, - pPCI->pci_vendor, pPCI->pci_device, pPCI->pci_rev_id, + pPCI->pci_vendor, pPCI->_pci_device, pPCI->pci_rev_id, pPCI->pci_base_class, pPCI->pci_sub_class); #else xf86MsgVerb(X_INFO, 2, "PCI: %.2x:%02x:%1x: chip %04x,%04x" " card %04x,%04x rev %02x class %02x,%02x,%02x hdr %02x\n", pPCI->busnum, pPCI->devnum, pPCI->funcnum, - pPCI->pci_vendor, pPCI->pci_device, + pPCI->pci_vendor, pPCI->_pci_device, pPCI->pci_subsys_vendor, pPCI->pci_subsys_card, pPCI->pci_rev_id, pPCI->pci_base_class, pPCI->pci_sub_class, pPCI->pci_prog_if, |