diff options
| author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-11-12 23:54:39 +0000 |
|---|---|---|
| committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-11-12 23:54:39 +0000 |
| commit | 417f38f066e21cf69f85d78eecbf6268c53a80bc (patch) | |
| tree | c8f48db409c13d90f9797854e4559bb9faad2de6 | |
| parent | 2d37be61e3a377843f4e8b8fcc837838294b8b3f (diff) | |
MIPS FPU fixes (Daniel Jacobowitz).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2213 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-mips/op.c | 2 | ||||
| -rw-r--r-- | target-mips/translate.c | 6 |
2 files changed, 5 insertions, 3 deletions
diff --git a/target-mips/op.c b/target-mips/op.c index 638fd3b33..534c90e51 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -799,7 +799,7 @@ FLOAT_OP(cvtd, w) } FLOAT_OP(cvts, d) { - FST2 = float64_to_float32(WT0, &env->fp_status); + FST2 = float64_to_float32(FDT0, &env->fp_status); DEBUG_FPU_STATE(); RETURN(); } diff --git a/target-mips/translate.c b/target-mips/translate.c index c0de12b0f..f5c3afdce 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1791,7 +1791,7 @@ static void gen_farith (DisasContext *ctx, int fmt, int ft, int fs, int fd, int break; case FOP(32, 17): /* cvt.s.d */ CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); + GEN_LOAD_FREG_FTN(DT0, fs); gen_op_float_cvts_d(); GEN_STORE_FTN_FREG(fd, WT2); opn = "cvt.s.d"; @@ -1812,7 +1812,7 @@ static void gen_farith (DisasContext *ctx, int fmt, int ft, int fs, int fd, int break; case FOP(36, 17): /* cvt.w.d */ CHECK_FR(ctx, fs | fd); - GEN_LOAD_FREG_FTN(WT0, fs); + GEN_LOAD_FREG_FTN(DT0, fs); gen_op_float_cvtw_d(); GEN_STORE_FTN_FREG(fd, WT2); opn = "cvt.w.d"; @@ -2089,6 +2089,7 @@ static void decode_opc (DisasContext *ctx) case 0x39: /* SWC1 */ case 0x3D: /* SDC1 */ #if defined(MIPS_USES_FPU) + save_cpu_state(ctx, 1); gen_op_cp1_enabled(); gen_flt_ldst(ctx, op, rt, rs, imm); #else @@ -2098,6 +2099,7 @@ static void decode_opc (DisasContext *ctx) case 0x11: /* CP1 opcode */ #if defined(MIPS_USES_FPU) + save_cpu_state(ctx, 1); gen_op_cp1_enabled(); op1 = ((ctx->opcode >> 21) & 0x1F); switch (op1) { |