From 89bba44e969f15bf20da6d700c493237b095a588 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 2 May 2008 11:52:52 -0700
Subject: Add intel_bufmgr_gem for new graphics execution manager.
---
src/mesa/drivers/dri/common/dri_bufmgr.c | 4 +-
src/mesa/drivers/dri/common/dri_bufmgr.h | 17 +-
src/mesa/drivers/dri/common/dri_bufmgr_fake.c | 4 +-
src/mesa/drivers/dri/i965/Makefile | 2 +-
src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 1 +
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 9 +-
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 818 +++++++++++++++++++++++++
src/mesa/drivers/dri/intel/intel_bufmgr_gem.h | 19 +
src/mesa/drivers/dri/intel/intel_ioctl.c | 32 +-
src/mesa/drivers/dri/intel/intel_ioctl.h | 3 +-
10 files changed, 869 insertions(+), 40 deletions(-)
create mode 120000 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
create mode 100644 src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
create mode 100644 src/mesa/drivers/dri/intel/intel_bufmgr_gem.h
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.c b/src/mesa/drivers/dri/common/dri_bufmgr.c
index 4df006fb9f..70ae091499 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr.c
+++ b/src/mesa/drivers/dri/common/dri_bufmgr.c
@@ -148,9 +148,9 @@ int dri_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
return reloc_buf->bufmgr->emit_reloc(reloc_buf, flags, delta, offset, target_buf);
}
-void *dri_process_relocs(dri_bo *batch_buf, GLuint *count)
+void *dri_process_relocs(dri_bo *batch_buf)
{
- return batch_buf->bufmgr->process_relocs(batch_buf, count);
+ return batch_buf->bufmgr->process_relocs(batch_buf);
}
void dri_post_submit(dri_bo *batch_buf, dri_fence **last_fence)
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.h b/src/mesa/drivers/dri/common/dri_bufmgr.h
index 4593eaf9f7..cbfeb9136d 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr.h
+++ b/src/mesa/drivers/dri/common/dri_bufmgr.h
@@ -41,7 +41,12 @@ typedef struct _dri_bo dri_bo;
typedef struct _dri_fence dri_fence;
struct _dri_bo {
- /** Size in bytes of the buffer object. */
+ /**
+ * Size in bytes of the buffer object.
+ *
+ * The size may be larger than the size originally requested for the
+ * allocation, such as being aligned to page size.
+ */
unsigned long size;
/**
* Card virtual address (offset from the beginning of the aperture) for the
@@ -169,10 +174,10 @@ struct _dri_bufmgr {
* into them the appopriate order.
*
* \param batch_buf buffer at the root of the tree of relocations
- * \param count returns the number of buffers validated.
- * \return relocation record for use in command submission.
- * */
- void *(*process_relocs)(dri_bo *batch_buf, GLuint *count);
+ * \return argument to be completed and passed to the execbuffers ioctl
+ * (if any).
+ */
+ void *(*process_relocs)(dri_bo *batch_buf);
void (*post_submit)(dri_bo *batch_buf, dri_fence **fence);
@@ -214,7 +219,7 @@ void dri_bufmgr_destroy(dri_bufmgr *bufmgr);
int dri_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
GLuint offset, dri_bo *target_buf);
-void *dri_process_relocs(dri_bo *batch_buf, uint32_t *count);
+void *dri_process_relocs(dri_bo *batch_buf);
void dri_post_process_relocs(dri_bo *batch_buf);
void dri_post_submit(dri_bo *batch_buf, dri_fence **last_fence);
int dri_bufmgr_check_aperture_space(dri_bo *bo);
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr_fake.c b/src/mesa/drivers/dri/common/dri_bufmgr_fake.c
index 9bf3f3437c..9dd06b07eb 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr_fake.c
+++ b/src/mesa/drivers/dri/common/dri_bufmgr_fake.c
@@ -1098,7 +1098,7 @@ dri_fake_reloc_and_validate_buffer(dri_bo *bo)
}
static void *
-dri_fake_process_relocs(dri_bo *batch_buf, GLuint *count_p)
+dri_fake_process_relocs(dri_bo *batch_buf)
{
dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)batch_buf->bufmgr;
dri_bo_fake *batch_fake = (dri_bo_fake *)batch_buf;
@@ -1126,8 +1126,6 @@ dri_fake_process_relocs(dri_bo *batch_buf, GLuint *count_p)
assert(ret == 0);
- *count_p = 0; /* junk */
-
bufmgr_fake->current_total_size = 0;
return NULL;
}
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index d46b3428f5..ca9b7da40f 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -9,7 +9,7 @@ DRIVER_SOURCES = \
intel_blit.c \
intel_buffer_objects.c \
intel_buffers.c \
- intel_bufmgr_ttm.c \
+ intel_bufmgr_gem.c \
intel_context.c \
intel_decode.c \
intel_depthstencil.c \
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
new file mode 120000
index 0000000000..dee0daf9c0
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -0,0 +1 @@
+../intel/intel_bufmgr_gem.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index a594fb6cc4..c5b0f531d4 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -131,11 +131,8 @@ do_flush_locked(struct intel_batchbuffer *batch,
GLuint used, GLboolean allow_unlock)
{
struct intel_context *intel = batch->intel;
- void *start;
- GLuint count;
dri_bo_unmap(batch->buf);
- start = dri_process_relocs(batch->buf, &count);
batch->map = NULL;
batch->ptr = NULL;
@@ -148,12 +145,16 @@ do_flush_locked(struct intel_batchbuffer *batch,
if (!(intel->numClipRects == 0 &&
batch->cliprect_mode == LOOP_CLIPRECTS)) {
if (intel->ttm == GL_TRUE) {
+ struct drm_i915_gem_execbuffer *execbuf;
+
+ execbuf = dri_process_relocs(batch->buf);
intel_exec_ioctl(batch->intel,
used,
batch->cliprect_mode != LOOP_CLIPRECTS,
allow_unlock,
- start, count, &batch->last_fence);
+ execbuf, &batch->last_fence);
} else {
+ dri_process_relocs(batch->buf);
intel_batch_ioctl(batch->intel,
batch->buf->offset,
used,
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
new file mode 100644
index 0000000000..2d8dced214
--- /dev/null
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -0,0 +1,818 @@
+/**************************************************************************
+ *
+ * Copyright © 2007 Red Hat Inc.
+ * Copyright © 2007 Intel Corporation
+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ *
+ **************************************************************************/
+/*
+ * Authors: Thomas Hellström
+ * Keith Whitwell
+ * Eric Anholt
+ * Dave Airlie
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "errno.h"
+#include "mtypes.h"
+#include "dri_bufmgr.h"
+#include "string.h"
+#include "imports.h"
+
+#include "i915_drm.h"
+
+#include "intel_bufmgr_gem.h"
+
+#define DBG(...) do { \
+ if (bufmgr_gem->bufmgr.debug) \
+ fprintf(stderr, __VA_ARGS__); \
+} while (0)
+
+struct intel_validate_entry {
+ dri_bo *bo;
+ struct drm_i915_op_arg bo_arg;
+};
+
+struct dri_gem_bo_bucket_entry {
+ uint32_t gem_handle;
+ struct dri_gem_bo_bucket_entry *next;
+};
+
+struct dri_gem_bo_bucket {
+ struct dri_gem_bo_bucket_entry *head;
+ struct dri_gem_bo_bucket_entry **tail;
+ /**
+ * Limit on the number of entries in this bucket.
+ *
+ * 0 means that this caching at this bucket size is disabled.
+ * -1 means that there is no limit to caching at this size.
+ */
+ int max_entries;
+ int num_entries;
+};
+
+/* Arbitrarily chosen, 16 means that the maximum size we'll cache for reuse
+ * is 1 << 16 pages, or 256MB.
+ */
+#define INTEL_GEM_BO_BUCKETS 16
+typedef struct _dri_bufmgr_gem {
+ dri_bufmgr bufmgr;
+
+ int fd;
+
+ uint32_t max_relocs;
+
+ struct drm_i915_gem_validate_entry *validate_array;
+ dri_bo **validate_bo;
+ int validate_array_size;
+ int validate_count;
+
+ /** Array of lists of cached gem objects of power-of-two sizes */
+ struct dri_gem_bo_bucket cache_bucket[INTEL_GEM_BO_BUCKETS];
+
+ struct drm_i915_gem_execbuffer exec_arg;
+} dri_bufmgr_gem;
+
+typedef struct _dri_bo_gem {
+ dri_bo bo;
+
+ int refcount;
+ unsigned int map_count;
+ uint32_t gem_handle;
+ const char *name;
+
+ /**
+ * Index of the buffer within the validation list while preparing a
+ * batchbuffer execution.
+ */
+ int validate_index;
+
+ /** Array passed to the DRM containing relocation information. */
+ struct drm_i915_gem_relocation_entry *relocs;
+ /** Array of bos corresponding to relocs[i].target_handle */
+ dri_bo **reloc_target_bo;
+ /** Number of entries in relocs */
+ int reloc_count;
+ /** Mapped address for the buffer */
+ void *virtual;
+} dri_bo_gem;
+
+typedef struct _dri_fence_gem
+{
+ dri_fence fence;
+
+ int refcount;
+ const char *name;
+ drmFence drm_fence;
+} dri_fence_gem;
+
+static int
+logbase2(int n)
+{
+ GLint i = 1;
+ GLint log2 = 0;
+
+ while (n > i) {
+ i *= 2;
+ log2++;
+ }
+
+ return log2;
+}
+
+static struct dri_gem_bo_bucket *
+dri_gem_bo_bucket_for_size(dri_bufmgr_gem *bufmgr_gem, unsigned long size)
+{
+ int i;
+
+ /* We only do buckets in power of two increments */
+ if ((size & (size - 1)) != 0)
+ return NULL;
+
+ /* We should only see sizes rounded to pages. */
+ assert((size % 4096) == 0);
+
+ /* We always allocate in units of pages */
+ i = ffs(size / 4096) - 1;
+ if (i >= INTEL_GEM_BO_BUCKETS)
+ return NULL;
+
+ return &bufmgr_gem->cache_bucket[i];
+}
+
+
+static void dri_gem_dump_validation_list(dri_bufmgr_gem *bufmgr_gem)
+{
+ int i, j;
+
+ for (i = 0; i < bufmgr_gem->validate_count; i++) {
+ dri_bo *bo = bufmgr_gem->validate_bo[i];
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+
+ if (bo_gem->relocs == NULL) {
+ DBG("%2d: %s\n", i, bo_gem->name);
+ continue;
+ }
+
+ for (j = 0; j < bo_gem->reloc_count; j++) {
+ dri_bo *target_bo = bo_gem->reloc_target_bo[j];
+ dri_bo_gem *target_gem = (dri_bo_gem *)target_bo;
+
+ DBG("%2d: %s@0x%08llx -> %s@0x%08lx + 0x%08x\n",
+ i,
+ bo_gem->name, bo_gem->relocs[j].offset,
+ target_gem->name, target_bo->offset,
+ bo_gem->relocs[j].delta);
+ }
+ }
+}
+
+/**
+ * Adds the given buffer to the list of buffers to be validated (moved into the
+ * appropriate memory type) with the next batch submission.
+ *
+ * If a buffer is validated multiple times in a batch submission, it ends up
+ * with the intersection of the memory type flags and the union of the
+ * access flags.
+ */
+static void
+intel_add_validate_buffer(dri_bo *bo)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+ int index;
+
+ if (bo_gem->validate_index != -1)
+ return;
+
+ /* Extend the array of validation entries as necessary. */
+ if (bufmgr_gem->validate_count == bufmgr_gem->validate_array_size) {
+ int new_size = bufmgr_gem->validate_array_size * 2;
+
+ if (new_size == 0)
+ new_size = 5;
+
+ bufmgr_gem->validate_array =
+ realloc(bufmgr_gem->validate_array,
+ sizeof(*bufmgr_gem->validate_array) * new_size);
+ bufmgr_gem->validate_bo =
+ realloc(bufmgr_gem->validate_bo,
+ sizeof(*bufmgr_gem->validate_bo) * new_size);
+ bufmgr_gem->validate_array_size = new_size;
+ }
+
+ index = bufmgr_gem->validate_count;
+ /* Fill in array entry */
+ bufmgr_gem->validate_array[index].buffer_handle = bo_gem->gem_handle;
+ bufmgr_gem->validate_array[index].relocation_count = bo_gem->reloc_count;
+ bufmgr_gem->validate_array[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
+ bufmgr_gem->validate_bo[index] = bo;
+ dri_bo_reference(bo);
+ bufmgr_gem->validate_count++;
+}
+
+
+#define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
+ sizeof(uint32_t))
+
+static int
+intel_setup_reloc_list(dri_bo *bo)
+{
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+
+ bo_gem->relocs = calloc(bufmgr_gem->max_relocs,
+ sizeof(struct drm_i915_gem_relocation_entry));
+ bo_gem->reloc_target_bo = calloc(1, sizeof(dri_bo *));
+
+ return 0;
+}
+
+static dri_bo *
+dri_gem_alloc(dri_bufmgr *bufmgr, const char *name,
+ unsigned long size, unsigned int alignment,
+ uint64_t location_mask)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr;
+ dri_bo_gem *bo_gem;
+ unsigned int page_size = getpagesize();
+ int ret;
+ struct dri_gem_bo_bucket *bucket;
+ GLboolean alloc_from_cache = GL_FALSE;
+
+ bo_gem = calloc(1, sizeof(*bo_gem));
+ if (!bo_gem)
+ return NULL;
+
+ /* Round the allocated size up to a power of two number of pages. */
+ bo_gem->bo.size = 1 << logbase2(size);
+ if (bo_gem->bo.size < page_size)
+ bo_gem->bo.size = page_size;
+ bucket = dri_gem_bo_bucket_for_size(bufmgr_gem, bo_gem->bo.size);
+
+ /* If we don't have caching at this size, don't actually round the
+ * allocation up.
+ */
+ if (bucket == NULL || bucket->max_entries == 0) {
+ bo_gem->bo.size = size;
+ if (bo_gem->bo.size < page_size)
+ bo_gem->bo.size = page_size;
+ }
+
+ /* Get a buffer out of the cache if available */
+ if (bucket != NULL && bucket->num_entries > 0) {
+ struct dri_gem_bo_bucket_entry *entry = bucket->head;
+#if 0
+ int busy;
+
+ /* XXX */
+ /* Check if the buffer is still in flight. If not, reuse it. */
+ ret = drmBOBusy(bufmgr_gem->fd, &entry->drm_bo, &busy);
+ alloc_from_cache = (ret == 0 && busy == 0);
+#else
+ alloc_from_cache = 0;
+#endif
+
+ if (alloc_from_cache) {
+ bucket->head = entry->next;
+ if (entry->next == NULL)
+ bucket->tail = &bucket->head;
+ bucket->num_entries--;
+
+ bo_gem->gem_handle = entry->gem_handle;
+ free(entry);
+ }
+ }
+
+ if (!alloc_from_cache) {
+ struct drm_gem_alloc alloc;
+
+ memset(&alloc, 0, sizeof(alloc));
+ alloc.size = bo_gem->bo.size;
+
+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_ALLOC, &alloc);
+ bo_gem->gem_handle = alloc.handle;
+ if (ret != 0) {
+ free(bo_gem);
+ return NULL;
+ }
+ }
+
+ bo_gem->bo.offset = 0;
+ bo_gem->bo.virtual = NULL;
+ bo_gem->bo.bufmgr = bufmgr;
+ bo_gem->name = name;
+ bo_gem->refcount = 1;
+ bo_gem->validate_index = -1;
+
+ DBG("bo_create: %p (%s) %ldb\n", &bo_gem->bo, bo_gem->name, size);
+
+ return &bo_gem->bo;
+}
+
+/* Our GEM backend doesn't allow creation of static buffers, as that requires
+ * privelege for the non-fake case, and the lock in the fake case where we were
+ * working around the X Server not creating buffers and passing handles to us.
+ */
+static dri_bo *
+dri_gem_alloc_static(dri_bufmgr *bufmgr, const char *name,
+ unsigned long offset, unsigned long size, void *virtual,
+ uint64_t location_mask)
+{
+ return NULL;
+}
+
+/**
+ * Returns a dri_bo wrapping the given buffer object handle.
+ *
+ * This can be used when one application needs to pass a buffer object
+ * to another.
+ */
+dri_bo *
+intel_gem_bo_create_from_handle(dri_bufmgr *bufmgr, const char *name,
+ unsigned int handle)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr;
+ dri_bo_gem *bo_gem;
+ int ret;
+ struct drm_gem_open open_arg;
+
+ bo_gem = calloc(1, sizeof(*bo_gem));
+ if (!bo_gem)
+ return NULL;
+
+ memset(&open_arg, 0, sizeof(open_arg));
+ open_arg.name = handle;
+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
+ if (ret != 0) {
+ fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
+ name, handle, strerror(-ret));
+ free(bo_gem);
+ return NULL;
+ }
+ bo_gem->bo.size = open_arg.size;
+ bo_gem->bo.offset = 0;
+ bo_gem->bo.virtual = NULL;
+ bo_gem->bo.bufmgr = bufmgr;
+ bo_gem->name = name;
+ bo_gem->refcount = 1;
+ bo_gem->validate_index = -1;
+
+ DBG("bo_create_from_handle: %p %08x (%s)\n",
+ &bo_gem->bo, handle, bo_gem->name);
+
+ return &bo_gem->bo;
+}
+
+static void
+dri_gem_bo_reference(dri_bo *bo)
+{
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+
+ bo_gem->refcount++;
+}
+
+static void
+dri_gem_bo_unreference(dri_bo *bo)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+
+ if (!bo)
+ return;
+
+ if (--bo_gem->refcount == 0) {
+ struct dri_gem_bo_bucket *bucket;
+ int ret;
+
+ assert(bo_gem->map_count == 0);
+
+ if (bo_gem->relocs != NULL) {
+ int i;
+
+ /* Unreference all the target buffers */
+ for (i = 0; i < bo_gem->reloc_count; i++)
+ dri_bo_unreference(bo_gem->reloc_target_bo[i]);
+ free(bo_gem->reloc_target_bo);
+ free(bo_gem->relocs);
+ }
+
+ bucket = dri_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
+ /* Put the buffer into our internal cache for reuse if we can. */
+ if (bucket != NULL &&
+ (bucket->max_entries == -1 ||
+ (bucket->max_entries > 0 &&
+ bucket->num_entries < bucket->max_entries)))
+ {
+ struct dri_gem_bo_bucket_entry *entry;
+
+ entry = calloc(1, sizeof(*entry));
+ entry->gem_handle = bo_gem->gem_handle;
+
+ entry->next = NULL;
+ *bucket->tail = entry;
+ bucket->tail = &entry->next;
+ bucket->num_entries++;
+ } else {
+ struct drm_gem_unreference unref;
+
+ /* Decrement the kernel refcount for the buffer. */
+ unref.handle = bo_gem->gem_handle;
+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_UNREFERENCE, &unref);
+ if (ret != 0) {
+ fprintf(stderr, "DRM_IOCTL_GEM_UNREFERENCE failed (%s): %s\n",
+ bo_gem->name, strerror(-ret));
+ }
+ }
+
+ DBG("bo_unreference final: %p (%s)\n", &bo_gem->bo, bo_gem->name);
+
+ free(bo);
+ return;
+ }
+}
+
+static int
+dri_gem_bo_map(dri_bo *bo, GLboolean write_enable)
+{
+ dri_bufmgr_gem *bufmgr_gem;
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+ int ret;
+
+ bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+
+ /* Allow recursive mapping. Mesa may recursively map buffers with
+ * nested display loops.
+ */
+ if (bo_gem->map_count++ != 0)
+ return 0;
+
+ assert(bo->virtual == NULL);
+
+ DBG("bo_map: %p (%s)\n", &bo_gem->bo, bo_gem->name);
+
+ if (bo_gem->virtual == NULL) {
+ struct drm_gem_mmap mmap_arg;
+
+ mmap_arg.handle = bo_gem->gem_handle;
+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_MMAP, &mmap_arg);
+ if (ret != 0) {
+ fprintf(stderr, "%s:%d: Error mapping buffer %s: %s .\n",
+ __FILE__, __LINE__, bo_gem->name, strerror(-ret));
+ }
+ bo_gem->virtual = (void *)(uintptr_t)mmap_arg.addr_ptr;
+ }
+
+ /* XXX Synchronization with hardware */
+
+ bo->virtual = bo_gem->virtual;
+
+ return 0;
+}
+
+static int
+dri_gem_bo_unmap(dri_bo *bo)
+{
+ dri_bufmgr_gem *bufmgr_gem;
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+
+ if (bo == NULL)
+ return 0;
+
+ assert(bo_gem->map_count != 0);
+ if (--bo_gem->map_count != 0)
+ return 0;
+
+ bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+
+ assert(bo->virtual != NULL);
+
+ DBG("bo_unmap: %p (%s)\n", &bo_gem->bo, bo_gem->name);
+
+ munmap(bo_gem->virtual, bo->size);
+ bo_gem->virtual = NULL;
+ bo->virtual = NULL;
+
+ return 0;
+}
+
+static void
+dri_gem_fence_reference(dri_fence *fence)
+{
+ dri_fence_gem *fence_gem = (dri_fence_gem *)fence;
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)fence->bufmgr;
+
+ ++fence_gem->refcount;
+ DBG("fence_reference: %p (%s)\n", &fence_gem->fence, fence_gem->name);
+}
+
+static void
+dri_gem_fence_unreference(dri_fence *fence)
+{
+ dri_fence_gem *fence_gem = (dri_fence_gem *)fence;
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)fence->bufmgr;
+
+ if (!fence)
+ return;
+
+ DBG("fence_unreference: %p (%s)\n", &fence_gem->fence, fence_gem->name);
+
+ if (--fence_gem->refcount == 0) {
+ int ret;
+
+ ret = drmFenceUnreference(bufmgr_gem->fd, &fence_gem->drm_fence);
+ if (ret != 0) {
+ fprintf(stderr, "drmFenceUnreference failed (%s): %s\n",
+ fence_gem->name, strerror(-ret));
+ }
+
+ free(fence);
+ return;
+ }
+}
+
+static void
+dri_gem_fence_wait(dri_fence *fence)
+{
+ dri_fence_gem *fence_gem = (dri_fence_gem *)fence;
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)fence->bufmgr;
+ int ret;
+
+ ret = drmFenceWait(bufmgr_gem->fd, DRM_FENCE_FLAG_WAIT_LAZY, &fence_gem->drm_fence, 0);
+ if (ret != 0) {
+ fprintf(stderr, "%s:%d: Error waiting for fence %s: %s.\n",
+ __FILE__, __LINE__, fence_gem->name, strerror(-ret));
+ abort();
+ }
+
+ DBG("fence_wait: %p (%s)\n", &fence_gem->fence, fence_gem->name);
+}
+
+static void
+dri_bufmgr_gem_destroy(dri_bufmgr *bufmgr)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr;
+ int i;
+
+ free(bufmgr_gem->validate_array);
+ free(bufmgr_gem->validate_bo);
+
+ /* Free any cached buffer objects we were going to reuse */
+ for (i = 0; i < INTEL_GEM_BO_BUCKETS; i++) {
+ struct dri_gem_bo_bucket *bucket = &bufmgr_gem->cache_bucket[i];
+ struct dri_gem_bo_bucket_entry *entry;
+
+ while ((entry = bucket->head) != NULL) {
+ struct drm_gem_unreference unref;
+ int ret;
+
+ bucket->head = entry->next;
+ if (entry->next == NULL)
+ bucket->tail = &bucket->head;
+ bucket->num_entries--;
+
+ /* Decrement the kernel refcount for the buffer. */
+ unref.handle = entry->gem_handle;
+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_UNREFERENCE, &unref);
+ if (ret != 0) {
+ fprintf(stderr, "DRM_IOCTL_GEM_UNREFERENCE failed: %s\n",
+ strerror(-ret));
+ }
+
+ free(entry);
+ }
+ }
+
+ free(bufmgr);
+}
+
+/**
+ * Adds the target buffer to the validation list and adds the relocation
+ * to the reloc_buffer's relocation list.
+ *
+ * The relocation entry at the given offset must already contain the
+ * precomputed relocation value, because the kernel will optimize out
+ * the relocation entry write when the buffer hasn't moved from the
+ * last known offset in target_bo.
+ */
+static int
+dri_gem_emit_reloc(dri_bo *bo, uint64_t flags, GLuint delta,
+ GLuint offset, dri_bo *target_bo)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+ dri_bo_gem *target_bo_gem = (dri_bo_gem *)target_bo;
+
+ /* Create a new relocation list if needed */
+ if (bo_gem->relocs == NULL)
+ intel_setup_reloc_list(bo);
+
+ /* Check overflow */
+ assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
+
+ bo_gem->relocs[bo_gem->reloc_count].offset = offset;
+ bo_gem->relocs[bo_gem->reloc_count].delta = delta;
+ bo_gem->relocs[bo_gem->reloc_count].target_handle =
+ target_bo_gem->gem_handle;
+
+ bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
+ dri_bo_reference(target_bo);
+
+ bo_gem->reloc_count++;
+ return 0;
+}
+
+/**
+ * Walk the tree of relocations rooted at BO and accumulate the list of
+ * validations to be performed and update the relocation buffers with
+ * index values into the validation list.
+ */
+static void
+dri_gem_bo_process_reloc(dri_bo *bo)
+{
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+ int i;
+
+ if (bo_gem->relocs == NULL)
+ return;
+
+ for (i = 0; i < bo_gem->reloc_count; i++) {
+ dri_bo *target_bo = bo_gem->reloc_target_bo[i];
+
+ /* Continue walking the tree depth-first. */
+ dri_gem_bo_process_reloc(target_bo);
+
+ /* Add the target to the validate list */
+ intel_add_validate_buffer(target_bo);
+ }
+}
+
+static void *
+dri_gem_process_reloc(dri_bo *batch_buf)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)batch_buf->bufmgr;
+
+ /* Update indices and set up the validate list. */
+ dri_gem_bo_process_reloc(batch_buf);
+
+ /* Add the batch buffer to the validation list. There are no relocations
+ * pointing to it.
+ */
+ intel_add_validate_buffer(batch_buf);
+
+ bufmgr_gem->exec_arg.buffers_ptr = (uintptr_t)bufmgr_gem->validate_array;
+ bufmgr_gem->exec_arg.buffer_count = bufmgr_gem->validate_count;
+ bufmgr_gem->exec_arg.batch_start_offset = bufmgr_gem->validate_count;
+
+ return &bufmgr_gem->exec_arg;
+}
+
+static void
+intel_update_buffer_offsets (dri_bufmgr_gem *bufmgr_gem)
+{
+ int i;
+
+ for (i = 0; i < bufmgr_gem->validate_count; i++) {
+ dri_bo *bo = bufmgr_gem->validate_bo[i];
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+
+ /* Update the buffer offset */
+ if (bufmgr_gem->validate_array[i].buffer_offset != bo->offset) {
+ DBG("BO %s migrated: 0x%08lx -> 0x%08llx\n",
+ bo_gem->name, bo->offset,
+ bufmgr_gem->validate_array[i].buffer_offset);
+ bo->offset = bufmgr_gem->validate_array[i].buffer_offset;
+ }
+ }
+}
+
+static void
+dri_gem_post_submit(dri_bo *batch_buf, dri_fence **last_fence)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)batch_buf->bufmgr;
+ int i;
+
+ intel_update_buffer_offsets (bufmgr_gem);
+
+ if (bufmgr_gem->bufmgr.debug)
+ dri_gem_dump_validation_list(bufmgr_gem);
+
+ for (i = 0; i < bufmgr_gem->validate_count; i++) {
+ dri_bo *bo = bufmgr_gem->validate_bo[i];
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+
+ /* Disconnect the buffer from the validate list */
+ bo_gem->validate_index = -1;
+ dri_bo_unreference(bo);
+ bufmgr_gem->validate_bo[i] = NULL;
+ }
+ bufmgr_gem->validate_count = 0;
+}
+
+/**
+ * Enables unlimited caching of buffer objects for reuse.
+ *
+ * This is potentially very memory expensive, as the cache at each bucket
+ * size is only bounded by how many buffers of that size we've managed to have
+ * in flight at once.
+ */
+void
+intel_gem_enable_bo_reuse(dri_bufmgr *bufmgr)
+{
+ /*
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr;
+ int i;
+
+ for (i = 0; i < INTEL_GEM_BO_BUCKETS; i++) {
+ bufmgr_gem->cache_bucket[i].max_entries = -1;
+ }
+ */
+}
+
+/*
+ *
+ */
+static int
+dri_gem_check_aperture_space(dri_bo *bo)
+{
+ return 0;
+}
+
+/**
+ * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
+ * and manage map buffer objections.
+ *
+ * \param fd File descriptor of the opened DRM device.
+ * \param fence_type Driver-specific fence type used for fences with no flush.
+ * \param fence_type_flush Driver-specific fence type used for fences with a
+ * flush.
+ */
+dri_bufmgr *
+intel_bufmgr_gem_init(int fd, int batch_size)
+{
+ dri_bufmgr_gem *bufmgr_gem;
+ int i;
+
+ bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
+ bufmgr_gem->fd = fd;
+
+ /* Let's go with one relocation per every 2 dwords (but round down a bit
+ * since a power of two will mean an extra page allocation for the reloc
+ * buffer).
+ *
+ * Every 4 was too few for the blender benchmark.
+ */
+ bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
+
+ bufmgr_gem->bufmgr.bo_alloc = dri_gem_alloc;
+ bufmgr_gem->bufmgr.bo_alloc_static = dri_gem_alloc_static;
+ bufmgr_gem->bufmgr.bo_reference = dri_gem_bo_reference;
+ bufmgr_gem->bufmgr.bo_unreference = dri_gem_bo_unreference;
+ bufmgr_gem->bufmgr.bo_map = dri_gem_bo_map;
+ bufmgr_gem->bufmgr.bo_unmap = dri_gem_bo_unmap;
+ bufmgr_gem->bufmgr.fence_reference = dri_gem_fence_reference;
+ bufmgr_gem->bufmgr.fence_unreference = dri_gem_fence_unreference;
+ bufmgr_gem->bufmgr.fence_wait = dri_gem_fence_wait;
+ bufmgr_gem->bufmgr.destroy = dri_bufmgr_gem_destroy;
+ bufmgr_gem->bufmgr.emit_reloc = dri_gem_emit_reloc;
+ bufmgr_gem->bufmgr.process_relocs = dri_gem_process_reloc;
+ bufmgr_gem->bufmgr.post_submit = dri_gem_post_submit;
+ bufmgr_gem->bufmgr.debug = GL_FALSE;
+ bufmgr_gem->bufmgr.check_aperture_space = dri_gem_check_aperture_space;
+ /* Initialize the linked lists for BO reuse cache. */
+ for (i = 0; i < INTEL_GEM_BO_BUCKETS; i++)
+ bufmgr_gem->cache_bucket[i].tail = &bufmgr_gem->cache_bucket[i].head;
+
+ return &bufmgr_gem->bufmgr;
+}
+
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.h b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.h
new file mode 100644
index 0000000000..a28f5ae814
--- /dev/null
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.h
@@ -0,0 +1,19 @@
+
+#ifndef INTEL_BUFMGR_GEM_H
+#define INTEL_BUFMGR_GEM_H
+
+#include "dri_bufmgr.h"
+
+extern dri_bo *intel_gem_bo_create_from_handle(dri_bufmgr *bufmgr, const char *name,
+ unsigned int handle);
+
+dri_fence *intel_gem_fence_create_from_arg(dri_bufmgr *bufmgr, const char *name,
+ drm_fence_arg_t *arg);
+
+
+dri_bufmgr *intel_bufmgr_gem_init(int fd, int batch_size);
+
+void
+intel_gem_enable_bo_reuse(dri_bufmgr *bufmgr);
+
+#endif /* INTEL_BUFMGR_GEM_H */
diff --git a/src/mesa/drivers/dri/intel/intel_ioctl.c b/src/mesa/drivers/dri/intel/intel_ioctl.c
index 66e36102b9..f9624a6abe 100644
--- a/src/mesa/drivers/dri/intel/intel_ioctl.c
+++ b/src/mesa/drivers/dri/intel/intel_ioctl.c
@@ -151,9 +151,9 @@ void
intel_exec_ioctl(struct intel_context *intel,
GLuint used,
GLboolean ignore_cliprects, GLboolean allow_unlock,
- void *start, GLuint count, dri_fence **fence)
+ struct drm_i915_gem_execbuffer *execbuf,
+ dri_fence **fence)
{
- struct drm_i915_execbuffer execbuf;
dri_fence *fo;
int ret;
@@ -169,16 +169,13 @@ intel_exec_ioctl(struct intel_context *intel,
memset(&execbuf, 0, sizeof(execbuf));
- execbuf.num_buffers = count;
- execbuf.batch.used = used;
- execbuf.batch.cliprects = intel->pClipRects;
- execbuf.batch.num_cliprects = ignore_cliprects ? 0 : intel->numClipRects;
- execbuf.batch.DR1 = 0;
- execbuf.batch.DR4 = ((((GLuint) intel->drawX) & 0xffff) |
- (((GLuint) intel->drawY) << 16));
-
- execbuf.ops_list = (unsigned long)start; // TODO
- execbuf.fence_arg.flags = DRM_FENCE_FLAG_SHAREABLE | DRM_I915_FENCE_FLAG_FLUSHED;
+ execbuf->batch_start_offset = 0;
+ execbuf->batch_len = used;
+ execbuf->cliprects_ptr = (uintptr_t)intel->pClipRects;
+ execbuf->num_cliprects = ignore_cliprects ? 0 : intel->numClipRects;
+ execbuf->DR1 = 0;
+ execbuf->DR4 = ((((GLuint) intel->drawX) & 0xffff) |
+ (((GLuint) intel->drawY) << 16));
do {
ret = drmCommandWriteRead(intel->driFd, DRM_I915_EXECBUFFER, &execbuf,
@@ -191,17 +188,6 @@ intel_exec_ioctl(struct intel_context *intel,
exit(1);
}
- if (execbuf.fence_arg.error != 0) {
-
- /*
- * Fence creation has failed, but the GPU has been
- * idled by the kernel. Safe to continue.
- */
-
- *fence = NULL;
- return;
- }
-
fo = intel_ttm_fence_create_from_arg(intel->bufmgr, "fence buffers",
&execbuf.fence_arg);
if (!fo) {
diff --git a/src/mesa/drivers/dri/intel/intel_ioctl.h b/src/mesa/drivers/dri/intel/intel_ioctl.h
index 8674aef723..7691a27f92 100644
--- a/src/mesa/drivers/dri/intel/intel_ioctl.h
+++ b/src/mesa/drivers/dri/intel/intel_ioctl.h
@@ -41,6 +41,7 @@ void intel_batch_ioctl( struct intel_context *intel,
void intel_exec_ioctl(struct intel_context *intel,
GLuint used,
GLboolean ignore_cliprects, GLboolean allow_unlock,
- void *start, GLuint count, dri_fence **fence);
+ struct drm_i915_gem_execbuffer *execbuf,
+ dri_fence **fence);
#endif
--
cgit v1.2.3
From eb10cdc838fc31ea2cf59f556f6f7d8b072f5bae Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 2 May 2008 14:11:19 -0700
Subject: [intel] Fix build for GEM. TTM is now disabled, and fencing is gone.
Fencing was used in two places: ensuring that we didn't get too many frames
ahead of ourselves, and glFinish. glFinish will be satisfied by waiting on
buffers like we would do for CPU access on them. The "don't get too far ahead"
is now the responsibility of the execution manager (kernel).
---
src/mesa/drivers/dri/common/dri_bufmgr.c | 25 +-------
src/mesa/drivers/dri/common/dri_bufmgr.h | 41 ++-----------
src/mesa/drivers/dri/common/dri_bufmgr_fake.c | 79 ++------------------------
src/mesa/drivers/dri/i915/Makefile | 2 +-
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 28 +++------
src/mesa/drivers/dri/intel/intel_batchbuffer.h | 3 -
src/mesa/drivers/dri/intel/intel_blit.c | 13 -----
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 69 +---------------------
src/mesa/drivers/dri/intel/intel_bufmgr_gem.h | 7 +--
src/mesa/drivers/dri/intel/intel_context.c | 56 +++++++-----------
src/mesa/drivers/dri/intel/intel_context.h | 3 -
src/mesa/drivers/dri/intel/intel_ioctl.c | 19 +------
src/mesa/drivers/dri/intel/intel_ioctl.h | 3 +-
src/mesa/drivers/dri/intel/intel_regions.c | 6 +-
src/mesa/drivers/dri/intel/intel_screen.c | 2 +-
15 files changed, 55 insertions(+), 301 deletions(-)
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.c b/src/mesa/drivers/dri/common/dri_bufmgr.c
index 70ae091499..69868b6665 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr.c
+++ b/src/mesa/drivers/dri/common/dri_bufmgr.c
@@ -90,27 +90,6 @@ dri_bo_unmap(dri_bo *buf)
return buf->bufmgr->bo_unmap(buf);
}
-void
-dri_fence_wait(dri_fence *fence)
-{
- fence->bufmgr->fence_wait(fence);
-}
-
-void
-dri_fence_reference(dri_fence *fence)
-{
- fence->bufmgr->fence_reference(fence);
-}
-
-void
-dri_fence_unreference(dri_fence *fence)
-{
- if (fence == NULL)
- return;
-
- fence->bufmgr->fence_unreference(fence);
-}
-
void
dri_bo_subdata(dri_bo *bo, unsigned long offset,
unsigned long size, const void *data)
@@ -153,9 +132,9 @@ void *dri_process_relocs(dri_bo *batch_buf)
return batch_buf->bufmgr->process_relocs(batch_buf);
}
-void dri_post_submit(dri_bo *batch_buf, dri_fence **last_fence)
+void dri_post_submit(dri_bo *batch_buf)
{
- batch_buf->bufmgr->post_submit(batch_buf, last_fence);
+ batch_buf->bufmgr->post_submit(batch_buf);
}
void
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.h b/src/mesa/drivers/dri/common/dri_bufmgr.h
index cbfeb9136d..dffeb4c601 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr.h
+++ b/src/mesa/drivers/dri/common/dri_bufmgr.h
@@ -38,7 +38,6 @@
typedef struct _dri_bufmgr dri_bufmgr;
typedef struct _dri_bo dri_bo;
-typedef struct _dri_fence dri_fence;
struct _dri_bo {
/**
@@ -61,18 +60,6 @@ struct _dri_bo {
dri_bufmgr *bufmgr;
};
-struct _dri_fence {
- /**
- * This is an ORed mask of DRM_BO_FLAG_READ, DRM_BO_FLAG_WRITE, and
- * DRM_FLAG_EXE indicating the operations associated with this fence.
- *
- * It is constant for the life of the fence object.
- */
- unsigned int type;
- /** Buffer manager context associated with this fence */
- dri_bufmgr *bufmgr;
-};
-
/**
* Context for a buffer manager instance.
*
@@ -113,28 +100,15 @@ struct _dri_bufmgr {
/**
* Maps the buffer into userspace.
*
- * This function will block waiting for any existing fence on the buffer to
- * clear, first. The resulting mapping is available at buf->virtual.
-\ */
+ * This function will block waiting for any existing execution on the
+ * buffer to complete, first. The resulting mapping is available at
+ * buf->virtual.
+ */
int (*bo_map)(dri_bo *buf, GLboolean write_enable);
/** Reduces the refcount on the userspace mapping of the buffer object. */
int (*bo_unmap)(dri_bo *buf);
- /** Takes a reference on a fence object */
- void (*fence_reference)(dri_fence *fence);
-
- /**
- * Releases a reference on a fence object, freeing the data if
- * rerefences remain.
- */
- void (*fence_unreference)(dri_fence *fence);
-
- /**
- * Blocks until the given fence is signaled.
- */
- void (*fence_wait)(dri_fence *fence);
-
/**
* Tears down the buffer manager instance.
*/
@@ -179,7 +153,7 @@ struct _dri_bufmgr {
*/
void *(*process_relocs)(dri_bo *batch_buf);
- void (*post_submit)(dri_bo *batch_buf, dri_fence **fence);
+ void (*post_submit)(dri_bo *batch_buf);
int (*check_aperture_space)(dri_bo *bo);
GLboolean debug; /**< Enables verbose debugging printouts */
@@ -194,9 +168,6 @@ void dri_bo_reference(dri_bo *bo);
void dri_bo_unreference(dri_bo *bo);
int dri_bo_map(dri_bo *buf, GLboolean write_enable);
int dri_bo_unmap(dri_bo *buf);
-void dri_fence_wait(dri_fence *fence);
-void dri_fence_reference(dri_fence *fence);
-void dri_fence_unreference(dri_fence *fence);
void dri_bo_subdata(dri_bo *bo, unsigned long offset,
unsigned long size, const void *data);
@@ -221,7 +192,7 @@ int dri_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
GLuint offset, dri_bo *target_buf);
void *dri_process_relocs(dri_bo *batch_buf);
void dri_post_process_relocs(dri_bo *batch_buf);
-void dri_post_submit(dri_bo *batch_buf, dri_fence **last_fence);
+void dri_post_submit(dri_bo *batch_buf);
int dri_bufmgr_check_aperture_space(dri_bo *bo);
#endif
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr_fake.c b/src/mesa/drivers/dri/common/dri_bufmgr_fake.c
index 9dd06b07eb..fc52674839 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr_fake.c
+++ b/src/mesa/drivers/dri/common/dri_bufmgr_fake.c
@@ -170,15 +170,6 @@ typedef struct _dri_bo_fake {
void *invalidate_ptr;
} dri_bo_fake;
-typedef struct _dri_fence_fake {
- dri_fence fence;
-
- const char *name;
- unsigned int refcount;
- unsigned int fence_cookie;
- GLboolean flushed;
-} dri_fence_fake;
-
static int clear_fenced(dri_bufmgr_fake *bufmgr_fake,
unsigned int fence_cookie);
@@ -898,63 +889,16 @@ dri_fake_bo_validate(dri_bo *bo, uint64_t flags)
return 0;
}
-static dri_fence *
-dri_fake_fence_validated(dri_bufmgr *bufmgr, const char *name,
- GLboolean flushed)
+static void
+dri_fake_fence_validated(dri_bufmgr *bufmgr)
{
- dri_fence_fake *fence_fake;
dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
unsigned int cookie;
- fence_fake = malloc(sizeof(*fence_fake));
- if (!fence_fake)
- return NULL;
-
- fence_fake->refcount = 1;
- fence_fake->name = name;
- fence_fake->flushed = flushed;
- fence_fake->fence.bufmgr = bufmgr;
-
cookie = _fence_emit_internal(bufmgr_fake);
- fence_fake->fence_cookie = cookie;
fence_blocks(bufmgr_fake, cookie);
- DBG("drm_fence_validated: 0x%08x cookie\n", fence_fake->fence_cookie);
-
- return &fence_fake->fence;
-}
-
-static void
-dri_fake_fence_reference(dri_fence *fence)
-{
- dri_fence_fake *fence_fake = (dri_fence_fake *)fence;
-
- ++fence_fake->refcount;
-}
-
-static void
-dri_fake_fence_unreference(dri_fence *fence)
-{
- dri_fence_fake *fence_fake = (dri_fence_fake *)fence;
-
- if (!fence)
- return;
-
- if (--fence_fake->refcount == 0) {
- free(fence);
- return;
- }
-}
-
-static void
-dri_fake_fence_wait(dri_fence *fence)
-{
- dri_fence_fake *fence_fake = (dri_fence_fake *)fence;
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)fence->bufmgr;
-
- DBG("drm_fence_wait: 0x%08x cookie\n", fence_fake->fence_cookie);
-
- _fence_wait_internal(bufmgr_fake, fence_fake->fence_cookie);
+ DBG("drm_fence_validated: 0x%08x cookie\n", cookie);
}
static void
@@ -1156,19 +1100,9 @@ dri_bo_fake_post_submit(dri_bo *bo)
static void
-dri_fake_post_submit(dri_bo *batch_buf, dri_fence **last_fence)
+dri_fake_post_submit(dri_bo *batch_buf)
{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)batch_buf->bufmgr;
- dri_fence *fo;
-
- fo = dri_fake_fence_validated(batch_buf->bufmgr, "Batch fence", GL_TRUE);
-
- if (bufmgr_fake->performed_rendering) {
- dri_fence_unreference(*last_fence);
- *last_fence = fo;
- } else {
- dri_fence_unreference(fo);
- }
+ dri_fake_fence_validated(batch_buf->bufmgr);
dri_bo_fake_post_submit(batch_buf);
}
@@ -1224,9 +1158,6 @@ dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual,
bufmgr_fake->bufmgr.bo_unreference = dri_fake_bo_unreference;
bufmgr_fake->bufmgr.bo_map = dri_fake_bo_map;
bufmgr_fake->bufmgr.bo_unmap = dri_fake_bo_unmap;
- bufmgr_fake->bufmgr.fence_wait = dri_fake_fence_wait;
- bufmgr_fake->bufmgr.fence_reference = dri_fake_fence_reference;
- bufmgr_fake->bufmgr.fence_unreference = dri_fake_fence_unreference;
bufmgr_fake->bufmgr.destroy = dri_fake_destroy;
bufmgr_fake->bufmgr.emit_reloc = dri_fake_emit_reloc;
bufmgr_fake->bufmgr.process_relocs = dri_fake_process_relocs;
diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index 7ef055ccad..ed23410697 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -52,7 +52,7 @@ DRIVER_SOURCES = \
intel_tris.c \
intel_fbo.c \
intel_depthstencil.c \
- intel_bufmgr_ttm.c
+ intel_bufmgr_gem.c
C_SOURCES = \
$(COMMON_SOURCES) \
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index c5b0f531d4..683d06a552 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -99,7 +99,6 @@ intel_batchbuffer_alloc(struct intel_context *intel)
struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1);
batch->intel = intel;
- batch->last_fence = NULL;
intel_batchbuffer_reset(batch);
return batch;
@@ -108,11 +107,6 @@ intel_batchbuffer_alloc(struct intel_context *intel)
void
intel_batchbuffer_free(struct intel_batchbuffer *batch)
{
- if (batch->last_fence) {
- dri_fence_wait(batch->last_fence);
- dri_fence_unreference(batch->last_fence);
- batch->last_fence = NULL;
- }
if (batch->map) {
dri_bo_unmap(batch->buf);
batch->map = NULL;
@@ -152,7 +146,7 @@ do_flush_locked(struct intel_batchbuffer *batch,
used,
batch->cliprect_mode != LOOP_CLIPRECTS,
allow_unlock,
- execbuf, &batch->last_fence);
+ execbuf);
} else {
dri_process_relocs(batch->buf);
intel_batch_ioctl(batch->intel,
@@ -162,8 +156,8 @@ do_flush_locked(struct intel_batchbuffer *batch,
allow_unlock);
}
}
-
- dri_post_submit(batch->buf, &batch->last_fence);
+
+ dri_post_submit(batch->buf);
if (intel->numClipRects == 0 &&
batch->cliprect_mode == LOOP_CLIPRECTS) {
@@ -243,9 +237,13 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
UNLOCK_HARDWARE(intel);
if (INTEL_DEBUG & DEBUG_SYNC) {
+ int irq;
+
fprintf(stderr, "waiting for idle\n");
- if (batch->last_fence != NULL)
- dri_fence_wait(batch->last_fence);
+ LOCK_HARDWARE(intel);
+ irq = intelEmitIrqLocked(intel);
+ UNLOCK_HARDWARE(intel);
+ intelWaitIrq(intel, irq);
}
/* Reset the buffer:
@@ -253,14 +251,6 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
intel_batchbuffer_reset(batch);
}
-void
-intel_batchbuffer_finish(struct intel_batchbuffer *batch)
-{
- intel_batchbuffer_flush(batch);
- if (batch->last_fence != NULL)
- dri_fence_wait(batch->last_fence);
-}
-
/* This is the only way buffers get added to the validate list.
*/
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
index 2d636df2ce..feddfb46df 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
@@ -40,7 +40,6 @@ struct intel_batchbuffer
struct intel_context *intel;
dri_bo *buf;
- dri_fence *last_fence;
GLubyte *map;
GLubyte *ptr;
@@ -58,8 +57,6 @@ struct intel_batchbuffer *intel_batchbuffer_alloc(struct intel_context
void intel_batchbuffer_free(struct intel_batchbuffer *batch);
-void intel_batchbuffer_finish(struct intel_batchbuffer *batch);
-
void _intel_batchbuffer_flush(struct intel_batchbuffer *batch,
const char *file, int line);
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 4890826a19..b7d36d8cd6 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -66,14 +66,6 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
intelScreen = intel->intelScreen;
- if (intel->last_swap_fence) {
- dri_fence_wait(intel->last_swap_fence);
- dri_fence_unreference(intel->last_swap_fence);
- intel->last_swap_fence = NULL;
- }
- intel->last_swap_fence = intel->first_swap_fence;
- intel->first_swap_fence = NULL;
-
/* The LOCK_HARDWARE is required for the cliprects. Buffer offsets
* should work regardless.
*/
@@ -163,12 +155,7 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
ADVANCE_BATCH();
}
- if (intel->first_swap_fence)
- dri_fence_unreference(intel->first_swap_fence);
intel_batchbuffer_flush(intel->batch);
- intel->first_swap_fence = intel->batch->last_fence;
- if (intel->first_swap_fence)
- dri_fence_reference(intel->first_swap_fence);
}
UNLOCK_HARDWARE(intel);
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index 2d8dced214..07f782ca3a 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -127,15 +127,6 @@ typedef struct _dri_bo_gem {
void *virtual;
} dri_bo_gem;
-typedef struct _dri_fence_gem
-{
- dri_fence fence;
-
- int refcount;
- const char *name;
- drmFence drm_fence;
-} dri_fence_gem;
-
static int
logbase2(int n)
{
@@ -526,58 +517,6 @@ dri_gem_bo_unmap(dri_bo *bo)
return 0;
}
-static void
-dri_gem_fence_reference(dri_fence *fence)
-{
- dri_fence_gem *fence_gem = (dri_fence_gem *)fence;
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)fence->bufmgr;
-
- ++fence_gem->refcount;
- DBG("fence_reference: %p (%s)\n", &fence_gem->fence, fence_gem->name);
-}
-
-static void
-dri_gem_fence_unreference(dri_fence *fence)
-{
- dri_fence_gem *fence_gem = (dri_fence_gem *)fence;
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)fence->bufmgr;
-
- if (!fence)
- return;
-
- DBG("fence_unreference: %p (%s)\n", &fence_gem->fence, fence_gem->name);
-
- if (--fence_gem->refcount == 0) {
- int ret;
-
- ret = drmFenceUnreference(bufmgr_gem->fd, &fence_gem->drm_fence);
- if (ret != 0) {
- fprintf(stderr, "drmFenceUnreference failed (%s): %s\n",
- fence_gem->name, strerror(-ret));
- }
-
- free(fence);
- return;
- }
-}
-
-static void
-dri_gem_fence_wait(dri_fence *fence)
-{
- dri_fence_gem *fence_gem = (dri_fence_gem *)fence;
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)fence->bufmgr;
- int ret;
-
- ret = drmFenceWait(bufmgr_gem->fd, DRM_FENCE_FLAG_WAIT_LAZY, &fence_gem->drm_fence, 0);
- if (ret != 0) {
- fprintf(stderr, "%s:%d: Error waiting for fence %s: %s.\n",
- __FILE__, __LINE__, fence_gem->name, strerror(-ret));
- abort();
- }
-
- DBG("fence_wait: %p (%s)\n", &fence_gem->fence, fence_gem->name);
-}
-
static void
dri_bufmgr_gem_destroy(dri_bufmgr *bufmgr)
{
@@ -717,7 +656,7 @@ intel_update_buffer_offsets (dri_bufmgr_gem *bufmgr_gem)
}
static void
-dri_gem_post_submit(dri_bo *batch_buf, dri_fence **last_fence)
+dri_gem_post_submit(dri_bo *batch_buf)
{
dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)batch_buf->bufmgr;
int i;
@@ -773,9 +712,6 @@ dri_gem_check_aperture_space(dri_bo *bo)
* and manage map buffer objections.
*
* \param fd File descriptor of the opened DRM device.
- * \param fence_type Driver-specific fence type used for fences with no flush.
- * \param fence_type_flush Driver-specific fence type used for fences with a
- * flush.
*/
dri_bufmgr *
intel_bufmgr_gem_init(int fd, int batch_size)
@@ -800,9 +736,6 @@ intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem->bufmgr.bo_unreference = dri_gem_bo_unreference;
bufmgr_gem->bufmgr.bo_map = dri_gem_bo_map;
bufmgr_gem->bufmgr.bo_unmap = dri_gem_bo_unmap;
- bufmgr_gem->bufmgr.fence_reference = dri_gem_fence_reference;
- bufmgr_gem->bufmgr.fence_unreference = dri_gem_fence_unreference;
- bufmgr_gem->bufmgr.fence_wait = dri_gem_fence_wait;
bufmgr_gem->bufmgr.destroy = dri_bufmgr_gem_destroy;
bufmgr_gem->bufmgr.emit_reloc = dri_gem_emit_reloc;
bufmgr_gem->bufmgr.process_relocs = dri_gem_process_reloc;
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.h b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.h
index a28f5ae814..36caeba214 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.h
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.h
@@ -4,13 +4,10 @@
#include "dri_bufmgr.h"
-extern dri_bo *intel_gem_bo_create_from_handle(dri_bufmgr *bufmgr, const char *name,
+extern dri_bo *intel_gem_bo_create_from_handle(dri_bufmgr *bufmgr,
+ const char *name,
unsigned int handle);
-dri_fence *intel_gem_fence_create_from_arg(dri_bufmgr *bufmgr, const char *name,
- drm_fence_arg_t *arg);
-
-
dri_bufmgr *intel_bufmgr_gem_init(int fd, int batch_size);
void
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 47e7d1afc2..4a1e1a9ac0 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -59,7 +59,7 @@
#include "intel_buffer_objects.h"
#include "intel_fbo.h"
#include "intel_decode.h"
-#include "intel_bufmgr_ttm.h"
+#include "intel_bufmgr_gem.h"
#include "drirenderbuffer.h"
#include "vblank.h"
@@ -368,12 +368,16 @@ intelFlush(GLcontext * ctx)
void
intelFinish(GLcontext * ctx)
{
- struct intel_context *intel = intel_context(ctx);
+ struct gl_framebuffer *fb = ctx->DrawBuffer;
+ int i;
+
intelFlush(ctx);
- if (intel->batch->last_fence) {
- dri_fence_wait(intel->batch->last_fence);
- dri_fence_unreference(intel->batch->last_fence);
- intel->batch->last_fence = NULL;
+
+ for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
+ /* XXX: Wait on buffer idle */
+ }
+ if (fb->_DepthBuffer) {
+ /* XXX: Wait on buffer idle */
}
}
@@ -439,28 +443,25 @@ static GLboolean
intel_init_bufmgr(struct intel_context *intel)
{
intelScreenPrivate *intelScreen = intel->intelScreen;
- GLboolean ttm_disable = getenv("INTEL_NO_TTM") != NULL;
- GLboolean ttm_supported;
+ GLboolean gem_disable = getenv("INTEL_NO_GEM") != NULL;
+ GLboolean gem_supported;
- /* If we've got a new enough DDX that's initializing TTM and giving us
+ /* If we've got a new enough DDX that's initializing GEM and giving us
* object handles for the shared buffers, use that.
*/
intel->ttm = GL_FALSE;
if (intel->intelScreen->driScrnPriv->dri2.enabled)
- ttm_supported = GL_TRUE;
+ gem_supported = GL_TRUE;
else if (intel->intelScreen->driScrnPriv->ddx_version.minor >= 9 &&
intel->intelScreen->drmMinor >= 11 &&
intel->intelScreen->front.bo_handle != -1)
- ttm_supported = GL_TRUE;
+ gem_supported = GL_TRUE;
else
- ttm_supported = GL_FALSE;
+ gem_supported = GL_FALSE;
- if (!ttm_disable && ttm_supported) {
+ if (!gem_disable && gem_supported) {
int bo_reuse_mode;
- intel->bufmgr = intel_bufmgr_ttm_init(intel->driFd,
- DRM_FENCE_TYPE_EXE,
- DRM_FENCE_TYPE_EXE |
- DRM_I915_FENCE_TYPE_RW,
+ intel->bufmgr = intel_bufmgr_gem_init(intel->driFd,
BATCH_SZ);
if (intel->bufmgr != NULL)
intel->ttm = GL_TRUE;
@@ -470,16 +471,16 @@ intel_init_bufmgr(struct intel_context *intel)
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
- intel_ttm_enable_bo_reuse(intel->bufmgr);
+ intel_gem_enable_bo_reuse(intel->bufmgr);
break;
}
}
/* Otherwise, use the classic buffer manager. */
if (intel->bufmgr == NULL) {
- if (ttm_disable) {
- fprintf(stderr, "TTM buffer manager disabled. Using classic.\n");
+ if (gem_disable) {
+ fprintf(stderr, "GEM disabled. Using classic.\n");
} else {
- fprintf(stderr, "Failed to initialize TTM buffer manager. "
+ fprintf(stderr, "Failed to initialize GEM. "
"Falling back to classic.\n");
}
@@ -663,8 +664,6 @@ intelInitContext(struct intel_context *intel,
intel_recreate_static_regions(intel);
intel->batch = intel_batchbuffer_alloc(intel);
- intel->last_swap_fence = NULL;
- intel->first_swap_fence = NULL;
intel_bufferobj_init(intel);
intel_fbo_init(intel);
@@ -718,17 +717,6 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv)
intel_batchbuffer_free(intel->batch);
- if (intel->last_swap_fence) {
- dri_fence_wait(intel->last_swap_fence);
- dri_fence_unreference(intel->last_swap_fence);
- intel->last_swap_fence = NULL;
- }
- if (intel->first_swap_fence) {
- dri_fence_wait(intel->first_swap_fence);
- dri_fence_unreference(intel->first_swap_fence);
- intel->first_swap_fence = NULL;
- }
-
if (release_texture_heaps) {
/* This share group is about to go away, free our private
* texture object data.
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 1348b0adcf..35ef22aa27 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -174,9 +174,6 @@ struct intel_context
*/
GLboolean ttm;
- dri_fence *last_swap_fence;
- dri_fence *first_swap_fence;
-
struct intel_batchbuffer *batch;
GLboolean no_batch_wrap;
unsigned batch_id;
diff --git a/src/mesa/drivers/dri/intel/intel_ioctl.c b/src/mesa/drivers/dri/intel/intel_ioctl.c
index f9624a6abe..2f4caf9535 100644
--- a/src/mesa/drivers/dri/intel/intel_ioctl.c
+++ b/src/mesa/drivers/dri/intel/intel_ioctl.c
@@ -43,7 +43,7 @@
#include "drm.h"
#include "i915_drm.h"
-#include "intel_bufmgr_ttm.h"
+#include "intel_bufmgr_gem.h"
#define FILE_DEBUG_FLAG DEBUG_IOCTL
@@ -151,10 +151,8 @@ void
intel_exec_ioctl(struct intel_context *intel,
GLuint used,
GLboolean ignore_cliprects, GLboolean allow_unlock,
- struct drm_i915_gem_execbuffer *execbuf,
- dri_fence **fence)
+ struct drm_i915_gem_execbuffer *execbuf)
{
- dri_fence *fo;
int ret;
assert(intel->locked);
@@ -163,10 +161,6 @@ intel_exec_ioctl(struct intel_context *intel,
if (intel->no_hw)
return;
- if (*fence) {
- dri_fence_unreference(*fence);
- }
-
memset(&execbuf, 0, sizeof(execbuf));
execbuf->batch_start_offset = 0;
@@ -187,13 +181,4 @@ intel_exec_ioctl(struct intel_context *intel,
UNLOCK_HARDWARE(intel);
exit(1);
}
-
- fo = intel_ttm_fence_create_from_arg(intel->bufmgr, "fence buffers",
- &execbuf.fence_arg);
- if (!fo) {
- fprintf(stderr, "failed to fence handle: %08x\n", execbuf.fence_arg.handle);
- UNLOCK_HARDWARE(intel);
- exit(1);
- }
- *fence = fo;
}
diff --git a/src/mesa/drivers/dri/intel/intel_ioctl.h b/src/mesa/drivers/dri/intel/intel_ioctl.h
index 7691a27f92..52b0ab6102 100644
--- a/src/mesa/drivers/dri/intel/intel_ioctl.h
+++ b/src/mesa/drivers/dri/intel/intel_ioctl.h
@@ -41,7 +41,6 @@ void intel_batch_ioctl( struct intel_context *intel,
void intel_exec_ioctl(struct intel_context *intel,
GLuint used,
GLboolean ignore_cliprects, GLboolean allow_unlock,
- struct drm_i915_gem_execbuffer *execbuf,
- dri_fence **fence);
+ struct drm_i915_gem_execbuffer *execbuf);
#endif
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 8bc548913f..7d78e4eca7 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -44,7 +44,7 @@
#include "intel_blit.h"
#include "intel_buffer_objects.h"
#include "dri_bufmgr.h"
-#include "intel_bufmgr_ttm.h"
+#include "intel_bufmgr_gem.h"
#include "intel_batchbuffer.h"
#define FILE_DEBUG_FLAG DEBUG_REGION
@@ -121,7 +121,7 @@ intel_region_alloc_for_handle(struct intel_context *intel,
{
dri_bo *buffer;
- buffer = intel_ttm_bo_create_from_handle(intel->bufmgr, "region", handle);
+ buffer = intel_gem_bo_create_from_handle(intel->bufmgr, "region", handle);
return intel_region_alloc_internal(intel,
cpp, pitch, height, tiled, buffer);
@@ -440,7 +440,7 @@ intel_recreate_static(struct intel_context *intel,
if (intel->ttm) {
assert(region_desc->bo_handle != -1);
- region->buffer = intel_ttm_bo_create_from_handle(intel->bufmgr,
+ region->buffer = intel_gem_bo_create_from_handle(intel->bufmgr,
name,
region_desc->bo_handle);
} else {
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 52e062eece..7e0713c4f4 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -49,7 +49,7 @@
#include "i830_dri.h"
#include "intel_regions.h"
#include "intel_batchbuffer.h"
-#include "intel_bufmgr_ttm.h"
+#include "intel_bufmgr_gem.h"
PUBLIC const char __driConfigOptions[] =
DRI_CONF_BEGIN
--
cgit v1.2.3
From ef33e76cebed39551aabce397d165d3990ba517c Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 2 May 2008 17:00:47 -0700
Subject: Minor fixups to get GEM to the point of execbuf ioctl.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 19 +++++++++++--------
src/mesa/drivers/dri/intel/intel_ioctl.c | 2 --
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index 07f782ca3a..a18ccd1637 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -250,9 +250,9 @@ intel_setup_reloc_list(dri_bo *bo)
}
static dri_bo *
-dri_gem_alloc(dri_bufmgr *bufmgr, const char *name,
- unsigned long size, unsigned int alignment,
- uint64_t location_mask)
+dri_gem_bo_alloc(dri_bufmgr *bufmgr, const char *name,
+ unsigned long size, unsigned int alignment,
+ uint64_t location_mask)
{
dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr;
dri_bo_gem *bo_gem;
@@ -336,9 +336,9 @@ dri_gem_alloc(dri_bufmgr *bufmgr, const char *name,
* working around the X Server not creating buffers and passing handles to us.
*/
static dri_bo *
-dri_gem_alloc_static(dri_bufmgr *bufmgr, const char *name,
- unsigned long offset, unsigned long size, void *virtual,
- uint64_t location_mask)
+dri_gem_bo_alloc_static(dri_bufmgr *bufmgr, const char *name,
+ unsigned long offset, unsigned long size, void *virtual,
+ uint64_t location_mask)
{
return NULL;
}
@@ -475,7 +475,10 @@ dri_gem_bo_map(dri_bo *bo, GLboolean write_enable)
if (bo_gem->virtual == NULL) {
struct drm_gem_mmap mmap_arg;
+ memset(&mmap_arg, 0, sizeof(mmap_arg));
mmap_arg.handle = bo_gem->gem_handle;
+ mmap_arg.offset = 0;
+ mmap_arg.size = bo->size;
ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_MMAP, &mmap_arg);
if (ret != 0) {
fprintf(stderr, "%s:%d: Error mapping buffer %s: %s .\n",
@@ -730,8 +733,8 @@ intel_bufmgr_gem_init(int fd, int batch_size)
*/
bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
- bufmgr_gem->bufmgr.bo_alloc = dri_gem_alloc;
- bufmgr_gem->bufmgr.bo_alloc_static = dri_gem_alloc_static;
+ bufmgr_gem->bufmgr.bo_alloc = dri_gem_bo_alloc;
+ bufmgr_gem->bufmgr.bo_alloc_static = dri_gem_bo_alloc_static;
bufmgr_gem->bufmgr.bo_reference = dri_gem_bo_reference;
bufmgr_gem->bufmgr.bo_unreference = dri_gem_bo_unreference;
bufmgr_gem->bufmgr.bo_map = dri_gem_bo_map;
diff --git a/src/mesa/drivers/dri/intel/intel_ioctl.c b/src/mesa/drivers/dri/intel/intel_ioctl.c
index 2f4caf9535..ec1dec0b1e 100644
--- a/src/mesa/drivers/dri/intel/intel_ioctl.c
+++ b/src/mesa/drivers/dri/intel/intel_ioctl.c
@@ -161,8 +161,6 @@ intel_exec_ioctl(struct intel_context *intel,
if (intel->no_hw)
return;
- memset(&execbuf, 0, sizeof(execbuf));
-
execbuf->batch_start_offset = 0;
execbuf->batch_len = used;
execbuf->cliprects_ptr = (uintptr_t)intel->pClipRects;
--
cgit v1.2.3
From 7349f218b47b21595a13103aaa45ddbfdc14dd13 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 2 May 2008 17:13:45 -0700
Subject: Fix to use GEM execbuf instead of TTM.
---
src/mesa/drivers/dri/intel/intel_ioctl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_ioctl.c b/src/mesa/drivers/dri/intel/intel_ioctl.c
index ec1dec0b1e..b84cb64633 100644
--- a/src/mesa/drivers/dri/intel/intel_ioctl.c
+++ b/src/mesa/drivers/dri/intel/intel_ioctl.c
@@ -170,12 +170,12 @@ intel_exec_ioctl(struct intel_context *intel,
(((GLuint) intel->drawY) << 16));
do {
- ret = drmCommandWriteRead(intel->driFd, DRM_I915_EXECBUFFER, &execbuf,
+ ret = drmCommandWriteRead(intel->driFd, DRM_I915_GEM_EXECBUFFER, &execbuf,
sizeof(execbuf));
} while (ret == -EAGAIN);
if (ret != 0) {
- fprintf(stderr, "DRM_I915_EXECBUFFER: %d\n", -errno);
+ fprintf(stderr, "DRM_I915_GEM_EXECBUFFER: %d\n", -errno);
UNLOCK_HARDWARE(intel);
exit(1);
}
--
cgit v1.2.3
From 3d19a095cda30ac8abdbe26cd3b664a4b97c899b Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 2 May 2008 18:24:13 -0700
Subject: Fix GEM execbuf ioctl argument.
---
src/mesa/drivers/dri/intel/intel_ioctl.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_ioctl.c b/src/mesa/drivers/dri/intel/intel_ioctl.c
index b84cb64633..317ff2c440 100644
--- a/src/mesa/drivers/dri/intel/intel_ioctl.c
+++ b/src/mesa/drivers/dri/intel/intel_ioctl.c
@@ -30,6 +30,8 @@
#include
#include
#include
+#include
+#include
#include "mtypes.h"
#include "context.h"
@@ -170,8 +172,7 @@ intel_exec_ioctl(struct intel_context *intel,
(((GLuint) intel->drawY) << 16));
do {
- ret = drmCommandWriteRead(intel->driFd, DRM_I915_GEM_EXECBUFFER, &execbuf,
- sizeof(execbuf));
+ ret = ioctl(intel->driFd, DRM_IOCTL_I915_GEM_EXECBUFFER, execbuf);
} while (ret == -EAGAIN);
if (ret != 0) {
--
cgit v1.2.3
From 81ec0545c93d57f72cff5099c6a34f04e9257a38 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 2 May 2008 18:25:00 -0700
Subject: Don't forget to set handle of shared buffers.
(And fix a nearby whitespace nit)
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index a18ccd1637..37e75081ec 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -227,6 +227,7 @@ intel_add_validate_buffer(dri_bo *bo)
bufmgr_gem->validate_array[index].buffer_handle = bo_gem->gem_handle;
bufmgr_gem->validate_array[index].relocation_count = bo_gem->reloc_count;
bufmgr_gem->validate_array[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
+ bufmgr_gem->validate_array[index].alignment = 0;
bufmgr_gem->validate_bo[index] = bo;
dri_bo_reference(bo);
bufmgr_gem->validate_count++;
@@ -366,7 +367,7 @@ intel_gem_bo_create_from_handle(dri_bufmgr *bufmgr, const char *name,
open_arg.name = handle;
ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
if (ret != 0) {
- fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
+ fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
name, handle, strerror(-ret));
free(bo_gem);
return NULL;
@@ -378,6 +379,7 @@ intel_gem_bo_create_from_handle(dri_bufmgr *bufmgr, const char *name,
bo_gem->name = name;
bo_gem->refcount = 1;
bo_gem->validate_index = -1;
+ bo_gem->gem_handle = open_arg.handle;
DBG("bo_create_from_handle: %p %08x (%s)\n",
&bo_gem->bo, handle, bo_gem->name);
--
cgit v1.2.3
From 367b1e35dc1dbeda65709b0ab4f7983d0c7a6cc2 Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Mon, 5 May 2008 10:45:30 -0700
Subject: Temporarily disable intel pixel ops on i915 for GEM
Instead of attempting to fix these for GEM, just disable until GEM is
working.
---
src/mesa/drivers/dri/i915/Makefile | 9 ++++++---
src/mesa/drivers/dri/i915/i830_context.c | 2 +-
src/mesa/drivers/dri/i915/i915_context.c | 2 +-
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index ed23410697..67f251a7fa 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -6,6 +6,11 @@ LIBNAME = i915_dri.so
MINIGLX_SOURCES = server/intel_dri.c
+PIXEL_SOURCES = \
+ intel_pixel.c \
+ intel_pixel_read.c \
+ intel_pixel_draw.c
+
DRIVER_SOURCES = \
i830_context.c \
i830_metaops.c \
@@ -27,10 +32,7 @@ DRIVER_SOURCES = \
intel_tex_validate.c \
intel_tex_format.c \
intel_tex.c \
- intel_pixel.c \
intel_pixel_copy.c \
- intel_pixel_read.c \
- intel_pixel_draw.c \
intel_buffers.c \
intel_blit.c \
i915_tex.c \
@@ -68,6 +70,7 @@ DRIVER_DEFINES = -I../intel -I../intel/server -DI915 \
include ../Makefile.template
intel_decode.o: ../intel/intel_decode.c
+
intel_tex_layout.o: ../intel/intel_tex_layout.c
symlinks:
diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c
index 240c57c9ad..166a3bc8e2 100644
--- a/src/mesa/drivers/dri/i915/i830_context.c
+++ b/src/mesa/drivers/dri/i915/i830_context.c
@@ -52,7 +52,7 @@ static void
i830InitDriverFunctions(struct dd_function_table *functions)
{
intelInitDriverFunctions(functions);
- intelInitPixelFuncs(functions);
+// intelInitPixelFuncs(functions);
i830InitStateFuncs(functions);
i830InitTextureFuncs(functions);
}
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index 0161959099..59da40229a 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -94,7 +94,7 @@ static void
i915InitDriverFunctions(struct dd_function_table *functions)
{
intelInitDriverFunctions(functions);
- intelInitPixelFuncs(functions);
+// intelInitPixelFuncs(functions);
i915InitStateFunctions(functions);
i915InitTextureFuncs(functions);
i915InitFragProgFuncs(functions);
--
cgit v1.2.3
From 87ccc03736166db9ef85f3eee3723b82f395d3cf Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Mon, 5 May 2008 10:46:27 -0700
Subject: Add intel_bufmgr_gem.c to i915
---
src/mesa/drivers/dri/i915/intel_bufmgr_gem.c | 1 +
1 file changed, 1 insertion(+)
create mode 120000 src/mesa/drivers/dri/i915/intel_bufmgr_gem.c
diff --git a/src/mesa/drivers/dri/i915/intel_bufmgr_gem.c b/src/mesa/drivers/dri/i915/intel_bufmgr_gem.c
new file mode 120000
index 0000000000..dee0daf9c0
--- /dev/null
+++ b/src/mesa/drivers/dri/i915/intel_bufmgr_gem.c
@@ -0,0 +1 @@
+../intel/intel_bufmgr_gem.c
\ No newline at end of file
--
cgit v1.2.3
From 1f810b85b1e9393c8e606d2f28250cbb19cf916b Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Mon, 5 May 2008 13:40:50 -0700
Subject: Make intel_{batch,exec}_ioctl return an error code so we can recover
better.
---
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 25 +++++++++++++++----------
src/mesa/drivers/dri/intel/intel_ioctl.c | 18 ++++++++++--------
src/mesa/drivers/dri/intel/intel_ioctl.h | 16 ++++++++--------
3 files changed, 33 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 683d06a552..a95abd9ec9 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -125,6 +125,7 @@ do_flush_locked(struct intel_batchbuffer *batch,
GLuint used, GLboolean allow_unlock)
{
struct intel_context *intel = batch->intel;
+ int ret = 0;
dri_bo_unmap(batch->buf);
@@ -142,18 +143,18 @@ do_flush_locked(struct intel_batchbuffer *batch,
struct drm_i915_gem_execbuffer *execbuf;
execbuf = dri_process_relocs(batch->buf);
- intel_exec_ioctl(batch->intel,
- used,
- batch->cliprect_mode != LOOP_CLIPRECTS,
- allow_unlock,
- execbuf);
+ ret = intel_exec_ioctl(batch->intel,
+ used,
+ batch->cliprect_mode != LOOP_CLIPRECTS,
+ allow_unlock,
+ execbuf);
} else {
dri_process_relocs(batch->buf);
- intel_batch_ioctl(batch->intel,
- batch->buf->offset,
- used,
- batch->cliprect_mode != LOOP_CLIPRECTS,
- allow_unlock);
+ ret = intel_batch_ioctl(batch->intel,
+ batch->buf->offset,
+ used,
+ batch->cliprect_mode != LOOP_CLIPRECTS,
+ allow_unlock);
}
}
@@ -182,6 +183,10 @@ do_flush_locked(struct intel_batchbuffer *batch,
intel->vtbl.debug_batch(intel);
}
+ if (ret != 0) {
+ UNLOCK_HARDWARE(intel);
+ exit(1);
+ }
intel->vtbl.new_batch(intel);
}
diff --git a/src/mesa/drivers/dri/intel/intel_ioctl.c b/src/mesa/drivers/dri/intel/intel_ioctl.c
index 317ff2c440..591548ae85 100644
--- a/src/mesa/drivers/dri/intel/intel_ioctl.c
+++ b/src/mesa/drivers/dri/intel/intel_ioctl.c
@@ -106,7 +106,7 @@ intelWaitIrq(struct intel_context *intel, int seq)
}
-void
+int
intel_batch_ioctl(struct intel_context *intel,
GLuint start_offset,
GLuint used,
@@ -115,7 +115,7 @@ intel_batch_ioctl(struct intel_context *intel,
struct drm_i915_batchbuffer batch;
if (intel->no_hw)
- return;
+ return 0;
assert(intel->locked);
assert(used);
@@ -144,12 +144,13 @@ intel_batch_ioctl(struct intel_context *intel,
if (drmCommandWrite(intel->driFd, DRM_I915_BATCHBUFFER, &batch,
sizeof(batch))) {
fprintf(stderr, "DRM_I915_BATCHBUFFER: %d\n", -errno);
- UNLOCK_HARDWARE(intel);
- exit(1);
+ return -errno;
}
+
+ return 0;
}
-void
+int
intel_exec_ioctl(struct intel_context *intel,
GLuint used,
GLboolean ignore_cliprects, GLboolean allow_unlock,
@@ -161,7 +162,7 @@ intel_exec_ioctl(struct intel_context *intel,
assert(used);
if (intel->no_hw)
- return;
+ return 0;
execbuf->batch_start_offset = 0;
execbuf->batch_len = used;
@@ -177,7 +178,8 @@ intel_exec_ioctl(struct intel_context *intel,
if (ret != 0) {
fprintf(stderr, "DRM_I915_GEM_EXECBUFFER: %d\n", -errno);
- UNLOCK_HARDWARE(intel);
- exit(1);
+ return -errno;
}
+
+ return 0;
}
diff --git a/src/mesa/drivers/dri/intel/intel_ioctl.h b/src/mesa/drivers/dri/intel/intel_ioctl.h
index 52b0ab6102..526e38358c 100644
--- a/src/mesa/drivers/dri/intel/intel_ioctl.h
+++ b/src/mesa/drivers/dri/intel/intel_ioctl.h
@@ -33,14 +33,14 @@
void intelWaitIrq( struct intel_context *intel, int seq );
int intelEmitIrqLocked( struct intel_context *intel );
-void intel_batch_ioctl( struct intel_context *intel,
- GLuint start_offset,
- GLuint used,
- GLboolean ignore_cliprects,
- GLboolean allow_unlock );
-void intel_exec_ioctl(struct intel_context *intel,
+int intel_batch_ioctl(struct intel_context *intel,
+ GLuint start_offset,
GLuint used,
- GLboolean ignore_cliprects, GLboolean allow_unlock,
- struct drm_i915_gem_execbuffer *execbuf);
+ GLboolean ignore_cliprects,
+ GLboolean allow_unlock);
+int intel_exec_ioctl(struct intel_context *intel,
+ GLuint used,
+ GLboolean ignore_cliprects, GLboolean allow_unlock,
+ struct drm_i915_gem_execbuffer *execbuf);
#endif
--
cgit v1.2.3
From 5290ec4756eb33ec27e06bb68d64c33472276ac3 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Mon, 5 May 2008 13:45:03 -0700
Subject: Initialize bufmgr_gem->validate_array[i].offset.
This is just cosmetic, to produce less scary values when the ioctl fails and
doesn't return values there.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index 37e75081ec..0b136b19da 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -228,6 +228,7 @@ intel_add_validate_buffer(dri_bo *bo)
bufmgr_gem->validate_array[index].relocation_count = bo_gem->reloc_count;
bufmgr_gem->validate_array[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
bufmgr_gem->validate_array[index].alignment = 0;
+ bufmgr_gem->validate_array[index].buffer_offset = 0;
bufmgr_gem->validate_bo[index] = bo;
dri_bo_reference(bo);
bufmgr_gem->validate_count++;
--
cgit v1.2.3
From be59d52ca0c0a5b93963297d596972fccb792b69 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Mon, 5 May 2008 14:15:40 -0700
Subject: Print GEM handles instead of BO pointers in debugging.
small integers are much prettier, and let me correlate to DRM debug output.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 33 +++++++++++++++------------
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index 0b136b19da..fd161cbeb8 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -171,7 +171,7 @@ static void dri_gem_dump_validation_list(dri_bufmgr_gem *bufmgr_gem)
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
if (bo_gem->relocs == NULL) {
- DBG("%2d: %s\n", i, bo_gem->name);
+ DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle, bo_gem->name);
continue;
}
@@ -179,9 +179,9 @@ static void dri_gem_dump_validation_list(dri_bufmgr_gem *bufmgr_gem)
dri_bo *target_bo = bo_gem->reloc_target_bo[j];
dri_bo_gem *target_gem = (dri_bo_gem *)target_bo;
- DBG("%2d: %s@0x%08llx -> %s@0x%08lx + 0x%08x\n",
+ DBG("%2d: %d (%s)@0x%08llx -> %s@0x%08lx + 0x%08x\n",
i,
- bo_gem->name, bo_gem->relocs[j].offset,
+ bo_gem->gem_handle, bo_gem->name, bo_gem->relocs[j].offset,
target_gem->name, target_bo->offset,
bo_gem->relocs[j].delta);
}
@@ -328,7 +328,8 @@ dri_gem_bo_alloc(dri_bufmgr *bufmgr, const char *name,
bo_gem->refcount = 1;
bo_gem->validate_index = -1;
- DBG("bo_create: %p (%s) %ldb\n", &bo_gem->bo, bo_gem->name, size);
+ DBG("bo_create: buf %d (%s) %ldb\n",
+ bo_gem->gem_handle, bo_gem->name, size);
return &bo_gem->bo;
}
@@ -382,8 +383,7 @@ intel_gem_bo_create_from_handle(dri_bufmgr *bufmgr, const char *name,
bo_gem->validate_index = -1;
bo_gem->gem_handle = open_arg.handle;
- DBG("bo_create_from_handle: %p %08x (%s)\n",
- &bo_gem->bo, handle, bo_gem->name);
+ DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
return &bo_gem->bo;
}
@@ -444,12 +444,14 @@ dri_gem_bo_unreference(dri_bo *bo)
unref.handle = bo_gem->gem_handle;
ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_UNREFERENCE, &unref);
if (ret != 0) {
- fprintf(stderr, "DRM_IOCTL_GEM_UNREFERENCE failed (%s): %s\n",
- bo_gem->name, strerror(-ret));
+ fprintf(stderr,
+ "DRM_IOCTL_GEM_UNREFERENCE %d failed (%s): %s\n",
+ bo_gem->gem_handle, bo_gem->name, strerror(-ret));
}
}
- DBG("bo_unreference final: %p (%s)\n", &bo_gem->bo, bo_gem->name);
+ DBG("bo_unreference final: %d (%s)\n",
+ bo_gem->gem_handle, bo_gem->name);
free(bo);
return;
@@ -473,7 +475,7 @@ dri_gem_bo_map(dri_bo *bo, GLboolean write_enable)
assert(bo->virtual == NULL);
- DBG("bo_map: %p (%s)\n", &bo_gem->bo, bo_gem->name);
+ DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
if (bo_gem->virtual == NULL) {
struct drm_gem_mmap mmap_arg;
@@ -484,8 +486,9 @@ dri_gem_bo_map(dri_bo *bo, GLboolean write_enable)
mmap_arg.size = bo->size;
ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_MMAP, &mmap_arg);
if (ret != 0) {
- fprintf(stderr, "%s:%d: Error mapping buffer %s: %s .\n",
- __FILE__, __LINE__, bo_gem->name, strerror(-ret));
+ fprintf(stderr, "%s:%d: Error mapping buffer %d (%s): %s .\n",
+ __FILE__, __LINE__,
+ bo_gem->gem_handle, bo_gem->name, strerror(-ret));
}
bo_gem->virtual = (void *)(uintptr_t)mmap_arg.addr_ptr;
}
@@ -514,7 +517,7 @@ dri_gem_bo_unmap(dri_bo *bo)
assert(bo->virtual != NULL);
- DBG("bo_unmap: %p (%s)\n", &bo_gem->bo, bo_gem->name);
+ DBG("bo_unmap: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
munmap(bo_gem->virtual, bo->size);
bo_gem->virtual = NULL;
@@ -653,8 +656,8 @@ intel_update_buffer_offsets (dri_bufmgr_gem *bufmgr_gem)
/* Update the buffer offset */
if (bufmgr_gem->validate_array[i].buffer_offset != bo->offset) {
- DBG("BO %s migrated: 0x%08lx -> 0x%08llx\n",
- bo_gem->name, bo->offset,
+ DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
+ bo_gem->gem_handle, bo_gem->name, bo->offset,
bufmgr_gem->validate_array[i].buffer_offset);
bo->offset = bufmgr_gem->validate_array[i].buffer_offset;
}
--
cgit v1.2.3
From 01d1a292bf53ab949cf2075f18986b58fa468a61 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Mon, 5 May 2008 14:20:18 -0700
Subject: GEM: Set validate index to keep the same buffer from being duped on
the list.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index fd161cbeb8..ca0a92cfe8 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -223,6 +223,7 @@ intel_add_validate_buffer(dri_bo *bo)
}
index = bufmgr_gem->validate_count;
+ bo_gem->validate_index = index;
/* Fill in array entry */
bufmgr_gem->validate_array[index].buffer_handle = bo_gem->gem_handle;
bufmgr_gem->validate_array[index].relocation_count = bo_gem->reloc_count;
--
cgit v1.2.3
From 1decab06d15f0dead0a544dbed2f10041caac844 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Mon, 5 May 2008 15:44:49 -0700
Subject: GEM: Include target buffer handle in relocation debug.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index ca0a92cfe8..6f0ecfbdb8 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -179,10 +179,10 @@ static void dri_gem_dump_validation_list(dri_bufmgr_gem *bufmgr_gem)
dri_bo *target_bo = bo_gem->reloc_target_bo[j];
dri_bo_gem *target_gem = (dri_bo_gem *)target_bo;
- DBG("%2d: %d (%s)@0x%08llx -> %s@0x%08lx + 0x%08x\n",
+ DBG("%2d: %d (%s)@0x%08llx -> %d (%s)@0x%08lx + 0x%08x\n",
i,
bo_gem->gem_handle, bo_gem->name, bo_gem->relocs[j].offset,
- target_gem->name, target_bo->offset,
+ target_gem->gem_handle, target_gem->name, target_bo->offset,
bo_gem->relocs[j].delta);
}
}
--
cgit v1.2.3
From e9a2a67745d46509928263f0556f5c0a4211b94f Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Mon, 5 May 2008 15:45:15 -0700
Subject: GEM: Allocate the right number of relocs, avoiding heap smashing.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index 6f0ecfbdb8..e4e8481b96 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -247,7 +247,7 @@ intel_setup_reloc_list(dri_bo *bo)
bo_gem->relocs = calloc(bufmgr_gem->max_relocs,
sizeof(struct drm_i915_gem_relocation_entry));
- bo_gem->reloc_target_bo = calloc(1, sizeof(dri_bo *));
+ bo_gem->reloc_target_bo = calloc(bufmgr_gem->max_relocs, sizeof(dri_bo *));
return 0;
}
--
cgit v1.2.3
From df4b49c2cedde60c02f869977ee426f280b2985b Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Mon, 5 May 2008 22:08:05 -0700
Subject: Dump buffer tiled status from intelPrintSAREA
---
src/mesa/drivers/dri/intel/intel_screen.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 7e0713c4f4..356e50e726 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -221,16 +221,16 @@ intelPrintSAREA(const struct drm_i915_sarea * sarea)
sarea->height);
fprintf(stderr, "SAREA: pitch: %d\n", sarea->pitch);
fprintf(stderr,
- "SAREA: front offset: 0x%08x size: 0x%x handle: 0x%x\n",
+ "SAREA: front offset: 0x%08x size: 0x%x handle: 0x%x tiled: %d\n",
sarea->front_offset, sarea->front_size,
- (unsigned) sarea->front_handle);
+ (unsigned) sarea->front_handle, sarea->front_tiled);
fprintf(stderr,
- "SAREA: back offset: 0x%08x size: 0x%x handle: 0x%x\n",
+ "SAREA: back offset: 0x%08x size: 0x%x handle: 0x%x tiled: %d\n",
sarea->back_offset, sarea->back_size,
- (unsigned) sarea->back_handle);
- fprintf(stderr, "SAREA: depth offset: 0x%08x size: 0x%x handle: 0x%x\n",
+ (unsigned) sarea->back_handle, sarea->back_tiled);
+ fprintf(stderr, "SAREA: depth offset: 0x%08x size: 0x%x handle: 0x%x tiled: %d\n",
sarea->depth_offset, sarea->depth_size,
- (unsigned) sarea->depth_handle);
+ (unsigned) sarea->depth_handle, sarea->depth_tiled);
fprintf(stderr, "SAREA: tex offset: 0x%08x size: 0x%x handle: 0x%x\n",
sarea->tex_offset, sarea->tex_size, (unsigned) sarea->tex_handle);
}
--
cgit v1.2.3
From 537bbe6dec780f6f85838fe7e6036579c509f8a6 Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Tue, 6 May 2008 10:51:08 -0700
Subject: [intel-GEM] Add tiling support to swrast.
Accessing tiled surfaces without using the fence registers requires that
software deal with the address swizzling itself.
---
src/mesa/drivers/dri/intel/intel_context.c | 3 +
src/mesa/drivers/dri/intel/intel_fbo.c | 16 +-
src/mesa/drivers/dri/intel/intel_fbo.h | 3 +-
src/mesa/drivers/dri/intel/intel_screen.c | 18 +-
src/mesa/drivers/dri/intel/intel_screen.h | 2 +
src/mesa/drivers/dri/intel/intel_span.c | 327 +++++++++++++++++++++++++++--
src/mesa/drivers/dri/intel/intel_span.h | 6 +-
7 files changed, 350 insertions(+), 25 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 4a1e1a9ac0..d258e669c0 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -498,6 +498,9 @@ intel_init_bufmgr(struct intel_context *intel)
intel);
}
+ /* XXX bufmgr should be per-screen, not per-context */
+ intelScreen->ttm = intel->ttm;
+
return GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index b3f6610546..bc0b579429 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -295,7 +295,8 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
rb->Height = height;
/* This sets the Get/PutRow/Value functions */
- intel_set_span_functions(&irb->Base);
+ /* XXX can we choose a different tile here? */
+ intel_set_span_functions(&irb->Base, INTEL_TILE_NONE);
return GL_TRUE;
}
@@ -375,7 +376,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb,
* not a user-created renderbuffer.
*/
struct intel_renderbuffer *
-intel_create_renderbuffer(GLenum intFormat)
+intel_create_renderbuffer(GLenum intFormat, int tiling)
{
GET_CURRENT_CONTEXT(ctx);
@@ -442,12 +443,14 @@ intel_create_renderbuffer(GLenum intFormat)
irb->Base.InternalFormat = intFormat;
+ irb->tiling = tiling;
+
/* intel-specific methods */
irb->Base.Delete = intel_delete_renderbuffer;
irb->Base.AllocStorage = intel_alloc_window_storage;
irb->Base.GetPointer = intel_get_pointer;
/* This sets the Get/PutRow/Value functions */
- intel_set_span_functions(&irb->Base);
+ intel_set_span_functions(&irb->Base, tiling);
return irb;
}
@@ -519,7 +522,7 @@ intel_framebuffer_renderbuffer(GLcontext * ctx,
static GLboolean
intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb,
- struct gl_texture_image *texImage)
+ struct gl_texture_image *texImage)
{
if (texImage->TexFormat == &_mesa_texformat_argb8888) {
irb->Base._ActualFormat = GL_RGBA8;
@@ -558,7 +561,7 @@ intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb,
irb->Base.Delete = intel_delete_renderbuffer;
irb->Base.AllocStorage = intel_nop_alloc_storage;
- intel_set_span_functions(&irb->Base);
+ intel_set_span_functions(&irb->Base, irb->tiling);
irb->RenderToTexture = GL_TRUE;
@@ -586,6 +589,9 @@ intel_wrap_texture(GLcontext * ctx, struct gl_texture_image *texImage)
_mesa_init_renderbuffer(&irb->Base, name);
irb->Base.ClassID = INTEL_RB_CLASS;
+ /* XXX can we fix this? */
+ irb->tiling = INTEL_TILE_NONE;
+
if (!intel_update_wrapper(ctx, irb, texImage)) {
_mesa_free(irb);
return NULL;
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index c90c84b48c..9e085a1992 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -72,6 +72,7 @@ struct intel_renderbuffer
struct intel_region *region;
void *pfMap; /* possibly paged flipped map pointer */
GLuint pfPitch; /* possibly paged flipped pitch */
+ int tiling;
GLboolean RenderToTexture; /* RTT? */
GLuint PairedDepth; /**< only used if this is a depth renderbuffer */
@@ -90,7 +91,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *irb,
struct intel_region *region);
extern struct intel_renderbuffer *
-intel_create_renderbuffer(GLenum intFormat);
+intel_create_renderbuffer(GLenum intFormat, int tiling);
extern void intel_fbo_init(struct intel_context *intel);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 356e50e726..a243324a39 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -524,20 +524,23 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
/* setup the hardware-based renderbuffers */
{
- intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat);
+ intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat,
+ screen->ttm ? screen->front.tiled : INTEL_TILE_NONE);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT,
&intel_fb->color_rb[0]->Base);
}
if (mesaVis->doubleBufferMode) {
- intel_fb->color_rb[1] = intel_create_renderbuffer(rgbFormat);
+ intel_fb->color_rb[1] = intel_create_renderbuffer(rgbFormat,
+ screen->ttm ? screen->back.tiled : INTEL_TILE_NONE);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT,
&intel_fb->color_rb[1]->Base);
if (screen->third.handle) {
struct gl_renderbuffer *tmp_rb = NULL;
- intel_fb->color_rb[2] = intel_create_renderbuffer(rgbFormat);
+ intel_fb->color_rb[2] = intel_create_renderbuffer(rgbFormat,
+ screen->ttm ? screen->third.tiled : INTEL_TILE_NONE);
_mesa_reference_renderbuffer(&tmp_rb, &intel_fb->color_rb[2]->Base);
}
}
@@ -546,7 +549,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
if (mesaVis->stencilBits == 8) {
/* combined depth/stencil buffer */
struct intel_renderbuffer *depthStencilRb
- = intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT);
+ = intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT,
+ screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
/* note: bind RB to two attachment points */
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
&depthStencilRb->Base);
@@ -554,7 +558,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
&depthStencilRb->Base);
} else {
struct intel_renderbuffer *depthRb
- = intel_create_renderbuffer(GL_DEPTH_COMPONENT24);
+ = intel_create_renderbuffer(GL_DEPTH_COMPONENT24,
+ screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
&depthRb->Base);
}
@@ -562,7 +567,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
else if (mesaVis->depthBits == 16) {
/* just 16-bit depth buffer, no hw stencil */
struct intel_renderbuffer *depthRb
- = intel_create_renderbuffer(GL_DEPTH_COMPONENT16);
+ = intel_create_renderbuffer(GL_DEPTH_COMPONENT16,
+ screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base);
}
diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h
index e62b2d7c89..9a73b13951 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.h
+++ b/src/mesa/drivers/dri/intel/intel_screen.h
@@ -74,6 +74,8 @@ typedef struct
int irq_active;
int allow_batchbuffer;
+ int ttm;
+
/**
* Configuration cache with default values for all contexts
*/
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index df4f5927a0..149b581d88 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -39,6 +39,111 @@
#include "swrast/swrast.h"
+/*
+ * Deal with tiled surfaces
+ */
+
+#if 0
+/* These are pre-965 tile swizzling functions -- power of two widths */
+static uintptr_t x_tile_swizzle_pow2 (uintptr_t addr, int n)
+{
+ uintptr_t a = addr;
+ uintptr_t base_mask = (((~0) << (n + 4)) | 0xff);
+ uintptr_t x_mask = ((~0) << 12) & ~base_mask;
+
+ a = ((a & base_mask) |
+ ((a >> (n-8)) & 0x7) |
+ ((a << 3) & x_mask));
+ _mesa_printf ("x_swizzle %08x (base %x yrow %x tile#x %x xsword %x byte %x) %08x\n",
+ addr,
+ addr >> (n + 4),
+ (addr >> (n + 1)) & 0x7,
+ (addr >> 9) & ((1 << (n-8)) - 1),
+ (addr >> 5) & 0xf,
+ (addr & 0x1f),
+ a);
+ return a;
+}
+
+static uintptr_t y_tile_swizzle_pow2 (uintptr_t addr, int n)
+{
+ uintptr_t a = (uintptr_t) addr;
+ uintptr_t base_mask = (((~0) << (n + 6)) | 0xf);
+ uintptr_t x_mask = ((~0) << 9) & ~base_mask;
+
+ a = ((a & base_mask) |
+ ((a >> (n-3)) & 0x1f) |
+ ((a << 5) & x_mask));
+ _mesa_printf ("y_swizzle %08x (base %x yrow %x tile#x %x xoword %x byte %x) %08x\n",
+ addr,
+ addr >> (n + 6),
+ (addr >> (n + 1)) & 0x01f,
+ (addr >> 7) & ((1 << (n-6)) - 1),
+ (addr >> 4) & 0x7,
+ (addr & 0xf),
+ a);
+ return a;
+}
+#endif
+
+static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_context *intel,
+ int x, int y)
+{
+ GLubyte *buf = (GLubyte *) irb->pfMap;
+ int tile_stride;
+ int xbyte;
+ int x_tile_off, y_tile_off;
+ int x_tile_number, y_tile_number;
+ int tile_off, tile_base;
+
+ tile_stride = (irb->pfPitch * irb->region->cpp) << 3;
+
+ x += intel->drawX;
+ y += intel->drawY;
+
+ xbyte = x * irb->region->cpp;
+
+ x_tile_off = xbyte & 0x1ff;
+ y_tile_off = y & 7;
+
+ x_tile_number = xbyte >> 9;
+ y_tile_number = y >> 3;
+
+ tile_off = (y_tile_off << 9) + x_tile_off;
+ tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
+
+ return buf + tile_base + tile_off;
+}
+
+static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_context *intel,
+ int x, int y)
+{
+ GLubyte *buf = (GLubyte *) irb->pfMap;
+ int tile_stride;
+ int xbyte;
+ int x_tile_off, y_tile_off;
+ int x_tile_number, y_tile_number;
+ int tile_off, tile_base;
+
+ tile_stride = (irb->pfPitch * irb->region->cpp) << 3;
+
+ x += intel->drawX;
+ y += intel->drawY;
+
+ xbyte = x * irb->region->cpp;
+
+ x_tile_off = xbyte & 0x7f;
+ y_tile_off = y & 0x1f;
+
+ x_tile_number = xbyte >> 7;
+ y_tile_number = y >> 5;
+
+ tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) + (x_tile_off & 0xf);
+ tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
+
+ return buf + tile_base + tile_off;
+}
+
/*
break intelWriteRGBASpan_ARGB8888
*/
@@ -55,7 +160,7 @@
+ (intel->drawY * irb->pfPitch + intel->drawX) * irb->region->cpp;\
GLuint p; \
assert(irb->pfMap);\
- (void) p;
+ (void) p; (void) buf;
/* XXX FBO: this is identical to the macro in spantmp2.h except we get
* the cliprect info from the context, not the driDrawable.
@@ -69,12 +174,14 @@
int miny = intel->pClipRects[_nc].y1 - intel->drawY; \
int maxx = intel->pClipRects[_nc].x2 - intel->drawX; \
int maxy = intel->pClipRects[_nc].y2 - intel->drawY;
-
-
-
+
+#if 0
+ }}
+#endif
#define Y_FLIP(_y) ((_y) * yScale + yBias)
+/* XXX with GEM, these need to tell the kernel */
#define HW_LOCK()
#define HW_UNLOCK()
@@ -99,6 +206,43 @@
#define GET_PTR(X,Y) (buf + ((Y) * irb->pfPitch + (X)) * 4)
#include "spantmp2.h"
+/* 16 bit RGB565 color tile spanline and pixel functions
+ */
+
+#define SPANTMP_PIXEL_FMT GL_RGB
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
+
+#define TAG(x) intel_XTile_##x##_RGB565
+#define TAG2(x,y) intel_XTile_##x##_RGB565##y
+#define GET_PTR(X,Y) x_tile_swizzle(irb, intel, X, Y)
+#include "spantmp2.h"
+
+#define SPANTMP_PIXEL_FMT GL_RGB
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
+
+#define TAG(x) intel_YTile_##x##_RGB565
+#define TAG2(x,y) intel_YTile_##x##_RGB565##y
+#define GET_PTR(X,Y) y_tile_swizzle(irb, intel, X, Y)
+#include "spantmp2.h"
+
+/* 32 bit ARGB888 color tile spanline and pixel functions
+ */
+
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x) intel_XTile_##x##_ARGB8888
+#define TAG2(x,y) intel_XTile_##x##_ARGB8888##y
+#define GET_PTR(X,Y) x_tile_swizzle(irb, intel, X, Y)
+#include "spantmp2.h"
+
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x) intel_YTile_##x##_ARGB8888
+#define TAG2(x,y) intel_YTile_##x##_ARGB8888##y
+#define GET_PTR(X,Y) y_tile_swizzle(irb, intel, X, Y)
+#include "spantmp2.h"
#define LOCAL_DEPTH_VARS \
struct intel_context *intel = intel_context(ctx); \
@@ -107,7 +251,7 @@
const GLint yScale = irb->RenderToTexture ? 1 : -1; \
const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; \
char *buf = (char *) irb->pfMap/*XXX use region->map*/ + \
- (intel->drawY * pitch + intel->drawX) * irb->region->cpp;
+ (intel->drawY * pitch + intel->drawX) * irb->region->cpp; (void) buf;
#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
@@ -126,6 +270,33 @@
#include "depthtmp.h"
+/**
+ ** 16-bit x tile depthbuffer functions.
+ **/
+#define WRITE_DEPTH( _x, _y, d ) \
+ (*((GLushort *)x_tile_swizzle (irb, intel, _x, _y)) = d)
+
+#define READ_DEPTH( d, _x, _y ) \
+ d = *((GLushort *)x_tile_swizzle (irb, intel, _x, _y))
+
+
+#define TAG(x) intel_XTile_##x##_z16
+#include "depthtmp.h"
+
+/**
+ ** 16-bit y tile depthbuffer functions.
+ **/
+#define WRITE_DEPTH( _x, _y, d ) \
+ (*((GLushort *)y_tile_swizzle (irb, intel, _x, _y)) = d)
+
+#define READ_DEPTH( d, _x, _y ) \
+ (d = *((GLushort *)y_tile_swizzle (irb, intel, _x, _y)))
+
+
+#define TAG(x) intel_YTile_##x##_z16
+#include "depthtmp.h"
+
+
/**
** 24/8-bit interleaved depth/stencil functions
** Note: we're actually reading back combined depth+stencil values.
@@ -148,6 +319,49 @@
#include "depthtmp.h"
+/**
+ ** 24/8-bit x-tile interleaved depth/stencil functions
+ ** Note: we're actually reading back combined depth+stencil values.
+ ** The wrappers in main/depthstencil.c are used to extract the depth
+ ** and stencil values.
+ **/
+/* Change ZZZS -> SZZZ */
+#define WRITE_DEPTH( _x, _y, d ) { \
+ GLuint tmp = ((d) >> 8) | ((d) << 24); \
+ *((GLuint *)x_tile_swizzle (irb, intel, _x, _y)) = tmp; \
+}
+
+/* Change SZZZ -> ZZZS */
+#define READ_DEPTH( d, _x, _y ) { \
+ GLuint tmp = *((GLuint *)x_tile_swizzle (irb, intel, _x, _y)); \
+ d = (tmp << 8) | (tmp >> 24); \
+}
+
+#define TAG(x) intel_XTile_##x##_z24_s8
+#include "depthtmp.h"
+
+/**
+ ** 24/8-bit y-tile interleaved depth/stencil functions
+ ** Note: we're actually reading back combined depth+stencil values.
+ ** The wrappers in main/depthstencil.c are used to extract the depth
+ ** and stencil values.
+ **/
+/* Change ZZZS -> SZZZ */
+#define WRITE_DEPTH( _x, _y, d ) { \
+ GLuint tmp = ((d) >> 8) | ((d) << 24); \
+ *((GLuint *)y_tile_swizzle (irb, intel, _x, _y)) = tmp; \
+}
+
+/* Change SZZZ -> ZZZS */
+#define READ_DEPTH( d, _x, _y ) { \
+ GLuint tmp = *((GLuint *)y_tile_swizzle (irb, intel, _x, _y)); \
+ d = (tmp << 8) | (tmp >> 24); \
+}
+
+#define TAG(x) intel_YTile_##x##_z24_s8
+#include "depthtmp.h"
+
+
/**
** 8-bit stencil function (XXX FBO: This is obsolete)
**/
@@ -164,6 +378,40 @@
#define TAG(x) intel##x##_z24_s8
#include "stenciltmp.h"
+/**
+ ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
+ **/
+#define WRITE_STENCIL( _x, _y, d ) { \
+ GLuint *a = (GLuint *) x_tile_swizzle (irb, intel, _x, _y); \
+ GLuint tmp = *a; \
+ tmp &= 0xffffff; \
+ tmp |= ((d) << 24); \
+ *a = tmp; \
+}
+
+#define READ_STENCIL( d, _x, _y ) \
+ (d = *((GLuint*) x_tile_swizzle (irb, intel, _x, _y)) >> 24)
+
+#define TAG(x) intel_XTile_##x##_z24_s8
+#include "stenciltmp.h"
+
+/**
+ ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
+ **/
+#define WRITE_STENCIL( _x, _y, d ) { \
+ GLuint *a = (GLuint *) y_tile_swizzle (irb, intel, _x, _y); \
+ GLuint tmp = *a; \
+ tmp &= 0xffffff; \
+ tmp |= ((d) << 24); \
+ *a = tmp; \
+}
+
+#define READ_STENCIL( d, _x, _y ) \
+ (d = *((GLuint*) y_tile_swizzle (irb, intel, _x, _y)) >> 24)
+
+#define TAG(x) intel_YTile_##x##_z24_s8
+#include "stenciltmp.h"
+
/**
@@ -379,25 +627,80 @@ intelInitSpanFuncs(GLcontext * ctx)
* These are used for the software fallbacks.
*/
void
-intel_set_span_functions(struct gl_renderbuffer *rb)
+intel_set_span_functions(struct gl_renderbuffer *rb, int tiling)
{
if (rb->_ActualFormat == GL_RGB5) {
/* 565 RGB */
- intelInitPointers_RGB565(rb);
+ switch (tiling) {
+ case INTEL_TILE_NONE:
+ default:
+ intelInitPointers_RGB565(rb);
+ break;
+ case INTEL_TILE_X:
+ intel_XTile_InitPointers_RGB565(rb);
+ break;
+ case INTEL_TILE_Y:
+ intel_YTile_InitPointers_RGB565(rb);
+ break;
+ }
}
else if (rb->_ActualFormat == GL_RGBA8) {
/* 8888 RGBA */
- intelInitPointers_ARGB8888(rb);
+ switch (tiling) {
+ case INTEL_TILE_NONE:
+ default:
+ intelInitPointers_ARGB8888(rb);
+ break;
+ case INTEL_TILE_X:
+ intel_XTile_InitPointers_ARGB8888(rb);
+ break;
+ case INTEL_TILE_Y:
+ intel_YTile_InitPointers_ARGB8888(rb);
+ break;
+ }
}
else if (rb->_ActualFormat == GL_DEPTH_COMPONENT16) {
- intelInitDepthPointers_z16(rb);
+ switch (tiling) {
+ case INTEL_TILE_NONE:
+ default:
+ intelInitDepthPointers_z16(rb);
+ break;
+ case INTEL_TILE_X:
+ intel_XTile_InitDepthPointers_z16(rb);
+ break;
+ case INTEL_TILE_Y:
+ intel_YTile_InitDepthPointers_z16(rb);
+ break;
+ }
}
else if (rb->_ActualFormat == GL_DEPTH_COMPONENT24 || /* XXX FBO remove */
rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
- intelInitDepthPointers_z24_s8(rb);
+ switch (tiling) {
+ case INTEL_TILE_NONE:
+ default:
+ intelInitDepthPointers_z24_s8(rb);
+ break;
+ case INTEL_TILE_X:
+ intel_XTile_InitDepthPointers_z24_s8(rb);
+ break;
+ case INTEL_TILE_Y:
+ intel_YTile_InitDepthPointers_z24_s8(rb);
+ break;
+ }
}
- else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) { /* XXX FBO remove */
- intelInitStencilPointers_z24_s8(rb);
+ else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
+ switch (tiling) {
+ case INTEL_TILE_NONE:
+ default:
+ intelInitStencilPointers_z24_s8(rb);
+ break;
+ case INTEL_TILE_X:
+ intel_XTile_InitStencilPointers_z24_s8(rb);
+ break;
+ case INTEL_TILE_Y:
+ intel_YTile_InitStencilPointers_z24_s8(rb);
+ break;
+ }
}
else {
_mesa_problem(NULL,
diff --git a/src/mesa/drivers/dri/intel/intel_span.h b/src/mesa/drivers/dri/intel/intel_span.h
index 5201f6d6c6..c56e5e1611 100644
--- a/src/mesa/drivers/dri/intel/intel_span.h
+++ b/src/mesa/drivers/dri/intel/intel_span.h
@@ -33,6 +33,10 @@ extern void intelInitSpanFuncs(GLcontext * ctx);
extern void intelSpanRenderFinish(GLcontext * ctx);
extern void intelSpanRenderStart(GLcontext * ctx);
-extern void intel_set_span_functions(struct gl_renderbuffer *rb);
+extern void intel_set_span_functions(struct gl_renderbuffer *rb, int tiling);
+
+#define INTEL_TILE_NONE 0
+#define INTEL_TILE_X 1
+#define INTEL_TILE_Y 2
#endif
--
cgit v1.2.3
From 96f52f089f42b4bca8fa5fb573c687d233851126 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Tue, 6 May 2008 13:57:08 -0700
Subject: GEM: Don't emit an extra MI_FLUSH in the batch since GEM handles it.
---
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 30 +++++++++++++-------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index a95abd9ec9..ef66fd75ac 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -195,7 +195,7 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
int line)
{
struct intel_context *intel = batch->intel;
- GLuint used = batch->ptr - batch->map;
+ GLuint used;
GLboolean was_locked = intel->locked;
if (used == 0)
@@ -204,20 +204,20 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
if (INTEL_DEBUG & DEBUG_BATCH)
fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
used);
- /* Add the MI_BATCH_BUFFER_END. Always add an MI_FLUSH - this is a
- * performance drain that we would like to avoid.
- */
- if (used & 4) {
- ((int *) batch->ptr)[0] = intel->vtbl.flush_cmd();
- ((int *) batch->ptr)[1] = 0;
- ((int *) batch->ptr)[2] = MI_BATCH_BUFFER_END;
- used += 12;
- }
- else {
- ((int *) batch->ptr)[0] = intel->vtbl.flush_cmd();
- ((int *) batch->ptr)[1] = MI_BATCH_BUFFER_END;
- used += 8;
- }
+
+ /* Emit a flush if the bufmgr doesn't do it for us. */
+ if (!intel->ttm)
+ intel_batchbuffer_emit_dword(intel->batch, intel->vtbl.flush_cmd());
+
+ /* Round batchbuffer usage to 2 DWORDs. */
+ used = batch->ptr - batch->map;
+ if ((used & 4) == 0)
+ intel_batchbuffer_emit_dword(intel->batch, 0); /* noop */
+
+ /* Mark the end of the buffer. */
+ intel_batchbuffer_emit_dword(intel->batch, MI_BATCH_BUFFER_END);
+
+ used = batch->ptr - batch->map;
/* Workaround for recursive batchbuffer flushing: If the window is
* moved, we can get into a case where we try to flush during a
--
cgit v1.2.3
From 42d4f89264f193e8beae7ba975df3507b81b6da0 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Tue, 6 May 2008 15:25:51 -0700
Subject: GEM: Fix previous commit to avoid asserting when we run into reserved
space.
These are the dwords that the reserved space is for.
---
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index ef66fd75ac..bab8e645d4 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -206,16 +206,21 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
used);
/* Emit a flush if the bufmgr doesn't do it for us. */
- if (!intel->ttm)
- intel_batchbuffer_emit_dword(intel->batch, intel->vtbl.flush_cmd());
+ if (!intel->ttm) {
+ *(GLuint *) (batch->ptr) = intel->vtbl.flush_cmd();
+ batch->ptr += 4;
+ }
/* Round batchbuffer usage to 2 DWORDs. */
used = batch->ptr - batch->map;
- if ((used & 4) == 0)
- intel_batchbuffer_emit_dword(intel->batch, 0); /* noop */
+ if ((used & 4) == 0) {
+ *(GLuint *) (batch->ptr) = 0; /* noop */
+ batch->ptr += 4;
+ }
/* Mark the end of the buffer. */
- intel_batchbuffer_emit_dword(intel->batch, MI_BATCH_BUFFER_END);
+ *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END; /* noop */
+ batch->ptr += 4;
used = batch->ptr - batch->map;
--
cgit v1.2.3
From a2ec8570aeb838700fa97b8c5ba6d9d383e5606e Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Tue, 6 May 2008 22:06:41 -0700
Subject: [intel-GEM] partial support for memory domains.
Doesn't deal with local modifications yet (need new kernel set_domain ioctl
for that to work). Also, guesses what domains are affected based on the
read/write bits set in the flags. Works for 915, probably not so much for
965.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index e4e8481b96..69d90e19d8 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -123,6 +123,8 @@ typedef struct _dri_bo_gem {
dri_bo **reloc_target_bo;
/** Number of entries in relocs */
int reloc_count;
+ /** Memory domains for synchronization */
+ uint32_t read_domains, write_domain;
/** Mapped address for the buffer */
void *virtual;
} dri_bo_gem;
@@ -230,6 +232,8 @@ intel_add_validate_buffer(dri_bo *bo)
bufmgr_gem->validate_array[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
bufmgr_gem->validate_array[index].alignment = 0;
bufmgr_gem->validate_array[index].buffer_offset = 0;
+ bufmgr_gem->validate_array[index].read_domains = bo_gem->read_domains;
+ bufmgr_gem->validate_array[index].write_domain = bo_gem->write_domain;
bufmgr_gem->validate_bo[index] = bo;
dri_bo_reference(bo);
bufmgr_gem->validate_count++;
@@ -597,6 +601,18 @@ dri_gem_emit_reloc(dri_bo *bo, uint64_t flags, GLuint delta,
bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
dri_bo_reference(target_bo);
+ /** XXX set memory domains, using existing TTM flags (which is wrong) */
+ if (flags & DRM_BO_FLAG_WRITE)
+ {
+ /* assume this means the rendering buffer */
+ target_bo_gem->read_domains |= DRM_GEM_DOMAIN_I915_RENDER;
+ target_bo_gem->write_domain = DRM_GEM_DOMAIN_I915_RENDER;
+ }
+ if (flags & DRM_BO_FLAG_READ)
+ {
+ /* assume this means the sampler buffer */
+ target_bo_gem->read_domains |= DRM_GEM_DOMAIN_I915_SAMPLER;
+ }
bo_gem->reloc_count++;
return 0;
}
@@ -629,7 +645,10 @@ dri_gem_bo_process_reloc(dri_bo *bo)
static void *
dri_gem_process_reloc(dri_bo *batch_buf)
{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)batch_buf->bufmgr;
+ dri_bo_gem *bo_gem = (dri_bo_gem *)batch_buf;
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *) batch_buf->bufmgr;
+
+ bo_gem->read_domains |= DRM_GEM_DOMAIN_I915_COMMAND;
/* Update indices and set up the validate list. */
dri_gem_bo_process_reloc(batch_buf);
@@ -680,6 +699,9 @@ dri_gem_post_submit(dri_bo *batch_buf)
dri_bo *bo = bufmgr_gem->validate_bo[i];
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+ /* clear read/write domain bits */
+ bo_gem->read_domains = 0;
+ bo_gem->write_domain = 0;
/* Disconnect the buffer from the validate list */
bo_gem->validate_index = -1;
dri_bo_unreference(bo);
--
cgit v1.2.3
From 8b2a7f08bc446deef497f2a0d3b54d9b70bdaf9c Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 7 May 2008 10:01:14 -0700
Subject: GEM: Don't emit an extra MI_FLUSH in the batch since GEM handles it.
---
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 31 +++++++++++++++-----------
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index a95abd9ec9..bab8e645d4 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -195,7 +195,7 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
int line)
{
struct intel_context *intel = batch->intel;
- GLuint used = batch->ptr - batch->map;
+ GLuint used;
GLboolean was_locked = intel->locked;
if (used == 0)
@@ -204,21 +204,26 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
if (INTEL_DEBUG & DEBUG_BATCH)
fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
used);
- /* Add the MI_BATCH_BUFFER_END. Always add an MI_FLUSH - this is a
- * performance drain that we would like to avoid.
- */
- if (used & 4) {
- ((int *) batch->ptr)[0] = intel->vtbl.flush_cmd();
- ((int *) batch->ptr)[1] = 0;
- ((int *) batch->ptr)[2] = MI_BATCH_BUFFER_END;
- used += 12;
+
+ /* Emit a flush if the bufmgr doesn't do it for us. */
+ if (!intel->ttm) {
+ *(GLuint *) (batch->ptr) = intel->vtbl.flush_cmd();
+ batch->ptr += 4;
}
- else {
- ((int *) batch->ptr)[0] = intel->vtbl.flush_cmd();
- ((int *) batch->ptr)[1] = MI_BATCH_BUFFER_END;
- used += 8;
+
+ /* Round batchbuffer usage to 2 DWORDs. */
+ used = batch->ptr - batch->map;
+ if ((used & 4) == 0) {
+ *(GLuint *) (batch->ptr) = 0; /* noop */
+ batch->ptr += 4;
}
+ /* Mark the end of the buffer. */
+ *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END; /* noop */
+ batch->ptr += 4;
+
+ used = batch->ptr - batch->map;
+
/* Workaround for recursive batchbuffer flushing: If the window is
* moved, we can get into a case where we try to flush during a
* flush. What happens is that when we try to grab the lock for
--
cgit v1.2.3
From ab50ddaa9173ae108833db0edb209045788efc41 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 7 May 2008 13:51:29 -0700
Subject: GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.
The GEM flags are much more descriptive for what we need. Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
---
src/mesa/drivers/dri/Makefile.template | 3 +-
src/mesa/drivers/dri/common/dri_bufmgr.c | 8 +-
src/mesa/drivers/dri/common/dri_bufmgr.h | 21 +-
src/mesa/drivers/dri/common/dri_bufmgr_fake.c | 1174 ----------------------
src/mesa/drivers/dri/i915/Makefile | 1 +
src/mesa/drivers/dri/i915/i830_vtbl.c | 6 +-
src/mesa/drivers/dri/i915/i915_vtbl.c | 6 +-
src/mesa/drivers/dri/i915/intel_bufmgr_fake.c | 1 +
src/mesa/drivers/dri/i965/Makefile | 1 +
src/mesa/drivers/dri/i965/brw_cc.c | 3 +-
src/mesa/drivers/dri/i965/brw_clip_state.c | 3 +-
src/mesa/drivers/dri/i965/brw_curbe.c | 3 +-
src/mesa/drivers/dri/i965/brw_draw_upload.c | 9 +-
src/mesa/drivers/dri/i965/brw_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_misc_state.c | 19 +-
src/mesa/drivers/dri/i965/brw_sf_state.c | 4 +-
src/mesa/drivers/dri/i965/brw_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_state.c | 6 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 +-
src/mesa/drivers/dri/i965/intel_bufmgr_fake.c | 1 +
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 6 +-
src/mesa/drivers/dri/intel/intel_batchbuffer.h | 9 +-
src/mesa/drivers/dri/intel/intel_blit.c | 31 +-
src/mesa/drivers/dri/intel/intel_bufmgr_fake.c | 1173 +++++++++++++++++++++
src/mesa/drivers/dri/intel/intel_bufmgr_fake.h | 50 +
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 30 +-
src/mesa/drivers/dri/intel/intel_context.c | 1 +
28 files changed, 1331 insertions(+), 1260 deletions(-)
delete mode 100644 src/mesa/drivers/dri/common/dri_bufmgr_fake.c
create mode 120000 src/mesa/drivers/dri/i915/intel_bufmgr_fake.c
create mode 120000 src/mesa/drivers/dri/i965/intel_bufmgr_fake.c
create mode 100644 src/mesa/drivers/dri/intel/intel_bufmgr_fake.c
create mode 100644 src/mesa/drivers/dri/intel/intel_bufmgr_fake.h
diff --git a/src/mesa/drivers/dri/Makefile.template b/src/mesa/drivers/dri/Makefile.template
index 53f9d80689..cb41662707 100644
--- a/src/mesa/drivers/dri/Makefile.template
+++ b/src/mesa/drivers/dri/Makefile.template
@@ -12,8 +12,7 @@ COMMON_SOURCES = \
../common/drirenderbuffer.c
COMMON_BM_SOURCES = \
- ../common/dri_bufmgr.c \
- ../common/dri_bufmgr_fake.c
+ ../common/dri_bufmgr.c
ifeq ($(WINDOW_SYSTEM),dri)
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.c b/src/mesa/drivers/dri/common/dri_bufmgr.c
index 69868b6665..5967d7dafb 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr.c
+++ b/src/mesa/drivers/dri/common/dri_bufmgr.c
@@ -121,10 +121,12 @@ dri_bufmgr_destroy(dri_bufmgr *bufmgr)
}
-int dri_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
- GLuint offset, dri_bo *target_buf)
+int dri_emit_reloc(dri_bo *reloc_buf,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t delta, uint32_t offset, dri_bo *target_buf)
{
- return reloc_buf->bufmgr->emit_reloc(reloc_buf, flags, delta, offset, target_buf);
+ return reloc_buf->bufmgr->emit_reloc(reloc_buf, read_domains, write_domain,
+ delta, offset, target_buf);
}
void *dri_process_relocs(dri_bo *batch_buf)
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.h b/src/mesa/drivers/dri/common/dri_bufmgr.h
index dffeb4c601..99cfb2cd05 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr.h
+++ b/src/mesa/drivers/dri/common/dri_bufmgr.h
@@ -135,8 +135,9 @@ struct _dri_bufmgr {
* \param target Buffer whose offset should be written into the relocation
* entry.
*/
- int (*emit_reloc)(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
- GLuint offset, dri_bo *target);
+ int (*emit_reloc)(dri_bo *reloc_buf,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t delta, uint32_t offset, dri_bo *target);
/**
* Processes the relocations, either in userland or by converting the list
@@ -174,22 +175,12 @@ void dri_bo_subdata(dri_bo *bo, unsigned long offset,
void dri_bo_get_subdata(dri_bo *bo, unsigned long offset,
unsigned long size, void *data);
-void dri_bufmgr_fake_contended_lock_take(dri_bufmgr *bufmgr);
-dri_bufmgr *dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual,
- unsigned long size,
- unsigned int (*fence_emit)(void *private),
- int (*fence_wait)(void *private,
- unsigned int cookie),
- void *driver_priv);
void dri_bufmgr_set_debug(dri_bufmgr *bufmgr, GLboolean enable_debug);
-void dri_bo_fake_disable_backing_store(dri_bo *bo,
- void (*invalidate_cb)(dri_bo *bo,
- void *ptr),
- void *ptr);
void dri_bufmgr_destroy(dri_bufmgr *bufmgr);
-int dri_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
- GLuint offset, dri_bo *target_buf);
+int dri_emit_reloc(dri_bo *reloc_buf,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t delta, uint32_t offset, dri_bo *target_buf);
void *dri_process_relocs(dri_bo *batch_buf);
void dri_post_process_relocs(dri_bo *batch_buf);
void dri_post_submit(dri_bo *batch_buf);
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr_fake.c b/src/mesa/drivers/dri/common/dri_bufmgr_fake.c
deleted file mode 100644
index fc52674839..0000000000
--- a/src/mesa/drivers/dri/common/dri_bufmgr_fake.c
+++ /dev/null
@@ -1,1174 +0,0 @@
-/**************************************************************************
- *
- * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-/* Originally a fake version of the buffer manager so that we can
- * prototype the changes in a driver fairly quickly, has been fleshed
- * out to a fully functional interim solution.
- *
- * Basically wraps the old style memory management in the new
- * programming interface, but is more expressive and avoids many of
- * the bugs in the old texture manager.
- */
-#include "mtypes.h"
-#include "dri_bufmgr.h"
-#include "drm.h"
-
-#include "simple_list.h"
-#include "mm.h"
-#include "imports.h"
-
-#define DBG(...) do { \
- if (bufmgr_fake->bufmgr.debug) \
- _mesa_printf(__VA_ARGS__); \
-} while (0)
-
-/* Internal flags:
- */
-#define BM_NO_BACKING_STORE 0x00000001
-#define BM_NO_FENCE_SUBDATA 0x00000002
-#define BM_PINNED 0x00000004
-
-/* Wrapper around mm.c's mem_block, which understands that you must
- * wait for fences to expire before memory can be freed. This is
- * specific to our use of memcpy for uploads - an upload that was
- * processed through the command queue wouldn't need to care about
- * fences.
- */
-#define MAX_RELOCS 4096
-
-struct fake_buffer_reloc
-{
- /** Buffer object that the relocation points at. */
- dri_bo *target_buf;
- /** Offset of the relocation entry within reloc_buf. */
- GLuint offset;
- /** Cached value of the offset when we last performed this relocation. */
- GLuint last_target_offset;
- /** Value added to target_buf's offset to get the relocation entry. */
- GLuint delta;
- /** Flags to validate the target buffer under. */
- uint64_t validate_flags;
-};
-
-struct block {
- struct block *next, *prev;
- struct mem_block *mem; /* BM_MEM_AGP */
-
- /**
- * Marks that the block is currently in the aperture and has yet to be
- * fenced.
- */
- unsigned on_hardware:1;
- /**
- * Marks that the block is currently fenced (being used by rendering) and
- * can't be freed until @fence is passed.
- */
- unsigned fenced:1;
-
- /** Fence cookie for the block. */
- unsigned fence; /* Split to read_fence, write_fence */
-
- dri_bo *bo;
- void *virtual;
-};
-
-typedef struct _bufmgr_fake {
- dri_bufmgr bufmgr;
-
- unsigned long low_offset;
- unsigned long size;
- void *virtual;
-
- struct mem_block *heap;
- struct block lru; /* only allocated, non-fence-pending blocks here */
-
- unsigned buf_nr; /* for generating ids */
-
- struct block on_hardware; /* after bmValidateBuffers */
- struct block fenced; /* after bmFenceBuffers (mi_flush, emit irq, write dword) */
- /* then to bufmgr->lru or free() */
-
- unsigned int last_fence;
-
- unsigned fail:1;
- unsigned need_fence:1;
- GLboolean thrashing;
-
- /**
- * Driver callback to emit a fence, returning the cookie.
- *
- * Currently, this also requires that a write flush be emitted before
- * emitting the fence, but this should change.
- */
- unsigned int (*fence_emit)(void *private);
- /** Driver callback to wait for a fence cookie to have passed. */
- int (*fence_wait)(void *private, unsigned int fence_cookie);
- /** Driver-supplied argument to driver callbacks */
- void *driver_priv;
-
- GLboolean debug;
-
- GLboolean performed_rendering;
-
- /* keep track of the current total size of objects we have relocs for */
- unsigned long current_total_size;
-} dri_bufmgr_fake;
-
-typedef struct _dri_bo_fake {
- dri_bo bo;
-
- unsigned id; /* debug only */
- const char *name;
-
- unsigned dirty:1;
- unsigned size_accounted:1; /*this buffers size has been accounted against the aperture */
- unsigned card_dirty:1; /* has the card written to this buffer - we make need to copy it back */
- unsigned int refcount;
- /* Flags may consist of any of the DRM_BO flags, plus
- * DRM_BO_NO_BACKING_STORE and BM_NO_FENCE_SUBDATA, which are the first two
- * driver private flags.
- */
- uint64_t flags;
- unsigned int alignment;
- GLboolean is_static, validated;
- unsigned int map_count;
-
- /* Flags for the buffer to be validated with in command submission */
- uint64_t validate_flags;
-
- /** relocation list */
- struct fake_buffer_reloc *relocs;
- GLuint nr_relocs;
-
- struct block *block;
- void *backing_store;
- void (*invalidate_cb)(dri_bo *bo, void *ptr);
- void *invalidate_ptr;
-} dri_bo_fake;
-
-static int clear_fenced(dri_bufmgr_fake *bufmgr_fake,
- unsigned int fence_cookie);
-
-static int dri_fake_check_aperture_space(dri_bo *bo);
-
-#define MAXFENCE 0x7fffffff
-
-static GLboolean FENCE_LTE( unsigned a, unsigned b )
-{
- if (a == b)
- return GL_TRUE;
-
- if (a < b && b - a < (1<<24))
- return GL_TRUE;
-
- if (a > b && MAXFENCE - a + b < (1<<24))
- return GL_TRUE;
-
- return GL_FALSE;
-}
-
-static unsigned int
-_fence_emit_internal(dri_bufmgr_fake *bufmgr_fake)
-{
- bufmgr_fake->last_fence = bufmgr_fake->fence_emit(bufmgr_fake->driver_priv);
- return bufmgr_fake->last_fence;
-}
-
-static void
-_fence_wait_internal(dri_bufmgr_fake *bufmgr_fake, unsigned int cookie)
-{
- int ret;
-
- ret = bufmgr_fake->fence_wait(bufmgr_fake->driver_priv, cookie);
- if (ret != 0) {
- _mesa_printf("%s:%d: Error %d waiting for fence.\n",
- __FILE__, __LINE__);
- abort();
- }
- clear_fenced(bufmgr_fake, cookie);
-}
-
-static GLboolean
-_fence_test(dri_bufmgr_fake *bufmgr_fake, unsigned fence)
-{
- /* Slight problem with wrap-around:
- */
- return fence == 0 || FENCE_LTE(fence, bufmgr_fake->last_fence);
-}
-
-/**
- * Allocate a memory manager block for the buffer.
- */
-static GLboolean
-alloc_block(dri_bo *bo)
-{
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- dri_bufmgr_fake *bufmgr_fake= (dri_bufmgr_fake *)bo->bufmgr;
- struct block *block = (struct block *)calloc(sizeof *block, 1);
- unsigned int align_log2 = _mesa_ffs(bo_fake->alignment) - 1;
- GLuint sz;
-
- if (!block)
- return GL_FALSE;
-
- sz = (bo->size + bo_fake->alignment - 1) & ~(bo_fake->alignment - 1);
-
- block->mem = mmAllocMem(bufmgr_fake->heap, sz, align_log2, 0);
- if (!block->mem) {
- free(block);
- return GL_FALSE;
- }
-
- make_empty_list(block);
-
- /* Insert at head or at tail???
- */
- insert_at_tail(&bufmgr_fake->lru, block);
-
- block->virtual = bufmgr_fake->virtual +
- block->mem->ofs - bufmgr_fake->low_offset;
- block->bo = bo;
-
- bo_fake->block = block;
-
- return GL_TRUE;
-}
-
-/* Release the card storage associated with buf:
- */
-static void free_block(dri_bufmgr_fake *bufmgr_fake, struct block *block)
-{
- dri_bo_fake *bo_fake;
- DBG("free block %p %08x %d %d\n", block, block->mem->ofs, block->on_hardware, block->fenced);
-
- if (!block)
- return;
-
- bo_fake = (dri_bo_fake *)block->bo;
- if (!(bo_fake->flags & BM_NO_BACKING_STORE) && (bo_fake->card_dirty == 1)) {
- memcpy(bo_fake->backing_store, block->virtual, block->bo->size);
- bo_fake->card_dirty = 1;
- bo_fake->dirty = 1;
- }
-
- if (block->on_hardware) {
- block->bo = NULL;
- }
- else if (block->fenced) {
- block->bo = NULL;
- }
- else {
- DBG(" - free immediately\n");
- remove_from_list(block);
-
- mmFreeMem(block->mem);
- free(block);
- }
-}
-
-static void
-alloc_backing_store(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- assert(!bo_fake->backing_store);
- assert(!(bo_fake->flags & (BM_PINNED|BM_NO_BACKING_STORE)));
-
- bo_fake->backing_store = ALIGN_MALLOC(bo->size, 64);
-
- DBG("alloc_backing - buf %d %p %d\n", bo_fake->id, bo_fake->backing_store, bo->size);
- assert(bo_fake->backing_store);
-}
-
-static void
-free_backing_store(dri_bo *bo)
-{
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- if (bo_fake->backing_store) {
- assert(!(bo_fake->flags & (BM_PINNED|BM_NO_BACKING_STORE)));
- ALIGN_FREE(bo_fake->backing_store);
- bo_fake->backing_store = NULL;
- }
-}
-
-static void
-set_dirty(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- if (bo_fake->flags & BM_NO_BACKING_STORE && bo_fake->invalidate_cb != NULL)
- bo_fake->invalidate_cb(bo, bo_fake->invalidate_ptr);
-
- assert(!(bo_fake->flags & BM_PINNED));
-
- DBG("set_dirty - buf %d\n", bo_fake->id);
- bo_fake->dirty = 1;
-}
-
-static GLboolean
-evict_lru(dri_bufmgr_fake *bufmgr_fake, GLuint max_fence)
-{
- struct block *block, *tmp;
-
- DBG("%s\n", __FUNCTION__);
-
- foreach_s(block, tmp, &bufmgr_fake->lru) {
- dri_bo_fake *bo_fake = (dri_bo_fake *)block->bo;
-
- if (bo_fake != NULL && (bo_fake->flags & BM_NO_FENCE_SUBDATA))
- continue;
-
- if (block->fence && max_fence && !FENCE_LTE(block->fence, max_fence))
- return 0;
-
- set_dirty(&bo_fake->bo);
- bo_fake->block = NULL;
-
- free_block(bufmgr_fake, block);
- return GL_TRUE;
- }
-
- return GL_FALSE;
-}
-
-#define foreach_s_rev(ptr, t, list) \
- for(ptr=(list)->prev,t=(ptr)->prev; list != ptr; ptr=t, t=(t)->prev)
-
-static GLboolean
-evict_mru(dri_bufmgr_fake *bufmgr_fake)
-{
- struct block *block, *tmp;
-
- DBG("%s\n", __FUNCTION__);
-
- foreach_s_rev(block, tmp, &bufmgr_fake->lru) {
- dri_bo_fake *bo_fake = (dri_bo_fake *)block->bo;
-
- if (bo_fake && (bo_fake->flags & BM_NO_FENCE_SUBDATA))
- continue;
-
- set_dirty(&bo_fake->bo);
- bo_fake->block = NULL;
-
- free_block(bufmgr_fake, block);
- return GL_TRUE;
- }
-
- return GL_FALSE;
-}
-
-/**
- * Removes all objects from the fenced list older than the given fence.
- */
-static int clear_fenced(dri_bufmgr_fake *bufmgr_fake,
- unsigned int fence_cookie)
-{
- struct block *block, *tmp;
- int ret = 0;
-
- foreach_s(block, tmp, &bufmgr_fake->fenced) {
- assert(block->fenced);
-
- if (_fence_test(bufmgr_fake, block->fence)) {
-
- block->fenced = 0;
-
- if (!block->bo) {
- DBG("delayed free: offset %x sz %x\n",
- block->mem->ofs, block->mem->size);
- remove_from_list(block);
- mmFreeMem(block->mem);
- free(block);
- }
- else {
- DBG("return to lru: offset %x sz %x\n",
- block->mem->ofs, block->mem->size);
- move_to_tail(&bufmgr_fake->lru, block);
- }
-
- ret = 1;
- }
- else {
- /* Blocks are ordered by fence, so if one fails, all from
- * here will fail also:
- */
- DBG("fence not passed: offset %x sz %x %d %d \n",
- block->mem->ofs, block->mem->size, block->fence, bufmgr_fake->last_fence);
- break;
- }
- }
-
- DBG("%s: %d\n", __FUNCTION__, ret);
- return ret;
-}
-
-static void fence_blocks(dri_bufmgr_fake *bufmgr_fake, unsigned fence)
-{
- struct block *block, *tmp;
-
- foreach_s (block, tmp, &bufmgr_fake->on_hardware) {
- DBG("Fence block %p (sz 0x%x ofs %x buf %p) with fence %d\n", block,
- block->mem->size, block->mem->ofs, block->bo, fence);
- block->fence = fence;
-
- block->on_hardware = 0;
- block->fenced = 1;
-
- /* Move to tail of pending list here
- */
- move_to_tail(&bufmgr_fake->fenced, block);
- }
-
- assert(is_empty_list(&bufmgr_fake->on_hardware));
-}
-
-static GLboolean evict_and_alloc_block(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- assert(bo_fake->block == NULL);
-
- /* Search for already free memory:
- */
- if (alloc_block(bo))
- return GL_TRUE;
-
- /* If we're not thrashing, allow lru eviction to dig deeper into
- * recently used textures. We'll probably be thrashing soon:
- */
- if (!bufmgr_fake->thrashing) {
- while (evict_lru(bufmgr_fake, 0))
- if (alloc_block(bo))
- return GL_TRUE;
- }
-
- /* Keep thrashing counter alive?
- */
- if (bufmgr_fake->thrashing)
- bufmgr_fake->thrashing = 20;
-
- /* Wait on any already pending fences - here we are waiting for any
- * freed memory that has been submitted to hardware and fenced to
- * become available:
- */
- while (!is_empty_list(&bufmgr_fake->fenced)) {
- GLuint fence = bufmgr_fake->fenced.next->fence;
- _fence_wait_internal(bufmgr_fake, fence);
-
- if (alloc_block(bo))
- return GL_TRUE;
- }
-
- if (!is_empty_list(&bufmgr_fake->on_hardware)) {
- while (!is_empty_list(&bufmgr_fake->fenced)) {
- GLuint fence = bufmgr_fake->fenced.next->fence;
- _fence_wait_internal(bufmgr_fake, fence);
- }
-
- if (!bufmgr_fake->thrashing) {
- DBG("thrashing\n");
- }
- bufmgr_fake->thrashing = 20;
-
- if (alloc_block(bo))
- return GL_TRUE;
- }
-
- while (evict_mru(bufmgr_fake))
- if (alloc_block(bo))
- return GL_TRUE;
-
- DBG("%s 0x%x bytes failed\n", __FUNCTION__, bo->size);
-
- return GL_FALSE;
-}
-
-/***********************************************************************
- * Public functions
- */
-
-/**
- * Wait for hardware idle by emitting a fence and waiting for it.
- */
-static void
-dri_bufmgr_fake_wait_idle(dri_bufmgr_fake *bufmgr_fake)
-{
- unsigned int cookie;
-
- cookie = bufmgr_fake->fence_emit(bufmgr_fake->driver_priv);
- _fence_wait_internal(bufmgr_fake, cookie);
-}
-
-/**
- * Wait for execution pending on a buffer
- */
-static void
-dri_bufmgr_fake_bo_wait_idle(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- if (bo_fake->block == NULL || !bo_fake->block->fenced)
- return;
-
- _fence_wait_internal(bufmgr_fake, bo_fake->block->fence);
-}
-
-/* Specifically ignore texture memory sharing.
- * -- just evict everything
- * -- and wait for idle
- */
-void
-dri_bufmgr_fake_contended_lock_take(dri_bufmgr *bufmgr)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
- struct block *block, *tmp;
-
- bufmgr_fake->need_fence = 1;
- bufmgr_fake->fail = 0;
-
- /* Wait for hardware idle. We don't know where acceleration has been
- * happening, so we'll need to wait anyway before letting anything get
- * put on the card again.
- */
- dri_bufmgr_fake_wait_idle(bufmgr_fake);
-
- /* Check that we hadn't released the lock without having fenced the last
- * set of buffers.
- */
- assert(is_empty_list(&bufmgr_fake->fenced));
- assert(is_empty_list(&bufmgr_fake->on_hardware));
-
- foreach_s(block, tmp, &bufmgr_fake->lru) {
- assert(_fence_test(bufmgr_fake, block->fence));
- set_dirty(block->bo);
- }
-}
-
-static dri_bo *
-dri_fake_bo_alloc(dri_bufmgr *bufmgr, const char *name,
- unsigned long size, unsigned int alignment,
- uint64_t location_mask)
-{
- dri_bufmgr_fake *bufmgr_fake;
- dri_bo_fake *bo_fake;
-
- bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
-
- assert(size != 0);
-
- bo_fake = calloc(1, sizeof(*bo_fake));
- if (!bo_fake)
- return NULL;
-
- bo_fake->bo.size = size;
- bo_fake->bo.offset = -1;
- bo_fake->bo.virtual = NULL;
- bo_fake->bo.bufmgr = bufmgr;
- bo_fake->refcount = 1;
-
- /* Alignment must be a power of two */
- assert((alignment & (alignment - 1)) == 0);
- if (alignment == 0)
- alignment = 1;
- bo_fake->alignment = alignment;
- bo_fake->id = ++bufmgr_fake->buf_nr;
- bo_fake->name = name;
- bo_fake->flags = 0;
- bo_fake->is_static = GL_FALSE;
-
- DBG("drm_bo_alloc: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
- bo_fake->bo.size / 1024);
-
- return &bo_fake->bo;
-}
-
-static dri_bo *
-dri_fake_bo_alloc_static(dri_bufmgr *bufmgr, const char *name,
- unsigned long offset, unsigned long size,
- void *virtual, uint64_t location_mask)
-{
- dri_bufmgr_fake *bufmgr_fake;
- dri_bo_fake *bo_fake;
-
- bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
-
- assert(size != 0);
-
- bo_fake = calloc(1, sizeof(*bo_fake));
- if (!bo_fake)
- return NULL;
-
- bo_fake->bo.size = size;
- bo_fake->bo.offset = offset;
- bo_fake->bo.virtual = virtual;
- bo_fake->bo.bufmgr = bufmgr;
- bo_fake->refcount = 1;
- bo_fake->id = ++bufmgr_fake->buf_nr;
- bo_fake->name = name;
- bo_fake->flags = BM_PINNED | DRM_BO_FLAG_NO_MOVE;
- bo_fake->is_static = GL_TRUE;
-
- DBG("drm_bo_alloc_static: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
- bo_fake->bo.size / 1024);
-
- return &bo_fake->bo;
-}
-
-static void
-dri_fake_bo_reference(dri_bo *bo)
-{
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- bo_fake->refcount++;
-}
-
-static void
-dri_fake_bo_unreference(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- int i;
-
- if (!bo)
- return;
-
- if (--bo_fake->refcount == 0) {
- assert(bo_fake->map_count == 0);
- /* No remaining references, so free it */
- if (bo_fake->block)
- free_block(bufmgr_fake, bo_fake->block);
- free_backing_store(bo);
-
- for (i = 0; i < bo_fake->nr_relocs; i++)
- dri_bo_unreference(bo_fake->relocs[i].target_buf);
-
- DBG("drm_bo_unreference: free buf %d %s\n", bo_fake->id, bo_fake->name);
-
- free(bo_fake->relocs);
- free(bo);
-
- return;
- }
-}
-
-/**
- * Set the buffer as not requiring backing store, and instead get the callback
- * invoked whenever it would be set dirty.
- */
-void dri_bo_fake_disable_backing_store(dri_bo *bo,
- void (*invalidate_cb)(dri_bo *bo,
- void *ptr),
- void *ptr)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- if (bo_fake->backing_store)
- free_backing_store(bo);
-
- bo_fake->flags |= BM_NO_BACKING_STORE;
-
- DBG("disable_backing_store set buf %d dirty\n", bo_fake->id);
- bo_fake->dirty = 1;
- bo_fake->invalidate_cb = invalidate_cb;
- bo_fake->invalidate_ptr = ptr;
-
- /* Note that it is invalid right from the start. Also note
- * invalidate_cb is called with the bufmgr locked, so cannot
- * itself make bufmgr calls.
- */
- if (invalidate_cb != NULL)
- invalidate_cb(bo, ptr);
-}
-
-/**
- * Map a buffer into bo->virtual, allocating either card memory space (If
- * BM_NO_BACKING_STORE or BM_PINNED) or backing store, as necessary.
- */
-static int
-dri_fake_bo_map(dri_bo *bo, GLboolean write_enable)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- /* Static buffers are always mapped. */
- if (bo_fake->is_static)
- return 0;
-
- /* Allow recursive mapping. Mesa may recursively map buffers with
- * nested display loops, and it is used internally in bufmgr_fake
- * for relocation.
- */
- if (bo_fake->map_count++ != 0)
- return 0;
-
- {
- DBG("drm_bo_map: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
- bo_fake->bo.size / 1024);
-
- if (bo->virtual != NULL) {
- _mesa_printf("%s: already mapped\n", __FUNCTION__);
- abort();
- }
- else if (bo_fake->flags & (BM_NO_BACKING_STORE|BM_PINNED)) {
-
- if (!bo_fake->block && !evict_and_alloc_block(bo)) {
- DBG("%s: alloc failed\n", __FUNCTION__);
- bufmgr_fake->fail = 1;
- return 1;
- }
- else {
- assert(bo_fake->block);
- bo_fake->dirty = 0;
-
- if (!(bo_fake->flags & BM_NO_FENCE_SUBDATA) &&
- bo_fake->block->fenced) {
- dri_bufmgr_fake_bo_wait_idle(bo);
- }
-
- bo->virtual = bo_fake->block->virtual;
- }
- }
- else {
- if (write_enable)
- set_dirty(bo);
-
- if (bo_fake->backing_store == 0)
- alloc_backing_store(bo);
-
- bo->virtual = bo_fake->backing_store;
- }
- }
-
- return 0;
-}
-
-static int
-dri_fake_bo_unmap(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- /* Static buffers are always mapped. */
- if (bo_fake->is_static)
- return 0;
-
- assert(bo_fake->map_count != 0);
- if (--bo_fake->map_count != 0)
- return 0;
-
- DBG("drm_bo_unmap: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
- bo_fake->bo.size / 1024);
-
- bo->virtual = NULL;
-
- return 0;
-}
-
-static void
-dri_fake_kick_all(dri_bufmgr_fake *bufmgr_fake)
-{
- struct block *block, *tmp;
-
- bufmgr_fake->performed_rendering = GL_FALSE;
- /* okay for ever BO that is on the HW kick it off.
- seriously not afraid of the POLICE right now */
- foreach_s(block, tmp, &bufmgr_fake->on_hardware) {
- dri_bo_fake *bo_fake = (dri_bo_fake *)block->bo;
-
- block->on_hardware = 0;
- free_block(bufmgr_fake, block);
- bo_fake->block = NULL;
- bo_fake->validated = GL_FALSE;
- if (!(bo_fake->flags & BM_NO_BACKING_STORE))
- bo_fake->dirty = 1;
- }
-}
-
-static int
-dri_fake_bo_validate(dri_bo *bo, uint64_t flags)
-{
- dri_bufmgr_fake *bufmgr_fake;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- /* XXX: Sanity-check whether we've already validated this one under
- * different flags. See drmAddValidateItem().
- */
- bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
-
- DBG("drm_bo_validate: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
- bo_fake->bo.size / 1024);
-
- /* Sanity check: Buffers should be unmapped before being validated.
- * This is not so much of a problem for bufmgr_fake, but TTM refuses,
- * and the problem is harder to debug there.
- */
- assert(bo_fake->map_count == 0);
-
- if (bo_fake->is_static) {
- /* Add it to the needs-fence list */
- bufmgr_fake->need_fence = 1;
- return 0;
- }
-
- /* reset size accounted */
- bo_fake->size_accounted = 0;
-
- /* Allocate the card memory */
- if (!bo_fake->block && !evict_and_alloc_block(bo)) {
- bufmgr_fake->fail = 1;
- DBG("Failed to validate buf %d:%s\n", bo_fake->id, bo_fake->name);
- return -1;
- }
-
- assert(bo_fake->block);
- assert(bo_fake->block->bo == &bo_fake->bo);
-
- bo->offset = bo_fake->block->mem->ofs;
-
- /* Upload the buffer contents if necessary */
- if (bo_fake->dirty) {
- DBG("Upload dirty buf %d:%s, sz %d offset 0x%x\n", bo_fake->id,
- bo_fake->name, bo->size, bo_fake->block->mem->ofs);
-
- assert(!(bo_fake->flags &
- (BM_NO_BACKING_STORE|BM_PINNED)));
-
- /* Actually, should be able to just wait for a fence on the memory,
- * which we would be tracking when we free it. Waiting for idle is
- * a sufficiently large hammer for now.
- */
- dri_bufmgr_fake_wait_idle(bufmgr_fake);
-
- /* we may never have mapped this BO so it might not have any backing
- * store if this happens it should be rare, but 0 the card memory
- * in any case */
- if (bo_fake->backing_store)
- memcpy(bo_fake->block->virtual, bo_fake->backing_store, bo->size);
- else
- memset(bo_fake->block->virtual, 0, bo->size);
-
- bo_fake->dirty = 0;
- }
-
- bo_fake->block->fenced = 0;
- bo_fake->block->on_hardware = 1;
- move_to_tail(&bufmgr_fake->on_hardware, bo_fake->block);
-
- bo_fake->validated = GL_TRUE;
- bufmgr_fake->need_fence = 1;
-
- return 0;
-}
-
-static void
-dri_fake_fence_validated(dri_bufmgr *bufmgr)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
- unsigned int cookie;
-
- cookie = _fence_emit_internal(bufmgr_fake);
- fence_blocks(bufmgr_fake, cookie);
-
- DBG("drm_fence_validated: 0x%08x cookie\n", cookie);
-}
-
-static void
-dri_fake_destroy(dri_bufmgr *bufmgr)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
-
- mmDestroy(bufmgr_fake->heap);
- free(bufmgr);
-}
-
-static int
-dri_fake_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
- GLuint offset, dri_bo *target_buf)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)reloc_buf->bufmgr;
- struct fake_buffer_reloc *r;
- dri_bo_fake *reloc_fake = (dri_bo_fake *)reloc_buf;
- dri_bo_fake *target_fake = (dri_bo_fake *)target_buf;
- int i;
-
- assert(reloc_buf);
- assert(target_buf);
-
- assert(target_fake->is_static || target_fake->size_accounted);
-
- if (reloc_fake->relocs == NULL) {
- reloc_fake->relocs = malloc(sizeof(struct fake_buffer_reloc) *
- MAX_RELOCS);
- }
-
- r = &reloc_fake->relocs[reloc_fake->nr_relocs++];
-
- assert(reloc_fake->nr_relocs <= MAX_RELOCS);
-
- dri_bo_reference(target_buf);
-
- r->target_buf = target_buf;
- r->offset = offset;
- r->last_target_offset = target_buf->offset;
- r->delta = delta;
- r->validate_flags = flags;
-
- if (bufmgr_fake->debug) {
- /* Check that a conflicting relocation hasn't already been emitted. */
- for (i = 0; i < reloc_fake->nr_relocs - 1; i++) {
- struct fake_buffer_reloc *r2 = &reloc_fake->relocs[i];
-
- assert(r->offset != r2->offset);
- }
- }
-
- return 0;
-}
-
-/**
- * Incorporates the validation flags associated with each relocation into
- * the combined validation flags for the buffer on this batchbuffer submission.
- */
-static void
-dri_fake_calculate_validate_flags(dri_bo *bo)
-{
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- int i;
-
- for (i = 0; i < bo_fake->nr_relocs; i++) {
- struct fake_buffer_reloc *r = &bo_fake->relocs[i];
- dri_bo_fake *target_fake = (dri_bo_fake *)r->target_buf;
-
- /* Do the same for the tree of buffers we depend on */
- dri_fake_calculate_validate_flags(r->target_buf);
-
- if (target_fake->validate_flags == 0) {
- target_fake->validate_flags = r->validate_flags;
- } else {
- /* Mask the memory location to the intersection of all the memory
- * locations the buffer is being validated to.
- */
- target_fake->validate_flags =
- (target_fake->validate_flags & ~DRM_BO_MASK_MEM) |
- (r->validate_flags & target_fake->validate_flags &
- DRM_BO_MASK_MEM);
- /* All the other flags just accumulate. */
- target_fake->validate_flags |= r->validate_flags & ~DRM_BO_MASK_MEM;
- }
- }
-}
-
-
-static int
-dri_fake_reloc_and_validate_buffer(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- int i, ret;
-
- assert(bo_fake->map_count == 0);
-
- for (i = 0; i < bo_fake->nr_relocs; i++) {
- struct fake_buffer_reloc *r = &bo_fake->relocs[i];
- dri_bo_fake *target_fake = (dri_bo_fake *)r->target_buf;
- uint32_t reloc_data;
-
- /* Validate the target buffer if that hasn't been done. */
- if (!target_fake->validated) {
- ret = dri_fake_reloc_and_validate_buffer(r->target_buf);
- if (ret != 0) {
- if (bo->virtual != NULL)
- dri_bo_unmap(bo);
- return ret;
- }
- }
-
- /* Calculate the value of the relocation entry. */
- if (r->target_buf->offset != r->last_target_offset) {
- reloc_data = r->target_buf->offset + r->delta;
-
- if (bo->virtual == NULL)
- dri_bo_map(bo, GL_TRUE);
-
- *(uint32_t *)(bo->virtual + r->offset) = reloc_data;
-
- r->last_target_offset = r->target_buf->offset;
- }
- }
-
- if (bo->virtual != NULL)
- dri_bo_unmap(bo);
-
- if (bo_fake->validate_flags & DRM_BO_FLAG_WRITE) {
- if (!(bo_fake->flags & (BM_NO_BACKING_STORE|BM_PINNED))) {
- if (bo_fake->backing_store == 0)
- alloc_backing_store(bo);
-
- bo_fake->card_dirty = 1;
- }
- bufmgr_fake->performed_rendering = GL_TRUE;
- }
-
- return dri_fake_bo_validate(bo, bo_fake->validate_flags);
-}
-
-static void *
-dri_fake_process_relocs(dri_bo *batch_buf)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)batch_buf->bufmgr;
- dri_bo_fake *batch_fake = (dri_bo_fake *)batch_buf;
- int ret;
- int retry_count = 0;
-
- bufmgr_fake->performed_rendering = GL_FALSE;
-
- dri_fake_calculate_validate_flags(batch_buf);
-
- batch_fake->validate_flags = DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ;
-
- /* we've ran out of RAM so blow the whole lot away and retry */
- restart:
- ret = dri_fake_reloc_and_validate_buffer(batch_buf);
- if (bufmgr_fake->fail == 1) {
- if (retry_count == 0) {
- retry_count++;
- dri_fake_kick_all(bufmgr_fake);
- bufmgr_fake->fail = 0;
- goto restart;
- } else /* dump out the memory here */
- mmDumpMemInfo(bufmgr_fake->heap);
- }
-
- assert(ret == 0);
-
- bufmgr_fake->current_total_size = 0;
- return NULL;
-}
-
-static void
-dri_bo_fake_post_submit(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- int i;
-
- for (i = 0; i < bo_fake->nr_relocs; i++) {
- struct fake_buffer_reloc *r = &bo_fake->relocs[i];
- dri_bo_fake *target_fake = (dri_bo_fake *)r->target_buf;
-
- if (target_fake->validated)
- dri_bo_fake_post_submit(r->target_buf);
-
- DBG("%s@0x%08x + 0x%08x -> %s@0x%08x + 0x%08x\n",
- bo_fake->name, (uint32_t)bo->offset, r->offset,
- target_fake->name, (uint32_t)r->target_buf->offset, r->delta);
- }
-
- assert(bo_fake->map_count == 0);
- bo_fake->validated = GL_FALSE;
- bo_fake->validate_flags = 0;
-}
-
-
-static void
-dri_fake_post_submit(dri_bo *batch_buf)
-{
- dri_fake_fence_validated(batch_buf->bufmgr);
-
- dri_bo_fake_post_submit(batch_buf);
-}
-
-static int
-dri_fake_check_aperture_space(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- GLuint sz;
-
- sz = (bo->size + bo_fake->alignment - 1) & ~(bo_fake->alignment - 1);
-
- if (bo_fake->size_accounted || bo_fake->is_static)
- return 0;
-
- if (bufmgr_fake->current_total_size + sz > bufmgr_fake->size) {
- DBG("check_space: %s bo %d %d overflowed bufmgr size %d\n", bo_fake->name, bo_fake->id, sz, bufmgr_fake->size);
- return -1;
- }
-
- bufmgr_fake->current_total_size += sz;
- bo_fake->size_accounted = 1;
- DBG("drm_check_space: buf %d, %s %d %d\n", bo_fake->id, bo_fake->name, bo->size, bufmgr_fake->current_total_size);
- return 0;
-}
-
-dri_bufmgr *
-dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual,
- unsigned long size,
- unsigned int (*fence_emit)(void *private),
- int (*fence_wait)(void *private, unsigned int cookie),
- void *driver_priv)
-{
- dri_bufmgr_fake *bufmgr_fake;
-
- bufmgr_fake = calloc(1, sizeof(*bufmgr_fake));
-
- /* Initialize allocator */
- make_empty_list(&bufmgr_fake->fenced);
- make_empty_list(&bufmgr_fake->on_hardware);
- make_empty_list(&bufmgr_fake->lru);
-
- bufmgr_fake->low_offset = low_offset;
- bufmgr_fake->virtual = low_virtual;
- bufmgr_fake->size = size;
- bufmgr_fake->heap = mmInit(low_offset, size);
-
- /* Hook in methods */
- bufmgr_fake->bufmgr.bo_alloc = dri_fake_bo_alloc;
- bufmgr_fake->bufmgr.bo_alloc_static = dri_fake_bo_alloc_static;
- bufmgr_fake->bufmgr.bo_reference = dri_fake_bo_reference;
- bufmgr_fake->bufmgr.bo_unreference = dri_fake_bo_unreference;
- bufmgr_fake->bufmgr.bo_map = dri_fake_bo_map;
- bufmgr_fake->bufmgr.bo_unmap = dri_fake_bo_unmap;
- bufmgr_fake->bufmgr.destroy = dri_fake_destroy;
- bufmgr_fake->bufmgr.emit_reloc = dri_fake_emit_reloc;
- bufmgr_fake->bufmgr.process_relocs = dri_fake_process_relocs;
- bufmgr_fake->bufmgr.post_submit = dri_fake_post_submit;
- bufmgr_fake->bufmgr.check_aperture_space = dri_fake_check_aperture_space;
- bufmgr_fake->bufmgr.debug = GL_FALSE;
-
- bufmgr_fake->fence_emit = fence_emit;
- bufmgr_fake->fence_wait = fence_wait;
- bufmgr_fake->driver_priv = driver_priv;
-
- return &bufmgr_fake->bufmgr;
-}
-
diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index 67f251a7fa..476814c4ec 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -54,6 +54,7 @@ DRIVER_SOURCES = \
intel_tris.c \
intel_fbo.c \
intel_depthstencil.c \
+ intel_bufmgr_fake.c \
intel_bufmgr_gem.c
C_SOURCES = \
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index c5a85fe035..86bf468a7e 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -490,14 +490,14 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+ DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
state->draw_region->draw_offset);
if (state->depth_region) {
OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
OUT_RELOC(state->depth_region->buffer,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+ DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
state->depth_region->draw_offset);
}
@@ -524,7 +524,7 @@ i830_emit_state(struct intel_context *intel)
if (state->tex_buffer[i]) {
OUT_RELOC(state->tex_buffer[i],
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_SAMPLER, 0,
state->tex_offset[i] | TM0S0_USE_FENCE);
}
else if (state == &i830->meta) {
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 135bfaa265..de1ec5effc 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -377,14 +377,14 @@ i915_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+ DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
state->draw_region->draw_offset);
if (state->depth_region) {
OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
OUT_RELOC(state->depth_region->buffer,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+ DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
state->depth_region->draw_offset);
}
@@ -427,7 +427,7 @@ i915_emit_state(struct intel_context *intel)
if (state->tex_buffer[i]) {
OUT_RELOC(state->tex_buffer[i],
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_SAMPLER, 0,
state->tex_offset[i]);
}
else if (state == &i915->meta) {
diff --git a/src/mesa/drivers/dri/i915/intel_bufmgr_fake.c b/src/mesa/drivers/dri/i915/intel_bufmgr_fake.c
new file mode 120000
index 0000000000..9b840a8123
--- /dev/null
+++ b/src/mesa/drivers/dri/i915/intel_bufmgr_fake.c
@@ -0,0 +1 @@
+../intel/intel_bufmgr_fake.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index ca9b7da40f..001f63ba12 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -9,6 +9,7 @@ DRIVER_SOURCES = \
intel_blit.c \
intel_buffer_objects.c \
intel_buffers.c \
+ intel_bufmgr_fake.c \
intel_bufmgr_gem.c \
intel_context.c \
intel_decode.c \
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index 9d8984f05c..b9338db0f5 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -257,7 +257,8 @@ cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key)
/* Emit CC viewport relocation */
dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION,
+ 0,
0,
offsetof(struct brw_cc_unit_state, cc4),
brw->cc.vp_bo);
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 7cb21f894e..26c322672c 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -120,7 +120,8 @@ clip_unit_create_from_key(struct brw_context *brw,
/* Emit clip program relocation */
assert(brw->clip.prog_bo);
dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION,
+ 0,
clip.thread0.grf_reg_count << 1,
offsetof(struct brw_clip_unit_state, thread0),
brw->clip.prog_bo);
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 5ff4e2964e..1b5e22f130 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -353,7 +353,8 @@ static void emit_constant_buffer(struct brw_context *brw)
OUT_BATCH(0);
} else {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
- OUT_RELOC(brw->curbe.curbe_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ OUT_RELOC(brw->curbe.curbe_bo,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
(sz - 1) + brw->curbe.curbe_offset);
}
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index aa985d68b6..5222d2e450 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -469,7 +469,7 @@ void brw_emit_vertices( struct brw_context *brw,
BRW_VB0_ACCESS_VERTEXDATA |
(input->stride << BRW_VB0_PITCH_SHIFT));
OUT_RELOC(input->bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_VERTEX, 0,
input->offset);
OUT_BATCH(max_index);
OUT_BATCH(0); /* Instance data step rate */
@@ -590,8 +590,11 @@ void brw_emit_indices(struct brw_context *brw,
BEGIN_BATCH(4, IGNORE_CLIPRECTS);
OUT_BATCH( ib.header.dword );
- OUT_RELOC( bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, offset);
- OUT_RELOC( bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ OUT_RELOC( bo,
+ DRM_GEM_DOMAIN_I915_VERTEX, 0,
+ offset);
+ OUT_RELOC( bo,
+ DRM_GEM_DOMAIN_I915_VERTEX, 0,
offset + ib_size);
OUT_BATCH( 0 );
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index f1f9e018f1..2bf86f5573 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -107,7 +107,7 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
if (key->prog_active) {
/* Emit GS program relocation */
dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
gs.thread0.grf_reg_count << 1,
offsetof(struct brw_gs_unit_state, thread0),
brw->gs.prog_bo);
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 26ec797b5f..24dfd2e24e 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -88,7 +88,9 @@ static void upload_binding_table_pointers(struct brw_context *brw)
OUT_BATCH(0); /* gs */
OUT_BATCH(0); /* clip */
OUT_BATCH(0); /* sf */
- OUT_RELOC(brw->wm.bind_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
+ OUT_RELOC(brw->wm.bind_bo,
+ DRM_GEM_DOMAIN_I915_SAMPLER, 0,
+ 0);
ADVANCE_BATCH();
}
@@ -114,18 +116,18 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
BEGIN_BATCH(7, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
- OUT_RELOC(brw->vs.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
+ OUT_RELOC(brw->vs.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
if (brw->gs.prog_active)
- OUT_RELOC(brw->gs.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 1);
+ OUT_RELOC(brw->gs.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 1);
else
OUT_BATCH(0);
if (!brw->metaops.active)
- OUT_RELOC(brw->clip.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 1);
+ OUT_RELOC(brw->clip.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 1);
else
OUT_BATCH(0);
- OUT_RELOC(brw->sf.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
- OUT_RELOC(brw->wm.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
- OUT_RELOC(brw->cc.state_bo, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
+ OUT_RELOC(brw->sf.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
+ OUT_RELOC(brw->wm.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
+ OUT_RELOC(brw->cc.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
ADVANCE_BATCH();
brw->state.dirty.brw |= BRW_NEW_PSP;
@@ -233,7 +235,8 @@ static void emit_depthbuffer(struct brw_context *brw)
(region->tiled << 27) |
(BRW_SURFACE_2D << 29));
OUT_RELOC(region->buffer,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0);
+ DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ 0);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
((region->pitch - 1) << 6) |
((region->height - 1) << 19));
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 24388b79a5..5cf3228486 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -254,14 +254,14 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
/* Emit SF program relocation */
dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
sf.thread0.grf_reg_count << 1,
offsetof(struct brw_sf_unit_state, thread0),
brw->sf.prog_bo);
/* Emit SF viewport relocation */
dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
offsetof(struct brw_sf_unit_state, sf5),
brw->sf.vp_bo);
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index 2a64f3df33..73f52d7428 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -116,7 +116,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
/* Emit VS program relocation */
dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
vs.thread0.grf_reg_count << 1,
offsetof(struct brw_vs_unit_state, thread0),
brw->vs.prog_bo);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index d40332e9ae..13f7f21800 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -306,7 +306,7 @@ static int upload_wm_samplers( struct brw_context *brw )
ret |= dri_bufmgr_check_aperture_space(brw->wm.sdc_bo[i]);
dri_emit_reloc(brw->wm.sampler_bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
0,
i * sizeof(struct brw_sampler_state) +
offsetof(struct brw_sampler_state, ss2),
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index f4da0f279e..f79b58ba7a 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -200,7 +200,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
/* Emit WM program relocation */
dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
wm.thread0.grf_reg_count << 1,
offsetof(struct brw_wm_unit_state, thread0),
brw->wm.prog_bo);
@@ -208,7 +208,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
/* Emit scratch space relocation */
if (key->total_scratch != 0) {
dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE,
+ 0, 0,
wm.thread2.per_thread_scratch_space,
offsetof(struct brw_wm_unit_state, thread2),
brw->wm.scratch_buffer);
@@ -217,7 +217,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
/* Emit sampler state relocation */
if (key->sampler_count != 0) {
dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
offsetof(struct brw_wm_unit_state, wm4),
brw->wm.sampler_bo);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 0d91391964..73f4b2b4a3 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -204,7 +204,7 @@ brw_create_texture_surface( struct brw_context *brw,
/* Emit relocation to surface contents */
dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ DRM_GEM_DOMAIN_I915_SAMPLER, 0,
0,
offsetof(struct brw_surface_state, ss1),
key->bo);
@@ -337,10 +337,14 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
&surf, sizeof(surf),
NULL, NULL);
if (region_bo != NULL) {
+ /* We might sample from it, and we might render to it, so flag
+ * them both. We might be able to figure out from other state
+ * a more restrictive relocation to emit.
+ */
dri_emit_reloc(brw->wm.surf_bo[unit],
- DRM_BO_FLAG_MEM_TT |
- DRM_BO_FLAG_READ |
- DRM_BO_FLAG_WRITE,
+ DRM_GEM_DOMAIN_I915_RENDER |
+ DRM_GEM_DOMAIN_I915_SAMPLER,
+ DRM_GEM_DOMAIN_I915_RENDER,
0,
offsetof(struct brw_surface_state, ss1),
region_bo);
@@ -388,9 +392,7 @@ brw_wm_get_binding_table(struct brw_context *brw)
for (i = 0; i < BRW_WM_MAX_SURF; i++) {
if (brw->wm.surf_bo[i] != NULL) {
dri_emit_reloc(bind_bo,
- DRM_BO_FLAG_MEM_TT |
- DRM_BO_FLAG_READ |
- DRM_BO_FLAG_WRITE,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
0,
i * sizeof(GLuint),
brw->wm.surf_bo[i]);
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_fake.c b/src/mesa/drivers/dri/i965/intel_bufmgr_fake.c
new file mode 120000
index 0000000000..9b840a8123
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_fake.c
@@ -0,0 +1 @@
+../intel/intel_bufmgr_fake.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index bab8e645d4..f22e6c0967 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -267,11 +267,13 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
GLboolean
intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
dri_bo *buffer,
- GLuint flags, GLuint delta)
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t delta)
{
int ret;
- ret = dri_emit_reloc(batch->buf, flags, delta, batch->ptr - batch->map, buffer);
+ ret = dri_emit_reloc(batch->buf, read_domains, write_domain,
+ delta, batch->ptr - batch->map, buffer);
/*
* Using the old buffer offset, write in what the right data would be, in case
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
index feddfb46df..7268bd59da 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
@@ -79,7 +79,9 @@ void intel_batchbuffer_release_space(struct intel_batchbuffer *batch,
GLboolean intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
dri_bo *buffer,
- GLuint flags, GLuint offset);
+ uint32_t read_domains,
+ uint32_t write_domain,
+ uint32_t offset);
/* Inline functions - might actually be better off with these
* non-inlined. Certainly better off switching all command packets to
@@ -131,9 +133,10 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
#define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel->batch, d)
-#define OUT_RELOC(buf, cliprect_mode, delta) do { \
+#define OUT_RELOC(buf, read_domains, write_domain, delta) do { \
assert((delta) >= 0); \
- intel_batchbuffer_emit_reloc(intel->batch, buf, cliprect_mode, delta); \
+ intel_batchbuffer_emit_reloc(intel->batch, buf, \
+ read_domains, write_domain, delta); \
} while (0)
#define ADVANCE_BATCH() do { } while(0)
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index b7d36d8cd6..3d7f64e28b 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -148,10 +148,14 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
OUT_BATCH((box.y1 << 16) | box.x1);
OUT_BATCH((box.y2 << 16) | box.x2);
- OUT_RELOC(dst->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, 0);
+ OUT_RELOC(dst->buffer,
+ DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ 0);
OUT_BATCH((src_y << 16) | src_x);
OUT_BATCH(src_pitch);
- OUT_RELOC(src->buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, 0);
+ OUT_RELOC(src->buffer,
+ DRM_GEM_DOMAIN_I915_RENDER, 0,
+ 0);
ADVANCE_BATCH();
}
@@ -212,7 +216,9 @@ intelEmitFillBlit(struct intel_context *intel,
OUT_BATCH(BR13 | dst_pitch);
OUT_BATCH((y << 16) | x);
OUT_BATCH(((y + h) << 16) | (x + w));
- OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, dst_offset);
+ OUT_RELOC(dst_buffer,
+ DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ dst_offset);
OUT_BATCH(color);
ADVANCE_BATCH();
}
@@ -332,11 +338,13 @@ intelEmitCopyBlit(struct intel_context *intel,
OUT_BATCH(BR13 | dst_pitch);
OUT_BATCH((dst_y << 16) | dst_x);
OUT_BATCH((dst_y2 << 16) | dst_x2);
- OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+ OUT_RELOC(dst_buffer,
+ DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
dst_offset);
OUT_BATCH((src_y << 16) | src_x);
OUT_BATCH(src_pitch);
- OUT_RELOC(src_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ OUT_RELOC(src_buffer,
+ DRM_GEM_DOMAIN_I915_RENDER, 0,
src_offset);
ADVANCE_BATCH();
}
@@ -349,11 +357,13 @@ intelEmitCopyBlit(struct intel_context *intel,
OUT_BATCH(BR13 | dst_pitch);
OUT_BATCH((0 << 16) | dst_x);
OUT_BATCH((h << 16) | dst_x2);
- OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+ OUT_RELOC(dst_buffer,
+ DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
dst_offset + dst_y * dst_pitch);
OUT_BATCH((0 << 16) | src_x);
OUT_BATCH(src_pitch);
- OUT_RELOC(src_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ OUT_RELOC(src_buffer,
+ DRM_GEM_DOMAIN_I915_RENDER, 0,
src_offset + src_y * src_pitch);
ADVANCE_BATCH();
}
@@ -528,7 +538,8 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
OUT_BATCH(BR13);
OUT_BATCH((b.y1 << 16) | b.x1);
OUT_BATCH((b.y2 << 16) | b.x2);
- OUT_RELOC(write_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
+ OUT_RELOC(write_buffer,
+ DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
irb_region->draw_offset);
OUT_BATCH(clearVal);
ADVANCE_BATCH();
@@ -600,7 +611,9 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
OUT_BATCH(br13);
OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
- OUT_RELOC(dst_buffer, DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE, dst_offset);
+ OUT_RELOC(dst_buffer,
+ DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ dst_offset);
OUT_BATCH(0); /* bg */
OUT_BATCH(fg_color); /* fg */
OUT_BATCH(0); /* pattern base addr */
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_fake.c b/src/mesa/drivers/dri/intel/intel_bufmgr_fake.c
new file mode 100644
index 0000000000..5d01a471c5
--- /dev/null
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_fake.c
@@ -0,0 +1,1173 @@
+/**************************************************************************
+ *
+ * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+/* Originally a fake version of the buffer manager so that we can
+ * prototype the changes in a driver fairly quickly, has been fleshed
+ * out to a fully functional interim solution.
+ *
+ * Basically wraps the old style memory management in the new
+ * programming interface, but is more expressive and avoids many of
+ * the bugs in the old texture manager.
+ */
+#include "mtypes.h"
+#include "dri_bufmgr.h"
+#include "intel_bufmgr_fake.h"
+#include "drm.h"
+#include "i915_drm.h"
+
+#include "simple_list.h"
+#include "mm.h"
+#include "imports.h"
+
+#define DBG(...) do { \
+ if (bufmgr_fake->bufmgr.debug) \
+ _mesa_printf(__VA_ARGS__); \
+} while (0)
+
+/* Internal flags:
+ */
+#define BM_NO_BACKING_STORE 0x00000001
+#define BM_NO_FENCE_SUBDATA 0x00000002
+#define BM_PINNED 0x00000004
+
+/* Wrapper around mm.c's mem_block, which understands that you must
+ * wait for fences to expire before memory can be freed. This is
+ * specific to our use of memcpy for uploads - an upload that was
+ * processed through the command queue wouldn't need to care about
+ * fences.
+ */
+#define MAX_RELOCS 4096
+
+struct fake_buffer_reloc
+{
+ /** Buffer object that the relocation points at. */
+ dri_bo *target_buf;
+ /** Offset of the relocation entry within reloc_buf. */
+ GLuint offset;
+ /** Cached value of the offset when we last performed this relocation. */
+ GLuint last_target_offset;
+ /** Value added to target_buf's offset to get the relocation entry. */
+ GLuint delta;
+ /** Cache domains the target buffer is read into. */
+ uint32_t read_domains;
+ /** Cache domain the target buffer will have dirty cachelines in. */
+ uint32_t write_domain;
+};
+
+struct block {
+ struct block *next, *prev;
+ struct mem_block *mem; /* BM_MEM_AGP */
+
+ /**
+ * Marks that the block is currently in the aperture and has yet to be
+ * fenced.
+ */
+ unsigned on_hardware:1;
+ /**
+ * Marks that the block is currently fenced (being used by rendering) and
+ * can't be freed until @fence is passed.
+ */
+ unsigned fenced:1;
+
+ /** Fence cookie for the block. */
+ unsigned fence; /* Split to read_fence, write_fence */
+
+ dri_bo *bo;
+ void *virtual;
+};
+
+typedef struct _bufmgr_fake {
+ dri_bufmgr bufmgr;
+
+ unsigned long low_offset;
+ unsigned long size;
+ void *virtual;
+
+ struct mem_block *heap;
+ struct block lru; /* only allocated, non-fence-pending blocks here */
+
+ unsigned buf_nr; /* for generating ids */
+
+ struct block on_hardware; /* after bmValidateBuffers */
+ struct block fenced; /* after bmFenceBuffers (mi_flush, emit irq, write dword) */
+ /* then to bufmgr->lru or free() */
+
+ unsigned int last_fence;
+
+ unsigned fail:1;
+ unsigned need_fence:1;
+ GLboolean thrashing;
+
+ /**
+ * Driver callback to emit a fence, returning the cookie.
+ *
+ * Currently, this also requires that a write flush be emitted before
+ * emitting the fence, but this should change.
+ */
+ unsigned int (*fence_emit)(void *private);
+ /** Driver callback to wait for a fence cookie to have passed. */
+ int (*fence_wait)(void *private, unsigned int fence_cookie);
+ /** Driver-supplied argument to driver callbacks */
+ void *driver_priv;
+
+ GLboolean debug;
+
+ GLboolean performed_rendering;
+
+ /* keep track of the current total size of objects we have relocs for */
+ unsigned long current_total_size;
+} dri_bufmgr_fake;
+
+typedef struct _dri_bo_fake {
+ dri_bo bo;
+
+ unsigned id; /* debug only */
+ const char *name;
+
+ unsigned dirty:1;
+ unsigned size_accounted:1; /*this buffers size has been accounted against the aperture */
+ unsigned card_dirty:1; /* has the card written to this buffer - we make need to copy it back */
+ unsigned int refcount;
+ /* Flags may consist of any of the DRM_BO flags, plus
+ * DRM_BO_NO_BACKING_STORE and BM_NO_FENCE_SUBDATA, which are the first two
+ * driver private flags.
+ */
+ uint64_t flags;
+ /** Cache domains the target buffer is read into. */
+ uint32_t read_domains;
+ /** Cache domain the target buffer will have dirty cachelines in. */
+ uint32_t write_domain;
+
+ unsigned int alignment;
+ GLboolean is_static, validated;
+ unsigned int map_count;
+
+ /** relocation list */
+ struct fake_buffer_reloc *relocs;
+ GLuint nr_relocs;
+
+ struct block *block;
+ void *backing_store;
+ void (*invalidate_cb)(dri_bo *bo, void *ptr);
+ void *invalidate_ptr;
+} dri_bo_fake;
+
+static int clear_fenced(dri_bufmgr_fake *bufmgr_fake,
+ unsigned int fence_cookie);
+
+static int dri_fake_check_aperture_space(dri_bo *bo);
+
+#define MAXFENCE 0x7fffffff
+
+static GLboolean FENCE_LTE( unsigned a, unsigned b )
+{
+ if (a == b)
+ return GL_TRUE;
+
+ if (a < b && b - a < (1<<24))
+ return GL_TRUE;
+
+ if (a > b && MAXFENCE - a + b < (1<<24))
+ return GL_TRUE;
+
+ return GL_FALSE;
+}
+
+static unsigned int
+_fence_emit_internal(dri_bufmgr_fake *bufmgr_fake)
+{
+ bufmgr_fake->last_fence = bufmgr_fake->fence_emit(bufmgr_fake->driver_priv);
+ return bufmgr_fake->last_fence;
+}
+
+static void
+_fence_wait_internal(dri_bufmgr_fake *bufmgr_fake, unsigned int cookie)
+{
+ int ret;
+
+ ret = bufmgr_fake->fence_wait(bufmgr_fake->driver_priv, cookie);
+ if (ret != 0) {
+ _mesa_printf("%s:%d: Error %d waiting for fence.\n",
+ __FILE__, __LINE__);
+ abort();
+ }
+ clear_fenced(bufmgr_fake, cookie);
+}
+
+static GLboolean
+_fence_test(dri_bufmgr_fake *bufmgr_fake, unsigned fence)
+{
+ /* Slight problem with wrap-around:
+ */
+ return fence == 0 || FENCE_LTE(fence, bufmgr_fake->last_fence);
+}
+
+/**
+ * Allocate a memory manager block for the buffer.
+ */
+static GLboolean
+alloc_block(dri_bo *bo)
+{
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+ dri_bufmgr_fake *bufmgr_fake= (dri_bufmgr_fake *)bo->bufmgr;
+ struct block *block = (struct block *)calloc(sizeof *block, 1);
+ unsigned int align_log2 = _mesa_ffs(bo_fake->alignment) - 1;
+ GLuint sz;
+
+ if (!block)
+ return GL_FALSE;
+
+ sz = (bo->size + bo_fake->alignment - 1) & ~(bo_fake->alignment - 1);
+
+ block->mem = mmAllocMem(bufmgr_fake->heap, sz, align_log2, 0);
+ if (!block->mem) {
+ free(block);
+ return GL_FALSE;
+ }
+
+ make_empty_list(block);
+
+ /* Insert at head or at tail???
+ */
+ insert_at_tail(&bufmgr_fake->lru, block);
+
+ block->virtual = bufmgr_fake->virtual +
+ block->mem->ofs - bufmgr_fake->low_offset;
+ block->bo = bo;
+
+ bo_fake->block = block;
+
+ return GL_TRUE;
+}
+
+/* Release the card storage associated with buf:
+ */
+static void free_block(dri_bufmgr_fake *bufmgr_fake, struct block *block)
+{
+ dri_bo_fake *bo_fake;
+ DBG("free block %p %08x %d %d\n", block, block->mem->ofs, block->on_hardware, block->fenced);
+
+ if (!block)
+ return;
+
+ bo_fake = (dri_bo_fake *)block->bo;
+ if (!(bo_fake->flags & BM_NO_BACKING_STORE) && (bo_fake->card_dirty == 1)) {
+ memcpy(bo_fake->backing_store, block->virtual, block->bo->size);
+ bo_fake->card_dirty = 1;
+ bo_fake->dirty = 1;
+ }
+
+ if (block->on_hardware) {
+ block->bo = NULL;
+ }
+ else if (block->fenced) {
+ block->bo = NULL;
+ }
+ else {
+ DBG(" - free immediately\n");
+ remove_from_list(block);
+
+ mmFreeMem(block->mem);
+ free(block);
+ }
+}
+
+static void
+alloc_backing_store(dri_bo *bo)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+ assert(!bo_fake->backing_store);
+ assert(!(bo_fake->flags & (BM_PINNED|BM_NO_BACKING_STORE)));
+
+ bo_fake->backing_store = ALIGN_MALLOC(bo->size, 64);
+
+ DBG("alloc_backing - buf %d %p %d\n", bo_fake->id, bo_fake->backing_store, bo->size);
+ assert(bo_fake->backing_store);
+}
+
+static void
+free_backing_store(dri_bo *bo)
+{
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+
+ if (bo_fake->backing_store) {
+ assert(!(bo_fake->flags & (BM_PINNED|BM_NO_BACKING_STORE)));
+ ALIGN_FREE(bo_fake->backing_store);
+ bo_fake->backing_store = NULL;
+ }
+}
+
+static void
+set_dirty(dri_bo *bo)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+
+ if (bo_fake->flags & BM_NO_BACKING_STORE && bo_fake->invalidate_cb != NULL)
+ bo_fake->invalidate_cb(bo, bo_fake->invalidate_ptr);
+
+ assert(!(bo_fake->flags & BM_PINNED));
+
+ DBG("set_dirty - buf %d\n", bo_fake->id);
+ bo_fake->dirty = 1;
+}
+
+static GLboolean
+evict_lru(dri_bufmgr_fake *bufmgr_fake, GLuint max_fence)
+{
+ struct block *block, *tmp;
+
+ DBG("%s\n", __FUNCTION__);
+
+ foreach_s(block, tmp, &bufmgr_fake->lru) {
+ dri_bo_fake *bo_fake = (dri_bo_fake *)block->bo;
+
+ if (bo_fake != NULL && (bo_fake->flags & BM_NO_FENCE_SUBDATA))
+ continue;
+
+ if (block->fence && max_fence && !FENCE_LTE(block->fence, max_fence))
+ return 0;
+
+ set_dirty(&bo_fake->bo);
+ bo_fake->block = NULL;
+
+ free_block(bufmgr_fake, block);
+ return GL_TRUE;
+ }
+
+ return GL_FALSE;
+}
+
+#define foreach_s_rev(ptr, t, list) \
+ for(ptr=(list)->prev,t=(ptr)->prev; list != ptr; ptr=t, t=(t)->prev)
+
+static GLboolean
+evict_mru(dri_bufmgr_fake *bufmgr_fake)
+{
+ struct block *block, *tmp;
+
+ DBG("%s\n", __FUNCTION__);
+
+ foreach_s_rev(block, tmp, &bufmgr_fake->lru) {
+ dri_bo_fake *bo_fake = (dri_bo_fake *)block->bo;
+
+ if (bo_fake && (bo_fake->flags & BM_NO_FENCE_SUBDATA))
+ continue;
+
+ set_dirty(&bo_fake->bo);
+ bo_fake->block = NULL;
+
+ free_block(bufmgr_fake, block);
+ return GL_TRUE;
+ }
+
+ return GL_FALSE;
+}
+
+/**
+ * Removes all objects from the fenced list older than the given fence.
+ */
+static int clear_fenced(dri_bufmgr_fake *bufmgr_fake,
+ unsigned int fence_cookie)
+{
+ struct block *block, *tmp;
+ int ret = 0;
+
+ foreach_s(block, tmp, &bufmgr_fake->fenced) {
+ assert(block->fenced);
+
+ if (_fence_test(bufmgr_fake, block->fence)) {
+
+ block->fenced = 0;
+
+ if (!block->bo) {
+ DBG("delayed free: offset %x sz %x\n",
+ block->mem->ofs, block->mem->size);
+ remove_from_list(block);
+ mmFreeMem(block->mem);
+ free(block);
+ }
+ else {
+ DBG("return to lru: offset %x sz %x\n",
+ block->mem->ofs, block->mem->size);
+ move_to_tail(&bufmgr_fake->lru, block);
+ }
+
+ ret = 1;
+ }
+ else {
+ /* Blocks are ordered by fence, so if one fails, all from
+ * here will fail also:
+ */
+ DBG("fence not passed: offset %x sz %x %d %d \n",
+ block->mem->ofs, block->mem->size, block->fence, bufmgr_fake->last_fence);
+ break;
+ }
+ }
+
+ DBG("%s: %d\n", __FUNCTION__, ret);
+ return ret;
+}
+
+static void fence_blocks(dri_bufmgr_fake *bufmgr_fake, unsigned fence)
+{
+ struct block *block, *tmp;
+
+ foreach_s (block, tmp, &bufmgr_fake->on_hardware) {
+ DBG("Fence block %p (sz 0x%x ofs %x buf %p) with fence %d\n", block,
+ block->mem->size, block->mem->ofs, block->bo, fence);
+ block->fence = fence;
+
+ block->on_hardware = 0;
+ block->fenced = 1;
+
+ /* Move to tail of pending list here
+ */
+ move_to_tail(&bufmgr_fake->fenced, block);
+ }
+
+ assert(is_empty_list(&bufmgr_fake->on_hardware));
+}
+
+static GLboolean evict_and_alloc_block(dri_bo *bo)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+
+ assert(bo_fake->block == NULL);
+
+ /* Search for already free memory:
+ */
+ if (alloc_block(bo))
+ return GL_TRUE;
+
+ /* If we're not thrashing, allow lru eviction to dig deeper into
+ * recently used textures. We'll probably be thrashing soon:
+ */
+ if (!bufmgr_fake->thrashing) {
+ while (evict_lru(bufmgr_fake, 0))
+ if (alloc_block(bo))
+ return GL_TRUE;
+ }
+
+ /* Keep thrashing counter alive?
+ */
+ if (bufmgr_fake->thrashing)
+ bufmgr_fake->thrashing = 20;
+
+ /* Wait on any already pending fences - here we are waiting for any
+ * freed memory that has been submitted to hardware and fenced to
+ * become available:
+ */
+ while (!is_empty_list(&bufmgr_fake->fenced)) {
+ GLuint fence = bufmgr_fake->fenced.next->fence;
+ _fence_wait_internal(bufmgr_fake, fence);
+
+ if (alloc_block(bo))
+ return GL_TRUE;
+ }
+
+ if (!is_empty_list(&bufmgr_fake->on_hardware)) {
+ while (!is_empty_list(&bufmgr_fake->fenced)) {
+ GLuint fence = bufmgr_fake->fenced.next->fence;
+ _fence_wait_internal(bufmgr_fake, fence);
+ }
+
+ if (!bufmgr_fake->thrashing) {
+ DBG("thrashing\n");
+ }
+ bufmgr_fake->thrashing = 20;
+
+ if (alloc_block(bo))
+ return GL_TRUE;
+ }
+
+ while (evict_mru(bufmgr_fake))
+ if (alloc_block(bo))
+ return GL_TRUE;
+
+ DBG("%s 0x%x bytes failed\n", __FUNCTION__, bo->size);
+
+ return GL_FALSE;
+}
+
+/***********************************************************************
+ * Public functions
+ */
+
+/**
+ * Wait for hardware idle by emitting a fence and waiting for it.
+ */
+static void
+dri_bufmgr_fake_wait_idle(dri_bufmgr_fake *bufmgr_fake)
+{
+ unsigned int cookie;
+
+ cookie = bufmgr_fake->fence_emit(bufmgr_fake->driver_priv);
+ _fence_wait_internal(bufmgr_fake, cookie);
+}
+
+/**
+ * Wait for execution pending on a buffer
+ */
+static void
+dri_bufmgr_fake_bo_wait_idle(dri_bo *bo)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+
+ if (bo_fake->block == NULL || !bo_fake->block->fenced)
+ return;
+
+ _fence_wait_internal(bufmgr_fake, bo_fake->block->fence);
+}
+
+/* Specifically ignore texture memory sharing.
+ * -- just evict everything
+ * -- and wait for idle
+ */
+void
+dri_bufmgr_fake_contended_lock_take(dri_bufmgr *bufmgr)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
+ struct block *block, *tmp;
+
+ bufmgr_fake->need_fence = 1;
+ bufmgr_fake->fail = 0;
+
+ /* Wait for hardware idle. We don't know where acceleration has been
+ * happening, so we'll need to wait anyway before letting anything get
+ * put on the card again.
+ */
+ dri_bufmgr_fake_wait_idle(bufmgr_fake);
+
+ /* Check that we hadn't released the lock without having fenced the last
+ * set of buffers.
+ */
+ assert(is_empty_list(&bufmgr_fake->fenced));
+ assert(is_empty_list(&bufmgr_fake->on_hardware));
+
+ foreach_s(block, tmp, &bufmgr_fake->lru) {
+ assert(_fence_test(bufmgr_fake, block->fence));
+ set_dirty(block->bo);
+ }
+}
+
+static dri_bo *
+dri_fake_bo_alloc(dri_bufmgr *bufmgr, const char *name,
+ unsigned long size, unsigned int alignment,
+ uint64_t location_mask)
+{
+ dri_bufmgr_fake *bufmgr_fake;
+ dri_bo_fake *bo_fake;
+
+ bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
+
+ assert(size != 0);
+
+ bo_fake = calloc(1, sizeof(*bo_fake));
+ if (!bo_fake)
+ return NULL;
+
+ bo_fake->bo.size = size;
+ bo_fake->bo.offset = -1;
+ bo_fake->bo.virtual = NULL;
+ bo_fake->bo.bufmgr = bufmgr;
+ bo_fake->refcount = 1;
+
+ /* Alignment must be a power of two */
+ assert((alignment & (alignment - 1)) == 0);
+ if (alignment == 0)
+ alignment = 1;
+ bo_fake->alignment = alignment;
+ bo_fake->id = ++bufmgr_fake->buf_nr;
+ bo_fake->name = name;
+ bo_fake->flags = 0;
+ bo_fake->is_static = GL_FALSE;
+
+ DBG("drm_bo_alloc: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
+ bo_fake->bo.size / 1024);
+
+ return &bo_fake->bo;
+}
+
+static dri_bo *
+dri_fake_bo_alloc_static(dri_bufmgr *bufmgr, const char *name,
+ unsigned long offset, unsigned long size,
+ void *virtual, uint64_t location_mask)
+{
+ dri_bufmgr_fake *bufmgr_fake;
+ dri_bo_fake *bo_fake;
+
+ bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
+
+ assert(size != 0);
+
+ bo_fake = calloc(1, sizeof(*bo_fake));
+ if (!bo_fake)
+ return NULL;
+
+ bo_fake->bo.size = size;
+ bo_fake->bo.offset = offset;
+ bo_fake->bo.virtual = virtual;
+ bo_fake->bo.bufmgr = bufmgr;
+ bo_fake->refcount = 1;
+ bo_fake->id = ++bufmgr_fake->buf_nr;
+ bo_fake->name = name;
+ bo_fake->flags = BM_PINNED | DRM_BO_FLAG_NO_MOVE;
+ bo_fake->is_static = GL_TRUE;
+
+ DBG("drm_bo_alloc_static: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
+ bo_fake->bo.size / 1024);
+
+ return &bo_fake->bo;
+}
+
+static void
+dri_fake_bo_reference(dri_bo *bo)
+{
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+
+ bo_fake->refcount++;
+}
+
+static void
+dri_fake_bo_unreference(dri_bo *bo)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+ int i;
+
+ if (!bo)
+ return;
+
+ if (--bo_fake->refcount == 0) {
+ assert(bo_fake->map_count == 0);
+ /* No remaining references, so free it */
+ if (bo_fake->block)
+ free_block(bufmgr_fake, bo_fake->block);
+ free_backing_store(bo);
+
+ for (i = 0; i < bo_fake->nr_relocs; i++)
+ dri_bo_unreference(bo_fake->relocs[i].target_buf);
+
+ DBG("drm_bo_unreference: free buf %d %s\n", bo_fake->id, bo_fake->name);
+
+ free(bo_fake->relocs);
+ free(bo);
+
+ return;
+ }
+}
+
+/**
+ * Set the buffer as not requiring backing store, and instead get the callback
+ * invoked whenever it would be set dirty.
+ */
+void dri_bo_fake_disable_backing_store(dri_bo *bo,
+ void (*invalidate_cb)(dri_bo *bo,
+ void *ptr),
+ void *ptr)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+
+ if (bo_fake->backing_store)
+ free_backing_store(bo);
+
+ bo_fake->flags |= BM_NO_BACKING_STORE;
+
+ DBG("disable_backing_store set buf %d dirty\n", bo_fake->id);
+ bo_fake->dirty = 1;
+ bo_fake->invalidate_cb = invalidate_cb;
+ bo_fake->invalidate_ptr = ptr;
+
+ /* Note that it is invalid right from the start. Also note
+ * invalidate_cb is called with the bufmgr locked, so cannot
+ * itself make bufmgr calls.
+ */
+ if (invalidate_cb != NULL)
+ invalidate_cb(bo, ptr);
+}
+
+/**
+ * Map a buffer into bo->virtual, allocating either card memory space (If
+ * BM_NO_BACKING_STORE or BM_PINNED) or backing store, as necessary.
+ */
+static int
+dri_fake_bo_map(dri_bo *bo, GLboolean write_enable)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+
+ /* Static buffers are always mapped. */
+ if (bo_fake->is_static)
+ return 0;
+
+ /* Allow recursive mapping. Mesa may recursively map buffers with
+ * nested display loops, and it is used internally in bufmgr_fake
+ * for relocation.
+ */
+ if (bo_fake->map_count++ != 0)
+ return 0;
+
+ {
+ DBG("drm_bo_map: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
+ bo_fake->bo.size / 1024);
+
+ if (bo->virtual != NULL) {
+ _mesa_printf("%s: already mapped\n", __FUNCTION__);
+ abort();
+ }
+ else if (bo_fake->flags & (BM_NO_BACKING_STORE|BM_PINNED)) {
+
+ if (!bo_fake->block && !evict_and_alloc_block(bo)) {
+ DBG("%s: alloc failed\n", __FUNCTION__);
+ bufmgr_fake->fail = 1;
+ return 1;
+ }
+ else {
+ assert(bo_fake->block);
+ bo_fake->dirty = 0;
+
+ if (!(bo_fake->flags & BM_NO_FENCE_SUBDATA) &&
+ bo_fake->block->fenced) {
+ dri_bufmgr_fake_bo_wait_idle(bo);
+ }
+
+ bo->virtual = bo_fake->block->virtual;
+ }
+ }
+ else {
+ if (write_enable)
+ set_dirty(bo);
+
+ if (bo_fake->backing_store == 0)
+ alloc_backing_store(bo);
+
+ bo->virtual = bo_fake->backing_store;
+ }
+ }
+
+ return 0;
+}
+
+static int
+dri_fake_bo_unmap(dri_bo *bo)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+
+ /* Static buffers are always mapped. */
+ if (bo_fake->is_static)
+ return 0;
+
+ assert(bo_fake->map_count != 0);
+ if (--bo_fake->map_count != 0)
+ return 0;
+
+ DBG("drm_bo_unmap: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
+ bo_fake->bo.size / 1024);
+
+ bo->virtual = NULL;
+
+ return 0;
+}
+
+static void
+dri_fake_kick_all(dri_bufmgr_fake *bufmgr_fake)
+{
+ struct block *block, *tmp;
+
+ bufmgr_fake->performed_rendering = GL_FALSE;
+ /* okay for ever BO that is on the HW kick it off.
+ seriously not afraid of the POLICE right now */
+ foreach_s(block, tmp, &bufmgr_fake->on_hardware) {
+ dri_bo_fake *bo_fake = (dri_bo_fake *)block->bo;
+
+ block->on_hardware = 0;
+ free_block(bufmgr_fake, block);
+ bo_fake->block = NULL;
+ bo_fake->validated = GL_FALSE;
+ if (!(bo_fake->flags & BM_NO_BACKING_STORE))
+ bo_fake->dirty = 1;
+ }
+}
+
+static int
+dri_fake_bo_validate(dri_bo *bo)
+{
+ dri_bufmgr_fake *bufmgr_fake;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+
+ /* XXX: Sanity-check whether we've already validated this one under
+ * different flags. See drmAddValidateItem().
+ */
+ bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+
+ DBG("drm_bo_validate: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
+ bo_fake->bo.size / 1024);
+
+ /* Sanity check: Buffers should be unmapped before being validated.
+ * This is not so much of a problem for bufmgr_fake, but TTM refuses,
+ * and the problem is harder to debug there.
+ */
+ assert(bo_fake->map_count == 0);
+
+ if (bo_fake->is_static) {
+ /* Add it to the needs-fence list */
+ bufmgr_fake->need_fence = 1;
+ return 0;
+ }
+
+ /* reset size accounted */
+ bo_fake->size_accounted = 0;
+
+ /* Allocate the card memory */
+ if (!bo_fake->block && !evict_and_alloc_block(bo)) {
+ bufmgr_fake->fail = 1;
+ DBG("Failed to validate buf %d:%s\n", bo_fake->id, bo_fake->name);
+ return -1;
+ }
+
+ assert(bo_fake->block);
+ assert(bo_fake->block->bo == &bo_fake->bo);
+
+ bo->offset = bo_fake->block->mem->ofs;
+
+ /* Upload the buffer contents if necessary */
+ if (bo_fake->dirty) {
+ DBG("Upload dirty buf %d:%s, sz %d offset 0x%x\n", bo_fake->id,
+ bo_fake->name, bo->size, bo_fake->block->mem->ofs);
+
+ assert(!(bo_fake->flags &
+ (BM_NO_BACKING_STORE|BM_PINNED)));
+
+ /* Actually, should be able to just wait for a fence on the memory,
+ * which we would be tracking when we free it. Waiting for idle is
+ * a sufficiently large hammer for now.
+ */
+ dri_bufmgr_fake_wait_idle(bufmgr_fake);
+
+ /* we may never have mapped this BO so it might not have any backing
+ * store if this happens it should be rare, but 0 the card memory
+ * in any case */
+ if (bo_fake->backing_store)
+ memcpy(bo_fake->block->virtual, bo_fake->backing_store, bo->size);
+ else
+ memset(bo_fake->block->virtual, 0, bo->size);
+
+ bo_fake->dirty = 0;
+ }
+
+ bo_fake->block->fenced = 0;
+ bo_fake->block->on_hardware = 1;
+ move_to_tail(&bufmgr_fake->on_hardware, bo_fake->block);
+
+ bo_fake->validated = GL_TRUE;
+ bufmgr_fake->need_fence = 1;
+
+ return 0;
+}
+
+static void
+dri_fake_fence_validated(dri_bufmgr *bufmgr)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
+ unsigned int cookie;
+
+ cookie = _fence_emit_internal(bufmgr_fake);
+ fence_blocks(bufmgr_fake, cookie);
+
+ DBG("drm_fence_validated: 0x%08x cookie\n", cookie);
+}
+
+static void
+dri_fake_destroy(dri_bufmgr *bufmgr)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
+
+ mmDestroy(bufmgr_fake->heap);
+ free(bufmgr);
+}
+
+static int
+dri_fake_emit_reloc(dri_bo *reloc_buf,
+ uint32_t read_domains, uint32_t write_domain,
+ uint32_t delta, uint32_t offset, dri_bo *target_buf)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)reloc_buf->bufmgr;
+ struct fake_buffer_reloc *r;
+ dri_bo_fake *reloc_fake = (dri_bo_fake *)reloc_buf;
+ dri_bo_fake *target_fake = (dri_bo_fake *)target_buf;
+ int i;
+
+ assert(reloc_buf);
+ assert(target_buf);
+
+ assert(target_fake->is_static || target_fake->size_accounted);
+
+ if (reloc_fake->relocs == NULL) {
+ reloc_fake->relocs = malloc(sizeof(struct fake_buffer_reloc) *
+ MAX_RELOCS);
+ }
+
+ r = &reloc_fake->relocs[reloc_fake->nr_relocs++];
+
+ assert(reloc_fake->nr_relocs <= MAX_RELOCS);
+
+ dri_bo_reference(target_buf);
+
+ r->target_buf = target_buf;
+ r->offset = offset;
+ r->last_target_offset = target_buf->offset;
+ r->delta = delta;
+ r->read_domains = read_domains;
+ r->write_domain = write_domain;
+
+ if (bufmgr_fake->debug) {
+ /* Check that a conflicting relocation hasn't already been emitted. */
+ for (i = 0; i < reloc_fake->nr_relocs - 1; i++) {
+ struct fake_buffer_reloc *r2 = &reloc_fake->relocs[i];
+
+ assert(r->offset != r2->offset);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * Incorporates the validation flags associated with each relocation into
+ * the combined validation flags for the buffer on this batchbuffer submission.
+ */
+static void
+dri_fake_calculate_domains(dri_bo *bo)
+{
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+ int i;
+
+ for (i = 0; i < bo_fake->nr_relocs; i++) {
+ struct fake_buffer_reloc *r = &bo_fake->relocs[i];
+ dri_bo_fake *target_fake = (dri_bo_fake *)r->target_buf;
+
+ /* Do the same for the tree of buffers we depend on */
+ dri_fake_calculate_domains(r->target_buf);
+
+ target_fake->read_domains |= r->read_domains;
+ if (target_fake->write_domain != 0)
+ target_fake->write_domain = r->write_domain;
+ }
+}
+
+
+static int
+dri_fake_reloc_and_validate_buffer(dri_bo *bo)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+ int i, ret;
+
+ assert(bo_fake->map_count == 0);
+
+ for (i = 0; i < bo_fake->nr_relocs; i++) {
+ struct fake_buffer_reloc *r = &bo_fake->relocs[i];
+ dri_bo_fake *target_fake = (dri_bo_fake *)r->target_buf;
+ uint32_t reloc_data;
+
+ /* Validate the target buffer if that hasn't been done. */
+ if (!target_fake->validated) {
+ ret = dri_fake_reloc_and_validate_buffer(r->target_buf);
+ if (ret != 0) {
+ if (bo->virtual != NULL)
+ dri_bo_unmap(bo);
+ return ret;
+ }
+ }
+
+ /* Calculate the value of the relocation entry. */
+ if (r->target_buf->offset != r->last_target_offset) {
+ reloc_data = r->target_buf->offset + r->delta;
+
+ if (bo->virtual == NULL)
+ dri_bo_map(bo, GL_TRUE);
+
+ *(uint32_t *)(bo->virtual + r->offset) = reloc_data;
+
+ r->last_target_offset = r->target_buf->offset;
+ }
+ }
+
+ if (bo->virtual != NULL)
+ dri_bo_unmap(bo);
+
+ if (bo_fake->write_domain != 0) {
+ if (!(bo_fake->flags & (BM_NO_BACKING_STORE|BM_PINNED))) {
+ if (bo_fake->backing_store == 0)
+ alloc_backing_store(bo);
+
+ bo_fake->card_dirty = 1;
+ }
+ bufmgr_fake->performed_rendering = GL_TRUE;
+ }
+
+ return dri_fake_bo_validate(bo);
+}
+
+static void *
+dri_fake_process_relocs(dri_bo *batch_buf)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)batch_buf->bufmgr;
+ dri_bo_fake *batch_fake = (dri_bo_fake *)batch_buf;
+ int ret;
+ int retry_count = 0;
+
+ bufmgr_fake->performed_rendering = GL_FALSE;
+
+ dri_fake_calculate_domains(batch_buf);
+
+ batch_fake->read_domains = DRM_GEM_DOMAIN_I915_COMMAND;
+
+ /* we've ran out of RAM so blow the whole lot away and retry */
+ restart:
+ ret = dri_fake_reloc_and_validate_buffer(batch_buf);
+ if (bufmgr_fake->fail == 1) {
+ if (retry_count == 0) {
+ retry_count++;
+ dri_fake_kick_all(bufmgr_fake);
+ bufmgr_fake->fail = 0;
+ goto restart;
+ } else /* dump out the memory here */
+ mmDumpMemInfo(bufmgr_fake->heap);
+ }
+
+ assert(ret == 0);
+
+ bufmgr_fake->current_total_size = 0;
+ return NULL;
+}
+
+static void
+dri_bo_fake_post_submit(dri_bo *bo)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+ int i;
+
+ for (i = 0; i < bo_fake->nr_relocs; i++) {
+ struct fake_buffer_reloc *r = &bo_fake->relocs[i];
+ dri_bo_fake *target_fake = (dri_bo_fake *)r->target_buf;
+
+ if (target_fake->validated)
+ dri_bo_fake_post_submit(r->target_buf);
+
+ DBG("%s@0x%08x + 0x%08x -> %s@0x%08x + 0x%08x\n",
+ bo_fake->name, (uint32_t)bo->offset, r->offset,
+ target_fake->name, (uint32_t)r->target_buf->offset, r->delta);
+ }
+
+ assert(bo_fake->map_count == 0);
+ bo_fake->validated = GL_FALSE;
+ bo_fake->read_domains = 0;
+ bo_fake->write_domain = 0;
+}
+
+
+static void
+dri_fake_post_submit(dri_bo *batch_buf)
+{
+ dri_fake_fence_validated(batch_buf->bufmgr);
+
+ dri_bo_fake_post_submit(batch_buf);
+}
+
+static int
+dri_fake_check_aperture_space(dri_bo *bo)
+{
+ dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
+ dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
+ GLuint sz;
+
+ sz = (bo->size + bo_fake->alignment - 1) & ~(bo_fake->alignment - 1);
+
+ if (bo_fake->size_accounted || bo_fake->is_static)
+ return 0;
+
+ if (bufmgr_fake->current_total_size + sz > bufmgr_fake->size) {
+ DBG("check_space: %s bo %d %d overflowed bufmgr size %d\n", bo_fake->name, bo_fake->id, sz, bufmgr_fake->size);
+ return -1;
+ }
+
+ bufmgr_fake->current_total_size += sz;
+ bo_fake->size_accounted = 1;
+ DBG("drm_check_space: buf %d, %s %d %d\n", bo_fake->id, bo_fake->name, bo->size, bufmgr_fake->current_total_size);
+ return 0;
+}
+
+dri_bufmgr *
+dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual,
+ unsigned long size,
+ unsigned int (*fence_emit)(void *private),
+ int (*fence_wait)(void *private, unsigned int cookie),
+ void *driver_priv)
+{
+ dri_bufmgr_fake *bufmgr_fake;
+
+ bufmgr_fake = calloc(1, sizeof(*bufmgr_fake));
+
+ /* Initialize allocator */
+ make_empty_list(&bufmgr_fake->fenced);
+ make_empty_list(&bufmgr_fake->on_hardware);
+ make_empty_list(&bufmgr_fake->lru);
+
+ bufmgr_fake->low_offset = low_offset;
+ bufmgr_fake->virtual = low_virtual;
+ bufmgr_fake->size = size;
+ bufmgr_fake->heap = mmInit(low_offset, size);
+
+ /* Hook in methods */
+ bufmgr_fake->bufmgr.bo_alloc = dri_fake_bo_alloc;
+ bufmgr_fake->bufmgr.bo_alloc_static = dri_fake_bo_alloc_static;
+ bufmgr_fake->bufmgr.bo_reference = dri_fake_bo_reference;
+ bufmgr_fake->bufmgr.bo_unreference = dri_fake_bo_unreference;
+ bufmgr_fake->bufmgr.bo_map = dri_fake_bo_map;
+ bufmgr_fake->bufmgr.bo_unmap = dri_fake_bo_unmap;
+ bufmgr_fake->bufmgr.destroy = dri_fake_destroy;
+ bufmgr_fake->bufmgr.emit_reloc = dri_fake_emit_reloc;
+ bufmgr_fake->bufmgr.process_relocs = dri_fake_process_relocs;
+ bufmgr_fake->bufmgr.post_submit = dri_fake_post_submit;
+ bufmgr_fake->bufmgr.check_aperture_space = dri_fake_check_aperture_space;
+ bufmgr_fake->bufmgr.debug = GL_FALSE;
+
+ bufmgr_fake->fence_emit = fence_emit;
+ bufmgr_fake->fence_wait = fence_wait;
+ bufmgr_fake->driver_priv = driver_priv;
+
+ return &bufmgr_fake->bufmgr;
+}
+
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_fake.h b/src/mesa/drivers/dri/intel/intel_bufmgr_fake.h
new file mode 100644
index 0000000000..bc7e59e61d
--- /dev/null
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_fake.h
@@ -0,0 +1,50 @@
+/**************************************************************************
+ *
+ * Copyright © 2007 Intel Corporation
+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ *
+ **************************************************************************/
+/*
+ * Authors: Thomas Hellström
+ * Keith Whitwell
+ * Eric Anholt
+ */
+
+#ifndef _INTEL_BUFMGR_FAKE_H_
+#define _INTEL_BUFMGR_FAKE_H_
+
+void dri_bufmgr_fake_contended_lock_take(dri_bufmgr *bufmgr);
+dri_bufmgr *dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual,
+ unsigned long size,
+ unsigned int (*fence_emit)(void *private),
+ int (*fence_wait)(void *private,
+ unsigned int cookie),
+ void *driver_priv);
+void dri_bo_fake_disable_backing_store(dri_bo *bo,
+ void (*invalidate_cb)(dri_bo *bo,
+ void *ptr),
+ void *ptr);
+#endif /* _INTEL_BUFMGR_FAKE_H_ */
+
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index 69d90e19d8..5e16f9de0b 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -579,8 +579,8 @@ dri_bufmgr_gem_destroy(dri_bufmgr *bufmgr)
* last known offset in target_bo.
*/
static int
-dri_gem_emit_reloc(dri_bo *bo, uint64_t flags, GLuint delta,
- GLuint offset, dri_bo *target_bo)
+dri_gem_emit_reloc(dri_bo *bo, uint32_t read_domains, uint32_t write_domain,
+ uint32_t delta, uint32_t offset, dri_bo *target_bo)
{
dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
@@ -601,18 +601,17 @@ dri_gem_emit_reloc(dri_bo *bo, uint64_t flags, GLuint delta,
bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
dri_bo_reference(target_bo);
- /** XXX set memory domains, using existing TTM flags (which is wrong) */
- if (flags & DRM_BO_FLAG_WRITE)
- {
- /* assume this means the rendering buffer */
- target_bo_gem->read_domains |= DRM_GEM_DOMAIN_I915_RENDER;
- target_bo_gem->write_domain = DRM_GEM_DOMAIN_I915_RENDER;
- }
- if (flags & DRM_BO_FLAG_READ)
- {
- /* assume this means the sampler buffer */
- target_bo_gem->read_domains |= DRM_GEM_DOMAIN_I915_SAMPLER;
- }
+ /* Just accumulate the read domains into the target buffer. We don't care
+ * enough about minimizing the flags associated with a buffer for a
+ * specific set of relocations being done against it.
+ */
+ target_bo_gem->read_domains |= read_domains;
+ /* XXX: this is broken if we have more than one write domain. We
+ * would need to be computing the write domain on the buffer based on
+ * order of relocs in the batchbuffer. But we only have one write buffer.
+ */
+ target_bo_gem->write_domain = write_domain;
+
bo_gem->reloc_count++;
return 0;
}
@@ -699,9 +698,6 @@ dri_gem_post_submit(dri_bo *batch_buf)
dri_bo *bo = bufmgr_gem->validate_bo[i];
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
- /* clear read/write domain bits */
- bo_gem->read_domains = 0;
- bo_gem->write_domain = 0;
/* Disconnect the buffer from the validate list */
bo_gem->validate_index = -1;
dri_bo_unreference(bo);
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index d258e669c0..ae9e53ce6e 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -59,6 +59,7 @@
#include "intel_buffer_objects.h"
#include "intel_fbo.h"
#include "intel_decode.h"
+#include "intel_bufmgr_fake.h"
#include "intel_bufmgr_gem.h"
#include "drirenderbuffer.h"
--
cgit v1.2.3
From ead798eb103e4cfe801704bc15eb4fe8df078fa8 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 7 May 2008 14:01:03 -0700
Subject: GEM: Remove already-disabled PIPE_CONTROL command.
This existed to get the icache flushed. However, GEM handles this for us
now for sure, and we had disabled it prematurely anyway.
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 34 ----------------------------
src/mesa/drivers/dri/i965/brw_state_upload.c | 1 -
2 files changed, 35 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 24dfd2e24e..c941e054a3 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -383,40 +383,6 @@ const struct brw_tracked_state brw_line_stipple = {
};
-
-/***********************************************************************
- * Misc constant state packets
- */
-
-static void upload_pipe_control(struct brw_context *brw)
-{
- struct brw_pipe_control pc;
-
- return;
-
- memset(&pc, 0, sizeof(pc));
-
- pc.header.opcode = CMD_PIPE_CONTROL;
- pc.header.length = sizeof(pc)/4 - 2;
- pc.header.post_sync_operation = PIPE_CONTROL_NOWRITE;
-
- pc.header.instruction_state_cache_flush_enable = 1;
-
- pc.bits1.dest_addr_type = PIPE_CONTROL_GTTWRITE_GLOBAL;
-
- BRW_BATCH_STRUCT(brw, &pc);
-}
-
-const struct brw_tracked_state brw_pipe_control = {
- .dirty = {
- .mesa = 0,
- .brw = BRW_NEW_BATCH,
- .cache = 0
- },
- .emit = upload_pipe_control
-};
-
-
/***********************************************************************
* Misc invarient state packets
*/
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 3b2ccd48c3..b8dfcf5b03 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -80,7 +80,6 @@ const struct brw_tracked_state *atoms[] =
*/
&brw_invarient_state,
&brw_state_base_address,
- &brw_pipe_control,
&brw_binding_table_pointers,
&brw_blend_constant_color,
--
cgit v1.2.3
From fda5687241f4ce5cab3bf2eac437b52d4b37dd10 Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Thu, 8 May 2008 10:37:23 -0700
Subject: [intel] intel_batchbuffer_flush using uninit 'used' to check for
buffer empty
Make sure 'used' tracks the right value through the whole function.
Also, use GLint for intel_batchbuffer_space in case we do bad things
in the future.
---
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 10 +++++++---
src/mesa/drivers/dri/intel/intel_batchbuffer.h | 2 +-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index f22e6c0967..b626e90476 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -195,7 +195,7 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
int line)
{
struct intel_context *intel = batch->intel;
- GLuint used;
+ GLuint used = batch->ptr - batch->map;
GLboolean was_locked = intel->locked;
if (used == 0)
@@ -209,19 +209,20 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
if (!intel->ttm) {
*(GLuint *) (batch->ptr) = intel->vtbl.flush_cmd();
batch->ptr += 4;
+ used = batch->ptr - batch->map;
}
/* Round batchbuffer usage to 2 DWORDs. */
- used = batch->ptr - batch->map;
+
if ((used & 4) == 0) {
*(GLuint *) (batch->ptr) = 0; /* noop */
batch->ptr += 4;
+ used = batch->ptr - batch->map;
}
/* Mark the end of the buffer. */
*(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END; /* noop */
batch->ptr += 4;
-
used = batch->ptr - batch->map;
/* Workaround for recursive batchbuffer flushing: If the window is
@@ -272,6 +273,9 @@ intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
{
int ret;
+ if (batch->ptr - batch->map > batch->buf->size)
+ _mesa_printf ("bad relocation ptr %p map %p offset %d size %d\n",
+ batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
ret = dri_emit_reloc(batch->buf, read_domains, write_domain,
delta, batch->ptr - batch->map, buffer);
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
index 7268bd59da..5e8b14b401 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
@@ -88,7 +88,7 @@ GLboolean intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
* be passed as structs rather than dwords, but that's a little bit of
* work...
*/
-static INLINE GLuint
+static INLINE GLint
intel_batchbuffer_space(struct intel_batchbuffer *batch)
{
return (batch->size - BATCH_RESERVED) - (batch->ptr - batch->map);
--
cgit v1.2.3
From 0cb006c1fdb75e1fe282120cc5455a4e8c59b1a7 Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Thu, 8 May 2008 10:38:55 -0700
Subject: [intel-gem] move domains to relocations. add set_domain to bo_map.
Fix the kernel API to place the read/write domain information in the
relocation instead of the buffer.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 42 +++++++++++++--------------
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index 5e16f9de0b..399a6a12e3 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -123,8 +123,6 @@ typedef struct _dri_bo_gem {
dri_bo **reloc_target_bo;
/** Number of entries in relocs */
int reloc_count;
- /** Memory domains for synchronization */
- uint32_t read_domains, write_domain;
/** Mapped address for the buffer */
void *virtual;
} dri_bo_gem;
@@ -232,8 +230,6 @@ intel_add_validate_buffer(dri_bo *bo)
bufmgr_gem->validate_array[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
bufmgr_gem->validate_array[index].alignment = 0;
bufmgr_gem->validate_array[index].buffer_offset = 0;
- bufmgr_gem->validate_array[index].read_domains = bo_gem->read_domains;
- bufmgr_gem->validate_array[index].write_domain = bo_gem->write_domain;
bufmgr_gem->validate_bo[index] = bo;
dri_bo_reference(bo);
bufmgr_gem->validate_count++;
@@ -468,6 +464,7 @@ dri_gem_bo_map(dri_bo *bo, GLboolean write_enable)
{
dri_bufmgr_gem *bufmgr_gem;
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+ struct drm_gem_set_domain set_domain;
int ret;
bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
@@ -493,14 +490,23 @@ dri_gem_bo_map(dri_bo *bo, GLboolean write_enable)
if (ret != 0) {
fprintf(stderr, "%s:%d: Error mapping buffer %d (%s): %s .\n",
__FILE__, __LINE__,
- bo_gem->gem_handle, bo_gem->name, strerror(-ret));
+ bo_gem->gem_handle, bo_gem->name, strerror(errno));
}
bo_gem->virtual = (void *)(uintptr_t)mmap_arg.addr_ptr;
}
-
- /* XXX Synchronization with hardware */
-
bo->virtual = bo_gem->virtual;
+ DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, bo_gem->virtual);
+
+ set_domain.handle = bo_gem->gem_handle;
+ set_domain.read_domains = DRM_GEM_DOMAIN_CPU;
+ set_domain.write_domain = write_enable ? DRM_GEM_DOMAIN_CPU : 0;
+ ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_GEM_SET_DOMAIN, &set_domain);
+ if (ret != 0) {
+ fprintf (stderr, "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
+ __FILE__, __LINE__,
+ bo_gem->gem_handle, set_domain.read_domains, set_domain.write_domain,
+ strerror (errno));
+ }
return 0;
}
@@ -593,25 +599,20 @@ dri_gem_emit_reloc(dri_bo *bo, uint32_t read_domains, uint32_t write_domain,
/* Check overflow */
assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
+ /* Check args */
+ assert (offset <= bo->size - 4);
+ assert ((write_domain & (write_domain-1)) == 0);
+
bo_gem->relocs[bo_gem->reloc_count].offset = offset;
bo_gem->relocs[bo_gem->reloc_count].delta = delta;
bo_gem->relocs[bo_gem->reloc_count].target_handle =
target_bo_gem->gem_handle;
+ bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
+ bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
dri_bo_reference(target_bo);
- /* Just accumulate the read domains into the target buffer. We don't care
- * enough about minimizing the flags associated with a buffer for a
- * specific set of relocations being done against it.
- */
- target_bo_gem->read_domains |= read_domains;
- /* XXX: this is broken if we have more than one write domain. We
- * would need to be computing the write domain on the buffer based on
- * order of relocs in the batchbuffer. But we only have one write buffer.
- */
- target_bo_gem->write_domain = write_domain;
-
bo_gem->reloc_count++;
return 0;
}
@@ -644,11 +645,8 @@ dri_gem_bo_process_reloc(dri_bo *bo)
static void *
dri_gem_process_reloc(dri_bo *batch_buf)
{
- dri_bo_gem *bo_gem = (dri_bo_gem *)batch_buf;
dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *) batch_buf->bufmgr;
- bo_gem->read_domains |= DRM_GEM_DOMAIN_I915_COMMAND;
-
/* Update indices and set up the validate list. */
dri_gem_bo_process_reloc(batch_buf);
--
cgit v1.2.3
From 145523ba3acb95a9ff390430a9e0a3fa958cae1b Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Sun, 11 May 2008 00:16:25 -0700
Subject: [intel] update GEM api. Add bo_subdata and bo_get_subdata driver
hooks.
Track DRM GEM name changes.
Add driver hooks for bo_subdata and bo_get_subdata so that GEM can use pread
and pwrite.
---
src/mesa/drivers/dri/common/dri_bufmgr.c | 25 +++-
src/mesa/drivers/dri/common/dri_bufmgr.h | 26 ++++-
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 26 ++++-
src/mesa/drivers/dri/intel/intel_batchbuffer.h | 2 +
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 155 ++++++++++++++++---------
5 files changed, 166 insertions(+), 68 deletions(-)
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.c b/src/mesa/drivers/dri/common/dri_bufmgr.c
index 5967d7dafb..19ea2a8f86 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr.c
+++ b/src/mesa/drivers/dri/common/dri_bufmgr.c
@@ -90,28 +90,41 @@ dri_bo_unmap(dri_bo *buf)
return buf->bufmgr->bo_unmap(buf);
}
-void
+int
dri_bo_subdata(dri_bo *bo, unsigned long offset,
unsigned long size, const void *data)
{
+ int ret;
+ if (bo->bufmgr->bo_subdata)
+ return bo->bufmgr->bo_subdata(bo, offset, size, data);
if (size == 0 || data == NULL)
- return;
+ return 0;
- dri_bo_map(bo, GL_TRUE);
+ ret = dri_bo_map(bo, GL_TRUE);
+ if (ret)
+ return ret;
memcpy((unsigned char *)bo->virtual + offset, data, size);
dri_bo_unmap(bo);
+ return 0;
}
-void
+int
dri_bo_get_subdata(dri_bo *bo, unsigned long offset,
unsigned long size, void *data)
{
+ int ret;
+ if (bo->bufmgr->bo_subdata)
+ return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
+
if (size == 0 || data == NULL)
- return;
+ return 0;
- dri_bo_map(bo, GL_FALSE);
+ ret = dri_bo_map(bo, GL_FALSE);
+ if (ret)
+ return ret;
memcpy(data, (unsigned char *)bo->virtual + offset, size);
dri_bo_unmap(bo);
+ return 0;
}
void
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.h b/src/mesa/drivers/dri/common/dri_bufmgr.h
index 99cfb2cd05..29f9aea2b1 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr.h
+++ b/src/mesa/drivers/dri/common/dri_bufmgr.h
@@ -109,6 +109,24 @@ struct _dri_bufmgr {
/** Reduces the refcount on the userspace mapping of the buffer object. */
int (*bo_unmap)(dri_bo *buf);
+ /**
+ * Write data into an object.
+ *
+ * This is an optional function, if missing,
+ * dri_bo will map/memcpy/unmap.
+ */
+ int (*bo_subdata) (dri_bo *buf, unsigned long offset,
+ unsigned long size, const void *data);
+
+ /**
+ * Read data from an object
+ *
+ * This is an optional function, if missing,
+ * dri_bo will map/memcpy/unmap.
+ */
+ int (*bo_get_subdata) (dri_bo *bo, unsigned long offset,
+ unsigned long size, void *data);
+
/**
* Tears down the buffer manager instance.
*/
@@ -170,10 +188,10 @@ void dri_bo_unreference(dri_bo *bo);
int dri_bo_map(dri_bo *buf, GLboolean write_enable);
int dri_bo_unmap(dri_bo *buf);
-void dri_bo_subdata(dri_bo *bo, unsigned long offset,
- unsigned long size, const void *data);
-void dri_bo_get_subdata(dri_bo *bo, unsigned long offset,
- unsigned long size, void *data);
+int dri_bo_subdata(dri_bo *bo, unsigned long offset,
+ unsigned long size, const void *data);
+int dri_bo_get_subdata(dri_bo *bo, unsigned long offset,
+ unsigned long size, void *data);
void dri_bufmgr_set_debug(dri_bufmgr *bufmgr, GLboolean enable_debug);
void dri_bufmgr_destroy(dri_bufmgr *bufmgr);
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index b626e90476..803ff5e90e 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -78,11 +78,18 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch)
batch->buf = NULL;
}
+ if (!batch->buffer && intel->ttm == GL_TRUE)
+ batch->buffer = malloc (intel->maxBatchSize);
+
batch->buf = dri_bo_alloc(intel->bufmgr, "batchbuffer",
intel->maxBatchSize, 4096,
DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_CACHED | DRM_BO_FLAG_CACHED_MAPPED);
- dri_bo_map(batch->buf, GL_TRUE);
- batch->map = batch->buf->virtual;
+ if (batch->buffer)
+ batch->map = batch->buffer;
+ else {
+ dri_bo_map(batch->buf, GL_TRUE);
+ batch->map = batch->buf->virtual;
+ }
batch->size = intel->maxBatchSize;
batch->ptr = batch->map;
batch->dirty_state = ~0;
@@ -107,9 +114,13 @@ intel_batchbuffer_alloc(struct intel_context *intel)
void
intel_batchbuffer_free(struct intel_batchbuffer *batch)
{
- if (batch->map) {
- dri_bo_unmap(batch->buf);
- batch->map = NULL;
+ if (batch->buffer)
+ free (batch->buffer);
+ else {
+ if (batch->map) {
+ dri_bo_unmap(batch->buf);
+ batch->map = NULL;
+ }
}
dri_bo_unreference(batch->buf);
batch->buf = NULL;
@@ -127,7 +138,10 @@ do_flush_locked(struct intel_batchbuffer *batch,
struct intel_context *intel = batch->intel;
int ret = 0;
- dri_bo_unmap(batch->buf);
+ if (batch->buffer)
+ dri_bo_subdata (batch->buf, 0, used, batch->buffer);
+ else
+ dri_bo_unmap(batch->buf);
batch->map = NULL;
batch->ptr = NULL;
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
index 5e8b14b401..d3c656c803 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
@@ -41,6 +41,8 @@ struct intel_batchbuffer
dri_bo *buf;
+ GLubyte *buffer;
+
GLubyte *map;
GLubyte *ptr;
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index 399a6a12e3..2de08f6529 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -92,10 +92,10 @@ typedef struct _dri_bufmgr_gem {
uint32_t max_relocs;
- struct drm_i915_gem_validate_entry *validate_array;
- dri_bo **validate_bo;
- int validate_array_size;
- int validate_count;
+ struct drm_i915_gem_exec_object *exec_objects;
+ dri_bo **exec_bos;
+ int exec_size;
+ int exec_count;
/** Array of lists of cached gem objects of power-of-two sizes */
struct dri_gem_bo_bucket cache_bucket[INTEL_GEM_BO_BUCKETS];
@@ -166,8 +166,8 @@ static void dri_gem_dump_validation_list(dri_bufmgr_gem *bufmgr_gem)
{
int i, j;
- for (i = 0; i < bufmgr_gem->validate_count; i++) {
- dri_bo *bo = bufmgr_gem->validate_bo[i];
+ for (i = 0; i < bufmgr_gem->exec_count; i++) {
+ dri_bo *bo = bufmgr_gem->exec_bos[i];
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
if (bo_gem->relocs == NULL) {
@@ -207,32 +207,32 @@ intel_add_validate_buffer(dri_bo *bo)
return;
/* Extend the array of validation entries as necessary. */
- if (bufmgr_gem->validate_count == bufmgr_gem->validate_array_size) {
- int new_size = bufmgr_gem->validate_array_size * 2;
+ if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
+ int new_size = bufmgr_gem->exec_size * 2;
if (new_size == 0)
new_size = 5;
- bufmgr_gem->validate_array =
- realloc(bufmgr_gem->validate_array,
- sizeof(*bufmgr_gem->validate_array) * new_size);
- bufmgr_gem->validate_bo =
- realloc(bufmgr_gem->validate_bo,
- sizeof(*bufmgr_gem->validate_bo) * new_size);
- bufmgr_gem->validate_array_size = new_size;
+ bufmgr_gem->exec_objects =
+ realloc(bufmgr_gem->exec_objects,
+ sizeof(*bufmgr_gem->exec_objects) * new_size);
+ bufmgr_gem->exec_bos =
+ realloc(bufmgr_gem->exec_bos,
+ sizeof(*bufmgr_gem->exec_bos) * new_size);
+ bufmgr_gem->exec_size = new_size;
}
- index = bufmgr_gem->validate_count;
+ index = bufmgr_gem->exec_count;
bo_gem->validate_index = index;
/* Fill in array entry */
- bufmgr_gem->validate_array[index].buffer_handle = bo_gem->gem_handle;
- bufmgr_gem->validate_array[index].relocation_count = bo_gem->reloc_count;
- bufmgr_gem->validate_array[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
- bufmgr_gem->validate_array[index].alignment = 0;
- bufmgr_gem->validate_array[index].buffer_offset = 0;
- bufmgr_gem->validate_bo[index] = bo;
+ bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
+ bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
+ bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
+ bufmgr_gem->exec_objects[index].alignment = 0;
+ bufmgr_gem->exec_objects[index].offset = 0;
+ bufmgr_gem->exec_bos[index] = bo;
dri_bo_reference(bo);
- bufmgr_gem->validate_count++;
+ bufmgr_gem->exec_count++;
}
@@ -309,13 +309,13 @@ dri_gem_bo_alloc(dri_bufmgr *bufmgr, const char *name,
}
if (!alloc_from_cache) {
- struct drm_gem_alloc alloc;
+ struct drm_gem_create create;
- memset(&alloc, 0, sizeof(alloc));
- alloc.size = bo_gem->bo.size;
+ memset(&create, 0, sizeof(create));
+ create.size = bo_gem->bo.size;
- ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_ALLOC, &alloc);
- bo_gem->gem_handle = alloc.handle;
+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CREATE, &create);
+ bo_gem->gem_handle = create.handle;
if (ret != 0) {
free(bo_gem);
return NULL;
@@ -439,14 +439,14 @@ dri_gem_bo_unreference(dri_bo *bo)
bucket->tail = &entry->next;
bucket->num_entries++;
} else {
- struct drm_gem_unreference unref;
+ struct drm_gem_close close;
- /* Decrement the kernel refcount for the buffer. */
- unref.handle = bo_gem->gem_handle;
- ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_UNREFERENCE, &unref);
+ /* Close this object */
+ close.handle = bo_gem->gem_handle;
+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
if (ret != 0) {
fprintf(stderr,
- "DRM_IOCTL_GEM_UNREFERENCE %d failed (%s): %s\n",
+ "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
bo_gem->gem_handle, bo_gem->name, strerror(-ret));
}
}
@@ -537,14 +537,62 @@ dri_gem_bo_unmap(dri_bo *bo)
return 0;
}
+static int
+dri_gem_bo_subdata (dri_bo *bo, unsigned long offset,
+ unsigned long size, const void *data)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+ struct drm_gem_pwrite pwrite;
+ int ret;
+
+ memset (&pwrite, 0, sizeof (pwrite));
+ pwrite.handle = bo_gem->gem_handle;
+ pwrite.offset = offset;
+ pwrite.size = size;
+ pwrite.data_ptr = (uint64_t) (uintptr_t) data;
+ ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_GEM_PWRITE, &pwrite);
+ if (ret != 0) {
+ fprintf (stderr, "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
+ __FILE__, __LINE__,
+ bo_gem->gem_handle, (int) offset, (int) size,
+ strerror (errno));
+ }
+ return 0;
+}
+
+static int
+dri_gem_bo_get_subdata (dri_bo *bo, unsigned long offset,
+ unsigned long size, void *data)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+ struct drm_gem_pread pread;
+ int ret;
+
+ memset (&pread, 0, sizeof (pread));
+ pread.handle = bo_gem->gem_handle;
+ pread.offset = offset;
+ pread.size = size;
+ pread.data_ptr = (uint64_t) (uintptr_t) data;
+ ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_GEM_PREAD, &pread);
+ if (ret != 0) {
+ fprintf (stderr, "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
+ __FILE__, __LINE__,
+ bo_gem->gem_handle, (int) offset, (int) size,
+ strerror (errno));
+ }
+ return 0;
+}
+
static void
dri_bufmgr_gem_destroy(dri_bufmgr *bufmgr)
{
dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr;
int i;
- free(bufmgr_gem->validate_array);
- free(bufmgr_gem->validate_bo);
+ free(bufmgr_gem->exec_objects);
+ free(bufmgr_gem->exec_bos);
/* Free any cached buffer objects we were going to reuse */
for (i = 0; i < INTEL_GEM_BO_BUCKETS; i++) {
@@ -552,7 +600,7 @@ dri_bufmgr_gem_destroy(dri_bufmgr *bufmgr)
struct dri_gem_bo_bucket_entry *entry;
while ((entry = bucket->head) != NULL) {
- struct drm_gem_unreference unref;
+ struct drm_gem_close close;
int ret;
bucket->head = entry->next;
@@ -560,11 +608,11 @@ dri_bufmgr_gem_destroy(dri_bufmgr *bufmgr)
bucket->tail = &bucket->head;
bucket->num_entries--;
- /* Decrement the kernel refcount for the buffer. */
- unref.handle = entry->gem_handle;
- ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_UNREFERENCE, &unref);
+ /* Close this object */
+ close.handle = entry->gem_handle;
+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
if (ret != 0) {
- fprintf(stderr, "DRM_IOCTL_GEM_UNREFERENCE failed: %s\n",
+ fprintf(stderr, "DRM_IOCTL_GEM_CLOSE failed: %s\n",
strerror(-ret));
}
@@ -655,9 +703,10 @@ dri_gem_process_reloc(dri_bo *batch_buf)
*/
intel_add_validate_buffer(batch_buf);
- bufmgr_gem->exec_arg.buffers_ptr = (uintptr_t)bufmgr_gem->validate_array;
- bufmgr_gem->exec_arg.buffer_count = bufmgr_gem->validate_count;
- bufmgr_gem->exec_arg.batch_start_offset = bufmgr_gem->validate_count;
+ bufmgr_gem->exec_arg.buffers_ptr = (uintptr_t)bufmgr_gem->exec_objects;
+ bufmgr_gem->exec_arg.buffer_count = bufmgr_gem->exec_count;
+ bufmgr_gem->exec_arg.batch_start_offset = 0;
+ bufmgr_gem->exec_arg.batch_len = 0; /* written in intel_exec_ioctl */
return &bufmgr_gem->exec_arg;
}
@@ -667,16 +716,16 @@ intel_update_buffer_offsets (dri_bufmgr_gem *bufmgr_gem)
{
int i;
- for (i = 0; i < bufmgr_gem->validate_count; i++) {
- dri_bo *bo = bufmgr_gem->validate_bo[i];
+ for (i = 0; i < bufmgr_gem->exec_count; i++) {
+ dri_bo *bo = bufmgr_gem->exec_bos[i];
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
/* Update the buffer offset */
- if (bufmgr_gem->validate_array[i].buffer_offset != bo->offset) {
+ if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
bo_gem->gem_handle, bo_gem->name, bo->offset,
- bufmgr_gem->validate_array[i].buffer_offset);
- bo->offset = bufmgr_gem->validate_array[i].buffer_offset;
+ bufmgr_gem->exec_objects[i].offset);
+ bo->offset = bufmgr_gem->exec_objects[i].offset;
}
}
}
@@ -692,16 +741,16 @@ dri_gem_post_submit(dri_bo *batch_buf)
if (bufmgr_gem->bufmgr.debug)
dri_gem_dump_validation_list(bufmgr_gem);
- for (i = 0; i < bufmgr_gem->validate_count; i++) {
- dri_bo *bo = bufmgr_gem->validate_bo[i];
+ for (i = 0; i < bufmgr_gem->exec_count; i++) {
+ dri_bo *bo = bufmgr_gem->exec_bos[i];
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
/* Disconnect the buffer from the validate list */
bo_gem->validate_index = -1;
dri_bo_unreference(bo);
- bufmgr_gem->validate_bo[i] = NULL;
+ bufmgr_gem->exec_bos[i] = NULL;
}
- bufmgr_gem->validate_count = 0;
+ bufmgr_gem->exec_count = 0;
}
/**
@@ -762,6 +811,8 @@ intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem->bufmgr.bo_unreference = dri_gem_bo_unreference;
bufmgr_gem->bufmgr.bo_map = dri_gem_bo_map;
bufmgr_gem->bufmgr.bo_unmap = dri_gem_bo_unmap;
+ bufmgr_gem->bufmgr.bo_subdata = dri_gem_bo_subdata;
+ bufmgr_gem->bufmgr.bo_get_subdata = dri_gem_bo_get_subdata;
bufmgr_gem->bufmgr.destroy = dri_bufmgr_gem_destroy;
bufmgr_gem->bufmgr.emit_reloc = dri_gem_emit_reloc;
bufmgr_gem->bufmgr.process_relocs = dri_gem_process_reloc;
--
cgit v1.2.3
From cba90d4a778ab5202f2f7547ad7ffeb84216d07b Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Tue, 13 May 2008 11:30:18 -0700
Subject: [GEM] Actually include the presumed offset in initial relocations.
This avoids kernel relocations for most batchbuffer relocs.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index 2de08f6529..a14f7830f9 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -657,6 +657,7 @@ dri_gem_emit_reloc(dri_bo *bo, uint32_t read_domains, uint32_t write_domain,
target_bo_gem->gem_handle;
bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
+ bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
dri_bo_reference(target_bo);
--
cgit v1.2.3
From 8b49cc104dd556218fc769178b96f4a8a428d057 Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Sat, 17 May 2008 23:34:47 -0700
Subject: [intel-gem] Don't calloc reloc buffers
Only a few relocations are typically used, so don't clear the
whole thing.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index a14f7830f9..e08e3952bc 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -245,9 +245,9 @@ intel_setup_reloc_list(dri_bo *bo)
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
- bo_gem->relocs = calloc(bufmgr_gem->max_relocs,
+ bo_gem->relocs = malloc(bufmgr_gem->max_relocs *
sizeof(struct drm_i915_gem_relocation_entry));
- bo_gem->reloc_target_bo = calloc(bufmgr_gem->max_relocs, sizeof(dri_bo *));
+ bo_gem->reloc_target_bo = malloc(bufmgr_gem->max_relocs * sizeof(dri_bo *));
return 0;
}
--
cgit v1.2.3
From 76286bc76c5ea2217378809a9dcab6794aae7b5e Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Thu, 22 May 2008 10:44:47 -0700
Subject: [intel-gem] Make sure set_domain is called often enough.
The write_domain needs to be set after any batch buffer uses an object,
track when that happens in the new 'cpu_domain_set' field.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 75 ++++++++++++++++-----------
1 file changed, 44 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index e08e3952bc..b472a8f6e1 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -117,6 +117,13 @@ typedef struct _dri_bo_gem {
*/
int validate_index;
+ /**
+ * Tracks whether set_domain to CPU is current
+ * Set when set_domain has been called
+ * Cleared when a batch has been submitted
+ */
+ GLboolean cpu_domain_set;
+
/** Array passed to the DRM containing relocation information. */
struct drm_i915_gem_relocation_entry *relocs;
/** Array of bos corresponding to relocs[i].target_handle */
@@ -472,40 +479,43 @@ dri_gem_bo_map(dri_bo *bo, GLboolean write_enable)
/* Allow recursive mapping. Mesa may recursively map buffers with
* nested display loops.
*/
- if (bo_gem->map_count++ != 0)
- return 0;
-
- assert(bo->virtual == NULL);
-
- DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
-
- if (bo_gem->virtual == NULL) {
- struct drm_gem_mmap mmap_arg;
-
- memset(&mmap_arg, 0, sizeof(mmap_arg));
- mmap_arg.handle = bo_gem->gem_handle;
- mmap_arg.offset = 0;
- mmap_arg.size = bo->size;
- ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_MMAP, &mmap_arg);
- if (ret != 0) {
- fprintf(stderr, "%s:%d: Error mapping buffer %d (%s): %s .\n",
- __FILE__, __LINE__,
- bo_gem->gem_handle, bo_gem->name, strerror(errno));
+ if (bo_gem->map_count++ == 0) {
+
+ assert(bo->virtual == NULL);
+
+ DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
+
+ if (bo_gem->virtual == NULL) {
+ struct drm_gem_mmap mmap_arg;
+
+ memset(&mmap_arg, 0, sizeof(mmap_arg));
+ mmap_arg.handle = bo_gem->gem_handle;
+ mmap_arg.offset = 0;
+ mmap_arg.size = bo->size;
+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_MMAP, &mmap_arg);
+ if (ret != 0) {
+ fprintf(stderr, "%s:%d: Error mapping buffer %d (%s): %s .\n",
+ __FILE__, __LINE__,
+ bo_gem->gem_handle, bo_gem->name, strerror(errno));
+ }
+ bo_gem->virtual = (void *)(uintptr_t)mmap_arg.addr_ptr;
}
- bo_gem->virtual = (void *)(uintptr_t)mmap_arg.addr_ptr;
+ bo->virtual = bo_gem->virtual;
+ DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, bo_gem->virtual);
}
- bo->virtual = bo_gem->virtual;
- DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, bo_gem->virtual);
- set_domain.handle = bo_gem->gem_handle;
- set_domain.read_domains = DRM_GEM_DOMAIN_CPU;
- set_domain.write_domain = write_enable ? DRM_GEM_DOMAIN_CPU : 0;
- ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_GEM_SET_DOMAIN, &set_domain);
- if (ret != 0) {
- fprintf (stderr, "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
- __FILE__, __LINE__,
- bo_gem->gem_handle, set_domain.read_domains, set_domain.write_domain,
- strerror (errno));
+ if (!bo_gem->cpu_domain_set) {
+ set_domain.handle = bo_gem->gem_handle;
+ set_domain.read_domains = DRM_GEM_DOMAIN_CPU;
+ set_domain.write_domain = write_enable ? DRM_GEM_DOMAIN_CPU : 0;
+ ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_GEM_SET_DOMAIN, &set_domain);
+ if (ret != 0) {
+ fprintf (stderr, "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
+ __FILE__, __LINE__,
+ bo_gem->gem_handle, set_domain.read_domains, set_domain.write_domain,
+ strerror (errno));
+ }
+ bo_gem->cpu_domain_set = GL_TRUE;
}
return 0;
@@ -746,6 +756,9 @@ dri_gem_post_submit(dri_bo *batch_buf)
dri_bo *bo = bufmgr_gem->exec_bos[i];
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+ /* Need to call set_domain on next bo_map */
+ bo_gem->cpu_domain_set = GL_FALSE;
+
/* Disconnect the buffer from the validate list */
bo_gem->validate_index = -1;
dri_bo_unreference(bo);
--
cgit v1.2.3
From 6cefae5354fb3015c5a14677071871613faa9c3a Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Mon, 19 May 2008 15:42:00 -0700
Subject: Add back a mostly-correct glFinish for GEM and fake.
The right solution would probably be keeping a list of regions which have been
rendered to.
---
src/mesa/drivers/dri/common/dri_bufmgr.c | 6 ++++++
src/mesa/drivers/dri/common/dri_bufmgr.h | 9 +++++++++
src/mesa/drivers/dri/intel/intel_bufmgr_fake.c | 10 +++++++---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 21 +++++++++++++++++++++
src/mesa/drivers/dri/intel/intel_context.c | 7 ++++++-
5 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.c b/src/mesa/drivers/dri/common/dri_bufmgr.c
index 19ea2a8f86..be2a7b740c 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr.c
+++ b/src/mesa/drivers/dri/common/dri_bufmgr.c
@@ -127,6 +127,12 @@ dri_bo_get_subdata(dri_bo *bo, unsigned long offset,
return 0;
}
+void
+dri_bo_wait_rendering(dri_bo *bo)
+{
+ bo->bufmgr->bo_wait_rendering(bo);
+}
+
void
dri_bufmgr_destroy(dri_bufmgr *bufmgr)
{
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.h b/src/mesa/drivers/dri/common/dri_bufmgr.h
index 29f9aea2b1..1abca08cc8 100644
--- a/src/mesa/drivers/dri/common/dri_bufmgr.h
+++ b/src/mesa/drivers/dri/common/dri_bufmgr.h
@@ -127,6 +127,14 @@ struct _dri_bufmgr {
int (*bo_get_subdata) (dri_bo *bo, unsigned long offset,
unsigned long size, void *data);
+ /**
+ * Waits for rendering to an object by the GPU to have completed.
+ *
+ * This is not required for any access to the BO by bo_map, bo_subdata, etc.
+ * It is merely a way for the driver to implement glFinish.
+ */
+ void (*bo_wait_rendering) (dri_bo *bo);
+
/**
* Tears down the buffer manager instance.
*/
@@ -192,6 +200,7 @@ int dri_bo_subdata(dri_bo *bo, unsigned long offset,
unsigned long size, const void *data);
int dri_bo_get_subdata(dri_bo *bo, unsigned long offset,
unsigned long size, void *data);
+void dri_bo_wait_rendering(dri_bo *bo);
void dri_bufmgr_set_debug(dri_bufmgr *bufmgr, GLboolean enable_debug);
void dri_bufmgr_destroy(dri_bufmgr *bufmgr);
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_fake.c b/src/mesa/drivers/dri/intel/intel_bufmgr_fake.c
index 5d01a471c5..2aed3d85be 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_fake.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_fake.c
@@ -533,10 +533,13 @@ dri_bufmgr_fake_wait_idle(dri_bufmgr_fake *bufmgr_fake)
}
/**
- * Wait for execution pending on a buffer
+ * Wait for rendering to a buffer to complete.
+ *
+ * It is assumed that the bathcbuffer which performed the rendering included
+ * the necessary flushing.
*/
static void
-dri_bufmgr_fake_bo_wait_idle(dri_bo *bo)
+dri_fake_bo_wait_rendering(dri_bo *bo)
{
dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
@@ -757,7 +760,7 @@ dri_fake_bo_map(dri_bo *bo, GLboolean write_enable)
if (!(bo_fake->flags & BM_NO_FENCE_SUBDATA) &&
bo_fake->block->fenced) {
- dri_bufmgr_fake_bo_wait_idle(bo);
+ dri_fake_bo_wait_rendering(bo);
}
bo->virtual = bo_fake->block->virtual;
@@ -1157,6 +1160,7 @@ dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual,
bufmgr_fake->bufmgr.bo_unreference = dri_fake_bo_unreference;
bufmgr_fake->bufmgr.bo_map = dri_fake_bo_map;
bufmgr_fake->bufmgr.bo_unmap = dri_fake_bo_unmap;
+ bufmgr_fake->bufmgr.bo_wait_rendering = dri_fake_bo_wait_rendering;
bufmgr_fake->bufmgr.destroy = dri_fake_destroy;
bufmgr_fake->bufmgr.emit_reloc = dri_fake_emit_reloc;
bufmgr_fake->bufmgr.process_relocs = dri_fake_process_relocs;
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index b472a8f6e1..8638d0af1a 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -595,6 +595,26 @@ dri_gem_bo_get_subdata (dri_bo *bo, unsigned long offset,
return 0;
}
+static void
+dri_gem_bo_wait_rendering(dri_bo *bo)
+{
+ dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
+ struct drm_gem_set_domain set_domain;
+ int ret;
+
+ set_domain.handle = bo_gem->gem_handle;
+ set_domain.read_domains = DRM_GEM_DOMAIN_CPU;
+ set_domain.write_domain = 0;
+ ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_GEM_SET_DOMAIN, &set_domain);
+ if (ret != 0) {
+ fprintf (stderr, "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
+ __FILE__, __LINE__,
+ bo_gem->gem_handle, set_domain.read_domains, set_domain.write_domain,
+ strerror (errno));
+ }
+}
+
static void
dri_bufmgr_gem_destroy(dri_bufmgr *bufmgr)
{
@@ -827,6 +847,7 @@ intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem->bufmgr.bo_unmap = dri_gem_bo_unmap;
bufmgr_gem->bufmgr.bo_subdata = dri_gem_bo_subdata;
bufmgr_gem->bufmgr.bo_get_subdata = dri_gem_bo_get_subdata;
+ bufmgr_gem->bufmgr.bo_wait_rendering = dri_gem_bo_wait_rendering;
bufmgr_gem->bufmgr.destroy = dri_bufmgr_gem_destroy;
bufmgr_gem->bufmgr.emit_reloc = dri_gem_emit_reloc;
bufmgr_gem->bufmgr.process_relocs = dri_gem_process_reloc;
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index ae9e53ce6e..6f187f719b 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -375,7 +375,12 @@ intelFinish(GLcontext * ctx)
intelFlush(ctx);
for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
- /* XXX: Wait on buffer idle */
+ struct intel_renderbuffer *irb;
+
+ irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]);
+
+ if (irb->region)
+ dri_bo_wait_rendering(irb->region->buffer);
}
if (fb->_DepthBuffer) {
/* XXX: Wait on buffer idle */
--
cgit v1.2.3
From a74bf4ef345d880d7d296313fed0240781d2ebd8 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 23 May 2008 12:18:50 -0700
Subject: Emit a flush after the swapbuffers blit, so contents end up on the
screen.
Otherwise, since the MI_FLUSH at the end of every batch had been removed,
non-automatic-flushing chips (965) wouldn't get flushed and apps with static
rendering would get partial screen contents until the server's blockhandler
flush kicked in.
---
src/mesa/drivers/dri/i915/i830_reg.h | 4 ----
src/mesa/drivers/dri/i915/i915_reg.h | 6 ------
src/mesa/drivers/dri/i965/brw_defines.h | 1 -
src/mesa/drivers/dri/intel/intel_blit.c | 8 ++++++++
src/mesa/drivers/dri/intel/intel_reg.h | 4 ++++
5 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_reg.h b/src/mesa/drivers/dri/i915/i830_reg.h
index 41280bca7c..d1084a84c0 100644
--- a/src/mesa/drivers/dri/i915/i830_reg.h
+++ b/src/mesa/drivers/dri/i915/i830_reg.h
@@ -635,8 +635,4 @@
#define ENABLE_TEX_STREAM_MAP_IDX (1<<3)
#define TEX_STREAM_MAP_IDX(x) (x)
-
-#define MI_FLUSH ((0<<29)|(4<<23))
-#define FLUSH_MAP_CACHE (1<<0)
-
#endif
diff --git a/src/mesa/drivers/dri/i915/i915_reg.h b/src/mesa/drivers/dri/i915/i915_reg.h
index b5585e70e7..b718b8610c 100644
--- a/src/mesa/drivers/dri/i915/i915_reg.h
+++ b/src/mesa/drivers/dri/i915/i915_reg.h
@@ -855,10 +855,4 @@
#define _3DSTATE_DEFAULT_DIFFUSE ((0x3<<29)|(0x1d<<24)|(0x99<<16))
#define _3DSTATE_DEFAULT_SPECULAR ((0x3<<29)|(0x1d<<24)|(0x9a<<16))
-
-#define MI_FLUSH ((0<<29)|(4<<23))
-#define FLUSH_MAP_CACHE (1<<0)
-#define INHIBIT_FLUSH_RENDER_CACHE (1<<2)
-
-
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 3aada8cab1..0fb531b1ee 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -38,7 +38,6 @@
#define MI_NOOP 0x00
#define MI_USER_INTERRUPT 0x02
#define MI_WAIT_FOR_EVENT 0x03
-#define MI_FLUSH 0x04
#define MI_REPORT_HEAD 0x07
#define MI_ARB_ON_OFF 0x08
#define MI_BATCH_BUFFER_END 0x0A
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 3d7f64e28b..a1f4997312 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -159,6 +159,14 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
ADVANCE_BATCH();
}
+ /* Emit a flush so that, on systems where we don't have automatic flushing
+ * set (such as 965), the results all land on the screen in a timely
+ * fashion.
+ */
+ BEGIN_BATCH(1, IGNORE_CLIPRECTS);
+ OUT_BATCH(MI_FLUSH);
+ ADVANCE_BATCH();
+
intel_batchbuffer_flush(intel->batch);
}
diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h
index 37629c07e2..c12ccf4ae1 100644
--- a/src/mesa/drivers/dri/intel/intel_reg.h
+++ b/src/mesa/drivers/dri/intel/intel_reg.h
@@ -31,6 +31,10 @@
#define MI_BATCH_BUFFER_END (CMD_MI | 0xA << 23)
+#define MI_FLUSH (CMD_MI | (4 << 23))
+#define FLUSH_MAP_CACHE (1 << 0)
+#define INHIBIT_FLUSH_RENDER_CACHE (1 << 2)
+
/* Stalls command execution waiting for the given events to have occurred. */
#define MI_WAIT_FOR_EVENT (CMD_MI | (0x3 << 23))
#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
--
cgit v1.2.3
From 200fd13d4a605bea07857d6c3e7c85ee07d663cb Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 23 May 2008 12:43:05 -0700
Subject: Remove stale comment about glFlush().
We don't need an MI_FLUSH there, because everything that's been flushed in the
batch will eventually hit the hardware.
---
src/mesa/drivers/dri/intel/intel_context.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 6f187f719b..e1941c302c 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -361,9 +361,6 @@ intelFlush(GLcontext * ctx)
if (intel->batch->map != intel->batch->ptr)
intel_batchbuffer_flush(intel->batch);
-
- /* XXX: Need to do an MI_FLUSH here.
- */
}
void
--
cgit v1.2.3
From 8ba91b4636a04145e683e7d7fe5ee5ff404d73ac Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Sun, 25 May 2008 20:49:53 -0700
Subject: [intel] Enable buffer re-use for gem
Use the new DRM_IOCTL_I915_GEM_BUSY ioctl to detect
idle buffers for re-use.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 17 +++++------------
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index 8638d0af1a..f561b71ebb 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -293,16 +293,11 @@ dri_gem_bo_alloc(dri_bufmgr *bufmgr, const char *name,
/* Get a buffer out of the cache if available */
if (bucket != NULL && bucket->num_entries > 0) {
struct dri_gem_bo_bucket_entry *entry = bucket->head;
-#if 0
- int busy;
-
- /* XXX */
- /* Check if the buffer is still in flight. If not, reuse it. */
- ret = drmBOBusy(bufmgr_gem->fd, &entry->drm_bo, &busy);
- alloc_from_cache = (ret == 0 && busy == 0);
-#else
- alloc_from_cache = 0;
-#endif
+ struct drm_i915_gem_busy busy;
+
+ busy.handle = entry->gem_handle;
+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
+ alloc_from_cache = (ret == 0 && busy.busy == 0);
if (alloc_from_cache) {
bucket->head = entry->next;
@@ -797,14 +792,12 @@ dri_gem_post_submit(dri_bo *batch_buf)
void
intel_gem_enable_bo_reuse(dri_bufmgr *bufmgr)
{
- /*
dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr;
int i;
for (i = 0; i < INTEL_GEM_BO_BUCKETS; i++) {
bufmgr_gem->cache_bucket[i].max_entries = -1;
}
- */
}
/*
--
cgit v1.2.3
From 924eaa2f955ecdc1080f5a8fdc165367a576a919 Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Mon, 26 May 2008 00:19:20 -0700
Subject: [intel] all flushing in intelEmitCopyBlit
Add both MI_FLUSH and intel_batchbuffer_flush to intelEmitCopyBlit.
This ensures that the data are flushed *and* the gem kernel driver sees the
various memory domain transitions.
---
src/mesa/drivers/dri/intel/intel_blit.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index a1f4997312..e8d2ad0ae4 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -375,6 +375,10 @@ intelEmitCopyBlit(struct intel_context *intel,
src_offset + src_y * src_pitch);
ADVANCE_BATCH();
}
+ BEGIN_BATCH(1, NO_LOOP_CLIPRECTS);
+ OUT_BATCH(MI_FLUSH);
+ ADVANCE_BATCH();
+ intel_batchbuffer_flush(intel->batch);
}
--
cgit v1.2.3
From d8395f9d9eed4040d6fa12f1631dd7c372c73be4 Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Mon, 26 May 2008 17:51:38 -0700
Subject: [intel-gem] Once mapped, leave buffers mapped.
Mapping and unmapping buffers is expensive, and having the map around isn't
harmful (other than consuming address space). So, once mapped, just leave
buffers mapped in case they get re-used.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 23 ++++++-----------------
1 file changed, 6 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index f561b71ebb..f762b485f6 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -107,7 +107,7 @@ typedef struct _dri_bo_gem {
dri_bo bo;
int refcount;
- unsigned int map_count;
+ GLboolean mapped;
uint32_t gem_handle;
const char *name;
@@ -412,7 +412,8 @@ dri_gem_bo_unreference(dri_bo *bo)
struct dri_gem_bo_bucket *bucket;
int ret;
- assert(bo_gem->map_count == 0);
+ if (bo_gem->mapped)
+ munmap (bo_gem->virtual, bo->size);
if (bo_gem->relocs != NULL) {
int i;
@@ -474,7 +475,7 @@ dri_gem_bo_map(dri_bo *bo, GLboolean write_enable)
/* Allow recursive mapping. Mesa may recursively map buffers with
* nested display loops.
*/
- if (bo_gem->map_count++ == 0) {
+ if (!bo_gem->mapped) {
assert(bo->virtual == NULL);
@@ -496,6 +497,7 @@ dri_gem_bo_map(dri_bo *bo, GLboolean write_enable)
bo_gem->virtual = (void *)(uintptr_t)mmap_arg.addr_ptr;
}
bo->virtual = bo_gem->virtual;
+ bo_gem->mapped = GL_TRUE;
DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, bo_gem->virtual);
}
@@ -519,25 +521,12 @@ dri_gem_bo_map(dri_bo *bo, GLboolean write_enable)
static int
dri_gem_bo_unmap(dri_bo *bo)
{
- dri_bufmgr_gem *bufmgr_gem;
dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
if (bo == NULL)
return 0;
- assert(bo_gem->map_count != 0);
- if (--bo_gem->map_count != 0)
- return 0;
-
- bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
-
- assert(bo->virtual != NULL);
-
- DBG("bo_unmap: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
-
- munmap(bo_gem->virtual, bo->size);
- bo_gem->virtual = NULL;
- bo->virtual = NULL;
+ assert(bo_gem->mapped);
return 0;
}
--
cgit v1.2.3
From fccc427aac17b3fa17160332e6e6f3c2cef25ca5 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 30 May 2008 15:12:15 -0700
Subject: [intel-gem] Remember last offset of reused BOs to avoid more kernel
relocs.
This is good for about 5% on ipers on 965, and should help any cpu-bound app.
---
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
index f762b485f6..3c1c3157e1 100644
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
@@ -65,6 +65,7 @@ struct intel_validate_entry {
struct dri_gem_bo_bucket_entry {
uint32_t gem_handle;
+ uint32_t last_offset;
struct dri_gem_bo_bucket_entry *next;
};
@@ -306,6 +307,7 @@ dri_gem_bo_alloc(dri_bufmgr *bufmgr, const char *name,
bucket->num_entries--;
bo_gem->gem_handle = entry->gem_handle;
+ bo_gem->bo.offset = entry->last_offset;
free(entry);
}
}
@@ -324,7 +326,6 @@ dri_gem_bo_alloc(dri_bufmgr *bufmgr, const char *name,
}
}
- bo_gem->bo.offset = 0;
bo_gem->bo.virtual = NULL;
bo_gem->bo.bufmgr = bufmgr;
bo_gem->name = name;
@@ -436,6 +437,7 @@ dri_gem_bo_unreference(dri_bo *bo)
entry = calloc(1, sizeof(*entry));
entry->gem_handle = bo_gem->gem_handle;
+ entry->last_offset = bo->offset;
entry->next = NULL;
*bucket->tail = entry;
--
cgit v1.2.3
From 4b5b008d54e86ac4f0a2176429d062100978ca8c Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Tue, 3 Jun 2008 14:43:48 -0700
Subject: [intel] Convert drivers to using libdrm bufmgr code.
---
src/mesa/drivers/dri/Makefile.template | 4 -
src/mesa/drivers/dri/common/dri_bufmgr.c | 171 ---
src/mesa/drivers/dri/common/dri_bufmgr.h | 216 ----
src/mesa/drivers/dri/i915/Makefile | 5 +-
src/mesa/drivers/dri/i915/intel_bufmgr_fake.c | 1 -
src/mesa/drivers/dri/i915/intel_bufmgr_gem.c | 1 -
src/mesa/drivers/dri/i915/intel_bufmgr_ttm.c | 1 -
src/mesa/drivers/dri/i965/Makefile | 3 -
src/mesa/drivers/dri/i965/brw_cc.c | 12 +-
src/mesa/drivers/dri/i965/brw_clip_state.c | 12 +-
src/mesa/drivers/dri/i965/brw_curbe.c | 5 +-
src/mesa/drivers/dri/i965/brw_draw_upload.c | 5 +-
src/mesa/drivers/dri/i965/brw_gs_state.c | 10 +-
src/mesa/drivers/dri/i965/brw_sf_state.c | 20 +-
src/mesa/drivers/dri/i965/brw_state_cache.c | 5 +-
src/mesa/drivers/dri/i965/brw_vs_state.c | 10 +-
src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 12 +-
src/mesa/drivers/dri/i965/brw_wm_state.c | 32 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 34 +-
src/mesa/drivers/dri/i965/intel_bufmgr_fake.c | 1 -
src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 1 -
src/mesa/drivers/dri/i965/intel_bufmgr_ttm.c | 1 -
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 8 +-
src/mesa/drivers/dri/intel/intel_buffer_objects.c | 3 +-
src/mesa/drivers/dri/intel/intel_bufmgr_fake.c | 1177 ---------------------
src/mesa/drivers/dri/intel/intel_bufmgr_fake.h | 50 -
src/mesa/drivers/dri/intel/intel_bufmgr_gem.c | 847 ---------------
src/mesa/drivers/dri/intel/intel_bufmgr_gem.h | 16 -
src/mesa/drivers/dri/intel/intel_bufmgr_ttm.c | 1102 -------------------
src/mesa/drivers/dri/intel/intel_bufmgr_ttm.h | 20 -
src/mesa/drivers/dri/intel/intel_context.c | 19 +-
src/mesa/drivers/dri/intel/intel_context.h | 1 +
src/mesa/drivers/dri/intel/intel_ioctl.c | 2 +-
src/mesa/drivers/dri/intel/intel_regions.c | 33 +-
src/mesa/drivers/dri/intel/intel_screen.c | 2 +-
35 files changed, 105 insertions(+), 3737 deletions(-)
delete mode 100644 src/mesa/drivers/dri/common/dri_bufmgr.c
delete mode 100644 src/mesa/drivers/dri/common/dri_bufmgr.h
delete mode 120000 src/mesa/drivers/dri/i915/intel_bufmgr_fake.c
delete mode 120000 src/mesa/drivers/dri/i915/intel_bufmgr_gem.c
delete mode 120000 src/mesa/drivers/dri/i915/intel_bufmgr_ttm.c
delete mode 120000 src/mesa/drivers/dri/i965/intel_bufmgr_fake.c
delete mode 120000 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
delete mode 120000 src/mesa/drivers/dri/i965/intel_bufmgr_ttm.c
delete mode 100644 src/mesa/drivers/dri/intel/intel_bufmgr_fake.c
delete mode 100644 src/mesa/drivers/dri/intel/intel_bufmgr_fake.h
delete mode 100644 src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
delete mode 100644 src/mesa/drivers/dri/intel/intel_bufmgr_gem.h
delete mode 100644 src/mesa/drivers/dri/intel/intel_bufmgr_ttm.c
delete mode 100644 src/mesa/drivers/dri/intel/intel_bufmgr_ttm.h
diff --git a/src/mesa/drivers/dri/Makefile.template b/src/mesa/drivers/dri/Makefile.template
index cb41662707..864c6234c8 100644
--- a/src/mesa/drivers/dri/Makefile.template
+++ b/src/mesa/drivers/dri/Makefile.template
@@ -11,10 +11,6 @@ COMMON_SOURCES = \
../common/xmlconfig.c \
../common/drirenderbuffer.c
-COMMON_BM_SOURCES = \
- ../common/dri_bufmgr.c
-
-
ifeq ($(WINDOW_SYSTEM),dri)
WINOBJ=
WINLIB=
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.c b/src/mesa/drivers/dri/common/dri_bufmgr.c
deleted file mode 100644
index be2a7b740c..0000000000
--- a/src/mesa/drivers/dri/common/dri_bufmgr.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright © 2007 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Eric Anholt
- *
- */
-
-#include
-#include
-#include
-#include "mtypes.h"
-#include "dri_bufmgr.h"
-
-/** @file dri_bufmgr.c
- *
- * Convenience functions for buffer management methods.
- */
-
-dri_bo *
-dri_bo_alloc(dri_bufmgr *bufmgr, const char *name, unsigned long size,
- unsigned int alignment, uint64_t location_mask)
-{
- assert((location_mask & ~(DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_MEM_TT |
- DRM_BO_FLAG_MEM_VRAM | DRM_BO_FLAG_MEM_PRIV0 |
- DRM_BO_FLAG_MEM_PRIV1 | DRM_BO_FLAG_MEM_PRIV2 |
- DRM_BO_FLAG_MEM_PRIV3 | DRM_BO_FLAG_MEM_PRIV4 |
- DRM_BO_FLAG_CACHED | DRM_BO_FLAG_CACHED_MAPPED)) == 0);
- return bufmgr->bo_alloc(bufmgr, name, size, alignment, location_mask);
-}
-
-dri_bo *
-dri_bo_alloc_static(dri_bufmgr *bufmgr, const char *name, unsigned long offset,
- unsigned long size, void *virtual,
- uint64_t location_mask)
-{
- assert((location_mask & ~(DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_MEM_TT |
- DRM_BO_FLAG_MEM_VRAM | DRM_BO_FLAG_MEM_PRIV0 |
- DRM_BO_FLAG_MEM_PRIV1 | DRM_BO_FLAG_MEM_PRIV2 |
- DRM_BO_FLAG_MEM_PRIV3 |
- DRM_BO_FLAG_MEM_PRIV4)) == 0);
-
- return bufmgr->bo_alloc_static(bufmgr, name, offset, size, virtual,
- location_mask);
-}
-
-void
-dri_bo_reference(dri_bo *bo)
-{
- bo->bufmgr->bo_reference(bo);
-}
-
-void
-dri_bo_unreference(dri_bo *bo)
-{
- if (bo == NULL)
- return;
-
- bo->bufmgr->bo_unreference(bo);
-}
-
-int
-dri_bo_map(dri_bo *buf, GLboolean write_enable)
-{
- return buf->bufmgr->bo_map(buf, write_enable);
-}
-
-int
-dri_bo_unmap(dri_bo *buf)
-{
- return buf->bufmgr->bo_unmap(buf);
-}
-
-int
-dri_bo_subdata(dri_bo *bo, unsigned long offset,
- unsigned long size, const void *data)
-{
- int ret;
- if (bo->bufmgr->bo_subdata)
- return bo->bufmgr->bo_subdata(bo, offset, size, data);
- if (size == 0 || data == NULL)
- return 0;
-
- ret = dri_bo_map(bo, GL_TRUE);
- if (ret)
- return ret;
- memcpy((unsigned char *)bo->virtual + offset, data, size);
- dri_bo_unmap(bo);
- return 0;
-}
-
-int
-dri_bo_get_subdata(dri_bo *bo, unsigned long offset,
- unsigned long size, void *data)
-{
- int ret;
- if (bo->bufmgr->bo_subdata)
- return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
-
- if (size == 0 || data == NULL)
- return 0;
-
- ret = dri_bo_map(bo, GL_FALSE);
- if (ret)
- return ret;
- memcpy(data, (unsigned char *)bo->virtual + offset, size);
- dri_bo_unmap(bo);
- return 0;
-}
-
-void
-dri_bo_wait_rendering(dri_bo *bo)
-{
- bo->bufmgr->bo_wait_rendering(bo);
-}
-
-void
-dri_bufmgr_destroy(dri_bufmgr *bufmgr)
-{
- bufmgr->destroy(bufmgr);
-}
-
-
-int dri_emit_reloc(dri_bo *reloc_buf,
- uint32_t read_domains, uint32_t write_domain,
- uint32_t delta, uint32_t offset, dri_bo *target_buf)
-{
- return reloc_buf->bufmgr->emit_reloc(reloc_buf, read_domains, write_domain,
- delta, offset, target_buf);
-}
-
-void *dri_process_relocs(dri_bo *batch_buf)
-{
- return batch_buf->bufmgr->process_relocs(batch_buf);
-}
-
-void dri_post_submit(dri_bo *batch_buf)
-{
- batch_buf->bufmgr->post_submit(batch_buf);
-}
-
-void
-dri_bufmgr_set_debug(dri_bufmgr *bufmgr, GLboolean enable_debug)
-{
- bufmgr->debug = enable_debug;
-}
-
-int
-dri_bufmgr_check_aperture_space(dri_bo *bo)
-{
- return bo->bufmgr->check_aperture_space(bo);
-}
diff --git a/src/mesa/drivers/dri/common/dri_bufmgr.h b/src/mesa/drivers/dri/common/dri_bufmgr.h
deleted file mode 100644
index 1abca08cc8..0000000000
--- a/src/mesa/drivers/dri/common/dri_bufmgr.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2007 Intel Corporation
- * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellström
- * Keith Whitwell
- * Eric Anholt
- */
-
-#ifndef _DRI_BUFMGR_H_
-#define _DRI_BUFMGR_H_
-#include
-
-typedef struct _dri_bufmgr dri_bufmgr;
-typedef struct _dri_bo dri_bo;
-
-struct _dri_bo {
- /**
- * Size in bytes of the buffer object.
- *
- * The size may be larger than the size originally requested for the
- * allocation, such as being aligned to page size.
- */
- unsigned long size;
- /**
- * Card virtual address (offset from the beginning of the aperture) for the
- * object. Only valid while validated.
- */
- unsigned long offset;
- /**
- * Virtual address for accessing the buffer data. Only valid while mapped.
- */
- void *virtual;
- /** Buffer manager context associated with this buffer object */
- dri_bufmgr *bufmgr;
-};
-
-/**
- * Context for a buffer manager instance.
- *
- * Contains public methods followed by private storage for the buffer manager.
- */
-struct _dri_bufmgr {
- /**
- * Allocate a buffer object.
- *
- * Buffer objects are not necessarily initially mapped into CPU virtual
- * address space or graphics device aperture. They must be mapped using
- * bo_map() to be used by the CPU, and validated for use using bo_validate()
- * to be used from the graphics device.
- */
- dri_bo *(*bo_alloc)(dri_bufmgr *bufmgr_ctx, const char *name,
- unsigned long size, unsigned int alignment,
- uint64_t location_mask);
-
- /**
- * Allocates a buffer object for a static allocation.
- *
- * Static allocations are ones such as the front buffer that are offered by
- * the X Server, which are never evicted and never moved.
- */
- dri_bo *(*bo_alloc_static)(dri_bufmgr *bufmgr_ctx, const char *name,
- unsigned long offset, unsigned long size,
- void *virtual, uint64_t location_mask);
-
- /** Takes a reference on a buffer object */
- void (*bo_reference)(dri_bo *bo);
-
- /**
- * Releases a reference on a buffer object, freeing the data if
- * rerefences remain.
- */
- void (*bo_unreference)(dri_bo *bo);
-
- /**
- * Maps the buffer into userspace.
- *
- * This function will block waiting for any existing execution on the
- * buffer to complete, first. The resulting mapping is available at
- * buf->virtual.
- */
- int (*bo_map)(dri_bo *buf, GLboolean write_enable);
-
- /** Reduces the refcount on the userspace mapping of the buffer object. */
- int (*bo_unmap)(dri_bo *buf);
-
- /**
- * Write data into an object.
- *
- * This is an optional function, if missing,
- * dri_bo will map/memcpy/unmap.
- */
- int (*bo_subdata) (dri_bo *buf, unsigned long offset,
- unsigned long size, const void *data);
-
- /**
- * Read data from an object
- *
- * This is an optional function, if missing,
- * dri_bo will map/memcpy/unmap.
- */
- int (*bo_get_subdata) (dri_bo *bo, unsigned long offset,
- unsigned long size, void *data);
-
- /**
- * Waits for rendering to an object by the GPU to have completed.
- *
- * This is not required for any access to the BO by bo_map, bo_subdata, etc.
- * It is merely a way for the driver to implement glFinish.
- */
- void (*bo_wait_rendering) (dri_bo *bo);
-
- /**
- * Tears down the buffer manager instance.
- */
- void (*destroy)(dri_bufmgr *bufmgr);
-
- /**
- * Add relocation entry in reloc_buf, which will be updated with the
- * target buffer's real offset on on command submission.
- *
- * Relocations remain in place for the lifetime of the buffer object.
- *
- * \param reloc_buf Buffer to write the relocation into.
- * \param flags BO flags to be used in validating the target buffer.
- * Applicable flags include:
- * - DRM_BO_FLAG_READ: The buffer will be read in the process of
- * command execution.
- * - DRM_BO_FLAG_WRITE: The buffer will be written in the process of
- * command execution.
- * - DRM_BO_FLAG_MEM_TT: The buffer should be validated in TT memory.
- * - DRM_BO_FLAG_MEM_VRAM: The buffer should be validated in video
- * memory.
- * \param delta Constant value to be added to the relocation target's offset.
- * \param offset Byte offset within batch_buf of the relocated pointer.
- * \param target Buffer whose offset should be written into the relocation
- * entry.
- */
- int (*emit_reloc)(dri_bo *reloc_buf,
- uint32_t read_domains, uint32_t write_domain,
- uint32_t delta, uint32_t offset, dri_bo *target);
-
- /**
- * Processes the relocations, either in userland or by converting the list
- * for use in batchbuffer submission.
- *
- * Kernel-based implementations will return a pointer to the arguments
- * to be handed with batchbuffer submission to the kernel. The userland
- * implementation performs the buffer validation and emits relocations
- * into them the appopriate order.
- *
- * \param batch_buf buffer at the root of the tree of relocations
- * \return argument to be completed and passed to the execbuffers ioctl
- * (if any).
- */
- void *(*process_relocs)(dri_bo *batch_buf);
-
- void (*post_submit)(dri_bo *batch_buf);
-
- int (*check_aperture_space)(dri_bo *bo);
- GLboolean debug; /**< Enables verbose debugging printouts */
-};
-
-dri_bo *dri_bo_alloc(dri_bufmgr *bufmgr, const char *name, unsigned long size,
- unsigned int alignment, uint64_t location_mask);
-dri_bo *dri_bo_alloc_static(dri_bufmgr *bufmgr, const char *name,
- unsigned long offset, unsigned long size,
- void *virtual, uint64_t location_mask);
-void dri_bo_reference(dri_bo *bo);
-void dri_bo_unreference(dri_bo *bo);
-int dri_bo_map(dri_bo *buf, GLboolean write_enable);
-int dri_bo_unmap(dri_bo *buf);
-
-int dri_bo_subdata(dri_bo *bo, unsigned long offset,
- unsigned long size, const void *data);
-int dri_bo_get_subdata(dri_bo *bo, unsigned long offset,
- unsigned long size, void *data);
-void dri_bo_wait_rendering(dri_bo *bo);
-
-void dri_bufmgr_set_debug(dri_bufmgr *bufmgr, GLboolean enable_debug);
-void dri_bufmgr_destroy(dri_bufmgr *bufmgr);
-
-int dri_emit_reloc(dri_bo *reloc_buf,
- uint32_t read_domains, uint32_t write_domain,
- uint32_t delta, uint32_t offset, dri_bo *target_buf);
-void *dri_process_relocs(dri_bo *batch_buf);
-void dri_post_process_relocs(dri_bo *batch_buf);
-void dri_post_submit(dri_bo *batch_buf);
-int dri_bufmgr_check_aperture_space(dri_bo *bo);
-
-#endif
diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index 476814c4ec..74f6169b2e 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -53,13 +53,10 @@ DRIVER_SOURCES = \
intel_state.c \
intel_tris.c \
intel_fbo.c \
- intel_depthstencil.c \
- intel_bufmgr_fake.c \
- intel_bufmgr_gem.c
+ intel_depthstencil.c
C_SOURCES = \
$(COMMON_SOURCES) \
- $(COMMON_BM_SOURCES) \
$(DRIVER_SOURCES)
ASM_SOURCES =
diff --git a/src/mesa/drivers/dri/i915/intel_bufmgr_fake.c b/src/mesa/drivers/dri/i915/intel_bufmgr_fake.c
deleted file mode 120000
index 9b840a8123..0000000000
--- a/src/mesa/drivers/dri/i915/intel_bufmgr_fake.c
+++ /dev/null
@@ -1 +0,0 @@
-../intel/intel_bufmgr_fake.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/i915/intel_bufmgr_gem.c b/src/mesa/drivers/dri/i915/intel_bufmgr_gem.c
deleted file mode 120000
index dee0daf9c0..0000000000
--- a/src/mesa/drivers/dri/i915/intel_bufmgr_gem.c
+++ /dev/null
@@ -1 +0,0 @@
-../intel/intel_bufmgr_gem.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/i915/intel_bufmgr_ttm.c b/src/mesa/drivers/dri/i915/intel_bufmgr_ttm.c
deleted file mode 120000
index e9df5c6279..0000000000
--- a/src/mesa/drivers/dri/i915/intel_bufmgr_ttm.c
+++ /dev/null
@@ -1 +0,0 @@
-../intel/intel_bufmgr_ttm.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 001f63ba12..c15418df06 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -9,8 +9,6 @@ DRIVER_SOURCES = \
intel_blit.c \
intel_buffer_objects.c \
intel_buffers.c \
- intel_bufmgr_fake.c \
- intel_bufmgr_gem.c \
intel_context.c \
intel_decode.c \
intel_depthstencil.c \
@@ -85,7 +83,6 @@ DRIVER_SOURCES = \
C_SOURCES = \
$(COMMON_SOURCES) \
- $(COMMON_BM_SOURCES) \
$(MINIGLX_SOURCES) \
$(DRIVER_SOURCES)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index b9338db0f5..afcfbcccb9 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -256,12 +256,12 @@ cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key)
NULL, NULL);
/* Emit CC viewport relocation */
- dri_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION,
- 0,
- 0,
- offsetof(struct brw_cc_unit_state, cc4),
- brw->cc.vp_bo);
+ intel_bo_emit_reloc(bo,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION,
+ 0,
+ 0,
+ offsetof(struct brw_cc_unit_state, cc4),
+ brw->cc.vp_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 26c322672c..fd5157bdb7 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -119,12 +119,12 @@ clip_unit_create_from_key(struct brw_context *brw,
/* Emit clip program relocation */
assert(brw->clip.prog_bo);
- dri_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION,
- 0,
- clip.thread0.grf_reg_count << 1,
- offsetof(struct brw_clip_unit_state, thread0),
- brw->clip.prog_bo);
+ intel_bo_emit_reloc(bo,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION,
+ 0,
+ clip.thread0.grf_reg_count << 1,
+ offsetof(struct brw_clip_unit_state, thread0),
+ brw->clip.prog_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 1b5e22f130..bd0b04c36f 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -306,10 +306,7 @@ static int prepare_constant_buffer(struct brw_context *brw)
* They're generally around 64b.
*/
brw->curbe.curbe_bo = dri_bo_alloc(brw->intel.bufmgr, "CURBE",
- 4096, 1 << 6,
- DRM_BO_FLAG_MEM_LOCAL |
- DRM_BO_FLAG_CACHED |
- DRM_BO_FLAG_CACHED_MAPPED);
+ 4096, 1 << 6);
brw->curbe.curbe_next_offset = 0;
}
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 5222d2e450..026c8ed898 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -247,10 +247,7 @@ static void wrap_buffers( struct brw_context *brw,
if (brw->vb.upload.bo != NULL)
dri_bo_unreference(brw->vb.upload.bo);
brw->vb.upload.bo = dri_bo_alloc(brw->intel.bufmgr, "temporary VBO",
- size, 1,
- DRM_BO_FLAG_MEM_LOCAL |
- DRM_BO_FLAG_CACHED |
- DRM_BO_FLAG_CACHED_MAPPED);
+ size, 1);
/* Set the internal VBO\ to no-backing-store. We only use them as a
* temporary within a brw_try_draw_prims while the lock is held.
diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index 2bf86f5573..953ccf777f 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -106,11 +106,11 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
if (key->prog_active) {
/* Emit GS program relocation */
- dri_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
- gs.thread0.grf_reg_count << 1,
- offsetof(struct brw_gs_unit_state, thread0),
- brw->gs.prog_bo);
+ intel_bo_emit_reloc(bo,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ gs.thread0.grf_reg_count << 1,
+ offsetof(struct brw_gs_unit_state, thread0),
+ brw->gs.prog_bo);
}
return bo;
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 5cf3228486..e8f36718a3 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -253,18 +253,18 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
NULL, NULL);
/* Emit SF program relocation */
- dri_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
- sf.thread0.grf_reg_count << 1,
- offsetof(struct brw_sf_unit_state, thread0),
- brw->sf.prog_bo);
+ intel_bo_emit_reloc(bo,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ sf.thread0.grf_reg_count << 1,
+ offsetof(struct brw_sf_unit_state, thread0),
+ brw->sf.prog_bo);
/* Emit SF viewport relocation */
- dri_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
- sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
- offsetof(struct brw_sf_unit_state, sf5),
- brw->sf.vp_bo);
+ intel_bo_emit_reloc(bo,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
+ offsetof(struct brw_sf_unit_state, sf5),
+ brw->sf.vp_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c
index d617650fad..fc0c3bd9ff 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -214,10 +214,7 @@ brw_upload_cache( struct brw_cache *cache,
/* Create the buffer object to contain the data */
bo = dri_bo_alloc(cache->brw->intel.bufmgr,
- cache->name[cache_id], data_size, 1 << 6,
- DRM_BO_FLAG_MEM_LOCAL |
- DRM_BO_FLAG_CACHED |
- DRM_BO_FLAG_CACHED_MAPPED);
+ cache->name[cache_id], data_size, 1 << 6);
/* Set up the memory containing the key, aux_data, and reloc_bufs */
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index 73f52d7428..a6b3db69ea 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -115,11 +115,11 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
NULL, NULL);
/* Emit VS program relocation */
- dri_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
- vs.thread0.grf_reg_count << 1,
- offsetof(struct brw_vs_unit_state, thread0),
- brw->vs.prog_bo);
+ intel_bo_emit_reloc(bo,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ vs.thread0.grf_reg_count << 1,
+ offsetof(struct brw_vs_unit_state, thread0),
+ brw->vs.prog_bo);
return bo;
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index 13f7f21800..2e0aff7ab2 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -305,12 +305,12 @@ static int upload_wm_samplers( struct brw_context *brw )
continue;
ret |= dri_bufmgr_check_aperture_space(brw->wm.sdc_bo[i]);
- dri_emit_reloc(brw->wm.sampler_bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
- 0,
- i * sizeof(struct brw_sampler_state) +
- offsetof(struct brw_sampler_state, ss2),
- brw->wm.sdc_bo[i]);
+ intel_bo_emit_reloc(brw->wm.sampler_bo,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ 0,
+ i * sizeof(struct brw_sampler_state) +
+ offsetof(struct brw_sampler_state, ss2),
+ brw->wm.sdc_bo[i]);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index f79b58ba7a..ef78d71bbb 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -199,28 +199,28 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
NULL, NULL);
/* Emit WM program relocation */
- dri_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
- wm.thread0.grf_reg_count << 1,
- offsetof(struct brw_wm_unit_state, thread0),
- brw->wm.prog_bo);
+ intel_bo_emit_reloc(bo,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ wm.thread0.grf_reg_count << 1,
+ offsetof(struct brw_wm_unit_state, thread0),
+ brw->wm.prog_bo);
/* Emit scratch space relocation */
if (key->total_scratch != 0) {
- dri_emit_reloc(bo,
- 0, 0,
- wm.thread2.per_thread_scratch_space,
- offsetof(struct brw_wm_unit_state, thread2),
- brw->wm.scratch_buffer);
+ intel_bo_emit_reloc(bo,
+ 0, 0,
+ wm.thread2.per_thread_scratch_space,
+ offsetof(struct brw_wm_unit_state, thread2),
+ brw->wm.scratch_buffer);
}
/* Emit sampler state relocation */
if (key->sampler_count != 0) {
- dri_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
- wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
- offsetof(struct brw_wm_unit_state, wm4),
- brw->wm.sampler_bo);
+ intel_bo_emit_reloc(bo,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
+ offsetof(struct brw_wm_unit_state, wm4),
+ brw->wm.sampler_bo);
}
return bo;
@@ -251,7 +251,7 @@ static int upload_wm_unit( struct brw_context *brw )
brw->wm.scratch_buffer = dri_bo_alloc(intel->bufmgr,
"wm scratch",
total,
- 4096, DRM_BO_FLAG_MEM_TT);
+ 4096);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 73f4b2b4a3..6fc6d9dfd8 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -203,11 +203,11 @@ brw_create_texture_surface( struct brw_context *brw,
NULL, NULL);
/* Emit relocation to surface contents */
- dri_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_SAMPLER, 0,
- 0,
- offsetof(struct brw_surface_state, ss1),
- key->bo);
+ intel_bo_emit_reloc(bo,
+ DRM_GEM_DOMAIN_I915_SAMPLER, 0,
+ 0,
+ offsetof(struct brw_surface_state, ss1),
+ key->bo);
return bo;
}
@@ -341,13 +341,13 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
* them both. We might be able to figure out from other state
* a more restrictive relocation to emit.
*/
- dri_emit_reloc(brw->wm.surf_bo[unit],
- DRM_GEM_DOMAIN_I915_RENDER |
- DRM_GEM_DOMAIN_I915_SAMPLER,
- DRM_GEM_DOMAIN_I915_RENDER,
- 0,
- offsetof(struct brw_surface_state, ss1),
- region_bo);
+ intel_bo_emit_reloc(brw->wm.surf_bo[unit],
+ DRM_GEM_DOMAIN_I915_RENDER |
+ DRM_GEM_DOMAIN_I915_SAMPLER,
+ DRM_GEM_DOMAIN_I915_RENDER,
+ 0,
+ offsetof(struct brw_surface_state, ss1),
+ region_bo);
}
}
@@ -391,11 +391,11 @@ brw_wm_get_binding_table(struct brw_context *brw)
/* Emit binding table relocations to surface state */
for (i = 0; i < BRW_WM_MAX_SURF; i++) {
if (brw->wm.surf_bo[i] != NULL) {
- dri_emit_reloc(bind_bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
- 0,
- i * sizeof(GLuint),
- brw->wm.surf_bo[i]);
+ intel_bo_emit_reloc(bind_bo,
+ DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ 0,
+ i * sizeof(GLuint),
+ brw->wm.surf_bo[i]);
}
}
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_fake.c b/src/mesa/drivers/dri/i965/intel_bufmgr_fake.c
deleted file mode 120000
index 9b840a8123..0000000000
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_fake.c
+++ /dev/null
@@ -1 +0,0 @@
-../intel/intel_bufmgr_fake.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
deleted file mode 120000
index dee0daf9c0..0000000000
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ /dev/null
@@ -1 +0,0 @@
-../intel/intel_bufmgr_gem.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_ttm.c b/src/mesa/drivers/dri/i965/intel_bufmgr_ttm.c
deleted file mode 120000
index e9df5c6279..0000000000
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_ttm.c
+++ /dev/null
@@ -1 +0,0 @@
-../intel/intel_bufmgr_ttm.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 803ff5e90e..019880581a 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -29,6 +29,7 @@
#include "intel_ioctl.h"
#include "intel_decode.h"
#include "intel_reg.h"
+#include "intel_bufmgr.h"
/* Relocations in kernel space:
* - pass dma buffer seperately
@@ -82,8 +83,7 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch)
batch->buffer = malloc (intel->maxBatchSize);
batch->buf = dri_bo_alloc(intel->bufmgr, "batchbuffer",
- intel->maxBatchSize, 4096,
- DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_CACHED | DRM_BO_FLAG_CACHED_MAPPED);
+ intel->maxBatchSize, 4096);
if (batch->buffer)
batch->map = batch->buffer;
else {
@@ -290,8 +290,8 @@ intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
if (batch->ptr - batch->map > batch->buf->size)
_mesa_printf ("bad relocation ptr %p map %p offset %d size %d\n",
batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
- ret = dri_emit_reloc(batch->buf, read_domains, write_domain,
- delta, batch->ptr - batch->map, buffer);
+ ret = intel_bo_emit_reloc(batch->buf, read_domains, write_domain,
+ delta, batch->ptr - batch->map, buffer);
/*
* Using the old buffer offset, write in what the right data would be, in case
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index 951b8cbfb7..4227f0c973 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -45,8 +45,7 @@ intel_bufferobj_alloc_buffer(struct intel_context *intel,
struct intel_buffer_object *intel_obj)
{
intel_obj->buffer = dri_bo_alloc(intel->bufmgr, "bufferobj",
- intel_obj->Base.Size, 64,
- DRM_BO_FLAG_MEM_LOCAL | DRM_BO_FLAG_CACHED | DRM_BO_FLAG_CACHED_MAPPED);
+ intel_obj->Base.Size, 64);
}
/**
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_fake.c b/src/mesa/drivers/dri/intel/intel_bufmgr_fake.c
deleted file mode 100644
index 2aed3d85be..0000000000
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_fake.c
+++ /dev/null
@@ -1,1177 +0,0 @@
-/**************************************************************************
- *
- * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-
-/* Originally a fake version of the buffer manager so that we can
- * prototype the changes in a driver fairly quickly, has been fleshed
- * out to a fully functional interim solution.
- *
- * Basically wraps the old style memory management in the new
- * programming interface, but is more expressive and avoids many of
- * the bugs in the old texture manager.
- */
-#include "mtypes.h"
-#include "dri_bufmgr.h"
-#include "intel_bufmgr_fake.h"
-#include "drm.h"
-#include "i915_drm.h"
-
-#include "simple_list.h"
-#include "mm.h"
-#include "imports.h"
-
-#define DBG(...) do { \
- if (bufmgr_fake->bufmgr.debug) \
- _mesa_printf(__VA_ARGS__); \
-} while (0)
-
-/* Internal flags:
- */
-#define BM_NO_BACKING_STORE 0x00000001
-#define BM_NO_FENCE_SUBDATA 0x00000002
-#define BM_PINNED 0x00000004
-
-/* Wrapper around mm.c's mem_block, which understands that you must
- * wait for fences to expire before memory can be freed. This is
- * specific to our use of memcpy for uploads - an upload that was
- * processed through the command queue wouldn't need to care about
- * fences.
- */
-#define MAX_RELOCS 4096
-
-struct fake_buffer_reloc
-{
- /** Buffer object that the relocation points at. */
- dri_bo *target_buf;
- /** Offset of the relocation entry within reloc_buf. */
- GLuint offset;
- /** Cached value of the offset when we last performed this relocation. */
- GLuint last_target_offset;
- /** Value added to target_buf's offset to get the relocation entry. */
- GLuint delta;
- /** Cache domains the target buffer is read into. */
- uint32_t read_domains;
- /** Cache domain the target buffer will have dirty cachelines in. */
- uint32_t write_domain;
-};
-
-struct block {
- struct block *next, *prev;
- struct mem_block *mem; /* BM_MEM_AGP */
-
- /**
- * Marks that the block is currently in the aperture and has yet to be
- * fenced.
- */
- unsigned on_hardware:1;
- /**
- * Marks that the block is currently fenced (being used by rendering) and
- * can't be freed until @fence is passed.
- */
- unsigned fenced:1;
-
- /** Fence cookie for the block. */
- unsigned fence; /* Split to read_fence, write_fence */
-
- dri_bo *bo;
- void *virtual;
-};
-
-typedef struct _bufmgr_fake {
- dri_bufmgr bufmgr;
-
- unsigned long low_offset;
- unsigned long size;
- void *virtual;
-
- struct mem_block *heap;
- struct block lru; /* only allocated, non-fence-pending blocks here */
-
- unsigned buf_nr; /* for generating ids */
-
- struct block on_hardware; /* after bmValidateBuffers */
- struct block fenced; /* after bmFenceBuffers (mi_flush, emit irq, write dword) */
- /* then to bufmgr->lru or free() */
-
- unsigned int last_fence;
-
- unsigned fail:1;
- unsigned need_fence:1;
- GLboolean thrashing;
-
- /**
- * Driver callback to emit a fence, returning the cookie.
- *
- * Currently, this also requires that a write flush be emitted before
- * emitting the fence, but this should change.
- */
- unsigned int (*fence_emit)(void *private);
- /** Driver callback to wait for a fence cookie to have passed. */
- int (*fence_wait)(void *private, unsigned int fence_cookie);
- /** Driver-supplied argument to driver callbacks */
- void *driver_priv;
-
- GLboolean debug;
-
- GLboolean performed_rendering;
-
- /* keep track of the current total size of objects we have relocs for */
- unsigned long current_total_size;
-} dri_bufmgr_fake;
-
-typedef struct _dri_bo_fake {
- dri_bo bo;
-
- unsigned id; /* debug only */
- const char *name;
-
- unsigned dirty:1;
- unsigned size_accounted:1; /*this buffers size has been accounted against the aperture */
- unsigned card_dirty:1; /* has the card written to this buffer - we make need to copy it back */
- unsigned int refcount;
- /* Flags may consist of any of the DRM_BO flags, plus
- * DRM_BO_NO_BACKING_STORE and BM_NO_FENCE_SUBDATA, which are the first two
- * driver private flags.
- */
- uint64_t flags;
- /** Cache domains the target buffer is read into. */
- uint32_t read_domains;
- /** Cache domain the target buffer will have dirty cachelines in. */
- uint32_t write_domain;
-
- unsigned int alignment;
- GLboolean is_static, validated;
- unsigned int map_count;
-
- /** relocation list */
- struct fake_buffer_reloc *relocs;
- GLuint nr_relocs;
-
- struct block *block;
- void *backing_store;
- void (*invalidate_cb)(dri_bo *bo, void *ptr);
- void *invalidate_ptr;
-} dri_bo_fake;
-
-static int clear_fenced(dri_bufmgr_fake *bufmgr_fake,
- unsigned int fence_cookie);
-
-static int dri_fake_check_aperture_space(dri_bo *bo);
-
-#define MAXFENCE 0x7fffffff
-
-static GLboolean FENCE_LTE( unsigned a, unsigned b )
-{
- if (a == b)
- return GL_TRUE;
-
- if (a < b && b - a < (1<<24))
- return GL_TRUE;
-
- if (a > b && MAXFENCE - a + b < (1<<24))
- return GL_TRUE;
-
- return GL_FALSE;
-}
-
-static unsigned int
-_fence_emit_internal(dri_bufmgr_fake *bufmgr_fake)
-{
- bufmgr_fake->last_fence = bufmgr_fake->fence_emit(bufmgr_fake->driver_priv);
- return bufmgr_fake->last_fence;
-}
-
-static void
-_fence_wait_internal(dri_bufmgr_fake *bufmgr_fake, unsigned int cookie)
-{
- int ret;
-
- ret = bufmgr_fake->fence_wait(bufmgr_fake->driver_priv, cookie);
- if (ret != 0) {
- _mesa_printf("%s:%d: Error %d waiting for fence.\n",
- __FILE__, __LINE__);
- abort();
- }
- clear_fenced(bufmgr_fake, cookie);
-}
-
-static GLboolean
-_fence_test(dri_bufmgr_fake *bufmgr_fake, unsigned fence)
-{
- /* Slight problem with wrap-around:
- */
- return fence == 0 || FENCE_LTE(fence, bufmgr_fake->last_fence);
-}
-
-/**
- * Allocate a memory manager block for the buffer.
- */
-static GLboolean
-alloc_block(dri_bo *bo)
-{
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- dri_bufmgr_fake *bufmgr_fake= (dri_bufmgr_fake *)bo->bufmgr;
- struct block *block = (struct block *)calloc(sizeof *block, 1);
- unsigned int align_log2 = _mesa_ffs(bo_fake->alignment) - 1;
- GLuint sz;
-
- if (!block)
- return GL_FALSE;
-
- sz = (bo->size + bo_fake->alignment - 1) & ~(bo_fake->alignment - 1);
-
- block->mem = mmAllocMem(bufmgr_fake->heap, sz, align_log2, 0);
- if (!block->mem) {
- free(block);
- return GL_FALSE;
- }
-
- make_empty_list(block);
-
- /* Insert at head or at tail???
- */
- insert_at_tail(&bufmgr_fake->lru, block);
-
- block->virtual = bufmgr_fake->virtual +
- block->mem->ofs - bufmgr_fake->low_offset;
- block->bo = bo;
-
- bo_fake->block = block;
-
- return GL_TRUE;
-}
-
-/* Release the card storage associated with buf:
- */
-static void free_block(dri_bufmgr_fake *bufmgr_fake, struct block *block)
-{
- dri_bo_fake *bo_fake;
- DBG("free block %p %08x %d %d\n", block, block->mem->ofs, block->on_hardware, block->fenced);
-
- if (!block)
- return;
-
- bo_fake = (dri_bo_fake *)block->bo;
- if (!(bo_fake->flags & BM_NO_BACKING_STORE) && (bo_fake->card_dirty == 1)) {
- memcpy(bo_fake->backing_store, block->virtual, block->bo->size);
- bo_fake->card_dirty = 1;
- bo_fake->dirty = 1;
- }
-
- if (block->on_hardware) {
- block->bo = NULL;
- }
- else if (block->fenced) {
- block->bo = NULL;
- }
- else {
- DBG(" - free immediately\n");
- remove_from_list(block);
-
- mmFreeMem(block->mem);
- free(block);
- }
-}
-
-static void
-alloc_backing_store(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- assert(!bo_fake->backing_store);
- assert(!(bo_fake->flags & (BM_PINNED|BM_NO_BACKING_STORE)));
-
- bo_fake->backing_store = ALIGN_MALLOC(bo->size, 64);
-
- DBG("alloc_backing - buf %d %p %d\n", bo_fake->id, bo_fake->backing_store, bo->size);
- assert(bo_fake->backing_store);
-}
-
-static void
-free_backing_store(dri_bo *bo)
-{
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- if (bo_fake->backing_store) {
- assert(!(bo_fake->flags & (BM_PINNED|BM_NO_BACKING_STORE)));
- ALIGN_FREE(bo_fake->backing_store);
- bo_fake->backing_store = NULL;
- }
-}
-
-static void
-set_dirty(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- if (bo_fake->flags & BM_NO_BACKING_STORE && bo_fake->invalidate_cb != NULL)
- bo_fake->invalidate_cb(bo, bo_fake->invalidate_ptr);
-
- assert(!(bo_fake->flags & BM_PINNED));
-
- DBG("set_dirty - buf %d\n", bo_fake->id);
- bo_fake->dirty = 1;
-}
-
-static GLboolean
-evict_lru(dri_bufmgr_fake *bufmgr_fake, GLuint max_fence)
-{
- struct block *block, *tmp;
-
- DBG("%s\n", __FUNCTION__);
-
- foreach_s(block, tmp, &bufmgr_fake->lru) {
- dri_bo_fake *bo_fake = (dri_bo_fake *)block->bo;
-
- if (bo_fake != NULL && (bo_fake->flags & BM_NO_FENCE_SUBDATA))
- continue;
-
- if (block->fence && max_fence && !FENCE_LTE(block->fence, max_fence))
- return 0;
-
- set_dirty(&bo_fake->bo);
- bo_fake->block = NULL;
-
- free_block(bufmgr_fake, block);
- return GL_TRUE;
- }
-
- return GL_FALSE;
-}
-
-#define foreach_s_rev(ptr, t, list) \
- for(ptr=(list)->prev,t=(ptr)->prev; list != ptr; ptr=t, t=(t)->prev)
-
-static GLboolean
-evict_mru(dri_bufmgr_fake *bufmgr_fake)
-{
- struct block *block, *tmp;
-
- DBG("%s\n", __FUNCTION__);
-
- foreach_s_rev(block, tmp, &bufmgr_fake->lru) {
- dri_bo_fake *bo_fake = (dri_bo_fake *)block->bo;
-
- if (bo_fake && (bo_fake->flags & BM_NO_FENCE_SUBDATA))
- continue;
-
- set_dirty(&bo_fake->bo);
- bo_fake->block = NULL;
-
- free_block(bufmgr_fake, block);
- return GL_TRUE;
- }
-
- return GL_FALSE;
-}
-
-/**
- * Removes all objects from the fenced list older than the given fence.
- */
-static int clear_fenced(dri_bufmgr_fake *bufmgr_fake,
- unsigned int fence_cookie)
-{
- struct block *block, *tmp;
- int ret = 0;
-
- foreach_s(block, tmp, &bufmgr_fake->fenced) {
- assert(block->fenced);
-
- if (_fence_test(bufmgr_fake, block->fence)) {
-
- block->fenced = 0;
-
- if (!block->bo) {
- DBG("delayed free: offset %x sz %x\n",
- block->mem->ofs, block->mem->size);
- remove_from_list(block);
- mmFreeMem(block->mem);
- free(block);
- }
- else {
- DBG("return to lru: offset %x sz %x\n",
- block->mem->ofs, block->mem->size);
- move_to_tail(&bufmgr_fake->lru, block);
- }
-
- ret = 1;
- }
- else {
- /* Blocks are ordered by fence, so if one fails, all from
- * here will fail also:
- */
- DBG("fence not passed: offset %x sz %x %d %d \n",
- block->mem->ofs, block->mem->size, block->fence, bufmgr_fake->last_fence);
- break;
- }
- }
-
- DBG("%s: %d\n", __FUNCTION__, ret);
- return ret;
-}
-
-static void fence_blocks(dri_bufmgr_fake *bufmgr_fake, unsigned fence)
-{
- struct block *block, *tmp;
-
- foreach_s (block, tmp, &bufmgr_fake->on_hardware) {
- DBG("Fence block %p (sz 0x%x ofs %x buf %p) with fence %d\n", block,
- block->mem->size, block->mem->ofs, block->bo, fence);
- block->fence = fence;
-
- block->on_hardware = 0;
- block->fenced = 1;
-
- /* Move to tail of pending list here
- */
- move_to_tail(&bufmgr_fake->fenced, block);
- }
-
- assert(is_empty_list(&bufmgr_fake->on_hardware));
-}
-
-static GLboolean evict_and_alloc_block(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- assert(bo_fake->block == NULL);
-
- /* Search for already free memory:
- */
- if (alloc_block(bo))
- return GL_TRUE;
-
- /* If we're not thrashing, allow lru eviction to dig deeper into
- * recently used textures. We'll probably be thrashing soon:
- */
- if (!bufmgr_fake->thrashing) {
- while (evict_lru(bufmgr_fake, 0))
- if (alloc_block(bo))
- return GL_TRUE;
- }
-
- /* Keep thrashing counter alive?
- */
- if (bufmgr_fake->thrashing)
- bufmgr_fake->thrashing = 20;
-
- /* Wait on any already pending fences - here we are waiting for any
- * freed memory that has been submitted to hardware and fenced to
- * become available:
- */
- while (!is_empty_list(&bufmgr_fake->fenced)) {
- GLuint fence = bufmgr_fake->fenced.next->fence;
- _fence_wait_internal(bufmgr_fake, fence);
-
- if (alloc_block(bo))
- return GL_TRUE;
- }
-
- if (!is_empty_list(&bufmgr_fake->on_hardware)) {
- while (!is_empty_list(&bufmgr_fake->fenced)) {
- GLuint fence = bufmgr_fake->fenced.next->fence;
- _fence_wait_internal(bufmgr_fake, fence);
- }
-
- if (!bufmgr_fake->thrashing) {
- DBG("thrashing\n");
- }
- bufmgr_fake->thrashing = 20;
-
- if (alloc_block(bo))
- return GL_TRUE;
- }
-
- while (evict_mru(bufmgr_fake))
- if (alloc_block(bo))
- return GL_TRUE;
-
- DBG("%s 0x%x bytes failed\n", __FUNCTION__, bo->size);
-
- return GL_FALSE;
-}
-
-/***********************************************************************
- * Public functions
- */
-
-/**
- * Wait for hardware idle by emitting a fence and waiting for it.
- */
-static void
-dri_bufmgr_fake_wait_idle(dri_bufmgr_fake *bufmgr_fake)
-{
- unsigned int cookie;
-
- cookie = bufmgr_fake->fence_emit(bufmgr_fake->driver_priv);
- _fence_wait_internal(bufmgr_fake, cookie);
-}
-
-/**
- * Wait for rendering to a buffer to complete.
- *
- * It is assumed that the bathcbuffer which performed the rendering included
- * the necessary flushing.
- */
-static void
-dri_fake_bo_wait_rendering(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- if (bo_fake->block == NULL || !bo_fake->block->fenced)
- return;
-
- _fence_wait_internal(bufmgr_fake, bo_fake->block->fence);
-}
-
-/* Specifically ignore texture memory sharing.
- * -- just evict everything
- * -- and wait for idle
- */
-void
-dri_bufmgr_fake_contended_lock_take(dri_bufmgr *bufmgr)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
- struct block *block, *tmp;
-
- bufmgr_fake->need_fence = 1;
- bufmgr_fake->fail = 0;
-
- /* Wait for hardware idle. We don't know where acceleration has been
- * happening, so we'll need to wait anyway before letting anything get
- * put on the card again.
- */
- dri_bufmgr_fake_wait_idle(bufmgr_fake);
-
- /* Check that we hadn't released the lock without having fenced the last
- * set of buffers.
- */
- assert(is_empty_list(&bufmgr_fake->fenced));
- assert(is_empty_list(&bufmgr_fake->on_hardware));
-
- foreach_s(block, tmp, &bufmgr_fake->lru) {
- assert(_fence_test(bufmgr_fake, block->fence));
- set_dirty(block->bo);
- }
-}
-
-static dri_bo *
-dri_fake_bo_alloc(dri_bufmgr *bufmgr, const char *name,
- unsigned long size, unsigned int alignment,
- uint64_t location_mask)
-{
- dri_bufmgr_fake *bufmgr_fake;
- dri_bo_fake *bo_fake;
-
- bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
-
- assert(size != 0);
-
- bo_fake = calloc(1, sizeof(*bo_fake));
- if (!bo_fake)
- return NULL;
-
- bo_fake->bo.size = size;
- bo_fake->bo.offset = -1;
- bo_fake->bo.virtual = NULL;
- bo_fake->bo.bufmgr = bufmgr;
- bo_fake->refcount = 1;
-
- /* Alignment must be a power of two */
- assert((alignment & (alignment - 1)) == 0);
- if (alignment == 0)
- alignment = 1;
- bo_fake->alignment = alignment;
- bo_fake->id = ++bufmgr_fake->buf_nr;
- bo_fake->name = name;
- bo_fake->flags = 0;
- bo_fake->is_static = GL_FALSE;
-
- DBG("drm_bo_alloc: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
- bo_fake->bo.size / 1024);
-
- return &bo_fake->bo;
-}
-
-static dri_bo *
-dri_fake_bo_alloc_static(dri_bufmgr *bufmgr, const char *name,
- unsigned long offset, unsigned long size,
- void *virtual, uint64_t location_mask)
-{
- dri_bufmgr_fake *bufmgr_fake;
- dri_bo_fake *bo_fake;
-
- bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
-
- assert(size != 0);
-
- bo_fake = calloc(1, sizeof(*bo_fake));
- if (!bo_fake)
- return NULL;
-
- bo_fake->bo.size = size;
- bo_fake->bo.offset = offset;
- bo_fake->bo.virtual = virtual;
- bo_fake->bo.bufmgr = bufmgr;
- bo_fake->refcount = 1;
- bo_fake->id = ++bufmgr_fake->buf_nr;
- bo_fake->name = name;
- bo_fake->flags = BM_PINNED | DRM_BO_FLAG_NO_MOVE;
- bo_fake->is_static = GL_TRUE;
-
- DBG("drm_bo_alloc_static: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
- bo_fake->bo.size / 1024);
-
- return &bo_fake->bo;
-}
-
-static void
-dri_fake_bo_reference(dri_bo *bo)
-{
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- bo_fake->refcount++;
-}
-
-static void
-dri_fake_bo_unreference(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- int i;
-
- if (!bo)
- return;
-
- if (--bo_fake->refcount == 0) {
- assert(bo_fake->map_count == 0);
- /* No remaining references, so free it */
- if (bo_fake->block)
- free_block(bufmgr_fake, bo_fake->block);
- free_backing_store(bo);
-
- for (i = 0; i < bo_fake->nr_relocs; i++)
- dri_bo_unreference(bo_fake->relocs[i].target_buf);
-
- DBG("drm_bo_unreference: free buf %d %s\n", bo_fake->id, bo_fake->name);
-
- free(bo_fake->relocs);
- free(bo);
-
- return;
- }
-}
-
-/**
- * Set the buffer as not requiring backing store, and instead get the callback
- * invoked whenever it would be set dirty.
- */
-void dri_bo_fake_disable_backing_store(dri_bo *bo,
- void (*invalidate_cb)(dri_bo *bo,
- void *ptr),
- void *ptr)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- if (bo_fake->backing_store)
- free_backing_store(bo);
-
- bo_fake->flags |= BM_NO_BACKING_STORE;
-
- DBG("disable_backing_store set buf %d dirty\n", bo_fake->id);
- bo_fake->dirty = 1;
- bo_fake->invalidate_cb = invalidate_cb;
- bo_fake->invalidate_ptr = ptr;
-
- /* Note that it is invalid right from the start. Also note
- * invalidate_cb is called with the bufmgr locked, so cannot
- * itself make bufmgr calls.
- */
- if (invalidate_cb != NULL)
- invalidate_cb(bo, ptr);
-}
-
-/**
- * Map a buffer into bo->virtual, allocating either card memory space (If
- * BM_NO_BACKING_STORE or BM_PINNED) or backing store, as necessary.
- */
-static int
-dri_fake_bo_map(dri_bo *bo, GLboolean write_enable)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- /* Static buffers are always mapped. */
- if (bo_fake->is_static)
- return 0;
-
- /* Allow recursive mapping. Mesa may recursively map buffers with
- * nested display loops, and it is used internally in bufmgr_fake
- * for relocation.
- */
- if (bo_fake->map_count++ != 0)
- return 0;
-
- {
- DBG("drm_bo_map: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
- bo_fake->bo.size / 1024);
-
- if (bo->virtual != NULL) {
- _mesa_printf("%s: already mapped\n", __FUNCTION__);
- abort();
- }
- else if (bo_fake->flags & (BM_NO_BACKING_STORE|BM_PINNED)) {
-
- if (!bo_fake->block && !evict_and_alloc_block(bo)) {
- DBG("%s: alloc failed\n", __FUNCTION__);
- bufmgr_fake->fail = 1;
- return 1;
- }
- else {
- assert(bo_fake->block);
- bo_fake->dirty = 0;
-
- if (!(bo_fake->flags & BM_NO_FENCE_SUBDATA) &&
- bo_fake->block->fenced) {
- dri_fake_bo_wait_rendering(bo);
- }
-
- bo->virtual = bo_fake->block->virtual;
- }
- }
- else {
- if (write_enable)
- set_dirty(bo);
-
- if (bo_fake->backing_store == 0)
- alloc_backing_store(bo);
-
- bo->virtual = bo_fake->backing_store;
- }
- }
-
- return 0;
-}
-
-static int
-dri_fake_bo_unmap(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- /* Static buffers are always mapped. */
- if (bo_fake->is_static)
- return 0;
-
- assert(bo_fake->map_count != 0);
- if (--bo_fake->map_count != 0)
- return 0;
-
- DBG("drm_bo_unmap: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
- bo_fake->bo.size / 1024);
-
- bo->virtual = NULL;
-
- return 0;
-}
-
-static void
-dri_fake_kick_all(dri_bufmgr_fake *bufmgr_fake)
-{
- struct block *block, *tmp;
-
- bufmgr_fake->performed_rendering = GL_FALSE;
- /* okay for ever BO that is on the HW kick it off.
- seriously not afraid of the POLICE right now */
- foreach_s(block, tmp, &bufmgr_fake->on_hardware) {
- dri_bo_fake *bo_fake = (dri_bo_fake *)block->bo;
-
- block->on_hardware = 0;
- free_block(bufmgr_fake, block);
- bo_fake->block = NULL;
- bo_fake->validated = GL_FALSE;
- if (!(bo_fake->flags & BM_NO_BACKING_STORE))
- bo_fake->dirty = 1;
- }
-}
-
-static int
-dri_fake_bo_validate(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
-
- /* XXX: Sanity-check whether we've already validated this one under
- * different flags. See drmAddValidateItem().
- */
- bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
-
- DBG("drm_bo_validate: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name,
- bo_fake->bo.size / 1024);
-
- /* Sanity check: Buffers should be unmapped before being validated.
- * This is not so much of a problem for bufmgr_fake, but TTM refuses,
- * and the problem is harder to debug there.
- */
- assert(bo_fake->map_count == 0);
-
- if (bo_fake->is_static) {
- /* Add it to the needs-fence list */
- bufmgr_fake->need_fence = 1;
- return 0;
- }
-
- /* reset size accounted */
- bo_fake->size_accounted = 0;
-
- /* Allocate the card memory */
- if (!bo_fake->block && !evict_and_alloc_block(bo)) {
- bufmgr_fake->fail = 1;
- DBG("Failed to validate buf %d:%s\n", bo_fake->id, bo_fake->name);
- return -1;
- }
-
- assert(bo_fake->block);
- assert(bo_fake->block->bo == &bo_fake->bo);
-
- bo->offset = bo_fake->block->mem->ofs;
-
- /* Upload the buffer contents if necessary */
- if (bo_fake->dirty) {
- DBG("Upload dirty buf %d:%s, sz %d offset 0x%x\n", bo_fake->id,
- bo_fake->name, bo->size, bo_fake->block->mem->ofs);
-
- assert(!(bo_fake->flags &
- (BM_NO_BACKING_STORE|BM_PINNED)));
-
- /* Actually, should be able to just wait for a fence on the memory,
- * which we would be tracking when we free it. Waiting for idle is
- * a sufficiently large hammer for now.
- */
- dri_bufmgr_fake_wait_idle(bufmgr_fake);
-
- /* we may never have mapped this BO so it might not have any backing
- * store if this happens it should be rare, but 0 the card memory
- * in any case */
- if (bo_fake->backing_store)
- memcpy(bo_fake->block->virtual, bo_fake->backing_store, bo->size);
- else
- memset(bo_fake->block->virtual, 0, bo->size);
-
- bo_fake->dirty = 0;
- }
-
- bo_fake->block->fenced = 0;
- bo_fake->block->on_hardware = 1;
- move_to_tail(&bufmgr_fake->on_hardware, bo_fake->block);
-
- bo_fake->validated = GL_TRUE;
- bufmgr_fake->need_fence = 1;
-
- return 0;
-}
-
-static void
-dri_fake_fence_validated(dri_bufmgr *bufmgr)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
- unsigned int cookie;
-
- cookie = _fence_emit_internal(bufmgr_fake);
- fence_blocks(bufmgr_fake, cookie);
-
- DBG("drm_fence_validated: 0x%08x cookie\n", cookie);
-}
-
-static void
-dri_fake_destroy(dri_bufmgr *bufmgr)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bufmgr;
-
- mmDestroy(bufmgr_fake->heap);
- free(bufmgr);
-}
-
-static int
-dri_fake_emit_reloc(dri_bo *reloc_buf,
- uint32_t read_domains, uint32_t write_domain,
- uint32_t delta, uint32_t offset, dri_bo *target_buf)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)reloc_buf->bufmgr;
- struct fake_buffer_reloc *r;
- dri_bo_fake *reloc_fake = (dri_bo_fake *)reloc_buf;
- dri_bo_fake *target_fake = (dri_bo_fake *)target_buf;
- int i;
-
- assert(reloc_buf);
- assert(target_buf);
-
- assert(target_fake->is_static || target_fake->size_accounted);
-
- if (reloc_fake->relocs == NULL) {
- reloc_fake->relocs = malloc(sizeof(struct fake_buffer_reloc) *
- MAX_RELOCS);
- }
-
- r = &reloc_fake->relocs[reloc_fake->nr_relocs++];
-
- assert(reloc_fake->nr_relocs <= MAX_RELOCS);
-
- dri_bo_reference(target_buf);
-
- r->target_buf = target_buf;
- r->offset = offset;
- r->last_target_offset = target_buf->offset;
- r->delta = delta;
- r->read_domains = read_domains;
- r->write_domain = write_domain;
-
- if (bufmgr_fake->debug) {
- /* Check that a conflicting relocation hasn't already been emitted. */
- for (i = 0; i < reloc_fake->nr_relocs - 1; i++) {
- struct fake_buffer_reloc *r2 = &reloc_fake->relocs[i];
-
- assert(r->offset != r2->offset);
- }
- }
-
- return 0;
-}
-
-/**
- * Incorporates the validation flags associated with each relocation into
- * the combined validation flags for the buffer on this batchbuffer submission.
- */
-static void
-dri_fake_calculate_domains(dri_bo *bo)
-{
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- int i;
-
- for (i = 0; i < bo_fake->nr_relocs; i++) {
- struct fake_buffer_reloc *r = &bo_fake->relocs[i];
- dri_bo_fake *target_fake = (dri_bo_fake *)r->target_buf;
-
- /* Do the same for the tree of buffers we depend on */
- dri_fake_calculate_domains(r->target_buf);
-
- target_fake->read_domains |= r->read_domains;
- if (target_fake->write_domain != 0)
- target_fake->write_domain = r->write_domain;
- }
-}
-
-
-static int
-dri_fake_reloc_and_validate_buffer(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- int i, ret;
-
- assert(bo_fake->map_count == 0);
-
- for (i = 0; i < bo_fake->nr_relocs; i++) {
- struct fake_buffer_reloc *r = &bo_fake->relocs[i];
- dri_bo_fake *target_fake = (dri_bo_fake *)r->target_buf;
- uint32_t reloc_data;
-
- /* Validate the target buffer if that hasn't been done. */
- if (!target_fake->validated) {
- ret = dri_fake_reloc_and_validate_buffer(r->target_buf);
- if (ret != 0) {
- if (bo->virtual != NULL)
- dri_bo_unmap(bo);
- return ret;
- }
- }
-
- /* Calculate the value of the relocation entry. */
- if (r->target_buf->offset != r->last_target_offset) {
- reloc_data = r->target_buf->offset + r->delta;
-
- if (bo->virtual == NULL)
- dri_bo_map(bo, GL_TRUE);
-
- *(uint32_t *)(bo->virtual + r->offset) = reloc_data;
-
- r->last_target_offset = r->target_buf->offset;
- }
- }
-
- if (bo->virtual != NULL)
- dri_bo_unmap(bo);
-
- if (bo_fake->write_domain != 0) {
- if (!(bo_fake->flags & (BM_NO_BACKING_STORE|BM_PINNED))) {
- if (bo_fake->backing_store == 0)
- alloc_backing_store(bo);
-
- bo_fake->card_dirty = 1;
- }
- bufmgr_fake->performed_rendering = GL_TRUE;
- }
-
- return dri_fake_bo_validate(bo);
-}
-
-static void *
-dri_fake_process_relocs(dri_bo *batch_buf)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)batch_buf->bufmgr;
- dri_bo_fake *batch_fake = (dri_bo_fake *)batch_buf;
- int ret;
- int retry_count = 0;
-
- bufmgr_fake->performed_rendering = GL_FALSE;
-
- dri_fake_calculate_domains(batch_buf);
-
- batch_fake->read_domains = DRM_GEM_DOMAIN_I915_COMMAND;
-
- /* we've ran out of RAM so blow the whole lot away and retry */
- restart:
- ret = dri_fake_reloc_and_validate_buffer(batch_buf);
- if (bufmgr_fake->fail == 1) {
- if (retry_count == 0) {
- retry_count++;
- dri_fake_kick_all(bufmgr_fake);
- bufmgr_fake->fail = 0;
- goto restart;
- } else /* dump out the memory here */
- mmDumpMemInfo(bufmgr_fake->heap);
- }
-
- assert(ret == 0);
-
- bufmgr_fake->current_total_size = 0;
- return NULL;
-}
-
-static void
-dri_bo_fake_post_submit(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- int i;
-
- for (i = 0; i < bo_fake->nr_relocs; i++) {
- struct fake_buffer_reloc *r = &bo_fake->relocs[i];
- dri_bo_fake *target_fake = (dri_bo_fake *)r->target_buf;
-
- if (target_fake->validated)
- dri_bo_fake_post_submit(r->target_buf);
-
- DBG("%s@0x%08x + 0x%08x -> %s@0x%08x + 0x%08x\n",
- bo_fake->name, (uint32_t)bo->offset, r->offset,
- target_fake->name, (uint32_t)r->target_buf->offset, r->delta);
- }
-
- assert(bo_fake->map_count == 0);
- bo_fake->validated = GL_FALSE;
- bo_fake->read_domains = 0;
- bo_fake->write_domain = 0;
-}
-
-
-static void
-dri_fake_post_submit(dri_bo *batch_buf)
-{
- dri_fake_fence_validated(batch_buf->bufmgr);
-
- dri_bo_fake_post_submit(batch_buf);
-}
-
-static int
-dri_fake_check_aperture_space(dri_bo *bo)
-{
- dri_bufmgr_fake *bufmgr_fake = (dri_bufmgr_fake *)bo->bufmgr;
- dri_bo_fake *bo_fake = (dri_bo_fake *)bo;
- GLuint sz;
-
- sz = (bo->size + bo_fake->alignment - 1) & ~(bo_fake->alignment - 1);
-
- if (bo_fake->size_accounted || bo_fake->is_static)
- return 0;
-
- if (bufmgr_fake->current_total_size + sz > bufmgr_fake->size) {
- DBG("check_space: %s bo %d %d overflowed bufmgr size %d\n", bo_fake->name, bo_fake->id, sz, bufmgr_fake->size);
- return -1;
- }
-
- bufmgr_fake->current_total_size += sz;
- bo_fake->size_accounted = 1;
- DBG("drm_check_space: buf %d, %s %d %d\n", bo_fake->id, bo_fake->name, bo->size, bufmgr_fake->current_total_size);
- return 0;
-}
-
-dri_bufmgr *
-dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual,
- unsigned long size,
- unsigned int (*fence_emit)(void *private),
- int (*fence_wait)(void *private, unsigned int cookie),
- void *driver_priv)
-{
- dri_bufmgr_fake *bufmgr_fake;
-
- bufmgr_fake = calloc(1, sizeof(*bufmgr_fake));
-
- /* Initialize allocator */
- make_empty_list(&bufmgr_fake->fenced);
- make_empty_list(&bufmgr_fake->on_hardware);
- make_empty_list(&bufmgr_fake->lru);
-
- bufmgr_fake->low_offset = low_offset;
- bufmgr_fake->virtual = low_virtual;
- bufmgr_fake->size = size;
- bufmgr_fake->heap = mmInit(low_offset, size);
-
- /* Hook in methods */
- bufmgr_fake->bufmgr.bo_alloc = dri_fake_bo_alloc;
- bufmgr_fake->bufmgr.bo_alloc_static = dri_fake_bo_alloc_static;
- bufmgr_fake->bufmgr.bo_reference = dri_fake_bo_reference;
- bufmgr_fake->bufmgr.bo_unreference = dri_fake_bo_unreference;
- bufmgr_fake->bufmgr.bo_map = dri_fake_bo_map;
- bufmgr_fake->bufmgr.bo_unmap = dri_fake_bo_unmap;
- bufmgr_fake->bufmgr.bo_wait_rendering = dri_fake_bo_wait_rendering;
- bufmgr_fake->bufmgr.destroy = dri_fake_destroy;
- bufmgr_fake->bufmgr.emit_reloc = dri_fake_emit_reloc;
- bufmgr_fake->bufmgr.process_relocs = dri_fake_process_relocs;
- bufmgr_fake->bufmgr.post_submit = dri_fake_post_submit;
- bufmgr_fake->bufmgr.check_aperture_space = dri_fake_check_aperture_space;
- bufmgr_fake->bufmgr.debug = GL_FALSE;
-
- bufmgr_fake->fence_emit = fence_emit;
- bufmgr_fake->fence_wait = fence_wait;
- bufmgr_fake->driver_priv = driver_priv;
-
- return &bufmgr_fake->bufmgr;
-}
-
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_fake.h b/src/mesa/drivers/dri/intel/intel_bufmgr_fake.h
deleted file mode 100644
index bc7e59e61d..0000000000
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_fake.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2007 Intel Corporation
- * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellström
- * Keith Whitwell
- * Eric Anholt
- */
-
-#ifndef _INTEL_BUFMGR_FAKE_H_
-#define _INTEL_BUFMGR_FAKE_H_
-
-void dri_bufmgr_fake_contended_lock_take(dri_bufmgr *bufmgr);
-dri_bufmgr *dri_bufmgr_fake_init(unsigned long low_offset, void *low_virtual,
- unsigned long size,
- unsigned int (*fence_emit)(void *private),
- int (*fence_wait)(void *private,
- unsigned int cookie),
- void *driver_priv);
-void dri_bo_fake_disable_backing_store(dri_bo *bo,
- void (*invalidate_cb)(dri_bo *bo,
- void *ptr),
- void *ptr);
-#endif /* _INTEL_BUFMGR_FAKE_H_ */
-
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
deleted file mode 100644
index 3c1c3157e1..0000000000
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.c
+++ /dev/null
@@ -1,847 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2007 Red Hat Inc.
- * Copyright © 2007 Intel Corporation
- * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellström
- * Keith Whitwell
- * Eric Anholt
- * Dave Airlie
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include "errno.h"
-#include "mtypes.h"
-#include "dri_bufmgr.h"
-#include "string.h"
-#include "imports.h"
-
-#include "i915_drm.h"
-
-#include "intel_bufmgr_gem.h"
-
-#define DBG(...) do { \
- if (bufmgr_gem->bufmgr.debug) \
- fprintf(stderr, __VA_ARGS__); \
-} while (0)
-
-struct intel_validate_entry {
- dri_bo *bo;
- struct drm_i915_op_arg bo_arg;
-};
-
-struct dri_gem_bo_bucket_entry {
- uint32_t gem_handle;
- uint32_t last_offset;
- struct dri_gem_bo_bucket_entry *next;
-};
-
-struct dri_gem_bo_bucket {
- struct dri_gem_bo_bucket_entry *head;
- struct dri_gem_bo_bucket_entry **tail;
- /**
- * Limit on the number of entries in this bucket.
- *
- * 0 means that this caching at this bucket size is disabled.
- * -1 means that there is no limit to caching at this size.
- */
- int max_entries;
- int num_entries;
-};
-
-/* Arbitrarily chosen, 16 means that the maximum size we'll cache for reuse
- * is 1 << 16 pages, or 256MB.
- */
-#define INTEL_GEM_BO_BUCKETS 16
-typedef struct _dri_bufmgr_gem {
- dri_bufmgr bufmgr;
-
- int fd;
-
- uint32_t max_relocs;
-
- struct drm_i915_gem_exec_object *exec_objects;
- dri_bo **exec_bos;
- int exec_size;
- int exec_count;
-
- /** Array of lists of cached gem objects of power-of-two sizes */
- struct dri_gem_bo_bucket cache_bucket[INTEL_GEM_BO_BUCKETS];
-
- struct drm_i915_gem_execbuffer exec_arg;
-} dri_bufmgr_gem;
-
-typedef struct _dri_bo_gem {
- dri_bo bo;
-
- int refcount;
- GLboolean mapped;
- uint32_t gem_handle;
- const char *name;
-
- /**
- * Index of the buffer within the validation list while preparing a
- * batchbuffer execution.
- */
- int validate_index;
-
- /**
- * Tracks whether set_domain to CPU is current
- * Set when set_domain has been called
- * Cleared when a batch has been submitted
- */
- GLboolean cpu_domain_set;
-
- /** Array passed to the DRM containing relocation information. */
- struct drm_i915_gem_relocation_entry *relocs;
- /** Array of bos corresponding to relocs[i].target_handle */
- dri_bo **reloc_target_bo;
- /** Number of entries in relocs */
- int reloc_count;
- /** Mapped address for the buffer */
- void *virtual;
-} dri_bo_gem;
-
-static int
-logbase2(int n)
-{
- GLint i = 1;
- GLint log2 = 0;
-
- while (n > i) {
- i *= 2;
- log2++;
- }
-
- return log2;
-}
-
-static struct dri_gem_bo_bucket *
-dri_gem_bo_bucket_for_size(dri_bufmgr_gem *bufmgr_gem, unsigned long size)
-{
- int i;
-
- /* We only do buckets in power of two increments */
- if ((size & (size - 1)) != 0)
- return NULL;
-
- /* We should only see sizes rounded to pages. */
- assert((size % 4096) == 0);
-
- /* We always allocate in units of pages */
- i = ffs(size / 4096) - 1;
- if (i >= INTEL_GEM_BO_BUCKETS)
- return NULL;
-
- return &bufmgr_gem->cache_bucket[i];
-}
-
-
-static void dri_gem_dump_validation_list(dri_bufmgr_gem *bufmgr_gem)
-{
- int i, j;
-
- for (i = 0; i < bufmgr_gem->exec_count; i++) {
- dri_bo *bo = bufmgr_gem->exec_bos[i];
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
-
- if (bo_gem->relocs == NULL) {
- DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle, bo_gem->name);
- continue;
- }
-
- for (j = 0; j < bo_gem->reloc_count; j++) {
- dri_bo *target_bo = bo_gem->reloc_target_bo[j];
- dri_bo_gem *target_gem = (dri_bo_gem *)target_bo;
-
- DBG("%2d: %d (%s)@0x%08llx -> %d (%s)@0x%08lx + 0x%08x\n",
- i,
- bo_gem->gem_handle, bo_gem->name, bo_gem->relocs[j].offset,
- target_gem->gem_handle, target_gem->name, target_bo->offset,
- bo_gem->relocs[j].delta);
- }
- }
-}
-
-/**
- * Adds the given buffer to the list of buffers to be validated (moved into the
- * appropriate memory type) with the next batch submission.
- *
- * If a buffer is validated multiple times in a batch submission, it ends up
- * with the intersection of the memory type flags and the union of the
- * access flags.
- */
-static void
-intel_add_validate_buffer(dri_bo *bo)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
- int index;
-
- if (bo_gem->validate_index != -1)
- return;
-
- /* Extend the array of validation entries as necessary. */
- if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
- int new_size = bufmgr_gem->exec_size * 2;
-
- if (new_size == 0)
- new_size = 5;
-
- bufmgr_gem->exec_objects =
- realloc(bufmgr_gem->exec_objects,
- sizeof(*bufmgr_gem->exec_objects) * new_size);
- bufmgr_gem->exec_bos =
- realloc(bufmgr_gem->exec_bos,
- sizeof(*bufmgr_gem->exec_bos) * new_size);
- bufmgr_gem->exec_size = new_size;
- }
-
- index = bufmgr_gem->exec_count;
- bo_gem->validate_index = index;
- /* Fill in array entry */
- bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
- bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
- bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
- bufmgr_gem->exec_objects[index].alignment = 0;
- bufmgr_gem->exec_objects[index].offset = 0;
- bufmgr_gem->exec_bos[index] = bo;
- dri_bo_reference(bo);
- bufmgr_gem->exec_count++;
-}
-
-
-#define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
- sizeof(uint32_t))
-
-static int
-intel_setup_reloc_list(dri_bo *bo)
-{
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
-
- bo_gem->relocs = malloc(bufmgr_gem->max_relocs *
- sizeof(struct drm_i915_gem_relocation_entry));
- bo_gem->reloc_target_bo = malloc(bufmgr_gem->max_relocs * sizeof(dri_bo *));
-
- return 0;
-}
-
-static dri_bo *
-dri_gem_bo_alloc(dri_bufmgr *bufmgr, const char *name,
- unsigned long size, unsigned int alignment,
- uint64_t location_mask)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr;
- dri_bo_gem *bo_gem;
- unsigned int page_size = getpagesize();
- int ret;
- struct dri_gem_bo_bucket *bucket;
- GLboolean alloc_from_cache = GL_FALSE;
-
- bo_gem = calloc(1, sizeof(*bo_gem));
- if (!bo_gem)
- return NULL;
-
- /* Round the allocated size up to a power of two number of pages. */
- bo_gem->bo.size = 1 << logbase2(size);
- if (bo_gem->bo.size < page_size)
- bo_gem->bo.size = page_size;
- bucket = dri_gem_bo_bucket_for_size(bufmgr_gem, bo_gem->bo.size);
-
- /* If we don't have caching at this size, don't actually round the
- * allocation up.
- */
- if (bucket == NULL || bucket->max_entries == 0) {
- bo_gem->bo.size = size;
- if (bo_gem->bo.size < page_size)
- bo_gem->bo.size = page_size;
- }
-
- /* Get a buffer out of the cache if available */
- if (bucket != NULL && bucket->num_entries > 0) {
- struct dri_gem_bo_bucket_entry *entry = bucket->head;
- struct drm_i915_gem_busy busy;
-
- busy.handle = entry->gem_handle;
- ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
- alloc_from_cache = (ret == 0 && busy.busy == 0);
-
- if (alloc_from_cache) {
- bucket->head = entry->next;
- if (entry->next == NULL)
- bucket->tail = &bucket->head;
- bucket->num_entries--;
-
- bo_gem->gem_handle = entry->gem_handle;
- bo_gem->bo.offset = entry->last_offset;
- free(entry);
- }
- }
-
- if (!alloc_from_cache) {
- struct drm_gem_create create;
-
- memset(&create, 0, sizeof(create));
- create.size = bo_gem->bo.size;
-
- ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CREATE, &create);
- bo_gem->gem_handle = create.handle;
- if (ret != 0) {
- free(bo_gem);
- return NULL;
- }
- }
-
- bo_gem->bo.virtual = NULL;
- bo_gem->bo.bufmgr = bufmgr;
- bo_gem->name = name;
- bo_gem->refcount = 1;
- bo_gem->validate_index = -1;
-
- DBG("bo_create: buf %d (%s) %ldb\n",
- bo_gem->gem_handle, bo_gem->name, size);
-
- return &bo_gem->bo;
-}
-
-/* Our GEM backend doesn't allow creation of static buffers, as that requires
- * privelege for the non-fake case, and the lock in the fake case where we were
- * working around the X Server not creating buffers and passing handles to us.
- */
-static dri_bo *
-dri_gem_bo_alloc_static(dri_bufmgr *bufmgr, const char *name,
- unsigned long offset, unsigned long size, void *virtual,
- uint64_t location_mask)
-{
- return NULL;
-}
-
-/**
- * Returns a dri_bo wrapping the given buffer object handle.
- *
- * This can be used when one application needs to pass a buffer object
- * to another.
- */
-dri_bo *
-intel_gem_bo_create_from_handle(dri_bufmgr *bufmgr, const char *name,
- unsigned int handle)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr;
- dri_bo_gem *bo_gem;
- int ret;
- struct drm_gem_open open_arg;
-
- bo_gem = calloc(1, sizeof(*bo_gem));
- if (!bo_gem)
- return NULL;
-
- memset(&open_arg, 0, sizeof(open_arg));
- open_arg.name = handle;
- ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
- if (ret != 0) {
- fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
- name, handle, strerror(-ret));
- free(bo_gem);
- return NULL;
- }
- bo_gem->bo.size = open_arg.size;
- bo_gem->bo.offset = 0;
- bo_gem->bo.virtual = NULL;
- bo_gem->bo.bufmgr = bufmgr;
- bo_gem->name = name;
- bo_gem->refcount = 1;
- bo_gem->validate_index = -1;
- bo_gem->gem_handle = open_arg.handle;
-
- DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
-
- return &bo_gem->bo;
-}
-
-static void
-dri_gem_bo_reference(dri_bo *bo)
-{
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
-
- bo_gem->refcount++;
-}
-
-static void
-dri_gem_bo_unreference(dri_bo *bo)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
-
- if (!bo)
- return;
-
- if (--bo_gem->refcount == 0) {
- struct dri_gem_bo_bucket *bucket;
- int ret;
-
- if (bo_gem->mapped)
- munmap (bo_gem->virtual, bo->size);
-
- if (bo_gem->relocs != NULL) {
- int i;
-
- /* Unreference all the target buffers */
- for (i = 0; i < bo_gem->reloc_count; i++)
- dri_bo_unreference(bo_gem->reloc_target_bo[i]);
- free(bo_gem->reloc_target_bo);
- free(bo_gem->relocs);
- }
-
- bucket = dri_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
- /* Put the buffer into our internal cache for reuse if we can. */
- if (bucket != NULL &&
- (bucket->max_entries == -1 ||
- (bucket->max_entries > 0 &&
- bucket->num_entries < bucket->max_entries)))
- {
- struct dri_gem_bo_bucket_entry *entry;
-
- entry = calloc(1, sizeof(*entry));
- entry->gem_handle = bo_gem->gem_handle;
- entry->last_offset = bo->offset;
-
- entry->next = NULL;
- *bucket->tail = entry;
- bucket->tail = &entry->next;
- bucket->num_entries++;
- } else {
- struct drm_gem_close close;
-
- /* Close this object */
- close.handle = bo_gem->gem_handle;
- ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
- if (ret != 0) {
- fprintf(stderr,
- "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
- bo_gem->gem_handle, bo_gem->name, strerror(-ret));
- }
- }
-
- DBG("bo_unreference final: %d (%s)\n",
- bo_gem->gem_handle, bo_gem->name);
-
- free(bo);
- return;
- }
-}
-
-static int
-dri_gem_bo_map(dri_bo *bo, GLboolean write_enable)
-{
- dri_bufmgr_gem *bufmgr_gem;
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
- struct drm_gem_set_domain set_domain;
- int ret;
-
- bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
-
- /* Allow recursive mapping. Mesa may recursively map buffers with
- * nested display loops.
- */
- if (!bo_gem->mapped) {
-
- assert(bo->virtual == NULL);
-
- DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
-
- if (bo_gem->virtual == NULL) {
- struct drm_gem_mmap mmap_arg;
-
- memset(&mmap_arg, 0, sizeof(mmap_arg));
- mmap_arg.handle = bo_gem->gem_handle;
- mmap_arg.offset = 0;
- mmap_arg.size = bo->size;
- ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_MMAP, &mmap_arg);
- if (ret != 0) {
- fprintf(stderr, "%s:%d: Error mapping buffer %d (%s): %s .\n",
- __FILE__, __LINE__,
- bo_gem->gem_handle, bo_gem->name, strerror(errno));
- }
- bo_gem->virtual = (void *)(uintptr_t)mmap_arg.addr_ptr;
- }
- bo->virtual = bo_gem->virtual;
- bo_gem->mapped = GL_TRUE;
- DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, bo_gem->virtual);
- }
-
- if (!bo_gem->cpu_domain_set) {
- set_domain.handle = bo_gem->gem_handle;
- set_domain.read_domains = DRM_GEM_DOMAIN_CPU;
- set_domain.write_domain = write_enable ? DRM_GEM_DOMAIN_CPU : 0;
- ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_GEM_SET_DOMAIN, &set_domain);
- if (ret != 0) {
- fprintf (stderr, "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
- __FILE__, __LINE__,
- bo_gem->gem_handle, set_domain.read_domains, set_domain.write_domain,
- strerror (errno));
- }
- bo_gem->cpu_domain_set = GL_TRUE;
- }
-
- return 0;
-}
-
-static int
-dri_gem_bo_unmap(dri_bo *bo)
-{
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
-
- if (bo == NULL)
- return 0;
-
- assert(bo_gem->mapped);
-
- return 0;
-}
-
-static int
-dri_gem_bo_subdata (dri_bo *bo, unsigned long offset,
- unsigned long size, const void *data)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
- struct drm_gem_pwrite pwrite;
- int ret;
-
- memset (&pwrite, 0, sizeof (pwrite));
- pwrite.handle = bo_gem->gem_handle;
- pwrite.offset = offset;
- pwrite.size = size;
- pwrite.data_ptr = (uint64_t) (uintptr_t) data;
- ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_GEM_PWRITE, &pwrite);
- if (ret != 0) {
- fprintf (stderr, "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
- __FILE__, __LINE__,
- bo_gem->gem_handle, (int) offset, (int) size,
- strerror (errno));
- }
- return 0;
-}
-
-static int
-dri_gem_bo_get_subdata (dri_bo *bo, unsigned long offset,
- unsigned long size, void *data)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
- struct drm_gem_pread pread;
- int ret;
-
- memset (&pread, 0, sizeof (pread));
- pread.handle = bo_gem->gem_handle;
- pread.offset = offset;
- pread.size = size;
- pread.data_ptr = (uint64_t) (uintptr_t) data;
- ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_GEM_PREAD, &pread);
- if (ret != 0) {
- fprintf (stderr, "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
- __FILE__, __LINE__,
- bo_gem->gem_handle, (int) offset, (int) size,
- strerror (errno));
- }
- return 0;
-}
-
-static void
-dri_gem_bo_wait_rendering(dri_bo *bo)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
- struct drm_gem_set_domain set_domain;
- int ret;
-
- set_domain.handle = bo_gem->gem_handle;
- set_domain.read_domains = DRM_GEM_DOMAIN_CPU;
- set_domain.write_domain = 0;
- ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_GEM_SET_DOMAIN, &set_domain);
- if (ret != 0) {
- fprintf (stderr, "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
- __FILE__, __LINE__,
- bo_gem->gem_handle, set_domain.read_domains, set_domain.write_domain,
- strerror (errno));
- }
-}
-
-static void
-dri_bufmgr_gem_destroy(dri_bufmgr *bufmgr)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr;
- int i;
-
- free(bufmgr_gem->exec_objects);
- free(bufmgr_gem->exec_bos);
-
- /* Free any cached buffer objects we were going to reuse */
- for (i = 0; i < INTEL_GEM_BO_BUCKETS; i++) {
- struct dri_gem_bo_bucket *bucket = &bufmgr_gem->cache_bucket[i];
- struct dri_gem_bo_bucket_entry *entry;
-
- while ((entry = bucket->head) != NULL) {
- struct drm_gem_close close;
- int ret;
-
- bucket->head = entry->next;
- if (entry->next == NULL)
- bucket->tail = &bucket->head;
- bucket->num_entries--;
-
- /* Close this object */
- close.handle = entry->gem_handle;
- ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
- if (ret != 0) {
- fprintf(stderr, "DRM_IOCTL_GEM_CLOSE failed: %s\n",
- strerror(-ret));
- }
-
- free(entry);
- }
- }
-
- free(bufmgr);
-}
-
-/**
- * Adds the target buffer to the validation list and adds the relocation
- * to the reloc_buffer's relocation list.
- *
- * The relocation entry at the given offset must already contain the
- * precomputed relocation value, because the kernel will optimize out
- * the relocation entry write when the buffer hasn't moved from the
- * last known offset in target_bo.
- */
-static int
-dri_gem_emit_reloc(dri_bo *bo, uint32_t read_domains, uint32_t write_domain,
- uint32_t delta, uint32_t offset, dri_bo *target_bo)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
- dri_bo_gem *target_bo_gem = (dri_bo_gem *)target_bo;
-
- /* Create a new relocation list if needed */
- if (bo_gem->relocs == NULL)
- intel_setup_reloc_list(bo);
-
- /* Check overflow */
- assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
-
- /* Check args */
- assert (offset <= bo->size - 4);
- assert ((write_domain & (write_domain-1)) == 0);
-
- bo_gem->relocs[bo_gem->reloc_count].offset = offset;
- bo_gem->relocs[bo_gem->reloc_count].delta = delta;
- bo_gem->relocs[bo_gem->reloc_count].target_handle =
- target_bo_gem->gem_handle;
- bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
- bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
- bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
-
- bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
- dri_bo_reference(target_bo);
-
- bo_gem->reloc_count++;
- return 0;
-}
-
-/**
- * Walk the tree of relocations rooted at BO and accumulate the list of
- * validations to be performed and update the relocation buffers with
- * index values into the validation list.
- */
-static void
-dri_gem_bo_process_reloc(dri_bo *bo)
-{
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
- int i;
-
- if (bo_gem->relocs == NULL)
- return;
-
- for (i = 0; i < bo_gem->reloc_count; i++) {
- dri_bo *target_bo = bo_gem->reloc_target_bo[i];
-
- /* Continue walking the tree depth-first. */
- dri_gem_bo_process_reloc(target_bo);
-
- /* Add the target to the validate list */
- intel_add_validate_buffer(target_bo);
- }
-}
-
-static void *
-dri_gem_process_reloc(dri_bo *batch_buf)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *) batch_buf->bufmgr;
-
- /* Update indices and set up the validate list. */
- dri_gem_bo_process_reloc(batch_buf);
-
- /* Add the batch buffer to the validation list. There are no relocations
- * pointing to it.
- */
- intel_add_validate_buffer(batch_buf);
-
- bufmgr_gem->exec_arg.buffers_ptr = (uintptr_t)bufmgr_gem->exec_objects;
- bufmgr_gem->exec_arg.buffer_count = bufmgr_gem->exec_count;
- bufmgr_gem->exec_arg.batch_start_offset = 0;
- bufmgr_gem->exec_arg.batch_len = 0; /* written in intel_exec_ioctl */
-
- return &bufmgr_gem->exec_arg;
-}
-
-static void
-intel_update_buffer_offsets (dri_bufmgr_gem *bufmgr_gem)
-{
- int i;
-
- for (i = 0; i < bufmgr_gem->exec_count; i++) {
- dri_bo *bo = bufmgr_gem->exec_bos[i];
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
-
- /* Update the buffer offset */
- if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
- DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
- bo_gem->gem_handle, bo_gem->name, bo->offset,
- bufmgr_gem->exec_objects[i].offset);
- bo->offset = bufmgr_gem->exec_objects[i].offset;
- }
- }
-}
-
-static void
-dri_gem_post_submit(dri_bo *batch_buf)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)batch_buf->bufmgr;
- int i;
-
- intel_update_buffer_offsets (bufmgr_gem);
-
- if (bufmgr_gem->bufmgr.debug)
- dri_gem_dump_validation_list(bufmgr_gem);
-
- for (i = 0; i < bufmgr_gem->exec_count; i++) {
- dri_bo *bo = bufmgr_gem->exec_bos[i];
- dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
-
- /* Need to call set_domain on next bo_map */
- bo_gem->cpu_domain_set = GL_FALSE;
-
- /* Disconnect the buffer from the validate list */
- bo_gem->validate_index = -1;
- dri_bo_unreference(bo);
- bufmgr_gem->exec_bos[i] = NULL;
- }
- bufmgr_gem->exec_count = 0;
-}
-
-/**
- * Enables unlimited caching of buffer objects for reuse.
- *
- * This is potentially very memory expensive, as the cache at each bucket
- * size is only bounded by how many buffers of that size we've managed to have
- * in flight at once.
- */
-void
-intel_gem_enable_bo_reuse(dri_bufmgr *bufmgr)
-{
- dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr;
- int i;
-
- for (i = 0; i < INTEL_GEM_BO_BUCKETS; i++) {
- bufmgr_gem->cache_bucket[i].max_entries = -1;
- }
-}
-
-/*
- *
- */
-static int
-dri_gem_check_aperture_space(dri_bo *bo)
-{
- return 0;
-}
-
-/**
- * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
- * and manage map buffer objections.
- *
- * \param fd File descriptor of the opened DRM device.
- */
-dri_bufmgr *
-intel_bufmgr_gem_init(int fd, int batch_size)
-{
- dri_bufmgr_gem *bufmgr_gem;
- int i;
-
- bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
- bufmgr_gem->fd = fd;
-
- /* Let's go with one relocation per every 2 dwords (but round down a bit
- * since a power of two will mean an extra page allocation for the reloc
- * buffer).
- *
- * Every 4 was too few for the blender benchmark.
- */
- bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
-
- bufmgr_gem->bufmgr.bo_alloc = dri_gem_bo_alloc;
- bufmgr_gem->bufmgr.bo_alloc_static = dri_gem_bo_alloc_static;
- bufmgr_gem->bufmgr.bo_reference = dri_gem_bo_reference;
- bufmgr_gem->bufmgr.bo_unreference = dri_gem_bo_unreference;
- bufmgr_gem->bufmgr.bo_map = dri_gem_bo_map;
- bufmgr_gem->bufmgr.bo_unmap = dri_gem_bo_unmap;
- bufmgr_gem->bufmgr.bo_subdata = dri_gem_bo_subdata;
- bufmgr_gem->bufmgr.bo_get_subdata = dri_gem_bo_get_subdata;
- bufmgr_gem->bufmgr.bo_wait_rendering = dri_gem_bo_wait_rendering;
- bufmgr_gem->bufmgr.destroy = dri_bufmgr_gem_destroy;
- bufmgr_gem->bufmgr.emit_reloc = dri_gem_emit_reloc;
- bufmgr_gem->bufmgr.process_relocs = dri_gem_process_reloc;
- bufmgr_gem->bufmgr.post_submit = dri_gem_post_submit;
- bufmgr_gem->bufmgr.debug = GL_FALSE;
- bufmgr_gem->bufmgr.check_aperture_space = dri_gem_check_aperture_space;
- /* Initialize the linked lists for BO reuse cache. */
- for (i = 0; i < INTEL_GEM_BO_BUCKETS; i++)
- bufmgr_gem->cache_bucket[i].tail = &bufmgr_gem->cache_bucket[i].head;
-
- return &bufmgr_gem->bufmgr;
-}
-
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.h b/src/mesa/drivers/dri/intel/intel_bufmgr_gem.h
deleted file mode 100644
index 36caeba214..0000000000
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_gem.h
+++ /dev/null
@@ -1,16 +0,0 @@
-
-#ifndef INTEL_BUFMGR_GEM_H
-#define INTEL_BUFMGR_GEM_H
-
-#include "dri_bufmgr.h"
-
-extern dri_bo *intel_gem_bo_create_from_handle(dri_bufmgr *bufmgr,
- const char *name,
- unsigned int handle);
-
-dri_bufmgr *intel_bufmgr_gem_init(int fd, int batch_size);
-
-void
-intel_gem_enable_bo_reuse(dri_bufmgr *bufmgr);
-
-#endif /* INTEL_BUFMGR_GEM_H */
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_ttm.c b/src/mesa/drivers/dri/intel/intel_bufmgr_ttm.c
deleted file mode 100644
index 545913fa31..0000000000
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_ttm.c
+++ /dev/null
@@ -1,1102 +0,0 @@
-/**************************************************************************
- *
- * Copyright © 2007 Red Hat Inc.
- * Copyright © 2007 Intel Corporation
- * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellström
- * Keith Whitwell
- * Eric Anholt
- * Dave Airlie
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include "errno.h"
-#include "mtypes.h"
-#include "dri_bufmgr.h"
-#include "string.h"
-#include "imports.h"
-
-#include "i915_drm.h"
-
-#include "intel_bufmgr_ttm.h"
-
-#define DBG(...) do { \
- if (bufmgr_ttm->bufmgr.debug) \
- fprintf(stderr, __VA_ARGS__); \
-} while (0)
-
-/*
- * These bits are always specified in each validation
- * request. Other bits are not supported at this point
- * as it would require a bit of investigation to figure
- * out what mask value should be used.
- */
-#define INTEL_BO_MASK (DRM_BO_MASK_MEM | \
- DRM_BO_FLAG_READ | \
- DRM_BO_FLAG_WRITE | \
- DRM_BO_FLAG_EXE)
-
-struct intel_validate_entry {
- dri_bo *bo;
- struct drm_i915_op_arg bo_arg;
-};
-
-struct dri_ttm_bo_bucket_entry {
- drmBO drm_bo;
- struct dri_ttm_bo_bucket_entry *next;
-};
-
-struct dri_ttm_bo_bucket {
- struct dri_ttm_bo_bucket_entry *head;
- struct dri_ttm_bo_bucket_entry **tail;
- /**
- * Limit on the number of entries in this bucket.
- *
- * 0 means that this caching at this bucket size is disabled.
- * -1 means that there is no limit to caching at this size.
- */
- int max_entries;
- int num_entries;
-};
-
-/* Arbitrarily chosen, 16 means that the maximum size we'll cache for reuse
- * is 1 << 16 pages, or 256MB.
- */
-#define INTEL_TTM_BO_BUCKETS 16
-typedef struct _dri_bufmgr_ttm {
- dri_bufmgr bufmgr;
-
- int fd;
- unsigned int fence_type;
- unsigned int fence_type_flush;
-
- uint32_t max_relocs;
-
- struct intel_validate_entry *validate_array;
- int validate_array_size;
- int validate_count;
-
- /** Array of lists of cached drmBOs of power-of-two sizes */
- struct dri_ttm_bo_bucket cache_bucket[INTEL_TTM_BO_BUCKETS];
-} dri_bufmgr_ttm;
-
-/**
- * Private information associated with a relocation that isn't already stored
- * in the relocation buffer to be passed to the kernel.
- */
-struct dri_ttm_reloc {
- dri_bo *target_buf;
- uint64_t validate_flags;
- /** Offset of target_buf after last execution of this relocation entry. */
- unsigned int last_target_offset;
-};
-
-typedef struct _dri_bo_ttm {
- dri_bo bo;
-
- int refcount;
- unsigned int map_count;
- drmBO drm_bo;
- const char *name;
-
- uint64_t last_flags;
-
- /**
- * Index of the buffer within the validation list while preparing a
- * batchbuffer execution.
- */
- int validate_index;
-
- /** DRM buffer object containing relocation list */
- uint32_t *reloc_buf_data;
- struct dri_ttm_reloc *relocs;
-
- /**
- * Indicates that the buffer may be shared with other processes, so we
- * can't hold maps beyond when the user does.
- */
- GLboolean shared;
-
- GLboolean delayed_unmap;
- /* Virtual address from the dri_bo_map whose unmap was delayed. */
- void *saved_virtual;
-} dri_bo_ttm;
-
-typedef struct _dri_fence_ttm
-{
- dri_fence fence;
-
- int refcount;
- const char *name;
- drmFence drm_fence;
-} dri_fence_ttm;
-
-static int
-logbase2(int n)
-{
- GLint i = 1;
- GLint log2 = 0;
-
- while (n > i) {
- i *= 2;
- log2++;
- }
-
- return log2;
-}
-
-static struct dri_ttm_bo_bucket *
-dri_ttm_bo_bucket_for_size(dri_bufmgr_ttm *bufmgr_ttm, unsigned long size)
-{
- int i;
-
- /* We only do buckets in power of two increments */
- if ((size & (size - 1)) != 0)
- return NULL;
-
- /* We should only see sizes rounded to pages. */
- assert((size % 4096) == 0);
-
- /* We always allocate in units of pages */
- i = ffs(size / 4096) - 1;
- if (i >= INTEL_TTM_BO_BUCKETS)
- return NULL;
-
- return &bufmgr_ttm->cache_bucket[i];
-}
-
-
-static void dri_ttm_dump_validation_list(dri_bufmgr_ttm *bufmgr_ttm)
-{
- int i, j;
-
- for (i = 0; i < bufmgr_ttm->validate_count; i++) {
- dri_bo *bo = bufmgr_ttm->validate_array[i].bo;
- dri_bo_ttm *bo_ttm = (dri_bo_ttm *)bo;
-
- if (bo_ttm->reloc_buf_data != NULL) {
- for (j = 0; j < (bo_ttm->reloc_buf_data[0] & 0xffff); j++) {
- uint32_t *reloc_entry = bo_ttm->reloc_buf_data +
- I915_RELOC_HEADER +
- j * I915_RELOC0_STRIDE;
- dri_bo *target_bo = bo_ttm->relocs[j].target_buf;
- dri_bo_ttm *target_ttm = (dri_bo_ttm *)target_bo;
-
- DBG("%2d: %s@0x%08x -> %s@0x%08lx + 0x%08x\n",
- i,
- bo_ttm->name, reloc_entry[0],
- target_ttm->name, target_bo->offset,
- reloc_entry[1]);
- }
- } else {
- DBG("%2d: %s\n", i, bo_ttm->name);
- }
- }
-}
-
-/**
- * Adds the given buffer to the list of buffers to be validated (moved into the
- * appropriate memory type) with the next batch submission.
- *
- * If a buffer is validated multiple times in a batch submission, it ends up
- * with the intersection of the memory type flags and the union of the
- * access flags.
- */
-static void
-intel_add_validate_buffer(dri_bo *buf,
- uint64_t flags)
-{
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)buf->bufmgr;
- dri_bo_ttm *ttm_buf = (dri_bo_ttm *)buf;
-
- /* If we delayed doing an unmap to mitigate map/unmap syscall thrashing,
- * do that now.
- */
- if (ttm_buf->delayed_unmap) {
- drmBOUnmap(bufmgr_ttm->fd, &ttm_buf->drm_bo);
- ttm_buf->delayed_unmap = GL_FALSE;
- }
-
- if (ttm_buf->validate_index == -1) {
- struct intel_validate_entry *entry;
- struct drm_i915_op_arg *arg;
- struct drm_bo_op_req *req;
- int index;
-
- /* Extend the array of validation entries as necessary. */
- if (bufmgr_ttm->validate_count == bufmgr_ttm->validate_array_size) {
- int i, new_size = bufmgr_ttm->validate_array_size * 2;
-
- if (new_size == 0)
- new_size = 5;
-
- bufmgr_ttm->validate_array =
- realloc(bufmgr_ttm->validate_array,
- sizeof(struct intel_validate_entry) * new_size);
- bufmgr_ttm->validate_array_size = new_size;
-
- /* Update pointers for realloced mem. */
- for (i = 0; i < bufmgr_ttm->validate_count - 1; i++) {
- bufmgr_ttm->validate_array[i].bo_arg.next = (unsigned long)
- &bufmgr_ttm->validate_array[i + 1].bo_arg;
- }
- }
-
- /* Pick out the new array entry for ourselves */
- index = bufmgr_ttm->validate_count;
- ttm_buf->validate_index = index;
- entry = &bufmgr_ttm->validate_array[index];
- bufmgr_ttm->validate_count++;
-
- /* Fill in array entry */
- entry->bo = buf;
- dri_bo_reference(buf);
-
- /* Fill in kernel arg */
- arg = &entry->bo_arg;
- req = &arg->d.req;
-
- memset(arg, 0, sizeof(*arg));
- req->bo_req.handle = ttm_buf->drm_bo.handle;
- req->op = drm_bo_validate;
- req->bo_req.flags = flags;
- req->bo_req.hint = 0;
-#ifdef DRM_BO_HINT_PRESUMED_OFFSET
- /* PRESUMED_OFFSET indicates that all relocations pointing at this
- * buffer have the correct offset. If any of our relocations don't,
- * this flag will be cleared off the buffer later in the relocation
- * processing.
- */
- req->bo_req.hint |= DRM_BO_HINT_PRESUMED_OFFSET;
- req->bo_req.presumed_offset = buf->offset;
-#endif
- req->bo_req.mask = INTEL_BO_MASK;
- req->bo_req.fence_class = 0; /* Backwards compat. */
-
- if (ttm_buf->reloc_buf_data != NULL)
- arg->reloc_ptr = (unsigned long)(void *)ttm_buf->reloc_buf_data;
- else
- arg->reloc_ptr = 0;
-
- /* Hook up the linked list of args for the kernel */
- arg->next = 0;
- if (index != 0) {
- bufmgr_ttm->validate_array[index - 1].bo_arg.next =
- (unsigned long)arg;
- }
- } else {
- struct intel_validate_entry *entry =
- &bufmgr_ttm->validate_array[ttm_buf->validate_index];
- struct drm_i915_op_arg *arg = &entry->bo_arg;
- struct drm_bo_op_req *req = &arg->d.req;
- uint64_t memFlags = req->bo_req.flags & flags & DRM_BO_MASK_MEM;
- uint64_t modeFlags = (req->bo_req.flags | flags) & ~DRM_BO_MASK_MEM;
-
- /* Buffer was already in the validate list. Extend its flags as
- * necessary.
- */
-
- if (memFlags == 0) {
- fprintf(stderr,
- "%s: No shared memory types between "
- "0x%16llx and 0x%16llx\n",
- __FUNCTION__, req->bo_req.flags, flags);
- abort();
- }
- if (flags & ~INTEL_BO_MASK) {
- fprintf(stderr,
- "%s: Flags bits 0x%16llx are not supposed to be used in a relocation\n",
- __FUNCTION__, flags & ~INTEL_BO_MASK);
- abort();
- }
- req->bo_req.flags = memFlags | modeFlags;
- }
-}
-
-
-#define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
- sizeof(uint32_t))
-
-static int
-intel_setup_reloc_list(dri_bo *bo)
-{
- dri_bo_ttm *bo_ttm = (dri_bo_ttm *)bo;
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)bo->bufmgr;
-
- bo_ttm->relocs = calloc(bufmgr_ttm->max_relocs,
- sizeof(struct dri_ttm_reloc));
- bo_ttm->reloc_buf_data = calloc(1, RELOC_BUF_SIZE(bufmgr_ttm->max_relocs));
-
- /* Initialize the relocation list with the header:
- * DWORD 0: relocation count
- * DWORD 1: relocation type
- * DWORD 2+3: handle to next relocation list (currently none) 64-bits
- */
- bo_ttm->reloc_buf_data[0] = 0;
- bo_ttm->reloc_buf_data[1] = I915_RELOC_TYPE_0;
- bo_ttm->reloc_buf_data[2] = 0;
- bo_ttm->reloc_buf_data[3] = 0;
-
- return 0;
-}
-
-#if 0
-int
-driFenceSignaled(DriFenceObject * fence, unsigned type)
-{
- int signaled;
- int ret;
-
- if (fence == NULL)
- return GL_TRUE;
-
- ret = drmFenceSignaled(bufmgr_ttm->fd, &fence->fence, type, &signaled);
- BM_CKFATAL(ret);
- return signaled;
-}
-#endif
-
-static dri_bo *
-dri_ttm_alloc(dri_bufmgr *bufmgr, const char *name,
- unsigned long size, unsigned int alignment,
- uint64_t location_mask)
-{
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)bufmgr;
- dri_bo_ttm *ttm_buf;
- unsigned int pageSize = getpagesize();
- int ret;
- uint64_t flags;
- unsigned int hint;
- unsigned long alloc_size;
- struct dri_ttm_bo_bucket *bucket;
- GLboolean alloc_from_cache = GL_FALSE;
-
- ttm_buf = calloc(1, sizeof(*ttm_buf));
- if (!ttm_buf)
- return NULL;
-
- /* The mask argument doesn't do anything for us that we want other than
- * determine which pool (TTM or local) the buffer is allocated into, so
- * just pass all of the allocation class flags.
- */
- flags = location_mask | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
- DRM_BO_FLAG_EXE;
- /* No hints we want to use. */
- hint = 0;
-
- /* Round the allocated size up to a power of two number of pages. */
- alloc_size = 1 << logbase2(size);
- if (alloc_size < pageSize)
- alloc_size = pageSize;
- bucket = dri_ttm_bo_bucket_for_size(bufmgr_ttm, alloc_size);
-
- /* If we don't have caching at this size, don't actually round the
- * allocation up.
- */
- if (bucket == NULL || bucket->max_entries == 0)
- alloc_size = size;
-
- /* Get a buffer out of the cache if available */
- if (bucket != NULL && bucket->num_entries > 0) {
- struct dri_ttm_bo_bucket_entry *entry = bucket->head;
- int busy;
-
- /* Check if the buffer is still in flight. If not, reuse it. */
- ret = drmBOBusy(bufmgr_ttm->fd, &entry->drm_bo, &busy);
- alloc_from_cache = (ret == 0 && busy == 0);
-
- if (alloc_from_cache) {
- bucket->head = entry->next;
- if (entry->next == NULL)
- bucket->tail = &bucket->head;
- bucket->num_entries--;
-
- ttm_buf->drm_bo = entry->drm_bo;
- free(entry);
- }
- }
-
- if (!alloc_from_cache) {
- ret = drmBOCreate(bufmgr_ttm->fd, alloc_size, alignment / pageSize,
- NULL, flags, hint, &ttm_buf->drm_bo);
- if (ret != 0) {
- free(ttm_buf);
- return NULL;
- }
- }
-
- ttm_buf->bo.size = size;
- ttm_buf->bo.offset = ttm_buf->drm_bo.offset;
- ttm_buf->bo.virtual = NULL;
- ttm_buf->bo.bufmgr = bufmgr;
- ttm_buf->name = name;
- ttm_buf->refcount = 1;
- ttm_buf->reloc_buf_data = NULL;
- ttm_buf->relocs = NULL;
- ttm_buf->last_flags = ttm_buf->drm_bo.flags;
- ttm_buf->shared = GL_FALSE;
- ttm_buf->delayed_unmap = GL_FALSE;
- ttm_buf->validate_index = -1;
-
- DBG("bo_create: %p (%s) %ldb\n", &ttm_buf->bo, ttm_buf->name, size);
-
- return &ttm_buf->bo;
-}
-
-/* Our TTM backend doesn't allow creation of static buffers, as that requires
- * privelege for the non-fake case, and the lock in the fake case where we were
- * working around the X Server not creating buffers and passing handles to us.
- */
-static dri_bo *
-dri_ttm_alloc_static(dri_bufmgr *bufmgr, const char *name,
- unsigned long offset, unsigned long size, void *virtual,
- uint64_t location_mask)
-{
- return NULL;
-}
-
-/**
- * Returns a dri_bo wrapping the given buffer object handle.
- *
- * This can be used when one application needs to pass a buffer object
- * to another.
- */
-dri_bo *
-intel_ttm_bo_create_from_handle(dri_bufmgr *bufmgr, const char *name,
- unsigned int handle)
-{
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)bufmgr;
- dri_bo_ttm *ttm_buf;
- int ret;
-
- ttm_buf = calloc(1, sizeof(*ttm_buf));
- if (!ttm_buf)
- return NULL;
-
- ret = drmBOReference(bufmgr_ttm->fd, handle, &ttm_buf->drm_bo);
- if (ret != 0) {
- fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
- name, handle, strerror(-ret));
- free(ttm_buf);
- return NULL;
- }
- ttm_buf->bo.size = ttm_buf->drm_bo.size;
- ttm_buf->bo.offset = ttm_buf->drm_bo.offset;
- ttm_buf->bo.virtual = NULL;
- ttm_buf->bo.bufmgr = bufmgr;
- ttm_buf->name = name;
- ttm_buf->refcount = 1;
- ttm_buf->reloc_buf_data = NULL;
- ttm_buf->relocs = NULL;
- ttm_buf->last_flags = ttm_buf->drm_bo.flags;
- ttm_buf->shared = GL_TRUE;
- ttm_buf->delayed_unmap = GL_FALSE;
- ttm_buf->validate_index = -1;
-
- DBG("bo_create_from_handle: %p %08x (%s)\n",
- &ttm_buf->bo, handle, ttm_buf->name);
-
- return &ttm_buf->bo;
-}
-
-static void
-dri_ttm_bo_reference(dri_bo *buf)
-{
- dri_bo_ttm *ttm_buf = (dri_bo_ttm *)buf;
-
- ttm_buf->refcount++;
-}
-
-static void
-dri_ttm_bo_unreference(dri_bo *buf)
-{
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)buf->bufmgr;
- dri_bo_ttm *ttm_buf = (dri_bo_ttm *)buf;
-
- if (!buf)
- return;
-
- if (--ttm_buf->refcount == 0) {
- struct dri_ttm_bo_bucket *bucket;
- int ret;
-
- assert(ttm_buf->map_count == 0);
-
- if (ttm_buf->reloc_buf_data) {
- int i;
-
- /* Unreference all the target buffers */
- for (i = 0; i < (ttm_buf->reloc_buf_data[0] & 0xffff); i++)
- dri_bo_unreference(ttm_buf->relocs[i].target_buf);
- free(ttm_buf->relocs);
-
- /* Free the kernel BO containing relocation entries */
- free(ttm_buf->reloc_buf_data);
- ttm_buf->reloc_buf_data = NULL;
- }
-
- if (ttm_buf->delayed_unmap) {
- int ret = drmBOUnmap(bufmgr_ttm->fd, &ttm_buf->drm_bo);
-
- if (ret != 0) {
- fprintf(stderr, "%s:%d: Error unmapping buffer %s: %s.\n",
- __FILE__, __LINE__, ttm_buf->name, strerror(-ret));
- }
- }
-
- bucket = dri_ttm_bo_bucket_for_size(bufmgr_ttm, ttm_buf->drm_bo.size);
- /* Put the buffer into our internal cache for reuse if we can. */
- if (!ttm_buf->shared &&
- bucket != NULL &&
- (bucket->max_entries == -1 ||
- (bucket->max_entries > 0 &&
- bucket->num_entries < bucket->max_entries)))
- {
- struct dri_ttm_bo_bucket_entry *entry;
-
- entry = calloc(1, sizeof(*entry));
- entry->drm_bo = ttm_buf->drm_bo;
-
- entry->next = NULL;
- *bucket->tail = entry;
- bucket->tail = &entry->next;
- bucket->num_entries++;
- } else {
- /* Decrement the kernel refcount for the buffer. */
- ret = drmBOUnreference(bufmgr_ttm->fd, &ttm_buf->drm_bo);
- if (ret != 0) {
- fprintf(stderr, "drmBOUnreference failed (%s): %s\n",
- ttm_buf->name, strerror(-ret));
- }
- }
-
- DBG("bo_unreference final: %p (%s)\n", &ttm_buf->bo, ttm_buf->name);
-
- free(buf);
- return;
- }
-}
-
-static int
-dri_ttm_bo_map(dri_bo *buf, GLboolean write_enable)
-{
- dri_bufmgr_ttm *bufmgr_ttm;
- dri_bo_ttm *ttm_buf = (dri_bo_ttm *)buf;
- uint64_t flags;
- int ret;
-
- bufmgr_ttm = (dri_bufmgr_ttm *)buf->bufmgr;
-
- flags = DRM_BO_FLAG_READ;
- if (write_enable)
- flags |= DRM_BO_FLAG_WRITE;
-
- /* Allow recursive mapping. Mesa may recursively map buffers with
- * nested display loops.
- */
- if (ttm_buf->map_count++ != 0)
- return 0;
-
- assert(buf->virtual == NULL);
-
- DBG("bo_map: %p (%s)\n", &ttm_buf->bo, ttm_buf->name);
-
- /* XXX: What about if we're upgrading from READ to WRITE? */
- if (ttm_buf->delayed_unmap) {
- buf->virtual = ttm_buf->saved_virtual;
- return 0;
- }
-
- ret = drmBOMap(bufmgr_ttm->fd, &ttm_buf->drm_bo, flags, 0, &buf->virtual);
- if (ret != 0) {
- fprintf(stderr, "%s:%d: Error mapping buffer %s: %s .\n",
- __FILE__, __LINE__, ttm_buf->name, strerror(-ret));
- }
-
- return ret;
-}
-
-static int
-dri_ttm_bo_unmap(dri_bo *buf)
-{
- dri_bufmgr_ttm *bufmgr_ttm;
- dri_bo_ttm *ttm_buf = (dri_bo_ttm *)buf;
- int ret;
-
- if (buf == NULL)
- return 0;
-
- assert(ttm_buf->map_count != 0);
- if (--ttm_buf->map_count != 0)
- return 0;
-
- bufmgr_ttm = (dri_bufmgr_ttm *)buf->bufmgr;
-
- assert(buf->virtual != NULL);
-
- DBG("bo_unmap: %p (%s)\n", &ttm_buf->bo, ttm_buf->name);
-
- if (!ttm_buf->shared) {
- ttm_buf->saved_virtual = buf->virtual;
- ttm_buf->delayed_unmap = GL_TRUE;
- buf->virtual = NULL;
-
- return 0;
- }
-
- buf->virtual = NULL;
-
- ret = drmBOUnmap(bufmgr_ttm->fd, &ttm_buf->drm_bo);
- if (ret != 0) {
- fprintf(stderr, "%s:%d: Error unmapping buffer %s: %s.\n",
- __FILE__, __LINE__, ttm_buf->name, strerror(-ret));
- }
-
- return ret;
-}
-
-/**
- * Returns a dri_bo wrapping the given buffer object handle.
- *
- * This can be used when one application needs to pass a buffer object
- * to another.
- */
-dri_fence *
-intel_ttm_fence_create_from_arg(dri_bufmgr *bufmgr, const char *name,
- drm_fence_arg_t *arg)
-{
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)bufmgr;
- dri_fence_ttm *ttm_fence;
-
- ttm_fence = malloc(sizeof(*ttm_fence));
- if (!ttm_fence)
- return NULL;
-
- ttm_fence->drm_fence.handle = arg->handle;
- ttm_fence->drm_fence.fence_class = arg->fence_class;
- ttm_fence->drm_fence.type = arg->type;
- ttm_fence->drm_fence.flags = arg->flags;
- ttm_fence->drm_fence.signaled = 0;
- ttm_fence->drm_fence.sequence = arg->sequence;
-
- ttm_fence->fence.bufmgr = bufmgr;
- ttm_fence->name = name;
- ttm_fence->refcount = 1;
-
- DBG("fence_create_from_handle: %p (%s)\n",
- &ttm_fence->fence, ttm_fence->name);
-
- return &ttm_fence->fence;
-}
-
-
-static void
-dri_ttm_fence_reference(dri_fence *fence)
-{
- dri_fence_ttm *fence_ttm = (dri_fence_ttm *)fence;
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)fence->bufmgr;
-
- ++fence_ttm->refcount;
- DBG("fence_reference: %p (%s)\n", &fence_ttm->fence, fence_ttm->name);
-}
-
-static void
-dri_ttm_fence_unreference(dri_fence *fence)
-{
- dri_fence_ttm *fence_ttm = (dri_fence_ttm *)fence;
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)fence->bufmgr;
-
- if (!fence)
- return;
-
- DBG("fence_unreference: %p (%s)\n", &fence_ttm->fence, fence_ttm->name);
-
- if (--fence_ttm->refcount == 0) {
- int ret;
-
- ret = drmFenceUnreference(bufmgr_ttm->fd, &fence_ttm->drm_fence);
- if (ret != 0) {
- fprintf(stderr, "drmFenceUnreference failed (%s): %s\n",
- fence_ttm->name, strerror(-ret));
- }
-
- free(fence);
- return;
- }
-}
-
-static void
-dri_ttm_fence_wait(dri_fence *fence)
-{
- dri_fence_ttm *fence_ttm = (dri_fence_ttm *)fence;
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)fence->bufmgr;
- int ret;
-
- ret = drmFenceWait(bufmgr_ttm->fd, DRM_FENCE_FLAG_WAIT_LAZY, &fence_ttm->drm_fence, 0);
- if (ret != 0) {
- fprintf(stderr, "%s:%d: Error waiting for fence %s: %s.\n",
- __FILE__, __LINE__, fence_ttm->name, strerror(-ret));
- abort();
- }
-
- DBG("fence_wait: %p (%s)\n", &fence_ttm->fence, fence_ttm->name);
-}
-
-static void
-dri_bufmgr_ttm_destroy(dri_bufmgr *bufmgr)
-{
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)bufmgr;
- int i;
-
- free(bufmgr_ttm->validate_array);
-
- /* Free any cached buffer objects we were going to reuse */
- for (i = 0; i < INTEL_TTM_BO_BUCKETS; i++) {
- struct dri_ttm_bo_bucket *bucket = &bufmgr_ttm->cache_bucket[i];
- struct dri_ttm_bo_bucket_entry *entry;
-
- while ((entry = bucket->head) != NULL) {
- int ret;
-
- bucket->head = entry->next;
- if (entry->next == NULL)
- bucket->tail = &bucket->head;
- bucket->num_entries--;
-
- /* Decrement the kernel refcount for the buffer. */
- ret = drmBOUnreference(bufmgr_ttm->fd, &entry->drm_bo);
- if (ret != 0) {
- fprintf(stderr, "drmBOUnreference failed: %s\n",
- strerror(-ret));
- }
-
- free(entry);
- }
- }
-
- free(bufmgr);
-}
-
-/**
- * Adds the target buffer to the validation list and adds the relocation
- * to the reloc_buffer's relocation list.
- *
- * The relocation entry at the given offset must already contain the
- * precomputed relocation value, because the kernel will optimize out
- * the relocation entry write when the buffer hasn't moved from the
- * last known offset in target_buf.
- */
-static int
-dri_ttm_emit_reloc(dri_bo *reloc_buf, uint64_t flags, GLuint delta,
- GLuint offset, dri_bo *target_buf)
-{
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)reloc_buf->bufmgr;
- dri_bo_ttm *reloc_buf_ttm = (dri_bo_ttm *)reloc_buf;
- dri_bo_ttm *target_buf_ttm = (dri_bo_ttm *)target_buf;
- int num_relocs;
- uint32_t *this_reloc;
-
- /* Create a new relocation list if needed */
- if (reloc_buf_ttm->reloc_buf_data == NULL)
- intel_setup_reloc_list(reloc_buf);
-
- num_relocs = reloc_buf_ttm->reloc_buf_data[0];
-
- /* Check overflow */
- assert(num_relocs < bufmgr_ttm->max_relocs);
-
- this_reloc = reloc_buf_ttm->reloc_buf_data + I915_RELOC_HEADER +
- num_relocs * I915_RELOC0_STRIDE;
-
- this_reloc[0] = offset;
- this_reloc[1] = delta;
- this_reloc[2] = target_buf_ttm->drm_bo.handle; /* To be filled in at exec time */
- this_reloc[3] = 0;
-
- reloc_buf_ttm->relocs[num_relocs].validate_flags = flags;
- reloc_buf_ttm->relocs[num_relocs].target_buf = target_buf;
- dri_bo_reference(target_buf);
-
- reloc_buf_ttm->reloc_buf_data[0]++; /* Increment relocation count */
- /* Check wraparound */
- assert(reloc_buf_ttm->reloc_buf_data[0] != 0);
- return 0;
-}
-
-/**
- * Walk the tree of relocations rooted at BO and accumulate the list of
- * validations to be performed and update the relocation buffers with
- * index values into the validation list.
- */
-static void
-dri_ttm_bo_process_reloc(dri_bo *bo)
-{
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)bo->bufmgr;
- dri_bo_ttm *bo_ttm = (dri_bo_ttm *)bo;
- unsigned int nr_relocs;
- int i;
-
- if (bo_ttm->reloc_buf_data == NULL)
- return;
-
- nr_relocs = bo_ttm->reloc_buf_data[0] & 0xffff;
-
- for (i = 0; i < nr_relocs; i++) {
- struct dri_ttm_reloc *r = &bo_ttm->relocs[i];
-
- /* Continue walking the tree depth-first. */
- dri_ttm_bo_process_reloc(r->target_buf);
-
- /* Add the target to the validate list */
- intel_add_validate_buffer(r->target_buf, r->validate_flags);
-
- /* Clear the PRESUMED_OFFSET flag from the validate list entry of the
- * target if this buffer has a stale relocated pointer at it.
- */
- if (r->last_target_offset != r->target_buf->offset) {
- dri_bo_ttm *target_buf_ttm = (dri_bo_ttm *)r->target_buf;
- struct intel_validate_entry *entry =
- &bufmgr_ttm->validate_array[target_buf_ttm->validate_index];
-
- entry->bo_arg.d.req.bo_req.hint &= ~DRM_BO_HINT_PRESUMED_OFFSET;
- }
- }
-}
-
-static void *
-dri_ttm_process_reloc(dri_bo *batch_buf, GLuint *count)
-{
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)batch_buf->bufmgr;
-
- /* Update indices and set up the validate list. */
- dri_ttm_bo_process_reloc(batch_buf);
-
- /* Add the batch buffer to the validation list. There are no relocations
- * pointing to it.
- */
- intel_add_validate_buffer(batch_buf,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_EXE);
-
- *count = bufmgr_ttm->validate_count;
- return &bufmgr_ttm->validate_array[0].bo_arg;
-}
-
-static const char *
-intel_get_flags_mem_type_string(uint64_t flags)
-{
- switch (flags & DRM_BO_MASK_MEM) {
- case DRM_BO_FLAG_MEM_LOCAL: return "local";
- case DRM_BO_FLAG_MEM_TT: return "ttm";
- case DRM_BO_FLAG_MEM_VRAM: return "vram";
- case DRM_BO_FLAG_MEM_PRIV0: return "priv0";
- case DRM_BO_FLAG_MEM_PRIV1: return "priv1";
- case DRM_BO_FLAG_MEM_PRIV2: return "priv2";
- case DRM_BO_FLAG_MEM_PRIV3: return "priv3";
- case DRM_BO_FLAG_MEM_PRIV4: return "priv4";
- default: return NULL;
- }
-}
-
-static const char *
-intel_get_flags_caching_string(uint64_t flags)
-{
- switch (flags & (DRM_BO_FLAG_CACHED | DRM_BO_FLAG_CACHED_MAPPED)) {
- case 0: return "UU";
- case DRM_BO_FLAG_CACHED: return "CU";
- case DRM_BO_FLAG_CACHED_MAPPED: return "UC";
- case DRM_BO_FLAG_CACHED | DRM_BO_FLAG_CACHED_MAPPED: return "CC";
- default: return NULL;
- }
-}
-
-static void
-intel_update_buffer_offsets (dri_bufmgr_ttm *bufmgr_ttm)
-{
- int i;
-
- for (i = 0; i < bufmgr_ttm->validate_count; i++) {
- dri_bo *bo = bufmgr_ttm->validate_array[i].bo;
- dri_bo_ttm *bo_ttm = (dri_bo_ttm *)bo;
- struct drm_i915_op_arg *arg = &bufmgr_ttm->validate_array[i].bo_arg;
- struct drm_bo_arg_rep *rep = &arg->d.rep;
-
- /* Update the flags */
- if (rep->bo_info.flags != bo_ttm->last_flags) {
- DBG("BO %s migrated: %s/%s -> %s/%s\n",
- bo_ttm->name,
- intel_get_flags_mem_type_string(bo_ttm->last_flags),
- intel_get_flags_caching_string(bo_ttm->last_flags),
- intel_get_flags_mem_type_string(rep->bo_info.flags),
- intel_get_flags_caching_string(rep->bo_info.flags));
-
- bo_ttm->last_flags = rep->bo_info.flags;
- }
- /* Update the buffer offset */
- if (rep->bo_info.offset != bo->offset) {
- DBG("BO %s migrated: 0x%08lx -> 0x%08lx\n",
- bo_ttm->name, bo->offset, (unsigned long)rep->bo_info.offset);
- bo->offset = rep->bo_info.offset;
- }
- }
-}
-
-/**
- * Update the last target offset field of relocation entries for PRESUMED_OFFSET
- * computation.
- */
-static void
-dri_ttm_bo_post_submit(dri_bo *bo)
-{
- dri_bo_ttm *bo_ttm = (dri_bo_ttm *)bo;
- unsigned int nr_relocs;
- int i;
-
- if (bo_ttm->reloc_buf_data == NULL)
- return;
-
- nr_relocs = bo_ttm->reloc_buf_data[0] & 0xffff;
-
- for (i = 0; i < nr_relocs; i++) {
- struct dri_ttm_reloc *r = &bo_ttm->relocs[i];
-
- /* Continue walking the tree depth-first. */
- dri_ttm_bo_post_submit(r->target_buf);
-
- r->last_target_offset = r->target_buf->offset;
- }
-}
-
-static void
-dri_ttm_post_submit(dri_bo *batch_buf, dri_fence **last_fence)
-{
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)batch_buf->bufmgr;
- int i;
-
- intel_update_buffer_offsets (bufmgr_ttm);
-
- dri_ttm_bo_post_submit(batch_buf);
-
- if (bufmgr_ttm->bufmgr.debug)
- dri_ttm_dump_validation_list(bufmgr_ttm);
-
- for (i = 0; i < bufmgr_ttm->validate_count; i++) {
- dri_bo *bo = bufmgr_ttm->validate_array[i].bo;
- dri_bo_ttm *bo_ttm = (dri_bo_ttm *)bo;
-
- /* Disconnect the buffer from the validate list */
- bo_ttm->validate_index = -1;
- dri_bo_unreference(bo);
- bufmgr_ttm->validate_array[i].bo = NULL;
- }
- bufmgr_ttm->validate_count = 0;
-}
-
-/**
- * Enables unlimited caching of buffer objects for reuse.
- *
- * This is potentially very memory expensive, as the cache at each bucket
- * size is only bounded by how many buffers of that size we've managed to have
- * in flight at once.
- */
-void
-intel_ttm_enable_bo_reuse(dri_bufmgr *bufmgr)
-{
- dri_bufmgr_ttm *bufmgr_ttm = (dri_bufmgr_ttm *)bufmgr;
- int i;
-
- for (i = 0; i < INTEL_TTM_BO_BUCKETS; i++) {
- bufmgr_ttm->cache_bucket[i].max_entries = -1;
- }
-}
-
-/*
- *
- */
-static int
-dri_ttm_check_aperture_space(dri_bo *bo)
-{
- return 0;
-}
-
-/**
- * Initializes the TTM buffer manager, which uses the kernel to allocate, map,
- * and manage map buffer objections.
- *
- * \param fd File descriptor of the opened DRM device.
- * \param fence_type Driver-specific fence type used for fences with no flush.
- * \param fence_type_flush Driver-specific fence type used for fences with a
- * flush.
- */
-dri_bufmgr *
-intel_bufmgr_ttm_init(int fd, unsigned int fence_type,
- unsigned int fence_type_flush, int batch_size)
-{
- dri_bufmgr_ttm *bufmgr_ttm;
- int i;
-
- bufmgr_ttm = calloc(1, sizeof(*bufmgr_ttm));
- bufmgr_ttm->fd = fd;
- bufmgr_ttm->fence_type = fence_type;
- bufmgr_ttm->fence_type_flush = fence_type_flush;
-
- /* Let's go with one relocation per every 2 dwords (but round down a bit
- * since a power of two will mean an extra page allocation for the reloc
- * buffer).
- *
- * Every 4 was too few for the blender benchmark.
- */
- bufmgr_ttm->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
-
- bufmgr_ttm->bufmgr.bo_alloc = dri_ttm_alloc;
- bufmgr_ttm->bufmgr.bo_alloc_static = dri_ttm_alloc_static;
- bufmgr_ttm->bufmgr.bo_reference = dri_ttm_bo_reference;
- bufmgr_ttm->bufmgr.bo_unreference = dri_ttm_bo_unreference;
- bufmgr_ttm->bufmgr.bo_map = dri_ttm_bo_map;
- bufmgr_ttm->bufmgr.bo_unmap = dri_ttm_bo_unmap;
- bufmgr_ttm->bufmgr.fence_reference = dri_ttm_fence_reference;
- bufmgr_ttm->bufmgr.fence_unreference = dri_ttm_fence_unreference;
- bufmgr_ttm->bufmgr.fence_wait = dri_ttm_fence_wait;
- bufmgr_ttm->bufmgr.destroy = dri_bufmgr_ttm_destroy;
- bufmgr_ttm->bufmgr.emit_reloc = dri_ttm_emit_reloc;
- bufmgr_ttm->bufmgr.process_relocs = dri_ttm_process_reloc;
- bufmgr_ttm->bufmgr.post_submit = dri_ttm_post_submit;
- bufmgr_ttm->bufmgr.debug = GL_FALSE;
- bufmgr_ttm->bufmgr.check_aperture_space = dri_ttm_check_aperture_space;
- /* Initialize the linked lists for BO reuse cache. */
- for (i = 0; i < INTEL_TTM_BO_BUCKETS; i++)
- bufmgr_ttm->cache_bucket[i].tail = &bufmgr_ttm->cache_bucket[i].head;
-
- return &bufmgr_ttm->bufmgr;
-}
-
diff --git a/src/mesa/drivers/dri/intel/intel_bufmgr_ttm.h b/src/mesa/drivers/dri/intel/intel_bufmgr_ttm.h
deleted file mode 100644
index d267a168cd..0000000000
--- a/src/mesa/drivers/dri/intel/intel_bufmgr_ttm.h
+++ /dev/null
@@ -1,20 +0,0 @@
-
-#ifndef INTEL_BUFMGR_TTM_H
-#define INTEL_BUFMGR_TTM_H
-
-#include "dri_bufmgr.h"
-
-extern dri_bo *intel_ttm_bo_create_from_handle(dri_bufmgr *bufmgr, const char *name,
- unsigned int handle);
-
-dri_fence *intel_ttm_fence_create_from_arg(dri_bufmgr *bufmgr, const char *name,
- drm_fence_arg_t *arg);
-
-
-dri_bufmgr *intel_bufmgr_ttm_init(int fd, unsigned int fence_type,
- unsigned int fence_type_flush, int batch_size);
-
-void
-intel_ttm_enable_bo_reuse(dri_bufmgr *bufmgr);
-
-#endif
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index e1941c302c..f33805ba05 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -59,8 +59,7 @@
#include "intel_buffer_objects.h"
#include "intel_fbo.h"
#include "intel_decode.h"
-#include "intel_bufmgr_fake.h"
-#include "intel_bufmgr_gem.h"
+#include "intel_bufmgr.h"
#include "drirenderbuffer.h"
#include "vblank.h"
@@ -474,7 +473,7 @@ intel_init_bufmgr(struct intel_context *intel)
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
- intel_gem_enable_bo_reuse(intel->bufmgr);
+ intel_bufmgr_gem_enable_reuse(intel->bufmgr);
break;
}
}
@@ -493,12 +492,12 @@ intel_init_bufmgr(struct intel_context *intel)
return GL_FALSE;
}
- intel->bufmgr = dri_bufmgr_fake_init(intelScreen->tex.offset,
- intelScreen->tex.map,
- intelScreen->tex.size,
- intel_fence_emit,
- intel_fence_wait,
- intel);
+ intel->bufmgr = intel_bufmgr_fake_init(intelScreen->tex.offset,
+ intelScreen->tex.map,
+ intelScreen->tex.size,
+ intel_fence_emit,
+ intel_fence_wait,
+ intel);
}
/* XXX bufmgr should be per-screen, not per-context */
@@ -873,7 +872,7 @@ intelContendedLock(struct intel_context *intel, GLuint flags)
*/
if (!intel->ttm && sarea->texAge != intel->hHWContext) {
sarea->texAge = intel->hHWContext;
- dri_bufmgr_fake_contended_lock_take(intel->bufmgr);
+ intel_bufmgr_fake_contended_lock_take(intel->bufmgr);
if (INTEL_DEBUG & DEBUG_BATCH)
intel_decode_context_reset();
if (INTEL_DEBUG & DEBUG_BUFMGR)
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 35ef22aa27..579883437f 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -35,6 +35,7 @@
#include "mm.h"
#include "texmem.h"
#include "dri_bufmgr.h"
+#include "intel_bufmgr.h"
#include "intel_screen.h"
#include "intel_tex_obj.h"
diff --git a/src/mesa/drivers/dri/intel/intel_ioctl.c b/src/mesa/drivers/dri/intel/intel_ioctl.c
index 591548ae85..58c81766cd 100644
--- a/src/mesa/drivers/dri/intel/intel_ioctl.c
+++ b/src/mesa/drivers/dri/intel/intel_ioctl.c
@@ -45,7 +45,7 @@
#include "drm.h"
#include "i915_drm.h"
-#include "intel_bufmgr_gem.h"
+#include "intel_bufmgr.h"
#define FILE_DEBUG_FLAG DEBUG_IOCTL
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 7d78e4eca7..c7e2c551dd 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -44,7 +44,7 @@
#include "intel_blit.h"
#include "intel_buffer_objects.h"
#include "dri_bufmgr.h"
-#include "intel_bufmgr_gem.h"
+#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
#define FILE_DEBUG_FLAG DEBUG_REGION
@@ -106,10 +106,7 @@ intel_region_alloc(struct intel_context *intel,
dri_bo *buffer;
buffer = dri_bo_alloc(intel->bufmgr, "region",
- pitch * cpp * height, 64,
- DRM_BO_FLAG_MEM_LOCAL |
- DRM_BO_FLAG_CACHED |
- DRM_BO_FLAG_CACHED_MAPPED);
+ pitch * cpp * height, 64);
return intel_region_alloc_internal(intel, cpp, pitch, height, 0, buffer);
}
@@ -121,7 +118,7 @@ intel_region_alloc_for_handle(struct intel_context *intel,
{
dri_bo *buffer;
- buffer = intel_gem_bo_create_from_handle(intel->bufmgr, "region", handle);
+ buffer = intel_bo_gem_create_from_name(intel->bufmgr, "region", handle);
return intel_region_alloc_internal(intel,
cpp, pitch, height, tiled, buffer);
@@ -355,10 +352,7 @@ intel_region_release_pbo(struct intel_context *intel,
region->buffer = dri_bo_alloc(intel->bufmgr, "region",
region->pitch * region->cpp * region->height,
- 64,
- DRM_BO_FLAG_MEM_LOCAL |
- DRM_BO_FLAG_CACHED |
- DRM_BO_FLAG_CACHED_MAPPED);
+ 64);
}
/* Break the COW tie to the pbo. Both the pbo and the region end up
@@ -440,17 +434,16 @@ intel_recreate_static(struct intel_context *intel,
if (intel->ttm) {
assert(region_desc->bo_handle != -1);
- region->buffer = intel_gem_bo_create_from_handle(intel->bufmgr,
- name,
- region_desc->bo_handle);
+ region->buffer = intel_bo_gem_create_from_name(intel->bufmgr,
+ name,
+ region_desc->bo_handle);
} else {
- region->buffer = dri_bo_alloc_static(intel->bufmgr,
- name,
- region_desc->offset,
- intelScreen->pitch *
- intelScreen->height,
- region_desc->map,
- DRM_BO_FLAG_MEM_TT);
+ region->buffer = intel_bo_fake_alloc_static(intel->bufmgr,
+ name,
+ region_desc->offset,
+ intelScreen->pitch *
+ intelScreen->height,
+ region_desc->map);
}
assert(region->buffer != NULL);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index a243324a39..f325e70359 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -49,7 +49,7 @@
#include "i830_dri.h"
#include "intel_regions.h"
#include "intel_batchbuffer.h"
-#include "intel_bufmgr_gem.h"
+#include "intel_bufmgr.h"
PUBLIC const char __driConfigOptions[] =
DRI_CONF_BEGIN
--
cgit v1.2.3
From f5d03af109e0c6fdd7cc6786f8ae40f8ae626f5a Mon Sep 17 00:00:00 2001
From: Keith Packard
Date: Fri, 6 Jun 2008 13:05:46 -0700
Subject: [intel-gem] Call the new throttle ioctl from swap buffers
Swap buffers is a fairly reasonable time to wait for the hardware for a
while; this keeps us from overrunning the ring.
---
src/mesa/drivers/dri/intel/intel_buffers.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c
index 2a25f079e9..d5257ae27e 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -848,6 +848,8 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv)
intel_fb->swap_ust = ust;
}
+ drmCommandNone(intel->driFd, DRM_I915_GEM_THROTTLE);
+
}
else {
/* XXX this shouldn't be an error but we can't handle it for now */
--
cgit v1.2.3
From 0227d91a9e3cf65aae3266d100eebd3459dff4c3 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 11 Jun 2008 11:45:51 -0700
Subject: [gem] Enable bo_reuse by default.
The objects are swappable, so we're less concerned by excessive object
allocation now, and it's about a 20% performance improvement. If we get
concerns about the memory consumption from others, we can look into a
compromise position later.
---
src/mesa/drivers/dri/intel/intel_screen.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index f325e70359..09a30e80a5 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -59,7 +59,7 @@ PUBLIC const char __driConfigOptions[] =
/* Options correspond to DRI_CONF_BO_REUSE_DISABLED,
* DRI_CONF_BO_REUSE_ALL
*/
- DRI_CONF_OPT_BEGIN_V(bo_reuse, enum, 0, "0:1")
+ DRI_CONF_OPT_BEGIN_V(bo_reuse, enum, 1, "0:1")
DRI_CONF_DESC_BEGIN(en, "Buffer object reuse")
DRI_CONF_ENUM(0, "Disable buffer object reuse")
DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects")
--
cgit v1.2.3
From 407ce3da3c53c9ebba0fbf827d7b0f610122d44b Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 11 Jun 2008 14:44:48 -0700
Subject: [intel-gem] Chase domain flag renaming in the DRM.
This is an API breakage only.
---
src/mesa/drivers/dri/i915/i830_vtbl.c | 6 +++---
src/mesa/drivers/dri/i915/i915_vtbl.c | 6 +++---
src/mesa/drivers/dri/i965/brw_cc.c | 2 +-
src/mesa/drivers/dri/i965/brw_clip_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_curbe.c | 2 +-
src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 +++---
src/mesa/drivers/dri/i965/brw_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_misc_state.c | 16 ++++++++--------
src/mesa/drivers/dri/i965/brw_sf_state.c | 4 ++--
src/mesa/drivers/dri/i965/brw_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_state.c | 4 ++--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 10 +++++-----
src/mesa/drivers/dri/intel/intel_blit.c | 18 +++++++++---------
14 files changed, 41 insertions(+), 41 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 86bf468a7e..cff051b16b 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -490,14 +490,14 @@ i830_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
- DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
state->draw_region->draw_offset);
if (state->depth_region) {
OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
OUT_RELOC(state->depth_region->buffer,
- DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
state->depth_region->draw_offset);
}
@@ -524,7 +524,7 @@ i830_emit_state(struct intel_context *intel)
if (state->tex_buffer[i]) {
OUT_RELOC(state->tex_buffer[i],
- DRM_GEM_DOMAIN_I915_SAMPLER, 0,
+ I915_GEM_DOMAIN_SAMPLER, 0,
state->tex_offset[i] | TM0S0_USE_FENCE);
}
else if (state == &i830->meta) {
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index de1ec5effc..43f5703d9e 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -377,14 +377,14 @@ i915_emit_state(struct intel_context *intel)
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
OUT_RELOC(state->draw_region->buffer,
- DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
state->draw_region->draw_offset);
if (state->depth_region) {
OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
OUT_RELOC(state->depth_region->buffer,
- DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
state->depth_region->draw_offset);
}
@@ -427,7 +427,7 @@ i915_emit_state(struct intel_context *intel)
if (state->tex_buffer[i]) {
OUT_RELOC(state->tex_buffer[i],
- DRM_GEM_DOMAIN_I915_SAMPLER, 0,
+ I915_GEM_DOMAIN_SAMPLER, 0,
state->tex_offset[i]);
}
else if (state == &i915->meta) {
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index afcfbcccb9..49a80d3e4a 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -257,7 +257,7 @@ cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key)
/* Emit CC viewport relocation */
intel_bo_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION,
+ I915_GEM_DOMAIN_INSTRUCTION,
0,
0,
offsetof(struct brw_cc_unit_state, cc4),
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index fd5157bdb7..22bd38a9f3 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -120,7 +120,7 @@ clip_unit_create_from_key(struct brw_context *brw,
/* Emit clip program relocation */
assert(brw->clip.prog_bo);
intel_bo_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION,
+ I915_GEM_DOMAIN_INSTRUCTION,
0,
clip.thread0.grf_reg_count << 1,
offsetof(struct brw_clip_unit_state, thread0),
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index bd0b04c36f..b603be8fc1 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -351,7 +351,7 @@ static void emit_constant_buffer(struct brw_context *brw)
} else {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
OUT_RELOC(brw->curbe.curbe_bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
(sz - 1) + brw->curbe.curbe_offset);
}
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 18ba02423d..0181b06764 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -467,7 +467,7 @@ void brw_emit_vertices( struct brw_context *brw,
BRW_VB0_ACCESS_VERTEXDATA |
(input->stride << BRW_VB0_PITCH_SHIFT));
OUT_RELOC(input->bo,
- DRM_GEM_DOMAIN_I915_VERTEX, 0,
+ I915_GEM_DOMAIN_VERTEX, 0,
input->offset);
OUT_BATCH(max_index);
OUT_BATCH(0); /* Instance data step rate */
@@ -589,10 +589,10 @@ void brw_emit_indices(struct brw_context *brw,
BEGIN_BATCH(4, IGNORE_CLIPRECTS);
OUT_BATCH( ib.header.dword );
OUT_RELOC( bo,
- DRM_GEM_DOMAIN_I915_VERTEX, 0,
+ I915_GEM_DOMAIN_VERTEX, 0,
offset);
OUT_RELOC( bo,
- DRM_GEM_DOMAIN_I915_VERTEX, 0,
+ I915_GEM_DOMAIN_VERTEX, 0,
offset + ib_size);
OUT_BATCH( 0 );
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c
index 953ccf777f..ae6b48a517 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -107,7 +107,7 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
if (key->prog_active) {
/* Emit GS program relocation */
intel_bo_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
gs.thread0.grf_reg_count << 1,
offsetof(struct brw_gs_unit_state, thread0),
brw->gs.prog_bo);
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index c941e054a3..9d925682c2 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -89,7 +89,7 @@ static void upload_binding_table_pointers(struct brw_context *brw)
OUT_BATCH(0); /* clip */
OUT_BATCH(0); /* sf */
OUT_RELOC(brw->wm.bind_bo,
- DRM_GEM_DOMAIN_I915_SAMPLER, 0,
+ I915_GEM_DOMAIN_SAMPLER, 0,
0);
ADVANCE_BATCH();
}
@@ -116,18 +116,18 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
BEGIN_BATCH(7, IGNORE_CLIPRECTS);
OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
- OUT_RELOC(brw->vs.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
+ OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
if (brw->gs.prog_active)
- OUT_RELOC(brw->gs.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 1);
+ OUT_RELOC(brw->gs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
else
OUT_BATCH(0);
if (!brw->metaops.active)
- OUT_RELOC(brw->clip.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 1);
+ OUT_RELOC(brw->clip.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
else
OUT_BATCH(0);
- OUT_RELOC(brw->sf.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
- OUT_RELOC(brw->wm.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
- OUT_RELOC(brw->cc.state_bo, DRM_GEM_DOMAIN_I915_INSTRUCTION, 0, 0);
+ OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_RELOC(brw->wm.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
ADVANCE_BATCH();
brw->state.dirty.brw |= BRW_NEW_PSP;
@@ -235,7 +235,7 @@ static void emit_depthbuffer(struct brw_context *brw)
(region->tiled << 27) |
(BRW_SURFACE_2D << 29));
OUT_RELOC(region->buffer,
- DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
((region->pitch - 1) << 6) |
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index e8f36718a3..cbed301d31 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -254,14 +254,14 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
/* Emit SF program relocation */
intel_bo_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
sf.thread0.grf_reg_count << 1,
offsetof(struct brw_sf_unit_state, thread0),
brw->sf.prog_bo);
/* Emit SF viewport relocation */
intel_bo_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
offsetof(struct brw_sf_unit_state, sf5),
brw->sf.vp_bo);
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index a6b3db69ea..e18cd42f4e 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -116,7 +116,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
/* Emit VS program relocation */
intel_bo_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
vs.thread0.grf_reg_count << 1,
offsetof(struct brw_vs_unit_state, thread0),
brw->vs.prog_bo);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index 2e0aff7ab2..461f977aac 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -306,7 +306,7 @@ static int upload_wm_samplers( struct brw_context *brw )
ret |= dri_bufmgr_check_aperture_space(brw->wm.sdc_bo[i]);
intel_bo_emit_reloc(brw->wm.sampler_bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
0,
i * sizeof(struct brw_sampler_state) +
offsetof(struct brw_sampler_state, ss2),
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index ef78d71bbb..6fe30f0a9a 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -200,7 +200,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
/* Emit WM program relocation */
intel_bo_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
wm.thread0.grf_reg_count << 1,
offsetof(struct brw_wm_unit_state, thread0),
brw->wm.prog_bo);
@@ -217,7 +217,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
/* Emit sampler state relocation */
if (key->sampler_count != 0) {
intel_bo_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
offsetof(struct brw_wm_unit_state, wm4),
brw->wm.sampler_bo);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 6fc6d9dfd8..a7da5e643c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -204,7 +204,7 @@ brw_create_texture_surface( struct brw_context *brw,
/* Emit relocation to surface contents */
intel_bo_emit_reloc(bo,
- DRM_GEM_DOMAIN_I915_SAMPLER, 0,
+ I915_GEM_DOMAIN_SAMPLER, 0,
0,
offsetof(struct brw_surface_state, ss1),
key->bo);
@@ -342,9 +342,9 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
* a more restrictive relocation to emit.
*/
intel_bo_emit_reloc(brw->wm.surf_bo[unit],
- DRM_GEM_DOMAIN_I915_RENDER |
- DRM_GEM_DOMAIN_I915_SAMPLER,
- DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER |
+ I915_GEM_DOMAIN_SAMPLER,
+ I915_GEM_DOMAIN_RENDER,
0,
offsetof(struct brw_surface_state, ss1),
region_bo);
@@ -392,7 +392,7 @@ brw_wm_get_binding_table(struct brw_context *brw)
for (i = 0; i < BRW_WM_MAX_SURF; i++) {
if (brw->wm.surf_bo[i] != NULL) {
intel_bo_emit_reloc(bind_bo,
- DRM_GEM_DOMAIN_I915_INSTRUCTION, 0,
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
0,
i * sizeof(GLuint),
brw->wm.surf_bo[i]);
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index e8d2ad0ae4..174f5ecab0 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -149,12 +149,12 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
OUT_BATCH((box.y2 << 16) | box.x2);
OUT_RELOC(dst->buffer,
- DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
OUT_BATCH((src_y << 16) | src_x);
OUT_BATCH(src_pitch);
OUT_RELOC(src->buffer,
- DRM_GEM_DOMAIN_I915_RENDER, 0,
+ I915_GEM_DOMAIN_RENDER, 0,
0);
ADVANCE_BATCH();
}
@@ -225,7 +225,7 @@ intelEmitFillBlit(struct intel_context *intel,
OUT_BATCH((y << 16) | x);
OUT_BATCH(((y + h) << 16) | (x + w));
OUT_RELOC(dst_buffer,
- DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
dst_offset);
OUT_BATCH(color);
ADVANCE_BATCH();
@@ -347,12 +347,12 @@ intelEmitCopyBlit(struct intel_context *intel,
OUT_BATCH((dst_y << 16) | dst_x);
OUT_BATCH((dst_y2 << 16) | dst_x2);
OUT_RELOC(dst_buffer,
- DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
dst_offset);
OUT_BATCH((src_y << 16) | src_x);
OUT_BATCH(src_pitch);
OUT_RELOC(src_buffer,
- DRM_GEM_DOMAIN_I915_RENDER, 0,
+ I915_GEM_DOMAIN_RENDER, 0,
src_offset);
ADVANCE_BATCH();
}
@@ -366,12 +366,12 @@ intelEmitCopyBlit(struct intel_context *intel,
OUT_BATCH((0 << 16) | dst_x);
OUT_BATCH((h << 16) | dst_x2);
OUT_RELOC(dst_buffer,
- DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
dst_offset + dst_y * dst_pitch);
OUT_BATCH((0 << 16) | src_x);
OUT_BATCH(src_pitch);
OUT_RELOC(src_buffer,
- DRM_GEM_DOMAIN_I915_RENDER, 0,
+ I915_GEM_DOMAIN_RENDER, 0,
src_offset + src_y * src_pitch);
ADVANCE_BATCH();
}
@@ -551,7 +551,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
OUT_BATCH((b.y1 << 16) | b.x1);
OUT_BATCH((b.y2 << 16) | b.x2);
OUT_RELOC(write_buffer,
- DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
irb_region->draw_offset);
OUT_BATCH(clearVal);
ADVANCE_BATCH();
@@ -624,7 +624,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
OUT_RELOC(dst_buffer,
- DRM_GEM_DOMAIN_I915_RENDER, DRM_GEM_DOMAIN_I915_RENDER,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
dst_offset);
OUT_BATCH(0); /* bg */
OUT_BATCH(fg_color); /* fg */
--
cgit v1.2.3
From e2baf564d1b9716611d194cf117b329a92ad603d Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Tue, 17 Jun 2008 11:15:59 -0700
Subject: [intel-gem] Bug #16326: Fix X tile unswizzling on 965.
Apparently a bit gets flipped in the addressing for some rows of each tile.
---
src/mesa/drivers/dri/intel/intel_span.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 149b581d88..c6778b16ff 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -106,12 +106,38 @@ static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
x_tile_off = xbyte & 0x1ff;
y_tile_off = y & 7;
+#ifndef I915
+ /* The documentation says that X tile layout is arranged in 8 512-byte
+ * lines of pixel data. However, that doesn't appear to be the case
+ * on GM965, tested by drawing a 128x8 quad in no_rast mode. For lines
+ * 1,2,4, and 7 of each tile, each consecutive pair of 64-byte spans
+ * has the locations of those spans swapped.
+ */
+ switch (y_tile_off) {
+ case 1:
+ case 2:
+ case 4:
+ case 7:
+ x_tile_off ^= 64;
+ break;
+ default:
+ break;
+ }
+#endif
+
x_tile_number = xbyte >> 9;
y_tile_number = y >> 3;
tile_off = (y_tile_off << 9) + x_tile_off;
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
+#if 0
+ printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
+ x, y, tile_off, tile_base,
+ tile_off + tile_base,
+ irb->pfPitch, tile_stride);
+#endif
+
return buf + tile_base + tile_off;
}
--
cgit v1.2.3
From 64adeb163d7da6d75b5664cd2ee3783cadaf63d8 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Tue, 17 Jun 2008 14:14:02 -0700
Subject: [intel] Fix no_rast option on non-965.
The no_rast fallback was getting partially overwritten by later TNL init,
resulting in a segfault when things were in a mixed-up state.
---
src/mesa/drivers/dri/i915/i830_context.c | 3 +++
src/mesa/drivers/dri/i915/i915_context.c | 3 +++
src/mesa/drivers/dri/intel/intel_context.c | 1 -
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c
index 166a3bc8e2..d6542f8b3a 100644
--- a/src/mesa/drivers/dri/i915/i830_context.c
+++ b/src/mesa/drivers/dri/i915/i830_context.c
@@ -88,6 +88,9 @@ i830CreateContext(const __GLcontextModes * mesaVis,
_tnl_destroy_pipeline(ctx);
_tnl_install_pipeline(ctx, intel_pipeline);
+ if (intel->no_rast)
+ FALLBACK(intel, INTEL_FALLBACK_USER, 1);
+
intel->ctx.Const.MaxTextureUnits = I830_TEX_UNITS;
intel->ctx.Const.MaxTextureImageUnits = I830_TEX_UNITS;
intel->ctx.Const.MaxTextureCoordUnits = I830_TEX_UNITS;
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index 59da40229a..bb77cff96c 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -140,6 +140,9 @@ i915CreateContext(const __GLcontextModes * mesaVis,
_tnl_destroy_pipeline(ctx);
_tnl_install_pipeline(ctx, intel_pipeline);
+ if (intel->no_rast)
+ FALLBACK(intel, INTEL_FALLBACK_USER, 1);
+
ctx->Const.MaxTextureUnits = I915_TEX_UNITS;
ctx->Const.MaxTextureImageUnits = I915_TEX_UNITS;
ctx->Const.MaxTextureCoordUnits = I915_TEX_UNITS;
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index f33805ba05..e668b7326a 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -686,7 +686,6 @@ intelInitContext(struct intel_context *intel,
/* Force all software fallbacks */
if (driQueryOptionb(&intel->optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D rasterization\n");
- FALLBACK(intel, INTEL_FALLBACK_USER, 1);
intel->no_rast = 1;
}
--
cgit v1.2.3
From bbe80af457316826f56ada767d26e8c1db7f1130 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 18 Jun 2008 14:19:18 -0700
Subject: i915: Restore the accelerated PBO pixel path functions after GEM
changes.
The fencing code is not required, and waiting on the fences defeated one of
the purposes of the extension, which is to allow asynchronous readpixels.
---
src/mesa/drivers/dri/i915/Makefile | 8 +++-----
src/mesa/drivers/dri/i915/i830_context.c | 2 +-
src/mesa/drivers/dri/i915/i915_context.c | 2 +-
src/mesa/drivers/dri/i915/intel_pixel_read.c | 9 ---------
src/mesa/drivers/dri/intel/intel_pixel_draw.c | 8 --------
5 files changed, 5 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile
index 74f6169b2e..ccba34d229 100644
--- a/src/mesa/drivers/dri/i915/Makefile
+++ b/src/mesa/drivers/dri/i915/Makefile
@@ -6,11 +6,6 @@ LIBNAME = i915_dri.so
MINIGLX_SOURCES = server/intel_dri.c
-PIXEL_SOURCES = \
- intel_pixel.c \
- intel_pixel_read.c \
- intel_pixel_draw.c
-
DRIVER_SOURCES = \
i830_context.c \
i830_metaops.c \
@@ -48,6 +43,9 @@ DRIVER_SOURCES = \
intel_context.c \
intel_decode.c \
intel_ioctl.c \
+ intel_pixel.c \
+ intel_pixel_draw.c \
+ intel_pixel_read.c \
intel_screen.c \
intel_span.c \
intel_state.c \
diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c
index d6542f8b3a..66f1566f16 100644
--- a/src/mesa/drivers/dri/i915/i830_context.c
+++ b/src/mesa/drivers/dri/i915/i830_context.c
@@ -52,7 +52,7 @@ static void
i830InitDriverFunctions(struct dd_function_table *functions)
{
intelInitDriverFunctions(functions);
-// intelInitPixelFuncs(functions);
+ intelInitPixelFuncs(functions);
i830InitStateFuncs(functions);
i830InitTextureFuncs(functions);
}
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index bb77cff96c..1128f497db 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -94,7 +94,7 @@ static void
i915InitDriverFunctions(struct dd_function_table *functions)
{
intelInitDriverFunctions(functions);
-// intelInitPixelFuncs(functions);
+ intelInitPixelFuncs(functions);
i915InitStateFunctions(functions);
i915InitTextureFuncs(functions);
i915InitFragProgFuncs(functions);
diff --git a/src/mesa/drivers/dri/i915/intel_pixel_read.c b/src/mesa/drivers/dri/i915/intel_pixel_read.c
index 2e31656e98..0b95421a25 100644
--- a/src/mesa/drivers/dri/i915/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i915/intel_pixel_read.c
@@ -173,7 +173,6 @@ do_blit_readpixels(GLcontext * ctx,
struct intel_buffer_object *dst = intel_buffer_object(pack->BufferObj);
GLuint dst_offset;
GLuint rowLength;
- dri_fence *fence = NULL;
if (INTEL_DEBUG & DEBUG_PIXEL)
_mesa_printf("%s\n", __FUNCTION__);
@@ -275,17 +274,9 @@ do_blit_readpixels(GLcontext * ctx,
}
intel_batchbuffer_flush(intel->batch);
- fence = intel->batch->last_fence;
- dri_fence_reference(fence);
-
}
UNLOCK_HARDWARE(intel);
- if (fence) {
- dri_fence_wait(fence);
- dri_fence_unreference(fence);
- }
-
if (INTEL_DEBUG & DEBUG_PIXEL)
_mesa_printf("%s - DONE\n", __FUNCTION__);
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
index 2804c8deea..f7082f299e 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
@@ -218,7 +218,6 @@ do_blit_drawpixels(GLcontext * ctx,
struct intel_buffer_object *src = intel_buffer_object(unpack->BufferObj);
GLuint src_offset;
GLuint rowLength;
- dri_fence *fence = NULL;
if (INTEL_DEBUG & DEBUG_PIXEL)
_mesa_printf("%s\n", __FUNCTION__);
@@ -323,16 +322,9 @@ do_blit_drawpixels(GLcontext * ctx,
ctx->Color.LogicOp : GL_COPY);
}
intel_batchbuffer_flush(intel->batch);
- fence = intel->batch->last_fence;
- dri_fence_reference(fence);
}
UNLOCK_HARDWARE(intel);
- if (fence) {
- dri_fence_wait(fence);
- dri_fence_unreference(fence);
- }
-
if (INTEL_DEBUG & DEBUG_PIXEL)
_mesa_printf("%s - DONE\n", __FUNCTION__);
--
cgit v1.2.3
From 0da9bc6a69fbd287f2e87ca9f868cb4ccc47735a Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 18 Jun 2008 14:35:59 -0700
Subject: i915: Note the non-PBO fallback for textured drawpixels under
DEBUG_PIXEL.
---
src/mesa/drivers/dri/intel/intel_pixel_draw.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
index f7082f299e..28cd4f0ba6 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
@@ -81,7 +81,8 @@ do_texture_drawpixels(GLcontext * ctx,
else {
/* PBO only for now:
*/
-/* _mesa_printf("%s - not PBO\n", __FUNCTION__); */
+ if (INTEL_DEBUG & DEBUG_PIXEL)
+ _mesa_printf("%s - not PBO\n", __FUNCTION__);
return GL_FALSE;
}
--
cgit v1.2.3
From 62d66caeba786f01f6159c980fda79606afe4c61 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 20 Jun 2008 15:00:44 -0700
Subject: i915: Convert to using VBs instead of inline prims.
---
src/mesa/drivers/dri/i915/i830_reg.h | 4 -
src/mesa/drivers/dri/i915/i830_vtbl.c | 7 +-
src/mesa/drivers/dri/i915/i915_reg.h | 112 ---------------
src/mesa/drivers/dri/i915/i915_vtbl.c | 6 +-
src/mesa/drivers/dri/i915/intel_render.c | 13 +-
src/mesa/drivers/dri/i915/intel_tris.c | 219 ++++++++++++++++++-----------
src/mesa/drivers/dri/i915/intel_tris.h | 13 +-
src/mesa/drivers/dri/intel/intel_context.h | 14 +-
src/mesa/drivers/dri/intel/intel_reg.h | 125 ++++++++++++++++
9 files changed, 299 insertions(+), 214 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_reg.h b/src/mesa/drivers/dri/i915/i830_reg.h
index d1084a84c0..d210c2d08e 100644
--- a/src/mesa/drivers/dri/i915/i830_reg.h
+++ b/src/mesa/drivers/dri/i915/i830_reg.h
@@ -494,10 +494,6 @@
#define VFT1_TEX0_FMT(x) (x)
#define VFT1_TEX0_MASK 3
#define VFT1_TEX1_SHIFT 2
-#define TEXCOORDFMT_2D 0
-#define TEXCOORDFMT_3D 1
-#define TEXCOORDFMT_4D 2
-#define TEXCOORDFMT_1D 3
/*New stuff picked up along the way */
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index cff051b16b..4d3ad0083a 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -31,6 +31,7 @@
#include "i830_reg.h"
#include "intel_batchbuffer.h"
#include "intel_regions.h"
+#include "intel_tris.h"
#include "tnl/t_context.h"
#include "tnl/t_vertex.h"
@@ -435,7 +436,8 @@ i830_emit_state(struct intel_context *intel)
* Set the space as LOOP_CLIPRECTS now, since that's what our primitives
* will be emitted under.
*/
- intel_batchbuffer_require_space(intel->batch, get_state_size(state) + 8,
+ intel_batchbuffer_require_space(intel->batch,
+ get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
LOOP_CLIPRECTS);
count = 0;
again:
@@ -675,6 +677,9 @@ i830_new_batch(struct intel_context *intel)
struct i830_context *i830 = i830_context(&intel->ctx);
i830->state.emitted = 0;
+ /* Signal that we should put new vertices into a new vertex buffer. */
+ intel->prim.needs_new_vb = GL_TRUE;
+
/* Check that we didn't just wrap our batchbuffer at a bad time. */
assert(!intel->no_batch_wrap);
}
diff --git a/src/mesa/drivers/dri/i915/i915_reg.h b/src/mesa/drivers/dri/i915/i915_reg.h
index b718b8610c..8891e11c6f 100644
--- a/src/mesa/drivers/dri/i915/i915_reg.h
+++ b/src/mesa/drivers/dri/i915/i915_reg.h
@@ -325,118 +325,6 @@
#define SCISSOR_RECT_0_YMAX(x) ((x)<<16)
#define SCISSOR_RECT_0_XMAX(x) (x)
-/* p189 */
-#define _3DSTATE_LOAD_STATE_IMMEDIATE_1 ((0x3<<29)|(0x1d<<24)|(0x04<<16))
-#define I1_LOAD_S(n) (1<<(4+n))
-
-#define S0_VB_OFFSET_MASK 0xffffffc
-#define S0_AUTO_CACHE_INV_DISABLE (1<<0)
-
-#define S1_VERTEX_WIDTH_SHIFT 24
-#define S1_VERTEX_WIDTH_MASK (0x3f<<24)
-#define S1_VERTEX_PITCH_SHIFT 16
-#define S1_VERTEX_PITCH_MASK (0x3f<<16)
-
-#define TEXCOORDFMT_2D 0x0
-#define TEXCOORDFMT_3D 0x1
-#define TEXCOORDFMT_4D 0x2
-#define TEXCOORDFMT_1D 0x3
-#define TEXCOORDFMT_2D_16 0x4
-#define TEXCOORDFMT_4D_16 0x5
-#define TEXCOORDFMT_NOT_PRESENT 0xf
-#define S2_TEXCOORD_FMT0_MASK 0xf
-#define S2_TEXCOORD_FMT1_SHIFT 4
-#define S2_TEXCOORD_FMT(unit, type) ((type)<<(unit*4))
-#define S2_TEXCOORD_NONE (~0)
-
-/* S3 not interesting */
-
-#define S4_POINT_WIDTH_SHIFT 23
-#define S4_POINT_WIDTH_MASK (0x1ff<<23)
-#define S4_LINE_WIDTH_SHIFT 19
-#define S4_LINE_WIDTH_ONE (0x2<<19)
-#define S4_LINE_WIDTH_MASK (0xf<<19)
-#define S4_FLATSHADE_ALPHA (1<<18)
-#define S4_FLATSHADE_FOG (1<<17)
-#define S4_FLATSHADE_SPECULAR (1<<16)
-#define S4_FLATSHADE_COLOR (1<<15)
-#define S4_CULLMODE_BOTH (0<<13)
-#define S4_CULLMODE_NONE (1<<13)
-#define S4_CULLMODE_CW (2<<13)
-#define S4_CULLMODE_CCW (3<<13)
-#define S4_CULLMODE_MASK (3<<13)
-#define S4_VFMT_POINT_WIDTH (1<<12)
-#define S4_VFMT_SPEC_FOG (1<<11)
-#define S4_VFMT_COLOR (1<<10)
-#define S4_VFMT_DEPTH_OFFSET (1<<9)
-#define S4_VFMT_XYZ (1<<6)
-#define S4_VFMT_XYZW (2<<6)
-#define S4_VFMT_XY (3<<6)
-#define S4_VFMT_XYW (4<<6)
-#define S4_VFMT_XYZW_MASK (7<<6)
-#define S4_FORCE_DEFAULT_DIFFUSE (1<<5)
-#define S4_FORCE_DEFAULT_SPECULAR (1<<4)
-#define S4_LOCAL_DEPTH_OFFSET_ENABLE (1<<3)
-#define S4_VFMT_FOG_PARAM (1<<2)
-#define S4_SPRITE_POINT_ENABLE (1<<1)
-#define S4_LINE_ANTIALIAS_ENABLE (1<<0)
-
-#define S4_VFMT_MASK (S4_VFMT_POINT_WIDTH | \
- S4_VFMT_SPEC_FOG | \
- S4_VFMT_COLOR | \
- S4_VFMT_DEPTH_OFFSET | \
- S4_VFMT_XYZW_MASK | \
- S4_VFMT_FOG_PARAM)
-
-
-#define S5_WRITEDISABLE_ALPHA (1<<31)
-#define S5_WRITEDISABLE_RED (1<<30)
-#define S5_WRITEDISABLE_GREEN (1<<29)
-#define S5_WRITEDISABLE_BLUE (1<<28)
-#define S5_WRITEDISABLE_MASK (0xf<<28)
-#define S5_FORCE_DEFAULT_POINT_SIZE (1<<27)
-#define S5_LAST_PIXEL_ENABLE (1<<26)
-#define S5_GLOBAL_DEPTH_OFFSET_ENABLE (1<<25)
-#define S5_FOG_ENABLE (1<<24)
-#define S5_STENCIL_REF_SHIFT 16
-#define S5_STENCIL_REF_MASK (0xff<<16)
-#define S5_STENCIL_TEST_FUNC_SHIFT 13
-#define S5_STENCIL_TEST_FUNC_MASK (0x7<<13)
-#define S5_STENCIL_FAIL_SHIFT 10
-#define S5_STENCIL_FAIL_MASK (0x7<<10)
-#define S5_STENCIL_PASS_Z_FAIL_SHIFT 7
-#define S5_STENCIL_PASS_Z_FAIL_MASK (0x7<<7)
-#define S5_STENCIL_PASS_Z_PASS_SHIFT 4
-#define S5_STENCIL_PASS_Z_PASS_MASK (0x7<<4)
-#define S5_STENCIL_WRITE_ENABLE (1<<3)
-#define S5_STENCIL_TEST_ENABLE (1<<2)
-#define S5_COLOR_DITHER_ENABLE (1<<1)
-#define S5_LOGICOP_ENABLE (1<<0)
-
-
-#define S6_ALPHA_TEST_ENABLE (1<<31)
-#define S6_ALPHA_TEST_FUNC_SHIFT 28
-#define S6_ALPHA_TEST_FUNC_MASK (0x7<<28)
-#define S6_ALPHA_REF_SHIFT 20
-#define S6_ALPHA_REF_MASK (0xff<<20)
-#define S6_DEPTH_TEST_ENABLE (1<<19)
-#define S6_DEPTH_TEST_FUNC_SHIFT 16
-#define S6_DEPTH_TEST_FUNC_MASK (0x7<<16)
-#define S6_CBUF_BLEND_ENABLE (1<<15)
-#define S6_CBUF_BLEND_FUNC_SHIFT 12
-#define S6_CBUF_BLEND_FUNC_MASK (0x7<<12)
-#define S6_CBUF_SRC_BLEND_FACT_SHIFT 8
-#define S6_CBUF_SRC_BLEND_FACT_MASK (0xf<<8)
-#define S6_CBUF_DST_BLEND_FACT_SHIFT 4
-#define S6_CBUF_DST_BLEND_FACT_MASK (0xf<<4)
-#define S6_DEPTH_WRITE_ENABLE (1<<3)
-#define S6_COLOR_WRITE_ENABLE (1<<2)
-#define S6_TRISTRIP_PV_SHIFT 0
-#define S6_TRISTRIP_PV_MASK (0x3<<0)
-
-#define S7_DEPTH_OFFSET_CONST_MASK ~0
-
-
/* Helper macros for blend factors
*/
#define DST_BLND_FACT(f) ((f)<batch, get_state_size(state) + 8,
+ intel_batchbuffer_require_space(intel->batch,
+ get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
LOOP_CLIPRECTS);
count = 0;
again:
@@ -587,6 +589,8 @@ i915_new_batch(struct intel_context *intel)
* difficulties associated with them (physical address requirements).
*/
i915->state.emitted = 0;
+ /* Signal that we should put new vertices into a new vertex buffer. */
+ intel->prim.needs_new_vb = GL_TRUE;
/* Check that we didn't just wrap our batchbuffer at a bad time. */
assert(!intel->no_batch_wrap);
diff --git a/src/mesa/drivers/dri/i915/intel_render.c b/src/mesa/drivers/dri/i915/intel_render.c
index 5e6500cfa1..838d450378 100644
--- a/src/mesa/drivers/dri/i915/intel_render.c
+++ b/src/mesa/drivers/dri/i915/intel_render.c
@@ -67,7 +67,7 @@
#define HAVE_ELTS 0
-static GLuint hw_prim[GL_POLYGON + 1] = {
+static uint32_t hw_prim[GL_POLYGON + 1] = {
0,
PRIM3D_LINELIST,
PRIM3D_LINESTRIP,
@@ -114,7 +114,7 @@ intelDmaPrimitive(struct intel_context *intel, GLenum prim)
fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr(prim));
INTEL_FIREVERTICES(intel);
intel->vtbl.reduced_primitive_state(intel, reduced_prim[prim]);
- intelStartInlinePrimitive(intel, hw_prim[prim], LOOP_CLIPRECTS);
+ intel_set_prim(intel, hw_prim[prim]);
}
@@ -126,12 +126,11 @@ do { \
#define FLUSH() INTEL_FIREVERTICES(intel)
-#define GET_SUBSEQUENT_VB_MAX_VERTS() \
- ((intel->batch->size - 1500) / (intel->vertex_size*4))
-#define GET_CURRENT_VB_MAX_VERTS() GET_SUBSEQUENT_VB_MAX_VERTS()
+#define GET_SUBSEQUENT_VB_MAX_VERTS() (INTEL_VB_SIZE / (intel->vertex_size * 4))
+#define GET_CURRENT_VB_MAX_VERTS() \
+ ((INTEL_VB_SIZE - intel->prim.current_offset) / (intel->vertex_size * 4))
-#define ALLOC_VERTS( nr ) \
- intelExtendInlinePrimitive( intel, (nr) * intel->vertex_size )
+#define ALLOC_VERTS(nr) intel_get_prim_space(intel, nr)
#define EMIT_VERTS( ctx, j, nr, buf ) \
_tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf )
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c
index bbb4e0f3cd..a1121925cb 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -25,6 +25,12 @@
*
**************************************************************************/
+/** @file intel_tris.c
+ *
+ * This file contains functions for managing the vertex buffer and emitting
+ * primitives into it.
+ */
+
#include "glheader.h"
#include "context.h"
#include "macros.h"
@@ -47,111 +53,159 @@
#include "intel_reg.h"
#include "intel_span.h"
#include "intel_tex.h"
+#include "intel_chipset.h"
+#include "i830_context.h"
+#include "i830_reg.h"
static void intelRenderPrimitive(GLcontext * ctx, GLenum prim);
static void intelRasterPrimitive(GLcontext * ctx, GLenum rprim,
GLuint hwprim);
-/*
- */
-static void
-intel_flush_inline_primitive(struct intel_context *intel)
+/** Sets the primitive type for a primitive sequence, flushing as needed. */
+void intel_set_prim(struct intel_context *intel, uint32_t prim)
{
- GLuint used = intel->batch->ptr - intel->prim.start_ptr;
+ if (prim != intel->prim.primitive) {
+ INTEL_FIREVERTICES(intel);
+ intel->prim.primitive = prim;
+ }
+}
- assert(intel->prim.primitive != ~0);
+/** Returns mapped VB space for the given number of vertices */
+uint32_t *intel_get_prim_space(struct intel_context *intel, unsigned int count)
+{
+ uint32_t *addr;
+
+ /* Check for space in the existing VB */
+ if (intel->prim.vb_bo == NULL ||
+ intel->prim.needs_new_vb ||
+ (intel->prim.current_offset +
+ count * intel->vertex_size * 4) > INTEL_VB_SIZE ||
+ (intel->prim.count + count) >= (1 << 16)) {
+ /* Flush existing prim if any */
+ INTEL_FIREVERTICES(intel);
-/* _mesa_printf("/\n"); */
+ /* Start a new VB */
+ dri_bo_unreference(intel->prim.vb_bo);
+ intel->prim.vb_bo = dri_bo_alloc(intel->bufmgr, "vb",
+ INTEL_VB_SIZE, 4);
+ intel->prim.start_offset = 0;
+ intel->prim.current_offset = 0;
- if (used < 8)
- goto do_discard;
+ dri_bufmgr_check_aperture_space(intel->prim.vb_bo);
- *(int *) intel->prim.start_ptr = (_3DPRIMITIVE |
- intel->prim.primitive | (used / 4 - 2));
+ intel->prim.needs_new_vb = GL_FALSE;
- goto finished;
+ dri_bo_map(intel->prim.vb_bo, GL_TRUE);
+ }
- do_discard:
- intel->batch->ptr -= used;
+ intel->prim.flush = intel_flush_prim;
- finished:
- intel->prim.primitive = ~0;
- intel->prim.start_ptr = 0;
- intel->prim.flush = 0;
-}
+ addr = (uint32_t *)((char *)intel->prim.vb_bo->virtual +
+ intel->prim.current_offset);
+ intel->prim.current_offset += intel->vertex_size * 4 * count;
+ intel->prim.count += count;
+ return addr;
+}
-/* Emit a primitive referencing vertices in a vertex buffer.
- */
-void
-intelStartInlinePrimitive(struct intel_context *intel,
- GLuint prim, GLuint batch_flags)
+/** Dispatches the accumulated primitive to the batchbuffer. */
+void intel_flush_prim(struct intel_context *intel)
{
BATCH_LOCALS;
+ /* Must be called after an intel_start_prim. */
+ assert(intel->prim.primitive != ~0);
+
+ if (intel->prim.count == 0)
+ return;
+
intel_wait_flips(intel);
+ dri_bo_unmap(intel->prim.vb_bo);
+
intel->vtbl.emit_state(intel);
+ /* Ensure that we don't start a new batch for the following emit, which
+ * depends on the state just emitted. emit_state should be making sure we
+ * have the space for this.
+ */
intel->no_batch_wrap = GL_TRUE;
-/* _mesa_printf("%s *", __progname); */
-
- /* Emit a slot which will be filled with the inline primitive
- * command later.
+ /* Check that we actually emitted the state into this batch, using the
+ * UPLOAD_CTX bit as the signal.
*/
- BEGIN_BATCH(2, batch_flags);
- OUT_BATCH(0);
-
assert((intel->batch->dirty_state & (1<<1)) == 0);
- intel->prim.start_ptr = intel->batch->ptr;
- intel->prim.primitive = prim;
- intel->prim.flush = intel_flush_inline_primitive;
+#if 0
+ printf("emitting %d..%d=%d vertices size %d\n", intel->prim.start_offset,
+ intel->prim.current_offset, intel->prim.count,
+ intel->vertex_size * 4);
+#endif
- OUT_BATCH(0);
- ADVANCE_BATCH();
+ if (IS_9XX(intel->intelScreen->deviceID)) {
+ BEGIN_BATCH(5, LOOP_CLIPRECTS);
+ OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
+ I1_LOAD_S(0) | I1_LOAD_S(1) | 1);
+ assert((intel->prim.start_offset & !S0_VB_OFFSET_MASK) == 0);
+ OUT_RELOC(intel->prim.vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
+ intel->prim.start_offset);
+ OUT_BATCH((intel->vertex_size << S1_VERTEX_WIDTH_SHIFT) |
+ (intel->vertex_size << S1_VERTEX_PITCH_SHIFT));
+
+ OUT_BATCH(_3DPRIMITIVE |
+ PRIM_INDIRECT |
+ PRIM_INDIRECT_SEQUENTIAL |
+ intel->prim.primitive |
+ intel->prim.count);
+ OUT_BATCH(0); /* Beginning vertex index */
+ ADVANCE_BATCH();
+ } else {
+ struct i830_context *i830 = i830_context(&intel->ctx);
+
+ BEGIN_BATCH(5, LOOP_CLIPRECTS);
+ OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
+ I1_LOAD_S(0) | I1_LOAD_S(2) | 1);
+ /* S0 */
+ assert((intel->prim.start_offset & !S0_VB_OFFSET_MASK_830) == 0);
+ OUT_RELOC(intel->prim.vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
+ intel->prim.start_offset |
+ (intel->vertex_size << S0_VB_PITCH_SHIFT_830) |
+ S0_VB_ENABLE_830);
+ /* S1
+ * This is somewhat unfortunate -- VB width is tied up with
+ * vertex format data that we've already uploaded through
+ * _3DSTATE_VFT[01]_CMD. We may want to replace emits of VFT state with
+ * STATE_IMMEDIATE_1 like this to avoid duplication.
+ */
+ OUT_BATCH((i830->state.Ctx[I830_CTXREG_VF] & VFT0_TEX_COUNT_MASK) >>
+ VFT0_TEX_COUNT_SHIFT << S2_TEX_COUNT_SHIFT_830 |
+ (i830->state.Ctx[I830_CTXREG_VF2] << 16) |
+ intel->vertex_size << S2_VERTEX_0_WIDTH_SHIFT_830);
+
+ OUT_BATCH(_3DPRIMITIVE |
+ PRIM_INDIRECT |
+ PRIM_INDIRECT_SEQUENTIAL |
+ intel->prim.primitive |
+ intel->prim.count);
+ OUT_BATCH(0); /* Beginning vertex index */
+ ADVANCE_BATCH();
+ }
intel->no_batch_wrap = GL_FALSE;
-/* _mesa_printf(">"); */
-}
-
-
-void
-intelWrapInlinePrimitive(struct intel_context *intel)
-{
- GLuint prim = intel->prim.primitive;
- enum cliprect_mode cliprect_mode = intel->batch->cliprect_mode;
-
- intel_flush_inline_primitive(intel);
- intel_batchbuffer_flush(intel->batch);
- intelStartInlinePrimitive(intel, prim, cliprect_mode); /* ??? */
-}
-
-GLuint *
-intelExtendInlinePrimitive(struct intel_context *intel, GLuint dwords)
-{
- GLuint sz = dwords * sizeof(GLuint);
- GLuint *ptr;
-
- assert(intel->prim.flush == intel_flush_inline_primitive);
-
- if (intel_batchbuffer_space(intel->batch) < sz)
- intelWrapInlinePrimitive(intel);
-
-/* _mesa_printf("."); */
-
- intel->vtbl.assert_not_dirty(intel);
-
- ptr = (GLuint *) intel->batch->ptr;
- intel->batch->ptr += sz;
-
- return ptr;
+ /* If we're going to keep using this VB for more primitives, map it
+ * again.
+ */
+ if (!intel->prim.needs_new_vb)
+ dri_bo_map(intel->prim.vb_bo, GL_TRUE);
+
+ intel->prim.flush = NULL;
+ intel->prim.start_offset = intel->prim.current_offset;
+ if (!IS_9XX(intel->intelScreen->deviceID))
+ intel->prim.start_offset = ALIGN(intel->prim.start_offset, 128);
+ intel->prim.count = 0;
}
-
-
/***********************************************************************
* Emit primitives as inline vertices *
***********************************************************************/
@@ -182,7 +236,7 @@ intel_draw_quad(struct intel_context *intel,
intelVertexPtr v1, intelVertexPtr v2, intelVertexPtr v3)
{
GLuint vertsize = intel->vertex_size;
- GLuint *vb = intelExtendInlinePrimitive(intel, 6 * vertsize);
+ GLuint *vb = intel_get_prim_space(intel, 6);
int j;
COPY_DWORDS(j, vb, vertsize, v0);
@@ -210,7 +264,7 @@ intel_draw_triangle(struct intel_context *intel,
intelVertexPtr v0, intelVertexPtr v1, intelVertexPtr v2)
{
GLuint vertsize = intel->vertex_size;
- GLuint *vb = intelExtendInlinePrimitive(intel, 3 * vertsize);
+ GLuint *vb = intel_get_prim_space(intel, 3);
int j;
COPY_DWORDS(j, vb, vertsize, v0);
@@ -224,7 +278,7 @@ intel_draw_line(struct intel_context *intel,
intelVertexPtr v0, intelVertexPtr v1)
{
GLuint vertsize = intel->vertex_size;
- GLuint *vb = intelExtendInlinePrimitive(intel, 2 * vertsize);
+ GLuint *vb = intel_get_prim_space(intel, 2);
int j;
COPY_DWORDS(j, vb, vertsize, v0);
@@ -236,7 +290,7 @@ static void
intel_draw_point(struct intel_context *intel, intelVertexPtr v0)
{
GLuint vertsize = intel->vertex_size;
- GLuint *vb = intelExtendInlinePrimitive(intel, vertsize);
+ GLuint *vb = intel_get_prim_space(intel, 1);
int j;
/* Adjust for sub pixel position -- still required for conform. */
@@ -745,7 +799,7 @@ intelFastRenderClippedPoly(GLcontext * ctx, const GLuint * elts, GLuint n)
{
struct intel_context *intel = intel_context(ctx);
const GLuint vertsize = intel->vertex_size;
- GLuint *vb = intelExtendInlinePrimitive(intel, (n - 2) * 3 * vertsize);
+ GLuint *vb = intel_get_prim_space(intel, (n - 2) * 3);
GLubyte *vertptr = (GLubyte *) intel->verts;
const GLuint *start = (const GLuint *) V(elts[0]);
int i, j;
@@ -950,7 +1004,7 @@ intelRasterPrimitive(GLcontext * ctx, GLenum rprim, GLuint hwprim)
if (hwprim != intel->prim.primitive) {
INTEL_FIREVERTICES(intel);
- intelStartInlinePrimitive(intel, hwprim, LOOP_CLIPRECTS);
+ intel_set_prim(intel, hwprim);
}
}
@@ -1083,15 +1137,18 @@ intel_meta_draw_poly(struct intel_context *intel,
union fi *vb;
GLint i;
GLboolean was_locked = intel->locked;
+ unsigned int saved_vertex_size = intel->vertex_size;
if (!was_locked)
LOCK_HARDWARE(intel);
+ intel->vertex_size = 6;
+
/* All 3d primitives should be emitted with LOOP_CLIPRECTS,
* otherwise the drawing origin (DR4) might not be set correctly.
*/
- intelStartInlinePrimitive(intel, PRIM3D_TRIFAN, LOOP_CLIPRECTS);
- vb = (union fi *) intelExtendInlinePrimitive(intel, n * 6);
+ intel_set_prim(intel, PRIM3D_TRIFAN);
+ vb = (union fi *) intel_get_prim_space(intel, n);
for (i = 0; i < n; i++) {
vb[0].f = xy[i][0];
@@ -1105,6 +1162,8 @@ intel_meta_draw_poly(struct intel_context *intel,
INTEL_FIREVERTICES(intel);
+ intel->vertex_size = saved_vertex_size;
+
if (!was_locked)
UNLOCK_HARDWARE(intel);
}
diff --git a/src/mesa/drivers/dri/i915/intel_tris.h b/src/mesa/drivers/dri/i915/intel_tris.h
index 021e5c6450..6b38cd6fbd 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.h
+++ b/src/mesa/drivers/dri/i915/intel_tris.h
@@ -30,7 +30,9 @@
#include "mtypes.h"
-
+#define INTEL_VB_SIZE (8 * 1024)
+/** 3 dwords of state_immediate and 2 of 3dprim, in intel_flush_prim */
+#define INTEL_PRIM_EMIT_SIZE (5 * 4)
#define _INTEL_NEW_RENDERSTATE (_DD_NEW_LINE_STIPPLE | \
_DD_NEW_TRI_UNFILLED | \
@@ -44,11 +46,8 @@ extern void intelInitTriFuncs(GLcontext * ctx);
extern void intelChooseRenderState(GLcontext * ctx);
-extern void intelStartInlinePrimitive(struct intel_context *intel,
- GLuint prim, GLuint flags);
-extern void intelWrapInlinePrimitive(struct intel_context *intel);
-
-GLuint *intelExtendInlinePrimitive(struct intel_context *intel,
- GLuint dwords);
+void intel_set_prim(struct intel_context *intel, uint32_t prim);
+GLuint *intel_get_prim_space(struct intel_context *intel, unsigned int count);
+void intel_flush_prim(struct intel_context *intel);
#endif
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 579883437f..1aa9c3d711 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -182,9 +182,19 @@ struct intel_context
struct
{
GLuint id;
- GLuint primitive;
- GLubyte *start_ptr;
+ uint32_t primitive; /**< Current hardware primitive type */
void (*flush) (struct intel_context *);
+ dri_bo *vb_bo;
+ unsigned int start_offset; /**< Byte offset of primitive sequence */
+ unsigned int current_offset; /**< Byte offset of next vertex */
+ unsigned int count; /**< Number of vertices in current primitive */
+ /**
+ * Signals when a new VB should be started, regardless of remaining
+ * space.
+ *
+ * Used to avoid rewriting a VB that's being rendered from.
+ */
+ GLboolean needs_new_vb;
} prim;
GLuint stats_wm;
diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h
index c12ccf4ae1..96af7e1a03 100644
--- a/src/mesa/drivers/dri/intel/intel_reg.h
+++ b/src/mesa/drivers/dri/intel/intel_reg.h
@@ -40,6 +40,131 @@
#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
+/* p189 */
+#define _3DSTATE_LOAD_STATE_IMMEDIATE_1 (CMD_3D | (0x1d<<24) | (0x04<<16))
+#define I1_LOAD_S(n) (1<<(4+n))
+
+/** @{
+ * 915 definitions
+ */
+#define S0_VB_OFFSET_MASK 0xffffffc
+#define S0_AUTO_CACHE_INV_DISABLE (1<<0)
+/** @} */
+
+/** @{
+ * 830 definitions
+ */
+#define S0_VB_OFFSET_MASK_830 0xffffff8
+#define S0_VB_PITCH_SHIFT_830 1
+#define S0_VB_ENABLE_830 0
+/** @} */
+
+#define S1_VERTEX_WIDTH_SHIFT 24
+#define S1_VERTEX_WIDTH_MASK (0x3f<<24)
+#define S1_VERTEX_PITCH_SHIFT 16
+#define S1_VERTEX_PITCH_MASK (0x3f<<16)
+
+#define TEXCOORDFMT_2D 0x0
+#define TEXCOORDFMT_3D 0x1
+#define TEXCOORDFMT_4D 0x2
+#define TEXCOORDFMT_1D 0x3
+#define TEXCOORDFMT_2D_16 0x4
+#define TEXCOORDFMT_4D_16 0x5
+#define TEXCOORDFMT_NOT_PRESENT 0xf
+#define S2_TEXCOORD_FMT0_MASK 0xf
+#define S2_TEXCOORD_FMT1_SHIFT 4
+#define S2_TEXCOORD_FMT(unit, type) ((type)<<(unit*4))
+#define S2_TEXCOORD_NONE (~0)
+#define S2_TEX_COUNT_SHIFT_830 12
+#define S2_VERTEX_0_WIDTH_SHIFT_830 0
+#define S2_VERTEX_1_WIDTH_SHIFT_830 6
+/* S3 not interesting */
+
+#define S4_POINT_WIDTH_SHIFT 23
+#define S4_POINT_WIDTH_MASK (0x1ff<<23)
+#define S4_LINE_WIDTH_SHIFT 19
+#define S4_LINE_WIDTH_ONE (0x2<<19)
+#define S4_LINE_WIDTH_MASK (0xf<<19)
+#define S4_FLATSHADE_ALPHA (1<<18)
+#define S4_FLATSHADE_FOG (1<<17)
+#define S4_FLATSHADE_SPECULAR (1<<16)
+#define S4_FLATSHADE_COLOR (1<<15)
+#define S4_CULLMODE_BOTH (0<<13)
+#define S4_CULLMODE_NONE (1<<13)
+#define S4_CULLMODE_CW (2<<13)
+#define S4_CULLMODE_CCW (3<<13)
+#define S4_CULLMODE_MASK (3<<13)
+#define S4_VFMT_POINT_WIDTH (1<<12)
+#define S4_VFMT_SPEC_FOG (1<<11)
+#define S4_VFMT_COLOR (1<<10)
+#define S4_VFMT_DEPTH_OFFSET (1<<9)
+#define S4_VFMT_XYZ (1<<6)
+#define S4_VFMT_XYZW (2<<6)
+#define S4_VFMT_XY (3<<6)
+#define S4_VFMT_XYW (4<<6)
+#define S4_VFMT_XYZW_MASK (7<<6)
+#define S4_FORCE_DEFAULT_DIFFUSE (1<<5)
+#define S4_FORCE_DEFAULT_SPECULAR (1<<4)
+#define S4_LOCAL_DEPTH_OFFSET_ENABLE (1<<3)
+#define S4_VFMT_FOG_PARAM (1<<2)
+#define S4_SPRITE_POINT_ENABLE (1<<1)
+#define S4_LINE_ANTIALIAS_ENABLE (1<<0)
+
+#define S4_VFMT_MASK (S4_VFMT_POINT_WIDTH | \
+ S4_VFMT_SPEC_FOG | \
+ S4_VFMT_COLOR | \
+ S4_VFMT_DEPTH_OFFSET | \
+ S4_VFMT_XYZW_MASK | \
+ S4_VFMT_FOG_PARAM)
+
+
+#define S5_WRITEDISABLE_ALPHA (1<<31)
+#define S5_WRITEDISABLE_RED (1<<30)
+#define S5_WRITEDISABLE_GREEN (1<<29)
+#define S5_WRITEDISABLE_BLUE (1<<28)
+#define S5_WRITEDISABLE_MASK (0xf<<28)
+#define S5_FORCE_DEFAULT_POINT_SIZE (1<<27)
+#define S5_LAST_PIXEL_ENABLE (1<<26)
+#define S5_GLOBAL_DEPTH_OFFSET_ENABLE (1<<25)
+#define S5_FOG_ENABLE (1<<24)
+#define S5_STENCIL_REF_SHIFT 16
+#define S5_STENCIL_REF_MASK (0xff<<16)
+#define S5_STENCIL_TEST_FUNC_SHIFT 13
+#define S5_STENCIL_TEST_FUNC_MASK (0x7<<13)
+#define S5_STENCIL_FAIL_SHIFT 10
+#define S5_STENCIL_FAIL_MASK (0x7<<10)
+#define S5_STENCIL_PASS_Z_FAIL_SHIFT 7
+#define S5_STENCIL_PASS_Z_FAIL_MASK (0x7<<7)
+#define S5_STENCIL_PASS_Z_PASS_SHIFT 4
+#define S5_STENCIL_PASS_Z_PASS_MASK (0x7<<4)
+#define S5_STENCIL_WRITE_ENABLE (1<<3)
+#define S5_STENCIL_TEST_ENABLE (1<<2)
+#define S5_COLOR_DITHER_ENABLE (1<<1)
+#define S5_LOGICOP_ENABLE (1<<0)
+
+
+#define S6_ALPHA_TEST_ENABLE (1<<31)
+#define S6_ALPHA_TEST_FUNC_SHIFT 28
+#define S6_ALPHA_TEST_FUNC_MASK (0x7<<28)
+#define S6_ALPHA_REF_SHIFT 20
+#define S6_ALPHA_REF_MASK (0xff<<20)
+#define S6_DEPTH_TEST_ENABLE (1<<19)
+#define S6_DEPTH_TEST_FUNC_SHIFT 16
+#define S6_DEPTH_TEST_FUNC_MASK (0x7<<16)
+#define S6_CBUF_BLEND_ENABLE (1<<15)
+#define S6_CBUF_BLEND_FUNC_SHIFT 12
+#define S6_CBUF_BLEND_FUNC_MASK (0x7<<12)
+#define S6_CBUF_SRC_BLEND_FACT_SHIFT 8
+#define S6_CBUF_SRC_BLEND_FACT_MASK (0xf<<8)
+#define S6_CBUF_DST_BLEND_FACT_SHIFT 4
+#define S6_CBUF_DST_BLEND_FACT_MASK (0xf<<4)
+#define S6_DEPTH_WRITE_ENABLE (1<<3)
+#define S6_COLOR_WRITE_ENABLE (1<<2)
+#define S6_TRISTRIP_PV_SHIFT 0
+#define S6_TRISTRIP_PV_MASK (0x3<<0)
+
+#define S7_DEPTH_OFFSET_CONST_MASK ~0
+
/* Primitive dispatch on 830-945 */
#define _3DPRIMITIVE (CMD_3D | (0x1f << 24))
#define PRIM_INDIRECT (1<<23)
--
cgit v1.2.3
From a42dac187973cbc17be6c59db89264cbc935ab91 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Mon, 23 Jun 2008 15:44:10 -0700
Subject: i915: Accumulate the VB into a local buffer and subdata it in.
This lets GEM use pwrite, for an additional 4% or so speedup.
---
src/mesa/drivers/dri/i915/i830_vtbl.c | 4 +-
src/mesa/drivers/dri/i915/i915_vtbl.c | 3 +-
src/mesa/drivers/dri/i915/intel_tris.c | 56 +++++++++++++++++---------
src/mesa/drivers/dri/i915/intel_tris.h | 3 +-
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 3 ++
src/mesa/drivers/dri/intel/intel_context.c | 1 +
src/mesa/drivers/dri/intel/intel_context.h | 9 +----
7 files changed, 48 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 4d3ad0083a..0af5ed0b50 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -677,9 +677,6 @@ i830_new_batch(struct intel_context *intel)
struct i830_context *i830 = i830_context(&intel->ctx);
i830->state.emitted = 0;
- /* Signal that we should put new vertices into a new vertex buffer. */
- intel->prim.needs_new_vb = GL_TRUE;
-
/* Check that we didn't just wrap our batchbuffer at a bad time. */
assert(!intel->no_batch_wrap);
}
@@ -722,4 +719,5 @@ i830InitVtbl(struct i830_context *i830)
i830->intel.vtbl.render_prevalidate = i830_render_prevalidate;
i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
i830->intel.vtbl.note_unlock = i830_note_unlock;
+ i830->intel.vtbl.finish_batch = intel_finish_vb;
}
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 23d63fb47a..27dfc2b890 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -589,8 +589,6 @@ i915_new_batch(struct intel_context *intel)
* difficulties associated with them (physical address requirements).
*/
i915->state.emitted = 0;
- /* Signal that we should put new vertices into a new vertex buffer. */
- intel->prim.needs_new_vb = GL_TRUE;
/* Check that we didn't just wrap our batchbuffer at a bad time. */
assert(!intel->no_batch_wrap);
@@ -633,4 +631,5 @@ i915InitVtbl(struct i915_context *i915)
i915->intel.vtbl.flush_cmd = i915_flush_cmd;
i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
i915->intel.vtbl.note_unlock = i915_note_unlock;
+ i915->intel.vtbl.finish_batch = intel_finish_vb;
}
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c
index a1121925cb..8714dd15f3 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -77,31 +77,28 @@ uint32_t *intel_get_prim_space(struct intel_context *intel, unsigned int count)
/* Check for space in the existing VB */
if (intel->prim.vb_bo == NULL ||
- intel->prim.needs_new_vb ||
(intel->prim.current_offset +
count * intel->vertex_size * 4) > INTEL_VB_SIZE ||
(intel->prim.count + count) >= (1 << 16)) {
/* Flush existing prim if any */
INTEL_FIREVERTICES(intel);
+ intel_finish_vb(intel);
+
/* Start a new VB */
- dri_bo_unreference(intel->prim.vb_bo);
+ if (intel->prim.vb == NULL)
+ intel->prim.vb = malloc(INTEL_VB_SIZE);
intel->prim.vb_bo = dri_bo_alloc(intel->bufmgr, "vb",
INTEL_VB_SIZE, 4);
intel->prim.start_offset = 0;
intel->prim.current_offset = 0;
dri_bufmgr_check_aperture_space(intel->prim.vb_bo);
-
- intel->prim.needs_new_vb = GL_FALSE;
-
- dri_bo_map(intel->prim.vb_bo, GL_TRUE);
}
intel->prim.flush = intel_flush_prim;
- addr = (uint32_t *)((char *)intel->prim.vb_bo->virtual +
- intel->prim.current_offset);
+ addr = (uint32_t *)(intel->prim.vb + intel->prim.current_offset);
intel->prim.current_offset += intel->vertex_size * 4 * count;
intel->prim.count += count;
@@ -112,6 +109,7 @@ uint32_t *intel_get_prim_space(struct intel_context *intel, unsigned int count)
void intel_flush_prim(struct intel_context *intel)
{
BATCH_LOCALS;
+ dri_bo *vb_bo;
/* Must be called after an intel_start_prim. */
assert(intel->prim.primitive != ~0);
@@ -119,9 +117,13 @@ void intel_flush_prim(struct intel_context *intel)
if (intel->prim.count == 0)
return;
- intel_wait_flips(intel);
+ /* Keep a reference on the BO as it may get finished as we start the
+ * batch emit.
+ */
+ vb_bo = intel->prim.vb_bo;
+ dri_bo_reference(vb_bo);
- dri_bo_unmap(intel->prim.vb_bo);
+ intel_wait_flips(intel);
intel->vtbl.emit_state(intel);
@@ -147,7 +149,7 @@ void intel_flush_prim(struct intel_context *intel)
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(0) | I1_LOAD_S(1) | 1);
assert((intel->prim.start_offset & !S0_VB_OFFSET_MASK) == 0);
- OUT_RELOC(intel->prim.vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
+ OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
intel->prim.start_offset);
OUT_BATCH((intel->vertex_size << S1_VERTEX_WIDTH_SHIFT) |
(intel->vertex_size << S1_VERTEX_PITCH_SHIFT));
@@ -167,7 +169,7 @@ void intel_flush_prim(struct intel_context *intel)
I1_LOAD_S(0) | I1_LOAD_S(2) | 1);
/* S0 */
assert((intel->prim.start_offset & !S0_VB_OFFSET_MASK_830) == 0);
- OUT_RELOC(intel->prim.vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
+ OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
intel->prim.start_offset |
(intel->vertex_size << S0_VB_PITCH_SHIFT_830) |
S0_VB_ENABLE_830);
@@ -193,17 +195,35 @@ void intel_flush_prim(struct intel_context *intel)
intel->no_batch_wrap = GL_FALSE;
- /* If we're going to keep using this VB for more primitives, map it
- * again.
- */
- if (!intel->prim.needs_new_vb)
- dri_bo_map(intel->prim.vb_bo, GL_TRUE);
-
intel->prim.flush = NULL;
intel->prim.start_offset = intel->prim.current_offset;
if (!IS_9XX(intel->intelScreen->deviceID))
intel->prim.start_offset = ALIGN(intel->prim.start_offset, 128);
intel->prim.count = 0;
+
+ dri_bo_unreference(vb_bo);
+}
+
+/**
+ * Uploads the locally-accumulated VB into the buffer object.
+ *
+ * This avoids us thrashing the cachelines in and out as the buffer gets
+ * filled, dispatched, then reused as the hardware completes rendering from it,
+ * and also lets us clflush less if we dispatch with a partially-filled VB.
+ *
+ * This is called normally from get_space when we're finishing a BO, but also
+ * at batch flush time so that we don't try accessing the contents of a
+ * just-dispatched buffer.
+ */
+void intel_finish_vb(struct intel_context *intel)
+{
+ if (intel->prim.vb_bo == NULL)
+ return;
+
+ dri_bo_subdata(intel->prim.vb_bo, 0, intel->prim.start_offset,
+ intel->prim.vb);
+ dri_bo_unreference(intel->prim.vb_bo);
+ intel->prim.vb_bo = NULL;
}
/***********************************************************************
diff --git a/src/mesa/drivers/dri/i915/intel_tris.h b/src/mesa/drivers/dri/i915/intel_tris.h
index 6b38cd6fbd..0e08986221 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.h
+++ b/src/mesa/drivers/dri/i915/intel_tris.h
@@ -30,7 +30,7 @@
#include "mtypes.h"
-#define INTEL_VB_SIZE (8 * 1024)
+#define INTEL_VB_SIZE (32 * 1024)
/** 3 dwords of state_immediate and 2 of 3dprim, in intel_flush_prim */
#define INTEL_PRIM_EMIT_SIZE (5 * 4)
@@ -49,5 +49,6 @@ extern void intelChooseRenderState(GLcontext * ctx);
void intel_set_prim(struct intel_context *intel, uint32_t prim);
GLuint *intel_get_prim_space(struct intel_context *intel, unsigned int count);
void intel_flush_prim(struct intel_context *intel);
+void intel_finish_vb(struct intel_context *intel);
#endif
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 019880581a..9ad9f6a6c0 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -250,6 +250,9 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file,
* avoid that in the first place. */
batch->ptr = batch->map;
+ if (intel->vtbl.finish_batch)
+ intel->vtbl.finish_batch(intel);
+
/* TODO: Just pass the relocation list and dma buffer up to the
* kernel.
*/
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index b9e1eae982..16ddbeea9e 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -727,6 +727,7 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv)
intel->Fallback = 0; /* don't call _swrast_Flush later */
intel_batchbuffer_free(intel->batch);
+ free(intel->prim.vb);
if (release_texture_heaps) {
/* This share group is about to go away, free our private
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 1aa9c3d711..c314b6e218 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -86,6 +86,7 @@ struct intel_context
{
void (*destroy) (struct intel_context * intel);
void (*emit_state) (struct intel_context * intel);
+ void (*finish_batch) (struct intel_context * intel);
void (*new_batch) (struct intel_context * intel);
void (*emit_invarient_state) (struct intel_context * intel);
void (*note_fence) (struct intel_context *intel, GLuint fence);
@@ -185,16 +186,10 @@ struct intel_context
uint32_t primitive; /**< Current hardware primitive type */
void (*flush) (struct intel_context *);
dri_bo *vb_bo;
+ uint8_t *vb;
unsigned int start_offset; /**< Byte offset of primitive sequence */
unsigned int current_offset; /**< Byte offset of next vertex */
unsigned int count; /**< Number of vertices in current primitive */
- /**
- * Signals when a new VB should be started, regardless of remaining
- * space.
- *
- * Used to avoid rewriting a VB that's being rendered from.
- */
- GLboolean needs_new_vb;
} prim;
GLuint stats_wm;
--
cgit v1.2.3
From 93f701bc3619864ac6f067d37212e96545a57e16 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Thu, 26 Jun 2008 13:45:31 -0700
Subject: intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or
nothing.
Most of these were to ensure that caches got synchronized between 2d (or meta)
rendering and later use of the target as a source, such as for texture
miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(),
which just drops an MI_FLUSH. Most of the remainder were to ensure that
REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped.
Those are now replaced by automatically flushing those when dropping the lock.
---
src/mesa/drivers/dri/i915/intel_pixel_read.c | 2 -
src/mesa/drivers/dri/i965/brw_defines.h | 63 -----------------------
src/mesa/drivers/dri/intel/intel_batchbuffer.h | 8 +++
src/mesa/drivers/dri/intel/intel_blit.c | 25 ++++-----
src/mesa/drivers/dri/intel/intel_buffer_objects.c | 1 +
src/mesa/drivers/dri/intel/intel_context.c | 3 +-
src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 5 +-
src/mesa/drivers/dri/intel/intel_pixel_copy.c | 6 +--
src/mesa/drivers/dri/intel/intel_pixel_draw.c | 3 +-
src/mesa/drivers/dri/intel/intel_regions.c | 4 --
src/mesa/drivers/dri/intel/intel_tex_copy.c | 2 -
src/mesa/drivers/dri/intel/intel_tex_image.c | 2 -
src/mesa/drivers/dri/intel/intel_tex_validate.c | 14 -----
13 files changed, 26 insertions(+), 112 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/intel_pixel_read.c b/src/mesa/drivers/dri/i915/intel_pixel_read.c
index 0b95421a25..72e1f9ed28 100644
--- a/src/mesa/drivers/dri/i915/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i915/intel_pixel_read.c
@@ -272,8 +272,6 @@ do_blit_readpixels(GLcontext * ctx,
rect.x2 - rect.x1, rect.y2 - rect.y1,
GL_COPY);
}
-
- intel_batchbuffer_flush(intel->batch);
}
UNLOCK_HARDWARE(intel);
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 0fb531b1ee..2ed417824d 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -33,68 +33,6 @@
#ifndef BRW_DEFINES_H
#define BRW_DEFINES_H
-/*
- */
-#define MI_NOOP 0x00
-#define MI_USER_INTERRUPT 0x02
-#define MI_WAIT_FOR_EVENT 0x03
-#define MI_REPORT_HEAD 0x07
-#define MI_ARB_ON_OFF 0x08
-#define MI_BATCH_BUFFER_END 0x0A
-#define MI_OVERLAY_FLIP 0x11
-#define MI_LOAD_SCAN_LINES_INCL 0x12
-#define MI_LOAD_SCAN_LINES_EXCL 0x13
-#define MI_DISPLAY_BUFFER_INFO 0x14
-#define MI_SET_CONTEXT 0x18
-#define MI_STORE_DATA_IMM 0x20
-#define MI_STORE_DATA_INDEX 0x21
-#define MI_LOAD_REGISTER_IMM 0x22
-#define MI_STORE_REGISTER_MEM 0x24
-#define MI_BATCH_BUFFER_START 0x31
-
-#define MI_SYNCHRONOUS_FLIP 0x0
-#define MI_ASYNCHRONOUS_FLIP 0x1
-
-#define MI_BUFFER_SECURE 0x0
-#define MI_BUFFER_NONSECURE 0x1
-
-#define MI_ARBITRATE_AT_CHAIN_POINTS 0x0
-#define MI_ARBITRATE_BETWEEN_INSTS 0x1
-#define MI_NO_ARBITRATION 0x3
-
-#define MI_CONDITION_CODE_WAIT_DISABLED 0x0
-#define MI_CONDITION_CODE_WAIT_0 0x1
-#define MI_CONDITION_CODE_WAIT_1 0x2
-#define MI_CONDITION_CODE_WAIT_2 0x3
-#define MI_CONDITION_CODE_WAIT_3 0x4
-#define MI_CONDITION_CODE_WAIT_4 0x5
-
-#define MI_DISPLAY_PIPE_A 0x0
-#define MI_DISPLAY_PIPE_B 0x1
-
-#define MI_DISPLAY_PLANE_A 0x0
-#define MI_DISPLAY_PLANE_B 0x1
-#define MI_DISPLAY_PLANE_C 0x2
-
-#define MI_STANDARD_FLIP 0x0
-#define MI_ENQUEUE_FLIP_PERFORM_BASE_FRAME_NUMBER_LOAD 0x1
-#define MI_ENQUEUE_FLIP_TARGET_FRAME_NUMBER_RELATIVE 0x2
-#define MI_ENQUEUE_FLIP_ABSOLUTE_TARGET_FRAME_NUMBER 0x3
-
-#define MI_PHYSICAL_ADDRESS 0x0
-#define MI_VIRTUAL_ADDRESS 0x1
-
-#define MI_BUFFER_MEMORY_MAIN 0x0
-#define MI_BUFFER_MEMORY_GTT 0x2
-#define MI_BUFFER_MEMORY_PER_PROCESS_GTT 0x3
-
-#define MI_FLIP_CONTINUE 0x0
-#define MI_FLIP_ON 0x1
-#define MI_FLIP_OFF 0x2
-
-#define MI_UNTRUSTED_REGISTER_SPACE 0x0
-#define MI_TRUSTED_REGISTER_SPACE 0x1
-
/* 3D state:
*/
#define _3DOP_3DSTATE_PIPELINED 0x0
@@ -118,7 +56,6 @@
#define _3DSTATE_LINE_STIPPLE 0x08
#define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09
#define _3DCONTROL 0x00
-#define _3DPRIMITIVE 0x00
#define PIPE_CONTROL_NOWRITE 0x00
#define PIPE_CONTROL_WRITEIMMEDIATE 0x01
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
index d3c656c803..80b87b40f7 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
@@ -4,6 +4,7 @@
#include "mtypes.h"
#include "dri_bufmgr.h"
+#include "intel_reg.h"
struct intel_context;
@@ -144,4 +145,11 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
#define ADVANCE_BATCH() do { } while(0)
+static INLINE void
+intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
+{
+ intel_batchbuffer_require_space(batch, 4, IGNORE_CLIPRECTS);
+ intel_batchbuffer_emit_dword(batch, MI_FLUSH);
+}
+
#endif
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 80d11a01b7..84a455d1cb 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -159,14 +159,10 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
ADVANCE_BATCH();
}
- /* Emit a flush so that, on systems where we don't have automatic flushing
- * set (such as 965), the results all land on the screen in a timely
- * fashion.
+ /* Flush the rendering and the batch so that the results all land on the
+ * screen in a timely fashion.
*/
- BEGIN_BATCH(1, IGNORE_CLIPRECTS);
- OUT_BATCH(MI_FLUSH);
- ADVANCE_BATCH();
-
+ intel_batchbuffer_emit_mi_flush(intel->batch);
intel_batchbuffer_flush(intel->batch);
}
@@ -372,10 +368,7 @@ intelEmitCopyBlit(struct intel_context *intel,
src_offset + src_y * src_pitch);
ADVANCE_BATCH();
}
- BEGIN_BATCH(1, NO_LOOP_CLIPRECTS);
- OUT_BATCH(MI_FLUSH);
- ADVANCE_BATCH();
- intel_batchbuffer_flush(intel->batch);
+ intel_batchbuffer_emit_mi_flush(intel->batch);
}
@@ -556,7 +549,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
}
}
}
- intel_batchbuffer_flush(intel->batch);
+ intel_batchbuffer_emit_mi_flush(intel->batch);
}
UNLOCK_HARDWARE(intel);
@@ -594,7 +587,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
(8 * 4) +
(3 * 4) +
dwords,
- NO_LOOP_CLIPRECTS );
+ REFERENCES_CLIPRECTS );
opcode = XY_SETUP_BLT_CMD;
if (cpp == 4)
@@ -616,7 +609,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
if (dst_tiled)
blit_cmd |= XY_DST_TILED;
- BEGIN_BATCH(8 + 3, NO_LOOP_CLIPRECTS);
+ BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS);
OUT_BATCH(opcode);
OUT_BATCH(br13);
OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
@@ -636,5 +629,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
intel_batchbuffer_data( intel->batch,
src_bits,
dwords * 4,
- NO_LOOP_CLIPRECTS );
+ REFERENCES_CLIPRECTS );
+
+ intel_batchbuffer_emit_mi_flush(intel->batch);
}
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index 4227f0c973..1923a21516 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -32,6 +32,7 @@
#include "intel_context.h"
#include "intel_buffer_objects.h"
+#include "intel_batchbuffer.h"
#include "intel_regions.h"
#include "dri_bufmgr.h"
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 6d7d6811ac..46acf79721 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -1008,6 +1008,7 @@ void UNLOCK_HARDWARE( struct intel_context *intel )
* Nothing should be left in batch outside of LOCK/UNLOCK which references
* cliprects.
*/
- assert(intel->batch->cliprect_mode != REFERENCES_CLIPRECTS);
+ if (intel->batch->cliprect_mode == REFERENCES_CLIPRECTS)
+ intel_batchbuffer_flush(intel->batch);
}
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
index 81238acfe4..ce6c6d204f 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
@@ -43,7 +43,7 @@
#include "intel_buffer_objects.h"
#include "intel_buffers.h"
#include "intel_pixel.h"
-
+#include "intel_reg.h"
#define FILE_DEBUG_FLAG DEBUG_PIXEL
@@ -301,9 +301,8 @@ do_blit_bitmap( GLcontext *ctx,
}
}
}
- out:
- intel_batchbuffer_flush(intel->batch);
}
+out:
UNLOCK_HARDWARE(intel);
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_copy.c b/src/mesa/drivers/dri/intel/intel_pixel_copy.c
index 45f72bac52..eb4f10e9d5 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_copy.c
@@ -229,7 +229,7 @@ do_texture_copypixels(GLcontext * ctx,
out:
intel->vtbl.leave_meta_state(intel);
- intel_batchbuffer_flush(intel->batch);
+ intel_batchbuffer_emit_mi_flush(intel->batch);
}
UNLOCK_HARDWARE(intel);
@@ -345,10 +345,8 @@ do_blit_copypixels(GLcontext * ctx,
ctx->Color.ColorLogicOpEnabled ?
ctx->Color.LogicOp : GL_COPY);
}
-
- out:
- intel_batchbuffer_flush(intel->batch);
}
+out:
UNLOCK_HARDWARE(intel);
DBG("%s: success\n", __FUNCTION__);
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
index 569e992b5e..2b3445cb28 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
@@ -181,7 +181,7 @@ do_texture_drawpixels(GLcontext * ctx,
srcx, srcx + width, srcy + height, srcy);
out:
intel->vtbl.leave_meta_state(intel);
- intel_batchbuffer_flush(intel->batch);
+ intel_batchbuffer_emit_mi_flush(intel->batch);
}
UNLOCK_HARDWARE(intel);
return GL_TRUE;
@@ -322,7 +322,6 @@ do_blit_drawpixels(GLcontext * ctx,
ctx->Color.ColorLogicOpEnabled ?
ctx->Color.LogicOp : GL_COPY);
}
- intel_batchbuffer_flush(intel->batch);
}
UNLOCK_HARDWARE(intel);
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index c7e2c551dd..ddeffc8ae4 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -376,8 +376,6 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region)
/* Now blit from the texture buffer to the new buffer:
*/
- intel_batchbuffer_flush(intel->batch);
-
was_locked = intel->locked;
if (intel->locked)
LOCK_HARDWARE(intel);
@@ -390,8 +388,6 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region)
region->pitch, region->height,
GL_COPY);
- intel_batchbuffer_flush(intel->batch);
-
if (was_locked)
UNLOCK_HARDWARE(intel);
}
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index 1add7c6188..8a8eec83aa 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -151,8 +151,6 @@ do_copy_texsubimage(struct intel_context *intel,
intelImage->mt->region->tiled,
x, y + height, dstx, dsty, width, height,
GL_COPY); /* ? */
-
- intel_batchbuffer_flush(intel->batch);
}
}
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 95ddbd5920..6d57b2b7dd 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -235,8 +235,6 @@ try_pbo_upload(struct intel_context *intel,
dst_stride, dst_buffer, dst_offset, GL_FALSE,
0, 0, 0, 0, width, height,
GL_COPY);
-
- intel_batchbuffer_flush(intel->batch);
}
UNLOCK_HARDWARE(intel);
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index d260a721d9..b5803fb813 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -124,13 +124,10 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit)
struct intel_texture_object *intelObj = intel_texture_object(tObj);
int comp_byte = 0;
int cpp;
-
GLuint face, i;
GLuint nr_faces = 0;
struct intel_texture_image *firstImage;
- GLboolean need_flush = GL_FALSE;
-
/* We know/require this is true by now:
*/
assert(intelObj->base._Complete);
@@ -223,21 +220,10 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit)
*/
if (intelObj->mt != intelImage->mt) {
copy_image_data_to_tree(intel, intelObj, intelImage);
- need_flush = GL_TRUE;
}
}
}
-#ifdef I915
- /* XXX: what is this flush about?
- * On 965, it causes a batch flush in the middle of the state relocation
- * emits, which means that the eventual rendering doesn't have all of the
- * required relocations in place.
- */
- if (need_flush)
- intel_batchbuffer_flush(intel->batch);
-#endif
-
return GL_TRUE;
}
--
cgit v1.2.3
From f059a3302260075e9cfd35649dc3877726291d8d Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Thu, 26 Jun 2008 15:34:27 -0700
Subject: intel: Fix locking when doing intel_region_cow().
This was broken in the merge of 965 blit support. It tried to lock only
when things were already locked.
---
src/mesa/drivers/dri/intel/intel_regions.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index ddeffc8ae4..5d23c72504 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -377,7 +377,7 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region)
*/
was_locked = intel->locked;
- if (intel->locked)
+ if (!was_locked)
LOCK_HARDWARE(intel);
intelEmitCopyBlit(intel,
@@ -388,7 +388,7 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region)
region->pitch, region->height,
GL_COPY);
- if (was_locked)
+ if (!was_locked)
UNLOCK_HARDWARE(intel);
}
--
cgit v1.2.3
From e74f54793e45dd2e36474f6fc527456647f32efd Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Tue, 1 Jul 2008 15:09:24 -0700
Subject: intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add
new mode.
It turns out that it's not just deviceID dependent, and there's some additional
undefined factor that determines the bit 6 swizzling. It's now controllable
with swizzle_mode=[012] until we get a response on how to automatically detect.
---
src/mesa/drivers/dri/intel/intel_context.c | 3 ++
src/mesa/drivers/dri/intel/intel_context.h | 1 +
src/mesa/drivers/dri/intel/intel_screen.c | 9 +++++-
src/mesa/drivers/dri/intel/intel_span.c | 51 ++++++++++++++++++++----------
4 files changed, 46 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 46acf79721..33b8843e33 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -697,6 +697,9 @@ intelInitContext(struct intel_context *intel,
intel->no_rast = 1;
}
+ intel->tiling_swizzle_mode = driQueryOptioni(&intel->optionCache,
+ "swizzle_mode");
+
/* Disable all hardware rendering (skip emitting batches and fences/waits
* to the kernel)
*/
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index f1116d2747..6ed9a377e4 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -266,6 +266,7 @@ struct intel_context
GLuint lastStamp;
GLboolean no_hw;
+ int tiling_swizzle_mode;
/**
* Configuration cache
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 8fd503ee8b..6597dbffed 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -69,13 +69,20 @@ PUBLIC const char __driConfigOptions[] =
DRI_CONF_SECTION_QUALITY
DRI_CONF_FORCE_S3TC_ENABLE(false)
DRI_CONF_ALLOW_LARGE_TEXTURES(2)
+ DRI_CONF_OPT_BEGIN_V(swizzle_mode, enum, 0, "0:2")
+ DRI_CONF_DESC_BEGIN(en, "Tiling swizzle mode for software fallbacks")
+ DRI_CONF_ENUM(0, "No swizzling")
+ DRI_CONF_ENUM(1, "addr[6] = addr[6] ^ addr[9]")
+ DRI_CONF_ENUM(2, "addr[6] = addr[6] ^ addr[9] ^ addr[10]")
+ DRI_CONF_DESC_END
+ DRI_CONF_OPT_END
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
-const GLuint __driNConfigOptions = 6;
+const GLuint __driNConfigOptions = 7;
#ifdef USE_NEW_INTERFACE
static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index c6778b16ff..8d7d913ca9 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -106,29 +106,46 @@ static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
x_tile_off = xbyte & 0x1ff;
y_tile_off = y & 7;
-#ifndef I915
- /* The documentation says that X tile layout is arranged in 8 512-byte
- * lines of pixel data. However, that doesn't appear to be the case
- * on GM965, tested by drawing a 128x8 quad in no_rast mode. For lines
- * 1,2,4, and 7 of each tile, each consecutive pair of 64-byte spans
- * has the locations of those spans swapped.
+ x_tile_number = xbyte >> 9;
+ y_tile_number = y >> 3;
+
+ tile_off = (y_tile_off << 9) + x_tile_off;
+
+ /* bit swizzling tricks your parents never told you about:
+ *
+ * The specs say that the X tiling layout is just 8 512-byte rows
+ * packed into a page. It turns out that there's some additional
+ * swizzling of bit 6 to reduce cache aliasing issues. Experimental
+ * results below:
+ *
+ * line bit GM965 945G/Q965
+ * 9 10 11
+ * 0 0 0 0 0 0
+ * 1 0 1 0 1 1
+ * 2 1 0 0 1 1
+ * 3 1 1 0 0 0
+ * 4 0 0 1 1 0
+ * 5 0 1 1 0 1
+ * 6 1 0 1 0 1
+ * 7 1 1 1 1 0
+ *
+ * So we see that the GM965 is bit 6 ^ 9 ^ 10 ^ 11, while other
+ * parts were just 6 ^ 9 ^ 10. However, some systems, including a
+ * GM965 we've seen, don't perform the swizzling at all. Information
+ * on how to detect it through register reads is expected soon.
*/
- switch (y_tile_off) {
+ switch (intel->tiling_swizzle_mode) {
+ case 0:
+ break;
case 1:
+ tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
+ break;
case 2:
- case 4:
- case 7:
- x_tile_off ^= 64;
- break;
- default:
+ tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
+ ((tile_off >> 5) & 64);
break;
}
-#endif
-
- x_tile_number = xbyte >> 9;
- y_tile_number = y >> 3;
- tile_off = (y_tile_off << 9) + x_tile_off;
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
#if 0
--
cgit v1.2.3
From 19f585a3cf65887e249d630fe43e83e7e7618dfa Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 2 Jul 2008 09:10:21 -0700
Subject: intel-gem: Fix Y-tiling span setup.
The boolean that the server gives us for whether the region is tiled was
getting used as the enum for what tiling mode. Instead, guess the correct
tiling in screen setup.
Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is
32 scanlines, not 8.
---
src/mesa/drivers/dri/intel/intel_fbo.c | 13 ++++++++---
src/mesa/drivers/dri/intel/intel_fbo.h | 7 +++---
src/mesa/drivers/dri/intel/intel_screen.c | 39 ++++++++++++++++++++-----------
src/mesa/drivers/dri/intel/intel_screen.h | 6 +++++
src/mesa/drivers/dri/intel/intel_span.c | 7 +++---
src/mesa/drivers/dri/intel/intel_span.h | 7 ++----
6 files changed, 52 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index bc0b579429..3a3ce68c59 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -376,7 +376,8 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb,
* not a user-created renderbuffer.
*/
struct intel_renderbuffer *
-intel_create_renderbuffer(GLenum intFormat, int tiling)
+intel_create_renderbuffer(intelScreenPrivate *intelScreen,
+ GLenum intFormat, enum tiling_mode tiling)
{
GET_CURRENT_CONTEXT(ctx);
@@ -449,8 +450,14 @@ intel_create_renderbuffer(GLenum intFormat, int tiling)
irb->Base.Delete = intel_delete_renderbuffer;
irb->Base.AllocStorage = intel_alloc_window_storage;
irb->Base.GetPointer = intel_get_pointer;
- /* This sets the Get/PutRow/Value functions */
- intel_set_span_functions(&irb->Base, tiling);
+ /* This sets the Get/PutRow/Value functions. In classic mode, all access
+ * is through the aperture and will be swizzled by the fence registers, so
+ * we don't need the span functions to perfom tile swizzling
+ */
+ if (intelScreen->ttm)
+ intel_set_span_functions(&irb->Base, tiling);
+ else
+ intel_set_span_functions(&irb->Base, INTEL_TILE_NONE);
return irb;
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 9e085a1992..23af593960 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -28,9 +28,9 @@
#ifndef INTEL_FBO_H
#define INTEL_FBO_H
+#include "intel_screen.h"
struct intel_context;
-struct intel_region;
/**
* Intel framebuffer, derived from gl_framebuffer.
@@ -72,7 +72,7 @@ struct intel_renderbuffer
struct intel_region *region;
void *pfMap; /* possibly paged flipped map pointer */
GLuint pfPitch; /* possibly paged flipped pitch */
- int tiling;
+ enum tiling_mode tiling;
GLboolean RenderToTexture; /* RTT? */
GLuint PairedDepth; /**< only used if this is a depth renderbuffer */
@@ -91,7 +91,8 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *irb,
struct intel_region *region);
extern struct intel_renderbuffer *
-intel_create_renderbuffer(GLenum intFormat, int tiling);
+intel_create_renderbuffer(intelScreenPrivate *intelScreen,
+ GLenum intFormat, enum tiling_mode tiling);
extern void intel_fbo_init(struct intel_context *intel);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 6597dbffed..9e4f48fbd7 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -528,6 +528,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
GLboolean swStencil = (mesaVis->stencilBits > 0 &&
mesaVis->depthBits != 24);
GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
+ enum tiling_mode tiling;
struct intel_framebuffer *intel_fb = CALLOC_STRUCT(intel_framebuffer);
@@ -537,34 +538,46 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
_mesa_initialize_framebuffer(&intel_fb->Base, mesaVis);
/* setup the hardware-based renderbuffers */
+ /* We get only a boolean value from the DDX for whether tiling is
+ * enabled, so we have to guess when it's Y and not X (965 depth).
+ */
{
- intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat,
- screen->ttm ? screen->front.tiled : INTEL_TILE_NONE);
+ tiling = screen->front.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
+ intel_fb->color_rb[0] = intel_create_renderbuffer(screen,
+ rgbFormat, tiling);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT,
&intel_fb->color_rb[0]->Base);
}
if (mesaVis->doubleBufferMode) {
- intel_fb->color_rb[1] = intel_create_renderbuffer(rgbFormat,
- screen->ttm ? screen->back.tiled : INTEL_TILE_NONE);
+ tiling = screen->back.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
+ intel_fb->color_rb[1] = intel_create_renderbuffer(screen,
+ rgbFormat, tiling);
+
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT,
&intel_fb->color_rb[1]->Base);
if (screen->third.handle) {
struct gl_renderbuffer *tmp_rb = NULL;
-
- intel_fb->color_rb[2] = intel_create_renderbuffer(rgbFormat,
- screen->ttm ? screen->third.tiled : INTEL_TILE_NONE);
+ tiling = screen->third.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
+ intel_fb->color_rb[2] = intel_create_renderbuffer(screen,
+ rgbFormat,
+ tiling);
_mesa_reference_renderbuffer(&tmp_rb, &intel_fb->color_rb[2]->Base);
}
}
+#ifdef I915
+ tiling = screen->depth.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
+#else
+ tiling = screen->depth.tiled ? INTEL_TILE_Y : INTEL_TILE_NONE;
+#endif
if (mesaVis->depthBits == 24) {
if (mesaVis->stencilBits == 8) {
/* combined depth/stencil buffer */
struct intel_renderbuffer *depthStencilRb
- = intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT,
- screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
+ = intel_create_renderbuffer(screen,
+ GL_DEPTH24_STENCIL8_EXT, tiling);
/* note: bind RB to two attachment points */
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
&depthStencilRb->Base);
@@ -572,8 +585,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
&depthStencilRb->Base);
} else {
struct intel_renderbuffer *depthRb
- = intel_create_renderbuffer(GL_DEPTH_COMPONENT24,
- screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
+ = intel_create_renderbuffer(screen,
+ GL_DEPTH_COMPONENT24, tiling);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
&depthRb->Base);
}
@@ -581,8 +594,8 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
else if (mesaVis->depthBits == 16) {
/* just 16-bit depth buffer, no hw stencil */
struct intel_renderbuffer *depthRb
- = intel_create_renderbuffer(GL_DEPTH_COMPONENT16,
- screen->ttm ? screen->depth.tiled : INTEL_TILE_NONE);
+ = intel_create_renderbuffer(screen,
+ GL_DEPTH_COMPONENT16, tiling);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base);
}
diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h
index 9a73b13951..648bf61240 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.h
+++ b/src/mesa/drivers/dri/intel/intel_screen.h
@@ -33,6 +33,12 @@
#include "i915_drm.h"
#include "xmlconfig.h"
+enum tiling_mode {
+ INTEL_TILE_NONE,
+ INTEL_TILE_X,
+ INTEL_TILE_Y
+};
+
/* XXX: change name or eliminate to avoid conflict with "struct
* intel_region"!!!
*/
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 8d7d913ca9..6138b262f4 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -168,7 +168,7 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
int x_tile_number, y_tile_number;
int tile_off, tile_base;
- tile_stride = (irb->pfPitch * irb->region->cpp) << 3;
+ tile_stride = (irb->pfPitch * irb->region->cpp) << 5;
x += intel->drawX;
y += intel->drawY;
@@ -181,7 +181,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
x_tile_number = xbyte >> 7;
y_tile_number = y >> 5;
- tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) + (x_tile_off & 0xf);
+ tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
+ (x_tile_off & 0xf);
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
return buf + tile_base + tile_off;
@@ -670,7 +671,7 @@ intelInitSpanFuncs(GLcontext * ctx)
* These are used for the software fallbacks.
*/
void
-intel_set_span_functions(struct gl_renderbuffer *rb, int tiling)
+intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling)
{
if (rb->_ActualFormat == GL_RGB5) {
/* 565 RGB */
diff --git a/src/mesa/drivers/dri/intel/intel_span.h b/src/mesa/drivers/dri/intel/intel_span.h
index c56e5e1611..1b47c2829c 100644
--- a/src/mesa/drivers/dri/intel/intel_span.h
+++ b/src/mesa/drivers/dri/intel/intel_span.h
@@ -33,10 +33,7 @@ extern void intelInitSpanFuncs(GLcontext * ctx);
extern void intelSpanRenderFinish(GLcontext * ctx);
extern void intelSpanRenderStart(GLcontext * ctx);
-extern void intel_set_span_functions(struct gl_renderbuffer *rb, int tiling);
-
-#define INTEL_TILE_NONE 0
-#define INTEL_TILE_X 1
-#define INTEL_TILE_Y 2
+extern void intel_set_span_functions(struct gl_renderbuffer *rb,
+ enum tiling_mode tiling);
#endif
--
cgit v1.2.3
From 4b3ed4d2d16811a624857519e95303017f4160b5 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 2 Jul 2008 10:21:44 -0700
Subject: intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.
Apparently in Y mode we get bit 6 ^ bit 9. The reflect demo in 'd' mode now
displays correctly.
---
src/mesa/drivers/dri/intel/intel_span.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 6138b262f4..7b079afa73 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -183,6 +183,16 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
(x_tile_off & 0xf);
+
+ switch (intel->tiling_swizzle_mode) {
+ case 0:
+ break;
+ case 1:
+ tile_off ^= (tile_off >> 3) & 64;
+ break;
+ case 2:
+ break;
+ }
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
return buf + tile_base + tile_off;
--
cgit v1.2.3
From a995bdced20a55759dffd901c10ec5fb251191cf Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 2 Jul 2008 11:16:30 -0700
Subject: intel-gem: Emit an MI_FLUSH at glFlush() so frontbuffer rendering is
flushed.
We have something similar in the X Server that covers X Server rendering, this
is the equivalent here for rendering to the front buffer. If we cared about
avoiding this at glFlush time, we could only do this when some actual
frontbuffer rendering had occurred.
Bug #16392.
---
src/mesa/drivers/dri/intel/intel_context.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 33b8843e33..fa0b4c5618 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -365,6 +365,12 @@ intelFlush(GLcontext * ctx)
if (!IS_965(intel->intelScreen->deviceID))
INTEL_FIREVERTICES(intel);
+ /* Emit a flush so that any frontbuffer rendering that might have occurred
+ * lands onscreen in a timely manner, even if the X Server doesn't trigger
+ * a flush for us.
+ */
+ intel_batchbuffer_emit_mi_flush(intel->batch);
+
if (intel->batch->map != intel->batch->ptr)
intel_batchbuffer_flush(intel->batch);
}
--
cgit v1.2.3
From def6e4f420feed4a07402a8da84e7822f6ddba99 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 2 Jul 2008 11:49:10 -0700
Subject: intel: span rendering requires just a flush before starting, not
finish.
The dri_bo_map()s that follow will take care of idling the hardware as needed.
---
src/mesa/drivers/dri/intel/intel_span.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 7b079afa73..b1392f794e 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -612,7 +612,7 @@ intelSpanRenderStart(GLcontext * ctx)
struct intel_context *intel = intel_context(ctx);
GLuint i;
- intelFinish(&intel->ctx);
+ intelFlush(&intel->ctx);
LOCK_HARDWARE(intel);
#if 0
--
cgit v1.2.3
From 2e841880cfc1006a2818d4a8bfefd21136dc39a9 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 11 Jul 2008 14:16:36 -0700
Subject: drm-gem: Use new GEM ioctls for tiling state, and support new swizzle
modes.
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 37 ++++--
src/mesa/drivers/dri/intel/intel_blit.c | 24 ++--
src/mesa/drivers/dri/intel/intel_blit.h | 8 +-
src/mesa/drivers/dri/intel/intel_context.c | 3 -
src/mesa/drivers/dri/intel/intel_context.h | 1 -
src/mesa/drivers/dri/intel/intel_fbo.c | 21 +---
src/mesa/drivers/dri/intel/intel_fbo.h | 4 +-
src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 2 +-
src/mesa/drivers/dri/intel/intel_pixel_copy.c | 4 +-
src/mesa/drivers/dri/intel/intel_pixel_draw.c | 2 +-
src/mesa/drivers/dri/intel/intel_regions.c | 129 ++++++++++++++-----
src/mesa/drivers/dri/intel/intel_regions.h | 13 +-
src/mesa/drivers/dri/intel/intel_screen.c | 133 ++------------------
src/mesa/drivers/dri/intel/intel_screen.h | 6 -
src/mesa/drivers/dri/intel/intel_span.c | 154 ++++++++++++-----------
src/mesa/drivers/dri/intel/intel_span.h | 3 -
src/mesa/drivers/dri/intel/intel_tex_copy.c | 2 +-
18 files changed, 250 insertions(+), 298 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 9d925682c2..bd28235281 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -232,7 +232,7 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(((region->pitch * region->cpp) - 1) |
(format << 18) |
(BRW_TILEWALK_YMAJOR << 26) |
- (region->tiled << 27) |
+ ((region->tiling != I915_TILING_NONE) << 27) |
(BRW_SURFACE_2D << 29));
OUT_RELOC(region->buffer,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a7da5e643c..761a5df33f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -154,9 +154,28 @@ struct brw_wm_surface_key {
GLint first_level, last_level;
GLint width, height, depth;
GLint pitch, cpp;
- GLboolean tiled;
+ uint32_t tiling;
};
+static void
+brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
+{
+ switch (tiling) {
+ case I915_TILING_NONE:
+ surf->ss3.tiled_surface = 0;
+ surf->ss3.tile_walk = 0;
+ break;
+ case I915_TILING_X:
+ surf->ss3.tiled_surface = 1;
+ surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
+ break;
+ case I915_TILING_Y:
+ surf->ss3.tiled_surface = 1;
+ surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
+ break;
+ }
+}
+
static dri_bo *
brw_create_texture_surface( struct brw_context *brw,
struct brw_wm_surface_key *key )
@@ -179,9 +198,7 @@ brw_create_texture_surface( struct brw_context *brw,
surf.ss2.mip_count = key->last_level - key->first_level;
surf.ss2.width = key->width - 1;
surf.ss2.height = key->height - 1;
-
- surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
- surf.ss3.tiled_surface = key->tiled;
+ brw_set_surface_tiling(&surf, key->tiling);
surf.ss3.pitch = (key->pitch * key->cpp) - 1;
surf.ss3.depth = key->depth - 1;
@@ -234,7 +251,7 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit )
key.pitch = intelObj->mt->pitch;
key.cpp = intelObj->mt->cpp;
key.depth = firstImage->Depth;
- key.tiled = intelObj->mt->region->tiled;
+ key.tiling = intelObj->mt->region->tiling;
ret |= dri_bufmgr_check_aperture_space(key.bo);
@@ -267,7 +284,8 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
unsigned int surface_format;
unsigned int width, height, cpp;
GLubyte color_mask[4];
- GLboolean tiled, color_blend;
+ GLboolean color_blend;
+ uint32_t tiling;
} key;
memset(&key, 0, sizeof(key));
@@ -280,7 +298,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
else
key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
- key.tiled = region->tiled;
+ key.tiling = region->tiling;
key.width = region->pitch; /* XXX: not really! */
key.height = region->height;
key.cpp = region->cpp;
@@ -289,7 +307,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
} else {
key.surface_type = BRW_SURFACE_NULL;
key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
- key.tiled = 0;
+ key.tiling = 0;
key.width = 1;
key.height = 1;
key.cpp = 4;
@@ -319,8 +337,7 @@ brw_update_region_surface(struct brw_context *brw, struct intel_region *region,
surf.ss2.width = key.width - 1;
surf.ss2.height = key.height - 1;
- surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
- surf.ss3.tiled_surface = key.tiled;
+ brw_set_surface_tiling(&surf, key.tiling);
surf.ss3.pitch = (key.width * key.cpp) - 1;
/* _NEW_COLOR */
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 84a455d1cb..2a05d29124 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -106,11 +106,11 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
}
#ifndef I915
- if (src->tiled) {
+ if (src->tiling != I915_TILING_NONE) {
CMD |= XY_SRC_TILED;
src_pitch /= 4;
}
- if (dst->tiled) {
+ if (dst->tiling != I915_TILING_NONE) {
CMD |= XY_DST_TILED;
dst_pitch /= 4;
}
@@ -178,7 +178,7 @@ intelEmitFillBlit(struct intel_context *intel,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
- GLboolean dst_tiled,
+ uint32_t dst_tiling,
GLshort x, GLshort y,
GLshort w, GLshort h,
GLuint color)
@@ -203,7 +203,7 @@ intelEmitFillBlit(struct intel_context *intel,
return;
}
#ifndef I915
- if (dst_tiled) {
+ if (dst_tiling != I915_TILING_NONE) {
CMD |= XY_DST_TILED;
dst_pitch /= 4;
}
@@ -259,11 +259,11 @@ intelEmitCopyBlit(struct intel_context *intel,
GLshort src_pitch,
dri_bo *src_buffer,
GLuint src_offset,
- GLboolean src_tiled,
+ uint32_t src_tiling,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
- GLboolean dst_tiled,
+ uint32_t dst_tiling,
GLshort src_x, GLshort src_y,
GLshort dst_x, GLshort dst_y,
GLshort w, GLshort h,
@@ -309,11 +309,11 @@ intelEmitCopyBlit(struct intel_context *intel,
}
#ifndef I915
- if (dst_tiled) {
+ if (dst_tiling != I915_TILING_NONE) {
CMD |= XY_DST_TILED;
dst_pitch /= 4;
}
- if (src_tiled) {
+ if (src_tiling != I915_TILING_NONE) {
CMD |= XY_SRC_TILED;
src_pitch /= 4;
}
@@ -512,7 +512,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
}
#ifndef I915
- if (irb_region->tiled) {
+ if (irb_region->tiling != I915_TILING_NONE) {
CMD |= XY_DST_TILED;
pitch /= 4;
}
@@ -563,7 +563,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
- GLboolean dst_tiled,
+ uint32_t dst_tiling,
GLshort x, GLshort y,
GLshort w, GLshort h,
GLenum logic_op)
@@ -593,7 +593,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
if (cpp == 4)
opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
#ifndef I915
- if (dst_tiled) {
+ if (dst_tiling != I915_TILING_NONE) {
opcode |= XY_DST_TILED;
dst_pitch /= 4;
}
@@ -606,7 +606,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
br13 |= BR13_8888;
blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
- if (dst_tiled)
+ if (dst_tiling != I915_TILING_NONE)
blit_cmd |= XY_DST_TILED;
BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS);
diff --git a/src/mesa/drivers/dri/intel/intel_blit.h b/src/mesa/drivers/dri/intel/intel_blit.h
index fc0620caba..0881cc4fdc 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.h
+++ b/src/mesa/drivers/dri/intel/intel_blit.h
@@ -42,11 +42,11 @@ extern void intelEmitCopyBlit(struct intel_context *intel,
GLshort src_pitch,
dri_bo *src_buffer,
GLuint src_offset,
- GLboolean src_tiled,
+ uint32_t src_tiling,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
- GLboolean dst_tiled,
+ uint32_t dst_tiling,
GLshort srcx, GLshort srcy,
GLshort dstx, GLshort dsty,
GLshort w, GLshort h,
@@ -57,7 +57,7 @@ extern void intelEmitFillBlit(struct intel_context *intel,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
- GLboolean dst_tiled,
+ uint32_t dst_tiling,
GLshort x, GLshort y,
GLshort w, GLshort h, GLuint color);
@@ -69,7 +69,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
GLshort dst_pitch,
dri_bo *dst_buffer,
GLuint dst_offset,
- GLboolean dst_tiled,
+ uint32_t dst_tiling,
GLshort x, GLshort y,
GLshort w, GLshort h,
GLenum logic_op);
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index fa0b4c5618..7e3f370ad0 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -703,9 +703,6 @@ intelInitContext(struct intel_context *intel,
intel->no_rast = 1;
}
- intel->tiling_swizzle_mode = driQueryOptioni(&intel->optionCache,
- "swizzle_mode");
-
/* Disable all hardware rendering (skip emitting batches and fences/waits
* to the kernel)
*/
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 6ed9a377e4..f1116d2747 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -266,7 +266,6 @@ struct intel_context
GLuint lastStamp;
GLboolean no_hw;
- int tiling_swizzle_mode;
/**
* Configuration cache
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 3a3ce68c59..7663393fba 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -294,10 +294,6 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
rb->Width = width;
rb->Height = height;
- /* This sets the Get/PutRow/Value functions */
- /* XXX can we choose a different tile here? */
- intel_set_span_functions(&irb->Base, INTEL_TILE_NONE);
-
return GL_TRUE;
}
}
@@ -376,8 +372,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb,
* not a user-created renderbuffer.
*/
struct intel_renderbuffer *
-intel_create_renderbuffer(intelScreenPrivate *intelScreen,
- GLenum intFormat, enum tiling_mode tiling)
+intel_create_renderbuffer(GLenum intFormat)
{
GET_CURRENT_CONTEXT(ctx);
@@ -444,20 +439,10 @@ intel_create_renderbuffer(intelScreenPrivate *intelScreen,
irb->Base.InternalFormat = intFormat;
- irb->tiling = tiling;
-
/* intel-specific methods */
irb->Base.Delete = intel_delete_renderbuffer;
irb->Base.AllocStorage = intel_alloc_window_storage;
irb->Base.GetPointer = intel_get_pointer;
- /* This sets the Get/PutRow/Value functions. In classic mode, all access
- * is through the aperture and will be swizzled by the fence registers, so
- * we don't need the span functions to perfom tile swizzling
- */
- if (intelScreen->ttm)
- intel_set_span_functions(&irb->Base, tiling);
- else
- intel_set_span_functions(&irb->Base, INTEL_TILE_NONE);
return irb;
}
@@ -568,7 +553,6 @@ intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb,
irb->Base.Delete = intel_delete_renderbuffer;
irb->Base.AllocStorage = intel_nop_alloc_storage;
- intel_set_span_functions(&irb->Base, irb->tiling);
irb->RenderToTexture = GL_TRUE;
@@ -596,9 +580,6 @@ intel_wrap_texture(GLcontext * ctx, struct gl_texture_image *texImage)
_mesa_init_renderbuffer(&irb->Base, name);
irb->Base.ClassID = INTEL_RB_CLASS;
- /* XXX can we fix this? */
- irb->tiling = INTEL_TILE_NONE;
-
if (!intel_update_wrapper(ctx, irb, texImage)) {
_mesa_free(irb);
return NULL;
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 23af593960..5fe0fd8abf 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -72,7 +72,6 @@ struct intel_renderbuffer
struct intel_region *region;
void *pfMap; /* possibly paged flipped map pointer */
GLuint pfPitch; /* possibly paged flipped pitch */
- enum tiling_mode tiling;
GLboolean RenderToTexture; /* RTT? */
GLuint PairedDepth; /**< only used if this is a depth renderbuffer */
@@ -91,8 +90,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *irb,
struct intel_region *region);
extern struct intel_renderbuffer *
-intel_create_renderbuffer(intelScreenPrivate *intelScreen,
- GLenum intFormat, enum tiling_mode tiling);
+intel_create_renderbuffer(GLenum intFormat);
extern void intel_fbo_init(struct intel_context *intel);
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
index ce6c6d204f..7e0d20e681 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
@@ -293,7 +293,7 @@ do_blit_bitmap( GLcontext *ctx,
dst->pitch,
dst->buffer,
0,
- dst->tiled,
+ dst->tiling,
rect.x1 + px,
rect.y2 - (py + h),
w, h,
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_copy.c b/src/mesa/drivers/dri/intel/intel_pixel_copy.c
index eb4f10e9d5..3093ccf7c6 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_copy.c
@@ -337,8 +337,8 @@ do_blit_copypixels(GLcontext * ctx,
continue;
intelEmitCopyBlit(intel, dst->cpp,
- src->pitch, src->buffer, 0, src->tiled,
- dst->pitch, dst->buffer, 0, dst->tiled,
+ src->pitch, src->buffer, 0, src->tiling,
+ dst->pitch, dst->buffer, 0, dst->tiling,
clip_x + delta_x, clip_y + delta_y, /* srcx, srcy */
clip_x, clip_y, /* dstx, dsty */
clip_w, clip_h,
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
index 2b3445cb28..5675084da5 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c
@@ -314,7 +314,7 @@ do_blit_drawpixels(GLcontext * ctx,
intelEmitCopyBlit(intel,
dest->cpp,
rowLength, src_buffer, src_offset, GL_FALSE,
- dest->pitch, dest->buffer, 0, dest->tiled,
+ dest->pitch, dest->buffer, 0, dest->tiling,
rect.x1 - dest_rect.x1,
rect.y2 - dest_rect.y2,
rect.x1,
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 5d23c72504..91b835d1aa 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -39,6 +39,9 @@
* last moment.
*/
+#include
+#include
+
#include "intel_context.h"
#include "intel_regions.h"
#include "intel_blit.h"
@@ -46,6 +49,7 @@
#include "dri_bufmgr.h"
#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
+#include "intel_chipset.h"
#define FILE_DEBUG_FLAG DEBUG_REGION
@@ -76,10 +80,34 @@ intel_region_unmap(struct intel_context *intel, struct intel_region *region)
}
}
+static int
+intel_set_region_tiling_gem(struct intel_context *intel,
+ struct intel_region *region,
+ uint32_t bo_handle)
+{
+ struct drm_i915_gem_get_tiling get_tiling;
+ int ret;
+
+ memset(&get_tiling, 0, sizeof(get_tiling));
+
+ get_tiling.handle = bo_handle;
+ ret = ioctl(intel->driFd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
+ if (ret != 0) {
+ fprintf(stderr, "Failed to get tiling state for region: %s\n",
+ strerror(errno));
+ return ret;
+ }
+
+ region->tiling = get_tiling.tiling_mode;
+ region->bit_6_swizzle = get_tiling.swizzle_mode;
+
+ return 0;
+}
+
static struct intel_region *
intel_region_alloc_internal(struct intel_context *intel,
GLuint cpp, GLuint pitch, GLuint height,
- GLuint tiled, dri_bo *buffer)
+ dri_bo *buffer)
{
struct intel_region *region;
@@ -93,9 +121,12 @@ intel_region_alloc_internal(struct intel_context *intel,
region->pitch = pitch;
region->height = height; /* needed? */
region->refcount = 1;
- region->tiled = tiled;
region->buffer = buffer;
+ /* Default to no tiling */
+ region->tiling = I915_TILING_NONE;
+ region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
+
return region;
}
@@ -108,20 +139,26 @@ intel_region_alloc(struct intel_context *intel,
buffer = dri_bo_alloc(intel->bufmgr, "region",
pitch * cpp * height, 64);
- return intel_region_alloc_internal(intel, cpp, pitch, height, 0, buffer);
+ return intel_region_alloc_internal(intel, cpp, pitch, height, buffer);
}
struct intel_region *
intel_region_alloc_for_handle(struct intel_context *intel,
GLuint cpp, GLuint pitch, GLuint height,
- GLuint tiled, GLuint handle)
+ GLuint handle)
{
+ struct intel_region *region;
dri_bo *buffer;
- buffer = intel_bo_gem_create_from_name(intel->bufmgr, "region", handle);
+ buffer = intel_bo_gem_create_from_name(intel->bufmgr, "dri2 region", handle);
+
+ region = intel_region_alloc_internal(intel, cpp, pitch, height, buffer);
+ if (region == NULL)
+ return region;
+
+ intel_set_region_tiling_gem(intel, region, handle);
- return intel_region_alloc_internal(intel,
- cpp, pitch, height, tiled, buffer);
+ return region;
}
void
@@ -135,26 +172,34 @@ intel_region_reference(struct intel_region **dst, struct intel_region *src)
}
void
-intel_region_release(struct intel_region **region)
+intel_region_release(struct intel_region **region_handle)
{
- if (!*region)
+ struct intel_region *region = *region_handle;
+
+ if (region == NULL)
return;
- DBG("%s %d\n", __FUNCTION__, (*region)->refcount - 1);
+ DBG("%s %d\n", __FUNCTION__, region->refcount - 1);
- ASSERT((*region)->refcount > 0);
- (*region)->refcount--;
+ ASSERT(region->refcount > 0);
+ region->refcount--;
- if ((*region)->refcount == 0) {
- assert((*region)->map_refcount == 0);
+ if (region->refcount == 0) {
+ assert(region->map_refcount == 0);
- if ((*region)->pbo)
- (*region)->pbo->region = NULL;
- (*region)->pbo = NULL;
- dri_bo_unreference((*region)->buffer);
- free(*region);
+ if (region->pbo)
+ region->pbo->region = NULL;
+ region->pbo = NULL;
+ dri_bo_unreference(region->buffer);
+
+ if (region->classic_map != NULL) {
+ drmUnmap(region->classic_map,
+ region->pitch * region->cpp * region->height);
+ }
+
+ free(region);
}
- *region = NULL;
+ *region_handle = NULL;
}
/*
@@ -269,8 +314,8 @@ intel_region_copy(struct intel_context *intel,
intelEmitCopyBlit(intel,
dst->cpp,
- src->pitch, src->buffer, src_offset, src->tiled,
- dst->pitch, dst->buffer, dst_offset, dst->tiled,
+ src->pitch, src->buffer, src_offset, src->tiling,
+ dst->pitch, dst->buffer, dst_offset, dst->tiling,
srcx, srcy, dstx, dsty, width, height,
GL_COPY);
}
@@ -300,7 +345,7 @@ intel_region_fill(struct intel_context *intel,
intelEmitFillBlit(intel,
dst->cpp,
- dst->pitch, dst->buffer, dst_offset, dst->tiled,
+ dst->pitch, dst->buffer, dst_offset, dst->tiling,
dstx, dsty, width, height, color);
}
@@ -382,8 +427,8 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region)
intelEmitCopyBlit(intel,
region->cpp,
- region->pitch, region->buffer, 0, region->tiled,
- region->pitch, pbo->buffer, 0, region->tiled,
+ region->pitch, region->buffer, 0, region->tiling,
+ region->pitch, pbo->buffer, 0, region->tiling,
0, 0, 0, 0,
region->pitch, region->height,
GL_COPY);
@@ -414,6 +459,7 @@ intel_recreate_static(struct intel_context *intel,
GLuint mem_type)
{
intelScreenPrivate *intelScreen = intel->intelScreen;
+ int ret;
if (region == NULL) {
region = calloc(sizeof(*region), 1);
@@ -426,20 +472,45 @@ intel_recreate_static(struct intel_context *intel,
region->cpp = intel->ctx.Visual.rgbBits / 8;
region->pitch = intelScreen->pitch;
region->height = intelScreen->height; /* needed? */
- region->tiled = region_desc->tiled;
if (intel->ttm) {
assert(region_desc->bo_handle != -1);
region->buffer = intel_bo_gem_create_from_name(intel->bufmgr,
name,
region_desc->bo_handle);
+
+ intel_set_region_tiling_gem(intel, region, region_desc->bo_handle);
} else {
+ ret = drmMap(intel->driFd, region_desc->handle,
+ region->pitch * region->cpp * region->height,
+ ®ion->classic_map);
+ if (ret != 0) {
+ fprintf(stderr, "Failed to drmMap %s buffer\n", name);
+ free(region);
+ return NULL;
+ }
+
region->buffer = intel_bo_fake_alloc_static(intel->bufmgr,
name,
region_desc->offset,
- intelScreen->pitch *
- intelScreen->height,
- region_desc->map);
+ region->pitch * region->cpp *
+ region->height,
+ region->classic_map);
+
+ /* The sarea just gives us a boolean for whether it's tiled or not,
+ * instead of which tiling mode it is. Guess.
+ */
+ if (region_desc->tiled) {
+ if (IS_965(intel->intelScreen->deviceID) &&
+ region_desc == &intelScreen->depth)
+ region->tiling = I915_TILING_Y;
+ else
+ region->tiling = I915_TILING_X;
+ } else {
+ region->tiling = I915_TILING_NONE;
+ }
+
+ region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
}
assert(region->buffer != NULL);
diff --git a/src/mesa/drivers/dri/intel/intel_regions.h b/src/mesa/drivers/dri/intel/intel_regions.h
index 229f79aeba..e5f19fbb45 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.h
+++ b/src/mesa/drivers/dri/intel/intel_regions.h
@@ -28,6 +28,12 @@
#ifndef INTEL_REGIONS_H
#define INTEL_REGIONS_H
+/** @file intel_regions.h
+ *
+ * Structure definitions and prototypes for intel_region handling, which is
+ * the basic structure for rectangular collections of pixels stored in a dri_bo.
+ */
+
#include "mtypes.h"
#include "dri_bufmgr.h"
@@ -53,8 +59,9 @@ struct intel_region
GLuint map_refcount; /**< Reference count for mapping */
GLuint draw_offset; /**< Offset of drawing address within the region */
- GLboolean tiled; /**< True if the region is X or Y-tiled. Used on 965. */
-
+ uint32_t tiling; /**< Which tiling mode the region is in */
+ uint32_t bit_6_swizzle; /**< GEM flag for address swizzling requirement */
+ drmAddress classic_map; /**< drmMap of the region when not in GEM mode */
struct intel_buffer_object *pbo; /* zero-copy uploads */
};
@@ -69,7 +76,7 @@ struct intel_region *intel_region_alloc(struct intel_context *intel,
struct intel_region *
intel_region_alloc_for_handle(struct intel_context *intel,
GLuint cpp, GLuint pitch, GLuint height,
- GLuint tiled, unsigned int handle);
+ unsigned int handle);
void intel_region_reference(struct intel_region **dst,
struct intel_region *src);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 9e4f48fbd7..36dce171c6 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -69,20 +69,13 @@ PUBLIC const char __driConfigOptions[] =
DRI_CONF_SECTION_QUALITY
DRI_CONF_FORCE_S3TC_ENABLE(false)
DRI_CONF_ALLOW_LARGE_TEXTURES(2)
- DRI_CONF_OPT_BEGIN_V(swizzle_mode, enum, 0, "0:2")
- DRI_CONF_DESC_BEGIN(en, "Tiling swizzle mode for software fallbacks")
- DRI_CONF_ENUM(0, "No swizzling")
- DRI_CONF_ENUM(1, "addr[6] = addr[6] ^ addr[9]")
- DRI_CONF_ENUM(2, "addr[6] = addr[6] ^ addr[9] ^ addr[10]")
- DRI_CONF_DESC_END
- DRI_CONF_OPT_END
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
-const GLuint __driNConfigOptions = 7;
+const GLuint __driNConfigOptions = 6;
#ifdef USE_NEW_INTERFACE
static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
@@ -97,51 +90,6 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv)
{
intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private;
- if (intelScreen->front.handle) {
- if (drmMap(sPriv->fd,
- intelScreen->front.handle,
- intelScreen->front.size,
- (drmAddress *) & intelScreen->front.map) != 0) {
- _mesa_problem(NULL, "drmMap(frontbuffer) failed!");
- return GL_FALSE;
- }
- }
- else {
- _mesa_warning(NULL, "no front buffer handle in intelMapScreenRegions!");
- }
-
- if (0)
- _mesa_printf("Back 0x%08x ", intelScreen->back.handle);
- if (drmMap(sPriv->fd,
- intelScreen->back.handle,
- intelScreen->back.size,
- (drmAddress *) & intelScreen->back.map) != 0) {
- intelUnmapScreenRegions(intelScreen);
- return GL_FALSE;
- }
-
- if (intelScreen->third.handle) {
- if (0)
- _mesa_printf("Third 0x%08x ", intelScreen->third.handle);
- if (drmMap(sPriv->fd,
- intelScreen->third.handle,
- intelScreen->third.size,
- (drmAddress *) & intelScreen->third.map) != 0) {
- intelUnmapScreenRegions(intelScreen);
- return GL_FALSE;
- }
- }
-
- if (0)
- _mesa_printf("Depth 0x%08x ", intelScreen->depth.handle);
- if (drmMap(sPriv->fd,
- intelScreen->depth.handle,
- intelScreen->depth.size,
- (drmAddress *) & intelScreen->depth.map) != 0) {
- intelUnmapScreenRegions(intelScreen);
- return GL_FALSE;
- }
-
if (0)
_mesa_printf("TEX 0x%08x ", intelScreen->tex.handle);
if (intelScreen->tex.size != 0) {
@@ -154,50 +102,15 @@ intelMapScreenRegions(__DRIscreenPrivate * sPriv)
}
}
- if (0)
- printf("Mappings: front: %p back: %p third: %p depth: %p tex: %p\n",
- intelScreen->front.map,
- intelScreen->back.map, intelScreen->third.map,
- intelScreen->depth.map, intelScreen->tex.map);
return GL_TRUE;
}
void
intelUnmapScreenRegions(intelScreenPrivate * intelScreen)
{
-#define REALLY_UNMAP 1
- if (intelScreen->front.map) {
-#if REALLY_UNMAP
- if (drmUnmap(intelScreen->front.map, intelScreen->front.size) != 0)
- printf("drmUnmap front failed!\n");
-#endif
- intelScreen->front.map = NULL;
- }
- if (intelScreen->back.map) {
-#if REALLY_UNMAP
- if (drmUnmap(intelScreen->back.map, intelScreen->back.size) != 0)
- printf("drmUnmap back failed!\n");
-#endif
- intelScreen->back.map = NULL;
- }
- if (intelScreen->third.map) {
-#if REALLY_UNMAP
- if (drmUnmap(intelScreen->third.map, intelScreen->third.size) != 0)
- printf("drmUnmap third failed!\n");
-#endif
- intelScreen->third.map = NULL;
- }
- if (intelScreen->depth.map) {
-#if REALLY_UNMAP
- drmUnmap(intelScreen->depth.map, intelScreen->depth.size);
- intelScreen->depth.map = NULL;
-#endif
- }
if (intelScreen->tex.map) {
-#if REALLY_UNMAP
drmUnmap(intelScreen->tex.map, intelScreen->tex.size);
intelScreen->tex.map = NULL;
-#endif
}
}
@@ -341,8 +254,6 @@ intelHandleDrawableConfig(__DRIdrawablePrivate *dPriv,
* attached. */
}
-#define BUFFER_FLAG_TILED 0x0100
-
/**
* DRI2 entrypoint
*/
@@ -355,7 +266,6 @@ intelHandleBufferAttach(__DRIdrawablePrivate *dPriv,
struct intel_renderbuffer *rb;
struct intel_region *region;
struct intel_context *intel = pcp->driverPrivate;
- GLuint tiled;
switch (ba->buffer.attachment) {
case DRI_DRAWABLE_BUFFER_FRONT_LEFT:
@@ -389,10 +299,9 @@ intelHandleBufferAttach(__DRIdrawablePrivate *dPriv,
return;
#endif
- tiled = (ba->buffer.flags & BUFFER_FLAG_TILED) > 0;
region = intel_region_alloc_for_handle(intel, ba->buffer.cpp,
ba->buffer.pitch / ba->buffer.cpp,
- dPriv->h, tiled,
+ dPriv->h,
ba->buffer.handle);
intel_renderbuffer_set_region(rb, region);
@@ -528,7 +437,6 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
GLboolean swStencil = (mesaVis->stencilBits > 0 &&
mesaVis->depthBits != 24);
GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
- enum tiling_mode tiling;
struct intel_framebuffer *intel_fb = CALLOC_STRUCT(intel_framebuffer);
@@ -538,46 +446,29 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
_mesa_initialize_framebuffer(&intel_fb->Base, mesaVis);
/* setup the hardware-based renderbuffers */
- /* We get only a boolean value from the DDX for whether tiling is
- * enabled, so we have to guess when it's Y and not X (965 depth).
- */
- {
- tiling = screen->front.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
- intel_fb->color_rb[0] = intel_create_renderbuffer(screen,
- rgbFormat, tiling);
- _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT,
- &intel_fb->color_rb[0]->Base);
- }
+ intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat);
+ _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_FRONT_LEFT,
+ &intel_fb->color_rb[0]->Base);
if (mesaVis->doubleBufferMode) {
- tiling = screen->back.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
- intel_fb->color_rb[1] = intel_create_renderbuffer(screen,
- rgbFormat, tiling);
+ intel_fb->color_rb[1] = intel_create_renderbuffer(rgbFormat);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_BACK_LEFT,
&intel_fb->color_rb[1]->Base);
if (screen->third.handle) {
struct gl_renderbuffer *tmp_rb = NULL;
- tiling = screen->third.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
- intel_fb->color_rb[2] = intel_create_renderbuffer(screen,
- rgbFormat,
- tiling);
+
+ intel_fb->color_rb[2] = intel_create_renderbuffer(rgbFormat);
_mesa_reference_renderbuffer(&tmp_rb, &intel_fb->color_rb[2]->Base);
}
}
-#ifdef I915
- tiling = screen->depth.tiled ? INTEL_TILE_X : INTEL_TILE_NONE;
-#else
- tiling = screen->depth.tiled ? INTEL_TILE_Y : INTEL_TILE_NONE;
-#endif
if (mesaVis->depthBits == 24) {
if (mesaVis->stencilBits == 8) {
/* combined depth/stencil buffer */
struct intel_renderbuffer *depthStencilRb
- = intel_create_renderbuffer(screen,
- GL_DEPTH24_STENCIL8_EXT, tiling);
+ = intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT);
/* note: bind RB to two attachment points */
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
&depthStencilRb->Base);
@@ -585,8 +476,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
&depthStencilRb->Base);
} else {
struct intel_renderbuffer *depthRb
- = intel_create_renderbuffer(screen,
- GL_DEPTH_COMPONENT24, tiling);
+ = intel_create_renderbuffer(GL_DEPTH_COMPONENT24);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH,
&depthRb->Base);
}
@@ -594,8 +484,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv,
else if (mesaVis->depthBits == 16) {
/* just 16-bit depth buffer, no hw stencil */
struct intel_renderbuffer *depthRb
- = intel_create_renderbuffer(screen,
- GL_DEPTH_COMPONENT16, tiling);
+ = intel_create_renderbuffer(GL_DEPTH_COMPONENT16);
_mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base);
}
diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h
index 648bf61240..9a73b13951 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.h
+++ b/src/mesa/drivers/dri/intel/intel_screen.h
@@ -33,12 +33,6 @@
#include "i915_drm.h"
#include "xmlconfig.h"
-enum tiling_mode {
- INTEL_TILE_NONE,
- INTEL_TILE_X,
- INTEL_TILE_Y
-};
-
/* XXX: change name or eliminate to avoid conflict with "struct
* intel_region"!!!
*/
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index b1392f794e..3065d15e32 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -39,6 +39,10 @@
#include "swrast/swrast.h"
+static void
+intel_set_span_functions(struct intel_context *intel,
+ struct gl_renderbuffer *rb);
+
/*
* Deal with tiled surfaces
*/
@@ -111,39 +115,26 @@ static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
tile_off = (y_tile_off << 9) + x_tile_off;
- /* bit swizzling tricks your parents never told you about:
- *
- * The specs say that the X tiling layout is just 8 512-byte rows
- * packed into a page. It turns out that there's some additional
- * swizzling of bit 6 to reduce cache aliasing issues. Experimental
- * results below:
- *
- * line bit GM965 945G/Q965
- * 9 10 11
- * 0 0 0 0 0 0
- * 1 0 1 0 1 1
- * 2 1 0 0 1 1
- * 3 1 1 0 0 0
- * 4 0 0 1 1 0
- * 5 0 1 1 0 1
- * 6 1 0 1 0 1
- * 7 1 1 1 1 0
- *
- * So we see that the GM965 is bit 6 ^ 9 ^ 10 ^ 11, while other
- * parts were just 6 ^ 9 ^ 10. However, some systems, including a
- * GM965 we've seen, don't perform the swizzling at all. Information
- * on how to detect it through register reads is expected soon.
- */
- switch (intel->tiling_swizzle_mode) {
- case 0:
+ switch (irb->region->bit_6_swizzle) {
+ case I915_BIT_6_SWIZZLE_NONE:
break;
- case 1:
+ case I915_BIT_6_SWIZZLE_9:
+ tile_off ^= ((tile_off >> 3) & 64);
+ break;
+ case I915_BIT_6_SWIZZLE_9_10:
tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
break;
- case 2:
+ case I915_BIT_6_SWIZZLE_9_11:
+ tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
+ break;
+ case I915_BIT_6_SWIZZLE_9_10_11:
tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
((tile_off >> 5) & 64);
break;
+ default:
+ fprintf(stderr, "Unknown tile swizzling mode %d\n",
+ irb->region->bit_6_swizzle);
+ exit(1);
}
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
@@ -184,15 +175,28 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
tile_off = ((x_tile_off & ~0xf) << 5) + (y_tile_off << 4) +
(x_tile_off & 0xf);
- switch (intel->tiling_swizzle_mode) {
- case 0:
+ switch (irb->region->bit_6_swizzle) {
+ case I915_BIT_6_SWIZZLE_NONE:
+ break;
+ case I915_BIT_6_SWIZZLE_9:
+ tile_off ^= ((tile_off >> 3) & 64);
+ break;
+ case I915_BIT_6_SWIZZLE_9_10:
+ tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64);
break;
- case 1:
- tile_off ^= (tile_off >> 3) & 64;
+ case I915_BIT_6_SWIZZLE_9_11:
+ tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 5) & 64);
break;
- case 2:
+ case I915_BIT_6_SWIZZLE_9_10_11:
+ tile_off ^= ((tile_off >> 3) & 64) ^ ((tile_off >> 4) & 64) ^
+ ((tile_off >> 5) & 64);
break;
+ default:
+ fprintf(stderr, "Unknown tile swizzling mode %d\n",
+ irb->region->bit_6_swizzle);
+ exit(1);
}
+
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
return buf + tile_base + tile_off;
@@ -491,16 +495,14 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) {
struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[j];
irb = intel_renderbuffer(rb);
- if (irb) {
- /* this is a user-created intel_renderbuffer */
- if (irb->region) {
- if (map)
- intel_region_map(intel, irb->region);
- else
- intel_region_unmap(intel, irb->region);
- irb->pfMap = irb->region->map;
- irb->pfPitch = irb->region->pitch;
- }
+ if (irb && irb->region) {
+ intel_set_span_functions(intel, rb);
+ if (map)
+ intel_region_map(intel, irb->region);
+ else
+ intel_region_unmap(intel, irb->region);
+ irb->pfMap = irb->region->map;
+ irb->pfPitch = irb->region->pitch;
}
}
@@ -526,6 +528,7 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
/* color read buffers */
irb = intel_renderbuffer(ctx->ReadBuffer->_ColorReadBuffer);
if (irb && irb->region) {
+ intel_set_span_functions(intel, ctx->ReadBuffer->_ColorReadBuffer);
if (map)
intel_region_map(intel, irb->region);
else
@@ -568,6 +571,8 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
irb = intel_renderbuffer(ctx->DrawBuffer->_DepthBuffer->Wrapped);
if (irb && irb->region) {
if (map) {
+ intel_set_span_functions(intel,
+ ctx->DrawBuffer->_DepthBuffer->Wrapped);
intel_region_map(intel, irb->region);
irb->pfMap = irb->region->map;
irb->pfPitch = irb->region->pitch;
@@ -585,6 +590,8 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
irb = intel_renderbuffer(ctx->DrawBuffer->_StencilBuffer->Wrapped);
if (irb && irb->region) {
if (map) {
+ intel_set_span_functions(intel,
+ ctx->DrawBuffer->_StencilBuffer->Wrapped);
intel_region_map(intel, irb->region);
irb->pfMap = irb->region->map;
irb->pfPitch = irb->region->pitch;
@@ -615,15 +622,6 @@ intelSpanRenderStart(GLcontext * ctx)
intelFlush(&intel->ctx);
LOCK_HARDWARE(intel);
-#if 0
- /* Just map the framebuffer and all textures. Bufmgr code will
- * take care of waiting on the necessary fences:
- */
- intel_region_map(intel, intel->front_region);
- intel_region_map(intel, intel->back_region);
- intel_region_map(intel, intel->depth_region);
-#endif
-
for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
if (ctx->Texture.Unit[i]._ReallyEnabled) {
struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
@@ -646,14 +644,6 @@ intelSpanRenderFinish(GLcontext * ctx)
_swrast_flush(ctx);
- /* Now unmap the framebuffer:
- */
-#if 0
- intel_region_unmap(intel, intel->front_region);
- intel_region_unmap(intel, intel->back_region);
- intel_region_unmap(intel, intel->depth_region);
-#endif
-
for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
if (ctx->Texture.Unit[i]._ReallyEnabled) {
struct gl_texture_object *texObj = ctx->Texture.Unit[i]._Current;
@@ -680,20 +670,32 @@ intelInitSpanFuncs(GLcontext * ctx)
* Plug in appropriate span read/write functions for the given renderbuffer.
* These are used for the software fallbacks.
*/
-void
-intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling)
+static void
+intel_set_span_functions(struct intel_context *intel,
+ struct gl_renderbuffer *rb)
{
+ struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
+ uint32_t tiling;
+
+ /* If in GEM mode, we need to do the tile address swizzling ourselves,
+ * instead of the fence registers handling it.
+ */
+ if (intel->ttm)
+ tiling = irb->region->tiling;
+ else
+ tiling = I915_TILING_NONE;
+
if (rb->_ActualFormat == GL_RGB5) {
/* 565 RGB */
switch (tiling) {
- case INTEL_TILE_NONE:
+ case I915_TILING_NONE:
default:
intelInitPointers_RGB565(rb);
break;
- case INTEL_TILE_X:
+ case I915_TILING_X:
intel_XTile_InitPointers_RGB565(rb);
break;
- case INTEL_TILE_Y:
+ case I915_TILING_Y:
intel_YTile_InitPointers_RGB565(rb);
break;
}
@@ -701,28 +703,28 @@ intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling)
else if (rb->_ActualFormat == GL_RGBA8) {
/* 8888 RGBA */
switch (tiling) {
- case INTEL_TILE_NONE:
+ case I915_TILING_NONE:
default:
intelInitPointers_ARGB8888(rb);
break;
- case INTEL_TILE_X:
+ case I915_TILING_X:
intel_XTile_InitPointers_ARGB8888(rb);
break;
- case INTEL_TILE_Y:
+ case I915_TILING_Y:
intel_YTile_InitPointers_ARGB8888(rb);
break;
}
}
else if (rb->_ActualFormat == GL_DEPTH_COMPONENT16) {
switch (tiling) {
- case INTEL_TILE_NONE:
+ case I915_TILING_NONE:
default:
intelInitDepthPointers_z16(rb);
break;
- case INTEL_TILE_X:
+ case I915_TILING_X:
intel_XTile_InitDepthPointers_z16(rb);
break;
- case INTEL_TILE_Y:
+ case I915_TILING_Y:
intel_YTile_InitDepthPointers_z16(rb);
break;
}
@@ -730,28 +732,28 @@ intel_set_span_functions(struct gl_renderbuffer *rb, enum tiling_mode tiling)
else if (rb->_ActualFormat == GL_DEPTH_COMPONENT24 || /* XXX FBO remove */
rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT) {
switch (tiling) {
- case INTEL_TILE_NONE:
+ case I915_TILING_NONE:
default:
intelInitDepthPointers_z24_s8(rb);
break;
- case INTEL_TILE_X:
+ case I915_TILING_X:
intel_XTile_InitDepthPointers_z24_s8(rb);
break;
- case INTEL_TILE_Y:
+ case I915_TILING_Y:
intel_YTile_InitDepthPointers_z24_s8(rb);
break;
}
}
else if (rb->_ActualFormat == GL_STENCIL_INDEX8_EXT) {
switch (tiling) {
- case INTEL_TILE_NONE:
+ case I915_TILING_NONE:
default:
intelInitStencilPointers_z24_s8(rb);
break;
- case INTEL_TILE_X:
+ case I915_TILING_X:
intel_XTile_InitStencilPointers_z24_s8(rb);
break;
- case INTEL_TILE_Y:
+ case I915_TILING_Y:
intel_YTile_InitStencilPointers_z24_s8(rb);
break;
}
diff --git a/src/mesa/drivers/dri/intel/intel_span.h b/src/mesa/drivers/dri/intel/intel_span.h
index 1b47c2829c..d2d4d6ecd4 100644
--- a/src/mesa/drivers/dri/intel/intel_span.h
+++ b/src/mesa/drivers/dri/intel/intel_span.h
@@ -33,7 +33,4 @@ extern void intelInitSpanFuncs(GLcontext * ctx);
extern void intelSpanRenderFinish(GLcontext * ctx);
extern void intelSpanRenderStart(GLcontext * ctx);
-extern void intel_set_span_functions(struct gl_renderbuffer *rb,
- enum tiling_mode tiling);
-
#endif
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index 8a8eec83aa..cf8eb4ed3c 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -148,7 +148,7 @@ do_copy_texsubimage(struct intel_context *intel,
intelImage->mt->pitch,
intelImage->mt->region->buffer,
image_offset,
- intelImage->mt->region->tiled,
+ intelImage->mt->region->tiling,
x, y + height, dstx, dsty, width, height,
GL_COPY); /* ? */
}
--
cgit v1.2.3
From 93115c4b235896df097b91edec7458a8a4488c4e Mon Sep 17 00:00:00 2001
From: Stephane Marchesin
Date: Mon, 14 Jul 2008 01:03:07 +0200
Subject: nouveau: say goodbye to the old DRI driver...
---
configs/linux-dri-xcb | 2 +-
src/mesa/drivers/dri/nouveau/Makefile | 54 -
src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c | 627 ---
src/mesa/drivers/dri/nouveau/nouveau_bufferobj.h | 77 -
src/mesa/drivers/dri/nouveau/nouveau_card.c | 17 -
src/mesa/drivers/dri/nouveau/nouveau_card.h | 49 -
src/mesa/drivers/dri/nouveau/nouveau_card_list.h | 226 -
src/mesa/drivers/dri/nouveau/nouveau_context.c | 422 --
src/mesa/drivers/dri/nouveau/nouveau_context.h | 241 -
src/mesa/drivers/dri/nouveau/nouveau_ctrlreg.h | 44 -
src/mesa/drivers/dri/nouveau/nouveau_dri.h | 28 -
src/mesa/drivers/dri/nouveau/nouveau_driver.c | 218 -
src/mesa/drivers/dri/nouveau/nouveau_driver.h | 42 -
src/mesa/drivers/dri/nouveau/nouveau_fbo.c | 289 --
src/mesa/drivers/dri/nouveau/nouveau_fbo.h | 30 -
src/mesa/drivers/dri/nouveau/nouveau_fifo.c | 153 -
src/mesa/drivers/dri/nouveau/nouveau_fifo.h | 222 -
src/mesa/drivers/dri/nouveau/nouveau_lock.c | 81 -
src/mesa/drivers/dri/nouveau/nouveau_lock.h | 69 -
src/mesa/drivers/dri/nouveau/nouveau_mem.c | 144 -
src/mesa/drivers/dri/nouveau/nouveau_mem.h | 23 -
src/mesa/drivers/dri/nouveau/nouveau_msg.h | 67 -
src/mesa/drivers/dri/nouveau/nouveau_object.c | 98 -
src/mesa/drivers/dri/nouveau/nouveau_object.h | 39 -
src/mesa/drivers/dri/nouveau/nouveau_query.c | 200 -
src/mesa/drivers/dri/nouveau/nouveau_query.h | 38 -
src/mesa/drivers/dri/nouveau/nouveau_reg.h | 4998 --------------------
src/mesa/drivers/dri/nouveau/nouveau_screen.c | 325 --
src/mesa/drivers/dri/nouveau/nouveau_screen.h | 61 -
src/mesa/drivers/dri/nouveau/nouveau_shader.c | 833 ----
src/mesa/drivers/dri/nouveau/nouveau_shader.h | 454 --
src/mesa/drivers/dri/nouveau/nouveau_shader_0.c | 1050 ----
src/mesa/drivers/dri/nouveau/nouveau_shader_1.c | 16 -
src/mesa/drivers/dri/nouveau/nouveau_shader_2.c | 264 --
src/mesa/drivers/dri/nouveau/nouveau_span.c | 123 -
src/mesa/drivers/dri/nouveau/nouveau_span.h | 39 -
src/mesa/drivers/dri/nouveau/nouveau_state.c | 368 --
src/mesa/drivers/dri/nouveau/nouveau_state.h | 50 -
src/mesa/drivers/dri/nouveau/nouveau_state_cache.c | 69 -
src/mesa/drivers/dri/nouveau/nouveau_state_cache.h | 29 -
src/mesa/drivers/dri/nouveau/nouveau_swtcl.c | 127 -
src/mesa/drivers/dri/nouveau/nouveau_swtcl.h | 55 -
src/mesa/drivers/dri/nouveau/nouveau_sync.c | 198 -
src/mesa/drivers/dri/nouveau/nouveau_sync.h | 69 -
src/mesa/drivers/dri/nouveau/nouveau_tex.c | 49 -
src/mesa/drivers/dri/nouveau/nouveau_tex.h | 38 -
src/mesa/drivers/dri/nouveau/nv04_state.c | 540 ---
src/mesa/drivers/dri/nouveau/nv04_swtcl.c | 619 ---
src/mesa/drivers/dri/nouveau/nv04_swtcl.h | 12 -
src/mesa/drivers/dri/nouveau/nv10_state.c | 1009 ----
src/mesa/drivers/dri/nouveau/nv10_swtcl.c | 714 ---
src/mesa/drivers/dri/nouveau/nv10_swtcl.h | 40 -
src/mesa/drivers/dri/nouveau/nv20_shader.h | 121 -
src/mesa/drivers/dri/nouveau/nv20_state.c | 824 ----
src/mesa/drivers/dri/nouveau/nv20_vertprog.c | 447 --
src/mesa/drivers/dri/nouveau/nv30_fragprog.c | 742 ---
src/mesa/drivers/dri/nouveau/nv30_shader.h | 379 --
src/mesa/drivers/dri/nouveau/nv30_state.c | 1002 ----
src/mesa/drivers/dri/nouveau/nv30_vertprog.c | 367 --
src/mesa/drivers/dri/nouveau/nv40_fragprog.c | 224 -
src/mesa/drivers/dri/nouveau/nv40_shader.h | 467 --
src/mesa/drivers/dri/nouveau/nv40_vertprog.c | 778 ---
src/mesa/drivers/dri/nouveau/nv50_state.c | 641 ---
63 files changed, 1 insertion(+), 21640 deletions(-)
delete mode 100644 src/mesa/drivers/dri/nouveau/Makefile
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_bufferobj.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_card.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_card.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_card_list.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_context.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_context.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_ctrlreg.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_dri.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_driver.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_driver.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_fbo.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_fbo.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_fifo.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_fifo.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_lock.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_lock.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_mem.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_mem.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_msg.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_object.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_object.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_query.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_query.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_reg.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_screen.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_screen.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_shader.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_shader.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_shader_0.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_shader_1.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_shader_2.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_span.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_span.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_state.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_state.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_state_cache.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_state_cache.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_swtcl.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_swtcl.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_sync.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_sync.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_tex.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nouveau_tex.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nv04_state.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nv04_swtcl.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nv04_swtcl.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nv10_state.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nv10_swtcl.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nv10_swtcl.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nv20_shader.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nv20_state.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nv20_vertprog.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nv30_fragprog.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nv30_shader.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nv30_state.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nv30_vertprog.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nv40_fragprog.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nv40_shader.h
delete mode 100644 src/mesa/drivers/dri/nouveau/nv40_vertprog.c
delete mode 100644 src/mesa/drivers/dri/nouveau/nv50_state.c
diff --git a/configs/linux-dri-xcb b/configs/linux-dri-xcb
index 69643718ad..6d11f1744c 100644
--- a/configs/linux-dri-xcb
+++ b/configs/linux-dri-xcb
@@ -70,4 +70,4 @@ WINDOW_SYSTEM=dri
# gamma are missing because they have not been converted to use the new
# interface.
DRI_DIRS = i810 i915 mach64 mga r128 r200 r300 radeon s3v \
- savage sis tdfx trident unichrome ffb nouveau
+ savage sis tdfx trident unichrome ffb
diff --git a/src/mesa/drivers/dri/nouveau/Makefile b/src/mesa/drivers/dri/nouveau/Makefile
deleted file mode 100644
index 6ea4594f1e..0000000000
--- a/src/mesa/drivers/dri/nouveau/Makefile
+++ /dev/null
@@ -1,54 +0,0 @@
-# src/mesa/drivers/dri/nouveau/Makefile
-
-TOP = ../../../../..
-include $(TOP)/configs/current
-
-LIBNAME = nouveau_dri.so
-
-MINIGLX_SOURCES =
-
-DRIVER_SOURCES = \
- nouveau_bufferobj.c \
- nouveau_card.c \
- nouveau_context.c \
- nouveau_driver.c \
- nouveau_fbo.c \
- nouveau_fifo.c \
- nouveau_lock.c \
- nouveau_mem.c \
- nouveau_object.c \
- nouveau_screen.c \
- nouveau_span.c \
- nouveau_state.c \
- nouveau_state_cache.c \
- nouveau_shader.c \
- nouveau_shader_0.c \
- nouveau_shader_1.c \
- nouveau_shader_2.c \
- nouveau_tex.c \
- nouveau_swtcl.c \
- nouveau_sync.c \
- nouveau_query.c \
- nv04_state.c \
- nv04_swtcl.c \
- nv10_state.c \
- nv10_swtcl.c \
- nv20_state.c \
- nv20_vertprog.c \
- nv30_state.c \
- nv30_fragprog.c \
- nv30_vertprog.c \
- nv40_fragprog.c \
- nv40_vertprog.c \
- nv50_state.c
-
-C_SOURCES = \
- $(COMMON_SOURCES) \
- $(DRIVER_SOURCES)
-
-ASM_SOURCES =
-
-
-include ../Makefile.template
-
-symlinks:
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c b/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c
deleted file mode 100644
index 25c7b8206a..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c
+++ /dev/null
@@ -1,627 +0,0 @@
-#include "bufferobj.h"
-#include "enums.h"
-
-#include "nouveau_bufferobj.h"
-#include "nouveau_context.h"
-#include "nouveau_drm.h"
-#include "nouveau_mem.h"
-#include "nouveau_msg.h"
-#include "nouveau_object.h"
-
-#define NOUVEAU_MEM_FREE(mem) do { \
- nouveau_mem_free(ctx, (mem)); \
- (mem) = NULL; \
-} while(0)
-
-#define DEBUG(fmt,args...) do { \
- if (NOUVEAU_DEBUG & DEBUG_BUFFEROBJ) { \
- fprintf(stderr, "%s: "fmt, __func__, ##args); \
- } \
-} while(0)
-
-static GLboolean
-nouveau_bo_download_from_screen(GLcontext *ctx, GLuint offset, GLuint size,
- struct gl_buffer_object *bo)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
- nouveau_mem *in_mem;
-
- DEBUG("bo=%p, offset=%d, size=%d\n", bo, offset, size);
-
- /* If there's a permanent backing store, blit directly into it */
- if (nbo->cpu_mem) {
- if (nbo->cpu_mem != nbo->gpu_mem) {
- DEBUG("..cpu_mem\n");
- nouveau_memformat_flat_emit(ctx, nbo->cpu_mem,
- nbo->gpu_mem,
- offset, offset, size);
- }
- } else {
- DEBUG("..sys_mem\n");
- in_mem = nouveau_mem_alloc(ctx, NOUVEAU_MEM_AGP, size, 0);
- if (in_mem) {
- DEBUG("....via GART\n");
- /* otherwise, try blitting to faster memory and
- * copying from there
- */
- nouveau_memformat_flat_emit(ctx, in_mem, nbo->gpu_mem,
- 0, offset, size);
- nouveau_notifier_wait_nop(ctx, nmesa->syncNotifier,
- NvSubMemFormat);
- _mesa_memcpy(nbo->cpu_mem_sys + offset,
- in_mem->map, size);
- NOUVEAU_MEM_FREE(in_mem);
- } else {
- DEBUG("....direct VRAM copy\n");
- /* worst case, copy directly from vram */
- _mesa_memcpy(nbo->cpu_mem_sys + offset,
- nbo->gpu_mem + offset,
- size);
- }
- }
-
- return GL_TRUE;
-}
-
-static GLboolean
-nouveau_bo_upload_to_screen(GLcontext *ctx, GLuint offset, GLuint size,
- struct gl_buffer_object *bo)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
- nouveau_mem *out_mem;
-
- DEBUG("bo=%p, offset=%d, size=%d\n", bo, offset, size);
-
- if (nbo->cpu_mem) {
- if (nbo->cpu_mem != nbo->gpu_mem) {
- DEBUG("..cpu_mem\n");
- nouveau_memformat_flat_emit(ctx, nbo->gpu_mem,
- nbo->cpu_mem,
- offset, offset, size);
- }
- } else {
- out_mem = nouveau_mem_alloc(ctx, NOUVEAU_MEM_AGP |
- NOUVEAU_MEM_MAPPED,
- size, 0);
- if (out_mem) {
- DEBUG("....via GART\n");
- _mesa_memcpy(out_mem->map,
- nbo->cpu_mem_sys + offset, size);
- nouveau_memformat_flat_emit(ctx, nbo->gpu_mem, out_mem,
- offset, 0, size);
- nouveau_notifier_wait_nop(ctx, nmesa->syncNotifier,
- NvSubMemFormat);
- NOUVEAU_MEM_FREE(out_mem);
- } else {
- DEBUG("....direct VRAM copy\n");
- _mesa_memcpy(nbo->gpu_mem->map + offset,
- nbo->cpu_mem_sys + offset,
- size);
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean
-nouveau_bo_move_in(GLcontext *ctx, struct gl_buffer_object *bo)
-{
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
-
- DEBUG("bo=%p\n", bo);
-
- if (bo->OnCard)
- return GL_TRUE;
- assert(nbo->gpu_mem_flags);
-
- nbo->gpu_mem = nouveau_mem_alloc(ctx, nbo->gpu_mem_flags |
- NOUVEAU_MEM_MAPPED,
- bo->Size, 0);
- assert(nbo->gpu_mem);
-
- if (nbo->cpu_mem_flags) {
- if ((nbo->cpu_mem_flags|NOUVEAU_MEM_MAPPED) != nbo->gpu_mem->type) {
- DEBUG("..need cpu_mem buffer\n");
-
- nbo->cpu_mem = nouveau_mem_alloc(ctx,
- nbo->cpu_mem_flags |
- NOUVEAU_MEM_MAPPED,
- bo->Size, 0);
-
- if (nbo->cpu_mem) {
- DEBUG("....alloc ok, kill sys_mem buffer\n");
- _mesa_memcpy(nbo->cpu_mem->map,
- nbo->cpu_mem_sys, bo->Size);
- FREE(nbo->cpu_mem_sys);
- }
- } else {
- DEBUG("..cpu direct access to GPU buffer\n");
- nbo->cpu_mem = nbo->gpu_mem;
- }
- }
- nouveau_bo_upload_to_screen(ctx, 0, bo->Size, bo);
-
- bo->OnCard = GL_TRUE;
- return GL_TRUE;
-}
-
-GLboolean
-nouveau_bo_move_out(GLcontext *ctx, struct gl_buffer_object *bo)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
- GLuint nr_dirty;
-
- DEBUG("bo=%p\n", bo);
- if (!bo->OnCard)
- return GL_TRUE;
-
- nr_dirty = nouveau_bo_download_dirty(ctx, bo);
- if (nbo->cpu_mem) {
- if (nr_dirty && nbo->cpu_mem != nbo->gpu_mem)
- nouveau_notifier_wait_nop(ctx, nmesa->syncNotifier,
- NvSubMemFormat);
- DEBUG("..destroy cpu_mem buffer\n");
- nbo->cpu_mem_sys = malloc(bo->Size);
- assert(nbo->cpu_mem_sys);
- _mesa_memcpy(nbo->cpu_mem_sys, nbo->cpu_mem->map, bo->Size);
- if (nbo->cpu_mem == nbo->gpu_mem)
- nbo->cpu_mem = NULL;
- else
- NOUVEAU_MEM_FREE(nbo->cpu_mem);
- }
- NOUVEAU_MEM_FREE(nbo->gpu_mem);
-
- bo->OnCard = GL_FALSE;
- return GL_TRUE;
-}
-
-static void
-nouveau_bo_choose_storage_method(GLcontext *ctx, GLenum usage,
- struct gl_buffer_object *bo)
-{
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
- GLuint gpu_type = 0;
- GLuint cpu_type = 0;
-
- switch (usage) {
- /* Client source, changes often, used by GL many times */
- case GL_DYNAMIC_DRAW_ARB:
- gpu_type = NOUVEAU_MEM_AGP | NOUVEAU_MEM_FB_ACCEPTABLE;
- cpu_type = NOUVEAU_MEM_AGP;
- break;
- /* GL source, changes often, client reads many times */
- case GL_DYNAMIC_READ_ARB:
- /* Client source, specified once, used by GL many times */
- case GL_STATIC_DRAW_ARB:
- /* GL source, specified once, client reads many times */
- case GL_STATIC_READ_ARB:
- /* Client source, specified once, used by GL a few times */
- case GL_STREAM_DRAW_ARB:
- /* GL source, specified once, client reads a few times */
- case GL_STREAM_READ_ARB:
- /* GL source, changes often, used by GL many times*/
- case GL_DYNAMIC_COPY_ARB:
- /* GL source, specified once, used by GL many times */
- case GL_STATIC_COPY_ARB:
- /* GL source, specified once, used by GL a few times */
- case GL_STREAM_COPY_ARB:
- gpu_type = NOUVEAU_MEM_FB;
- break;
- default:
- assert(0);
- }
-
- nbo->gpu_mem_flags = gpu_type;
- nbo->cpu_mem_flags = cpu_type;
- nbo->usage = usage;
-}
-
-void
-nouveau_bo_init_storage(GLcontext *ctx, GLuint valid_gpu_access,
- GLsizeiptrARB size,
- const GLvoid *data,
- GLenum usage,
- struct gl_buffer_object *bo, int flags)
-{
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
-
- DEBUG("bo=%p\n", bo);
-
- /* Free up previous buffers if we can't reuse them */
- if (nbo->usage != usage ||
- (nbo->gpu_mem && (nbo->gpu_mem->size != size))) {
- if (nbo->cpu_mem_sys)
- FREE(nbo->cpu_mem_sys);
- if (nbo->cpu_mem) {
- if (nbo->cpu_mem != nbo->gpu_mem)
- NOUVEAU_MEM_FREE(nbo->cpu_mem);
- else
- nbo->cpu_mem = NULL;
- }
- if (nbo->gpu_mem)
- NOUVEAU_MEM_FREE(nbo->gpu_mem);
-
- bo->OnCard = GL_FALSE;
- nbo->cpu_mem_sys = calloc(1, size);
- }
-
- nouveau_bo_choose_storage_method(ctx, usage, bo);
- /* Force off flags that may not be ok for a given buffer */
- nbo->gpu_mem_flags &= valid_gpu_access;
-
- bo->Usage = usage;
- bo->Size = size;
-
- if (data) {
- GLvoid *map = nouveau_bo_map(ctx, GL_WRITE_ONLY_ARB, bo);
-#ifdef MESA_BIG_ENDIAN
- int i;
- if (flags) {
- for (i = 0; i < size; i+=4) {
- uint32_t _data = *(unsigned int *)(data+i);
- _data = ((_data >> 16) | ((_data & 0xffff) << 16));
- *(unsigned int *)(map+i) = _data;
- }
- } else
-#endif
- _mesa_memcpy(map, data, size);
- (void)flags; /* get rid of warning */
- nouveau_bo_dirty_all(ctx, GL_FALSE, bo);
- nouveau_bo_unmap(ctx, bo);
- }
-}
-
-void *
-nouveau_bo_map(GLcontext *ctx, GLenum access, struct gl_buffer_object *bo)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
-
- DEBUG("bo=%p, access=%s\n", bo, _mesa_lookup_enum_by_nr(access));
-
- if (bo->OnCard &&
- (access == GL_READ_ONLY_ARB || access == GL_READ_WRITE_ARB)) {
- GLuint nr_dirty;
-
- DEBUG("..on card\n");
- nr_dirty = nouveau_bo_download_dirty(ctx, bo);
-
- /* nouveau_bo_download_dirty won't wait unless it needs to
- * free a temp buffer, which isn't the case if cpu_mem is
- * present.
- */
- if (nr_dirty && nbo->cpu_mem && nbo->cpu_mem != nbo->gpu_mem)
- nouveau_notifier_wait_nop(ctx, nmesa->syncNotifier,
- NvSubMemFormat);
- }
-
- if (nbo->cpu_mem) {
- DEBUG("..access via cpu_mem\n");
- return nbo->cpu_mem->map;
- } else {
- DEBUG("..access via cpu_mem_sys\n");
- return nbo->cpu_mem_sys;
- }
-}
-
-void
-nouveau_bo_unmap(GLcontext *ctx, struct gl_buffer_object *bo)
-{
- DEBUG("unmap bo=%p\n", bo);
-}
-
-uint32_t
-nouveau_bo_gpu_ref(GLcontext *ctx, struct gl_buffer_object *bo)
-{
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
-
- assert(nbo->mapped == GL_FALSE);
-
- DEBUG("gpu_ref\n");
-
- if (!bo->OnCard) {
- nouveau_bo_move_in(ctx, bo);
- bo->OnCard = GL_TRUE;
- }
- nouveau_bo_upload_dirty(ctx, bo);
-
- return nouveau_mem_gpu_offset_get(ctx, nbo->gpu_mem);
-}
-
-void
-nouveau_bo_dirty_linear(GLcontext *ctx, GLboolean on_card,
- uint32_t offset, uint32_t size,
- struct gl_buffer_object *bo)
-{
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
- nouveau_bufferobj_dirty *dirty;
- uint32_t start = offset;
- uint32_t end = offset + size;
- int i;
-
- if (nbo->cpu_mem == nbo->gpu_mem)
- return;
-
- dirty = on_card ? &nbo->gpu_dirty : &nbo->cpu_dirty;
-
- DEBUG("on_card=%d, offset=%d, size=%d, bo=%p\n",
- on_card, offset, size, bo);
-
- for (i=0; inr_dirty; i++) {
- nouveau_bufferobj_region *r = &dirty->dirty[i];
-
- /* already dirty */
- if (start >= r->start && end <= r->end) {
- DEBUG("..already dirty\n");
- return;
- }
-
- /* add to the end of a region */
- if (start >= r->start && start <= r->end) {
- if (end > r->end) {
- DEBUG("..extend end of region\n");
- r->end = end;
- return;
- }
- }
-
- /* add to the start of a region */
- if (start < r->start && end >= r->end) {
- DEBUG("..extend start of region\n");
- r->start = start;
- /* .. and to the end */
- if (end > r->end) {
- DEBUG("....and end\n");
- r->end = end;
- }
- return;
- }
- }
-
- /* new region */
- DEBUG("..new dirty\n");
- dirty->nr_dirty++;
- dirty->dirty = realloc(dirty->dirty,
- sizeof(nouveau_bufferobj_region) *
- dirty->nr_dirty);
- dirty->dirty[dirty->nr_dirty - 1].start = start;
- dirty->dirty[dirty->nr_dirty - 1].end = end;
-}
-
-void
-nouveau_bo_dirty_all(GLcontext *ctx, GLboolean on_card,
- struct gl_buffer_object *bo)
-{
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
- nouveau_bufferobj_dirty *dirty;
-
- dirty = on_card ? &nbo->gpu_dirty : &nbo->cpu_dirty;
-
- DEBUG("dirty all\n");
- if (dirty->nr_dirty) {
- FREE(dirty->dirty);
- dirty->dirty = NULL;
- dirty->nr_dirty = 0;
- }
-
- nouveau_bo_dirty_linear(ctx, on_card, 0, bo->Size, bo);
-}
-
-GLuint
-nouveau_bo_upload_dirty(GLcontext *ctx, struct gl_buffer_object *bo)
-{
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
- nouveau_bufferobj_dirty *dirty = &nbo->cpu_dirty;
- GLuint nr_dirty;
- int i;
-
- nr_dirty = dirty->nr_dirty;
- if (!nr_dirty) {
- DEBUG("clean\n");
- return nr_dirty;
- }
-
- for (i=0; idirty[i];
-
- DEBUG("dirty %d: o=0x%08x, s=0x%08x\n",
- i, r->start, r->end - r->start);
- nouveau_bo_upload_to_screen(ctx,
- r->start, r->end - r->start, bo);
- }
-
- FREE(dirty->dirty);
- dirty->dirty = NULL;
- dirty->nr_dirty = 0;
-
- return nr_dirty;
-}
-
-GLuint
-nouveau_bo_download_dirty(GLcontext *ctx, struct gl_buffer_object *bo)
-{
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)bo;
- nouveau_bufferobj_dirty *dirty = &nbo->gpu_dirty;
- GLuint nr_dirty;
- int i;
-
- nr_dirty = dirty->nr_dirty;
- if (nr_dirty) {
- DEBUG("clean\n");
- return nr_dirty;
- }
-
- for (i=0; idirty[i];
-
- DEBUG("dirty %d: o=0x%08x, s=0x%08x\n",
- i, r->start, r->end - r->start);
- nouveau_bo_download_from_screen(ctx,
- r->start,
- r->end - r->start, bo);
- }
-
- FREE(dirty->dirty);
- dirty->dirty = NULL;
- dirty->nr_dirty = 0;
-
- return nr_dirty;
-}
-
-static void
-nouveauBindBuffer(GLcontext *ctx, GLenum target, struct gl_buffer_object *obj)
-{
-}
-
-static struct gl_buffer_object *
-nouveauNewBufferObject(GLcontext *ctx, GLuint buffer, GLenum target)
-{
- nouveau_buffer_object *nbo;
-
- nbo = CALLOC_STRUCT(nouveau_buffer_object_t);
- if (nbo)
- _mesa_initialize_buffer_object(&nbo->mesa, buffer, target);
- DEBUG("bo=%p\n", nbo);
-
- return nbo ? &nbo->mesa : NULL;
-}
-
-static void
-nouveauDeleteBuffer(GLcontext *ctx, struct gl_buffer_object *obj)
-{
- nouveau_buffer_object *nbo = (nouveau_buffer_object *)obj;
-
- if (nbo->gpu_dirty.nr_dirty)
- FREE(nbo->gpu_dirty.dirty);
- if (nbo->cpu_dirty.nr_dirty)
- FREE(nbo->cpu_dirty.dirty);
- if (nbo->cpu_mem) nouveau_mem_free(ctx, nbo->cpu_mem);
- if (nbo->gpu_mem) nouveau_mem_free(ctx, nbo->gpu_mem);
-
- _mesa_delete_buffer_object(ctx, obj);
-}
-
-static void
-nouveauBufferData(GLcontext *ctx, GLenum target, GLsizeiptrARB size,
- const GLvoid *data, GLenum usage,
- struct gl_buffer_object *obj)
-{
- GLuint gpu_flags;
-
- DEBUG("target=%s, size=%d, data=%p, usage=%s, obj=%p\n",
- _mesa_lookup_enum_by_nr(target),
- (GLuint)size, data,
- _mesa_lookup_enum_by_nr(usage),
- obj);
-
- switch (target) {
- case GL_ELEMENT_ARRAY_BUFFER_ARB:
- gpu_flags = 0;
- break;
- default:
- gpu_flags = NOUVEAU_BO_VRAM_OK | NOUVEAU_BO_GART_OK;
- break;
- }
- nouveau_bo_init_storage(ctx, gpu_flags, size, data, usage, obj, 0);
-}
-
-static void
-nouveauBufferSubData(GLcontext *ctx, GLenum target, GLintptrARB offset,
- GLsizeiptrARB size, const GLvoid *data,
- struct gl_buffer_object *obj)
-{
- GLvoid *out;
-
- DEBUG("target=%s, offset=0x%x, size=%d, data=%p, obj=%p\n",
- _mesa_lookup_enum_by_nr(target),
- (GLuint)offset, (GLuint)size, data, obj);
-
- out = nouveau_bo_map(ctx, GL_WRITE_ONLY_ARB, obj);
- _mesa_memcpy(out + offset, data, size);
- nouveau_bo_dirty_linear(ctx, GL_FALSE, offset, size, obj);
- nouveau_bo_unmap(ctx, obj);
-}
-
-static void
-nouveauGetBufferSubData(GLcontext *ctx, GLenum target, GLintptrARB offset,
- GLsizeiptrARB size, GLvoid *data,
- struct gl_buffer_object *obj)
-{
- const GLvoid *in;
-
- DEBUG("target=%s, offset=0x%x, size=%d, data=%p, obj=%p\n",
- _mesa_lookup_enum_by_nr(target),
- (GLuint)offset, (GLuint)size, data, obj);
-
- in = nouveau_bo_map(ctx, GL_READ_ONLY_ARB, obj);
- _mesa_memcpy(data, in + offset, size);
- nouveau_bo_unmap(ctx, obj);
-}
-
-static void *
-nouveauMapBuffer(GLcontext *ctx, GLenum target, GLenum access,
- struct gl_buffer_object *obj)
-{
- DEBUG("target=%s, access=%s, obj=%p\n",
- _mesa_lookup_enum_by_nr(target),
- _mesa_lookup_enum_by_nr(access),
- obj
- );
-
- /* Already mapped.. */
- if (obj->Pointer)
- return NULL;
-
- /* Have to pass READ_WRITE here, nouveau_bo_map will only ensure that
- * the cpu_mem buffer is up-to-date if we ask for read access.
- *
- * However, even if the client only asks for write access, we're still
- * forced to reupload the entire buffer. So, we need the cpu_mem buffer
- * to have the correct data all the time.
- */
- obj->Pointer = nouveau_bo_map(ctx, GL_READ_WRITE_ARB, obj);
-
- /* The GL spec says that a client attempting to write to a bufferobj
- * mapped READ_ONLY object may have unpredictable results, possibly
- * even program termination.
- *
- * We're going to use this, and only mark the buffer as dirtied if
- * the client asks for write access.
- */
- if (target != GL_READ_ONLY_ARB) {
- /* We have no way of knowing what was modified by the client,
- * so the entire buffer gets dirtied. */
- nouveau_bo_dirty_all(ctx, GL_FALSE, obj);
- }
-
- return obj->Pointer;
-}
-
-static GLboolean
-nouveauUnmapBuffer(GLcontext *ctx, GLenum target, struct gl_buffer_object *obj)
-{
- DEBUG("target=%s, obj=%p\n", _mesa_lookup_enum_by_nr(target), obj);
-
- assert(obj->Pointer);
-
- nouveau_bo_unmap(ctx, obj);
- obj->Pointer = NULL;
- return GL_TRUE;
-}
-
-void
-nouveauInitBufferObjects(GLcontext *ctx)
-{
- ctx->Driver.BindBuffer = nouveauBindBuffer;
- ctx->Driver.NewBufferObject = nouveauNewBufferObject;
- ctx->Driver.DeleteBuffer = nouveauDeleteBuffer;
- ctx->Driver.BufferData = nouveauBufferData;
- ctx->Driver.BufferSubData = nouveauBufferSubData;
- ctx->Driver.GetBufferSubData = nouveauGetBufferSubData;
- ctx->Driver.MapBuffer = nouveauMapBuffer;
- ctx->Driver.UnmapBuffer = nouveauUnmapBuffer;
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.h b/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.h
deleted file mode 100644
index fb3afc1c30..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.h
+++ /dev/null
@@ -1,77 +0,0 @@
-#ifndef __NOUVEAU_BUFFEROBJ_H__
-#define __NOUVEAU_BUFFEROBJ_H__
-
-#include "mtypes.h"
-#include "nouveau_mem.h"
-
-#define NOUVEAU_BO_VRAM_OK (NOUVEAU_MEM_FB | NOUVEAU_MEM_FB_ACCEPTABLE)
-#define NOUVEAU_BO_GART_OK (NOUVEAU_MEM_AGP | NOUVEAU_MEM_AGP_ACCEPTABLE)
-
-typedef struct nouveau_bufferobj_region_t {
- uint32_t start;
- uint32_t end;
-} nouveau_bufferobj_region;
-
-typedef struct nouveau_bufferobj_dirty_t {
- nouveau_bufferobj_region *dirty;
- int nr_dirty;
-} nouveau_bufferobj_dirty;
-
-typedef struct nouveau_buffer_object_t {
- /* Base class, must be first */
- struct gl_buffer_object mesa;
-
- GLboolean mapped;
- GLenum usage;
-
- /* Memory used for GPU access to the buffer*/
- GLuint gpu_mem_flags;
- nouveau_mem * gpu_mem;
- nouveau_bufferobj_dirty gpu_dirty;
-
- /* Memory used for CPU access to the buffer */
- GLuint cpu_mem_flags;
- nouveau_mem * cpu_mem;
- GLvoid * cpu_mem_sys;
- nouveau_bufferobj_dirty cpu_dirty;
-} nouveau_buffer_object;
-
-extern void
-nouveau_bo_init_storage(GLcontext *ctx, GLuint valid_gpu_access,
- GLsizeiptrARB size, const GLvoid *data, GLenum usage,
- struct gl_buffer_object *bo, int flags);
-
-extern GLboolean
-nouveau_bo_move_in(GLcontext *ctx, struct gl_buffer_object *bo);
-
-extern GLboolean
-nouveau_bo_move_out(GLcontext *ctx, struct gl_buffer_object *bo);
-
-extern void *
-nouveau_bo_map(GLcontext *ctx, GLenum usage, struct gl_buffer_object *bo);
-
-extern void
-nouveau_bo_unmap(GLcontext *ctx, struct gl_buffer_object *bo);
-
-extern uint32_t
-nouveau_bo_gpu_ref(GLcontext *ctx, struct gl_buffer_object *bo);
-
-extern void
-nouveau_bo_dirty_linear(GLcontext *ctx, GLboolean on_card,
- uint32_t offset, uint32_t size,
- struct gl_buffer_object *bo);
-
-extern void
-nouveau_bo_dirty_all(GLcontext *ctx, GLboolean on_card,
- struct gl_buffer_object *bo);
-
-extern GLuint
-nouveau_bo_upload_dirty(GLcontext *ctx, struct gl_buffer_object *bo);
-
-extern GLuint
-nouveau_bo_download_dirty(GLcontext *ctx, struct gl_buffer_object *bo);
-
-extern void
-nouveauInitBufferObjects(GLcontext *ctx);
-
-#endif
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_card.c b/src/mesa/drivers/dri/nouveau/nouveau_card.c
deleted file mode 100644
index 91f12f0d70..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_card.c
+++ /dev/null
@@ -1,17 +0,0 @@
-
-#include "nouveau_card.h"
-#include "nouveau_reg.h"
-#include "nouveau_drm.h"
-#include "nouveau_card_list.h"
-
-
-nouveau_card* nouveau_card_lookup(uint32_t device_id)
-{
- int i;
- for(i=0;idriScreenPriv;
- struct dd_function_table functions;
- nouveauContextPtr nmesa;
- nouveauScreenPtr screen;
-
- /* Allocate the context */
- nmesa = (nouveauContextPtr) CALLOC( sizeof(*nmesa) );
- if ( !nmesa )
- return GL_FALSE;
-
- nmesa->driContext = driContextPriv;
- nmesa->driScreen = sPriv;
- nmesa->driDrawable = NULL;
- nmesa->hHWContext = driContextPriv->hHWContext;
- nmesa->driHwLock = &sPriv->pSAREA->lock;
- nmesa->driFd = sPriv->fd;
-
- nmesa->screen = (nouveauScreenPtr)(sPriv->private);
- screen=nmesa->screen;
-
- /* Create the hardware context */
- if (!nouveauDRMGetParam(nmesa, NOUVEAU_GETPARAM_FB_PHYSICAL,
- &nmesa->vram_phys))
- return GL_FALSE;
- if (!nouveauDRMGetParam(nmesa, NOUVEAU_GETPARAM_FB_SIZE,
- &nmesa->vram_size))
- return GL_FALSE;
- if (!nouveauDRMGetParam(nmesa, NOUVEAU_GETPARAM_AGP_PHYSICAL,
- &nmesa->gart_phys))
- return GL_FALSE;
- if (!nouveauDRMGetParam(nmesa, NOUVEAU_GETPARAM_AGP_SIZE,
- &nmesa->gart_size))
- return GL_FALSE;
- if (!nouveauFifoInit(nmesa))
- return GL_FALSE;
- nouveauObjectInit(nmesa);
-
-
- /* Init default driver functions then plug in our nouveau-specific functions
- * (the texture functions are especially important)
- */
- _mesa_init_driver_functions( &functions );
- nouveauDriverInitFunctions( &functions );
- nouveauTexInitFunctions( &functions );
-
- /* Allocate the Mesa context */
- if (sharedContextPrivate)
- shareCtx = ((nouveauContextPtr) sharedContextPrivate)->glCtx;
- else
- shareCtx = NULL;
- nmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
- &functions, (void *) nmesa);
- if (!nmesa->glCtx) {
- FREE(nmesa);
- return GL_FALSE;
- }
- driContextPriv->driverPrivate = nmesa;
- ctx = nmesa->glCtx;
-
- /* Parse configuration files */
- driParseConfigFiles (&nmesa->optionCache, &screen->optionCache,
- screen->driScreen->myNum, "nouveau");
-
- nmesa->sarea = (struct drm_nouveau_sarea *)((char *)sPriv->pSAREA +
- screen->sarea_priv_offset);
-
- /* Enable any supported extensions */
- driInitExtensions(ctx, common_extensions, GL_TRUE);
- if (nmesa->screen->card->type >= NV_10)
- driInitExtensions(ctx, nv10_extensions, GL_FALSE);
- if (nmesa->screen->card->type >= NV_20)
- driInitExtensions(ctx, nv20_extensions, GL_FALSE);
- if (nmesa->screen->card->type >= NV_30)
- driInitExtensions(ctx, nv30_extensions, GL_FALSE);
- if (nmesa->screen->card->type >= NV_40)
- driInitExtensions(ctx, nv40_extensions, GL_FALSE);
- if (nmesa->screen->card->type >= NV_50)
- driInitExtensions(ctx, nv50_extensions, GL_FALSE);
-
- nmesa->current_primitive = -1;
-
- nouveauShaderInitFuncs(ctx);
- /* Install Mesa's fixed-function texenv shader support */
- if (nmesa->screen->card->type >= NV_40)
- ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
-
- /* Initialize the swrast */
- _swrast_CreateContext( ctx );
- _vbo_CreateContext( ctx );
- _tnl_CreateContext( ctx );
- _swsetup_CreateContext( ctx );
-
- _math_matrix_ctr(&nmesa->viewport);
-
- nouveauDDInitStateFuncs( ctx );
- nouveauSpanInitFunctions( ctx );
- nouveauDDInitState( nmesa );
- switch(nmesa->screen->card->type)
- {
- case NV_04:
- case NV_05:
- nv04TriInitFunctions( ctx );
- break;
- case NV_10:
- case NV_11:
- case NV_17:
- case NV_20:
- case NV_30:
- case NV_40:
- case NV_44:
- case NV_50:
- default:
- nv10TriInitFunctions( ctx );
- break;
- }
-
- nouveauInitBufferObjects(ctx);
- if (!nouveauSyncInitFuncs(ctx))
- return GL_FALSE;
- nouveauQueryInitFuncs(ctx);
- nmesa->hw_func.InitCard(nmesa);
- nouveauInitState(ctx);
-
- driContextPriv->driverPrivate = (void *)nmesa;
-
- NOUVEAU_DEBUG = driParseDebugString( getenv( "NOUVEAU_DEBUG" ),
- debug_control );
-
- if (driQueryOptionb(&nmesa->optionCache, "no_rast")) {
- fprintf(stderr, "disabling 3D acceleration\n");
- FALLBACK(nmesa, NOUVEAU_FALLBACK_DISABLE, 1);
- }
-
- return GL_TRUE;
-}
-
-/* Destroy the device specific context. */
-void nouveauDestroyContext( __DRIcontextPrivate *driContextPriv )
-{
- nouveauContextPtr nmesa = (nouveauContextPtr) driContextPriv->driverPrivate;
-
- assert(nmesa);
- if ( nmesa ) {
- /* free the option cache */
- driDestroyOptionCache (&nmesa->optionCache);
-
- FREE( nmesa );
- }
-
-}
-
-
-/* Force the context `c' to be the current context and associate with it
- * buffer `b'.
- */
-GLboolean nouveauMakeCurrent( __DRIcontextPrivate *driContextPriv,
- __DRIdrawablePrivate *driDrawPriv,
- __DRIdrawablePrivate *driReadPriv )
-{
- if ( driContextPriv ) {
- nouveauContextPtr nmesa = (nouveauContextPtr) driContextPriv->driverPrivate;
- struct gl_framebuffer *draw_fb =
- (struct gl_framebuffer*)driDrawPriv->driverPrivate;
- struct gl_framebuffer *read_fb =
- (struct gl_framebuffer*)driReadPriv->driverPrivate;
-
- if (driDrawPriv->swap_interval == (unsigned)-1) {
- driDrawPriv->vblFlags =
- driGetDefaultVBlankFlags(&nmesa->optionCache);
-
- driDrawableInitVBlank(driDrawPriv);
- }
-
- nmesa->driDrawable = driDrawPriv;
-
- _mesa_resize_framebuffer(nmesa->glCtx, draw_fb,
- driDrawPriv->w, driDrawPriv->h);
- if (draw_fb != read_fb) {
- _mesa_resize_framebuffer(nmesa->glCtx, draw_fb,
- driReadPriv->w,
- driReadPriv->h);
- }
- _mesa_make_current(nmesa->glCtx, draw_fb, read_fb);
-
- nouveau_build_framebuffer(nmesa->glCtx,
- driDrawPriv->driverPrivate);
- } else {
- _mesa_make_current( NULL, NULL, NULL );
- }
-
- return GL_TRUE;
-}
-
-
-/* Force the context `c' to be unbound from its buffer.
- */
-GLboolean nouveauUnbindContext( __DRIcontextPrivate *driContextPriv )
-{
- return GL_TRUE;
-}
-
-void
-nouveauDoSwapBuffers(nouveauContextPtr nmesa, __DRIdrawablePrivate *dPriv)
-{
- struct gl_framebuffer *fb;
- nouveauScreenPtr screen = dPriv->driScreenPriv->private;
- nouveau_renderbuffer_t *src;
- drm_clip_rect_t *box;
- int nbox, i;
-
- fb = (struct gl_framebuffer *)dPriv->driverPrivate;
- if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) {
- src = (nouveau_renderbuffer_t *)
- fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
- } else {
- src = (nouveau_renderbuffer_t *)
- fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
- }
-
- LOCK_HARDWARE(nmesa);
- nbox = dPriv->numClipRects;
- box = dPriv->pClipRects;
-
- if (nbox) {
- BEGIN_RING_SIZE(NvSubCtxSurf2D,
- NV10_CONTEXT_SURFACES_2D_FORMAT, 4);
- if (src->mesa._ActualFormat == GL_RGBA8)
- OUT_RING (6); /* X8R8G8B8 */
- else
- OUT_RING (4); /* R5G6B5 */
- OUT_RING(((screen->frontPitch * screen->fbFormat) << 16) |
- src->pitch);
- OUT_RING(src->offset);
- OUT_RING(screen->frontOffset);
- }
-
- for (i=0; iy1 - dPriv->y) << 16) |
- (box->x1 - dPriv->x));
- OUT_RING ((box->y1 << 16) | box->x1);
- OUT_RING (((box->y2 - box->y1) << 16) |
- (box->x2 - box->x1));
- }
- FIRE_RING();
-
- UNLOCK_HARDWARE(nmesa);
-}
-
-void nouveauSwapBuffers(__DRIdrawablePrivate *dPriv)
-{
- if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
- nouveauContextPtr nmesa = dPriv->driContextPriv->driverPrivate;
-
- if (nmesa->glCtx->Visual.doubleBufferMode) {
- _mesa_notifySwapBuffers(nmesa->glCtx);
- nouveauDoSwapBuffers(nmesa, dPriv);
- }
-
- }
-}
-
-void nouveauCopySubBuffer(__DRIdrawablePrivate *dPriv,
- int x, int y, int w, int h)
-{
-}
-
-void nouveauClearBuffer(GLcontext *ctx, nouveau_renderbuffer_t *buffer,
- int fill, int mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- int dimensions;
-
- if (!buffer) {
- return;
- }
-
- /* FIXME: only support 32 bits atm */
-
- /* Surface that we will work on */
- nouveauObjectOnSubchannel(nmesa, NvSubCtxSurf2D, NvCtxSurf2D);
-
- BEGIN_RING_SIZE(NvSubCtxSurf2D, NV10_CONTEXT_SURFACES_2D_FORMAT, 4);
- OUT_RING(0x0b); /* Y32 color format */
- OUT_RING((buffer->pitch<<16)|buffer->pitch);
- OUT_RING(buffer->offset);
- OUT_RING(buffer->offset);
-
- /* Now clear a rectangle */
- dimensions = ((buffer->mesa.Height)<<16) | (buffer->mesa.Width);
-
- nouveauObjectOnSubchannel(nmesa, NvSubGdiRectText, NvGdiRectText);
-
- BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
- OUT_RING(3); /* SRCCOPY */
-
- BEGIN_RING_SIZE(NvSubGdiRectText, NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL, 5);
- OUT_RING(0); /* top left */
- OUT_RING(dimensions); /* bottom right */
- OUT_RING(fill);
- OUT_RING(0); /* top left */
- OUT_RING(dimensions); /* bottom right */
-}
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.h b/src/mesa/drivers/dri/nouveau/nouveau_context.h
deleted file mode 100644
index a617dd6282..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_context.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-
-#ifndef __NOUVEAU_CONTEXT_H__
-#define __NOUVEAU_CONTEXT_H__
-
-#include "dri_util.h"
-#include "drm.h"
-#include "nouveau_drm.h"
-
-#include "mtypes.h"
-#include "tnl/t_vertex.h"
-
-#include "nouveau_fbo.h"
-#include "nouveau_screen.h"
-#include "nouveau_shader.h"
-#include "nouveau_state_cache.h"
-#include "nouveau_sync.h"
-
-#include "xmlconfig.h"
-
-typedef struct nouveau_fifo {
- struct drm_nouveau_channel_alloc drm;
- uint32_t *pushbuf;
- uint32_t *mmio;
- uint32_t *notifier_block;
- uint32_t current;
- uint32_t put;
- uint32_t free;
- uint32_t max;
-} nouveau_fifo_t;
-
-#define TAG(x) nouveau##x
-#include "tnl_dd/t_dd_vertex.h"
-#undef TAG
-
-/* Subpixel offsets for window coordinates (triangles): */
-#define SUBPIXEL_X (0.0F)
-#define SUBPIXEL_Y (0.125F)
-
-struct nouveau_context;
-
-typedef void (*nouveau_tri_func)( struct nouveau_context*,
- nouveauVertex *,
- nouveauVertex *,
- nouveauVertex * );
-
-typedef void (*nouveau_line_func)( struct nouveau_context*,
- nouveauVertex *,
- nouveauVertex * );
-
-typedef void (*nouveau_point_func)( struct nouveau_context*,
- nouveauVertex * );
-
-typedef struct nouveau_hw_func_t {
- /* Initialise any card-specific non-GL related state */
- GLboolean (*InitCard)(struct nouveau_context *);
- /* Update buffer offset/pitch/format */
- GLboolean (*BindBuffers)(struct nouveau_context *, int num_color,
- nouveau_renderbuffer_t **color,
- nouveau_renderbuffer_t *depth);
- /* Update anything that depends on the window position/size */
- void (*WindowMoved)(struct nouveau_context *);
-
- /* Update projection matrix */
- void (*UpdateProjectionMatrix)(GLcontext *);
-
- /* Update modelview matrix (used for lighting and vertex weight) */
- void (*UpdateModelviewMatrix)(GLcontext *);
-} nouveau_hw_func;
-
-typedef struct nouveau_context {
- /* Mesa context */
- GLcontext *glCtx;
-
- /* The per-context fifo */
- nouveau_fifo_t fifo;
-
- /* Physical addresses of AGP/VRAM apertures */
- uint64_t vram_phys;
- uint64_t vram_size;
- uint64_t gart_phys;
- uint64_t gart_size;
-
- /* Channel synchronisation */
- struct drm_nouveau_notifierobj_alloc *syncNotifier;
-
- /* ARB_occlusion_query / EXT_timer_query */
- GLuint query_object_max;
- GLboolean * query_alloc;
- struct drm_nouveau_notifierobj_alloc *queryNotifier;
-
- /* Additional hw-specific functions */
- nouveau_hw_func hw_func;
-
- /* FIXME : do we want to put all state into a separate struct ? */
- /* State for tris */
- GLuint color_offset;
- GLuint specular_offset;
-
- /* Vertex state */
- GLuint vertex_size;
- GLubyte *verts;
- struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
- GLuint vertex_attr_count;
-
- /* Color and depth renderbuffers */
- nouveau_renderbuffer_t *color_buffer;
- nouveau_renderbuffer_t *depth_buffer;
-
- /* Depth/stencil clear value */
- uint32_t clear_value;
-
- /* Light state */
- GLboolean lighting_enabled;
- uint32_t enabled_lights;
-
- /* Cached state */
- nouveau_state_cache state_cache;
-
- /* The drawing fallbacks */
- GLuint Fallback;
- nouveau_tri_func draw_tri;
- nouveau_line_func draw_line;
- nouveau_point_func draw_point;
-
- /* Cliprects information */
- GLuint numClipRects;
- drm_clip_rect_t *pClipRects;
- drm_clip_rect_t osClipRect;
- GLuint drawX, drawY, drawW, drawH;
-
- /* The rendering context information */
- GLenum current_primitive; /* the current primitive enum */
- DECLARE_RENDERINPUTS(render_inputs_bitset); /* the current render inputs */
-
- /* Shader state */
- nvsFunc VPfunc;
- nvsFunc FPfunc;
- nouveauShader *current_fragprog;
- nouveauShader *current_vertprog;
- nouveauShader *passthrough_vp;
- nouveauShader *passthrough_fp;
-
- nouveauScreenRec *screen;
- struct drm_nouveau_sarea *sarea;
-
- __DRIcontextPrivate *driContext; /* DRI context */
- __DRIscreenPrivate *driScreen; /* DRI screen */
- __DRIdrawablePrivate *driDrawable; /* DRI drawable bound to this ctx */
- GLint lastStamp;
-
- drm_context_t hHWContext;
- drm_hw_lock_t *driHwLock;
- int driFd;
-
- /* Configuration cache */
- driOptionCache optionCache;
-
- GLuint new_state;
- GLuint new_render_state;
- GLuint render_index;
- GLmatrix viewport;
- GLfloat depth_scale;
-
-}nouveauContextRec, *nouveauContextPtr;
-
-
-#define NOUVEAU_CONTEXT(ctx) ((nouveauContextPtr)(ctx->DriverCtx))
-
-/* Flags for software fallback cases: */
-#define NOUVEAU_FALLBACK_TEXTURE 0x0001
-#define NOUVEAU_FALLBACK_DRAW_BUFFER 0x0002
-#define NOUVEAU_FALLBACK_READ_BUFFER 0x0004
-#define NOUVEAU_FALLBACK_STENCIL 0x0008
-#define NOUVEAU_FALLBACK_RENDER_MODE 0x0010
-#define NOUVEAU_FALLBACK_LOGICOP 0x0020
-#define NOUVEAU_FALLBACK_SEP_SPECULAR 0x0040
-#define NOUVEAU_FALLBACK_BLEND_EQ 0x0080
-#define NOUVEAU_FALLBACK_BLEND_FUNC 0x0100
-#define NOUVEAU_FALLBACK_PROJTEX 0x0200
-#define NOUVEAU_FALLBACK_DISABLE 0x0400
-
-
-extern GLboolean nouveauCreateContext( const __GLcontextModes *glVisual,
- __DRIcontextPrivate *driContextPriv,
- void *sharedContextPrivate );
-
-extern void nouveauDestroyContext( __DRIcontextPrivate * );
-
-extern GLboolean nouveauMakeCurrent( __DRIcontextPrivate *driContextPriv,
- __DRIdrawablePrivate *driDrawPriv,
- __DRIdrawablePrivate *driReadPriv );
-
-extern GLboolean nouveauUnbindContext( __DRIcontextPrivate *driContextPriv );
-
-extern void nouveauDoSwapBuffers(nouveauContextPtr nmesa,
- __DRIdrawablePrivate *dPriv);
-
-extern void nouveauSwapBuffers(__DRIdrawablePrivate *dPriv);
-
-extern void nouveauCopySubBuffer(__DRIdrawablePrivate *dPriv,
- int x, int y, int w, int h);
-
-extern void nouveauClearBuffer(GLcontext *ctx, nouveau_renderbuffer_t *buffer,
- int fill, int mask);
-
-/* Debugging utils: */
-extern int NOUVEAU_DEBUG;
-
-#define DEBUG_SHADERS 0x00000001
-#define DEBUG_MEM 0x00000002
-#define DEBUG_BUFFEROBJ 0x00000004
-
-#endif /* __NOUVEAU_CONTEXT_H__ */
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_ctrlreg.h b/src/mesa/drivers/dri/nouveau/nouveau_ctrlreg.h
deleted file mode 100644
index c9b2d59007..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_ctrlreg.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin, Sylvain Munaut
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-
-
-#define NV03_STATUS 0x004006b0
-#define NV04_STATUS 0x00400700
-
-#define NV03_FIFO_REGS_SIZE 0x10000
-# define NV03_FIFO_REGS_DMAPUT 0x00000040
-# define NV03_FIFO_REGS_DMAGET 0x00000044
-
-/* Fifo commands. These are not regs, neither masks */
-#define NV03_FIFO_CMD_JUMP 0x20000000
-#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc
-#define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK))
-
-
-#define NONINC_METHOD 0x40000000
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_dri.h b/src/mesa/drivers/dri/nouveau/nouveau_dri.h
deleted file mode 100644
index ce3c3fb9cc..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_dri.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef _NOUVEAU_DRI_
-#define _NOUVEAU_DRI_
-
-#include "xf86drm.h"
-#include "drm.h"
-#include "nouveau_drm.h"
-
-typedef struct {
- uint32_t device_id; /**< \brief PCI device ID */
- uint32_t width; /**< \brief width in pixels of display */
- uint32_t height; /**< \brief height in scanlines of display */
- uint32_t depth; /**< \brief depth of display (8, 15, 16, 24) */
- uint32_t bpp; /**< \brief bit depth of display (8, 16, 24, 32) */
-
- uint32_t bus_type; /**< \brief ths bus type */
- uint32_t bus_mode; /**< \brief bus mode (used for AGP, maybe also for PCI-E ?) */
-
- uint32_t front_offset; /**< \brief front buffer offset */
- uint32_t front_pitch; /**< \brief front buffer pitch */
- uint32_t back_offset; /**< \brief private back buffer offset */
- uint32_t back_pitch; /**< \brief private back buffer pitch */
- uint32_t depth_offset; /**< \brief private depth buffer offset */
- uint32_t depth_pitch; /**< \brief private depth buffer pitch */
-
-} NOUVEAUDRIRec, *NOUVEAUDRIPtr;
-
-#endif
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_driver.c b/src/mesa/drivers/dri/nouveau/nouveau_driver.c
deleted file mode 100644
index 7bd42fdfe2..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_driver.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-#include "nouveau_context.h"
-//#include "nouveau_state.h"
-#include "nouveau_lock.h"
-#include "nouveau_fifo.h"
-#include "nouveau_driver.h"
-#include "swrast/swrast.h"
-
-#include "context.h"
-#include "framebuffer.h"
-
-#include "utils.h"
-#include "colormac.h"
-
-/* Wrapper for DRM_NOUVEAU_GETPARAM ioctl */
-GLboolean nouveauDRMGetParam(nouveauContextPtr nmesa,
- unsigned int param,
- uint64_t* value)
-{
- struct drm_nouveau_getparam getp;
-
- getp.param = param;
- if (!value || drmCommandWriteRead(nmesa->driFd, DRM_NOUVEAU_GETPARAM,
- &getp, sizeof(getp)))
- return GL_FALSE;
- *value = getp.value;
- return GL_TRUE;
-}
-
-/* Wrapper for DRM_NOUVEAU_GETPARAM ioctl */
-GLboolean nouveauDRMSetParam(nouveauContextPtr nmesa,
- unsigned int param,
- uint64_t value)
-{
- struct drm_nouveau_setparam setp;
-
- setp.param = param;
- setp.value = value;
- if (drmCommandWrite(nmesa->driFd, DRM_NOUVEAU_SETPARAM, &setp,
- sizeof(setp)))
- return GL_FALSE;
- return GL_TRUE;
-}
-
-/* Return the width and height of the current color buffer */
-static void nouveauGetBufferSize( GLframebuffer *buffer,
- GLuint *width, GLuint *height )
-{
- GET_CURRENT_CONTEXT(ctx);
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- LOCK_HARDWARE( nmesa );
- *width = nmesa->driDrawable->w;
- *height = nmesa->driDrawable->h;
- UNLOCK_HARDWARE( nmesa );
-}
-
-/* glGetString */
-static const GLubyte *nouveauGetString( GLcontext *ctx, GLenum name )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- static char buffer[128];
- const char * card_name = "Unknown";
- GLuint agp_mode = 0;
-
- switch ( name ) {
- case GL_VENDOR:
- return (GLubyte *)DRIVER_AUTHOR;
-
- case GL_RENDERER:
- card_name=nmesa->screen->card->name;
-
- switch(nmesa->screen->bus_type)
- {
- case NV_PCI:
- case NV_PCIE:
- default:
- agp_mode=0;
- break;
- case NV_AGP:
- agp_mode=nmesa->screen->agp_mode;
- break;
- }
- driGetRendererString( buffer, card_name, DRIVER_DATE,
- agp_mode );
- return (GLubyte *)buffer;
- default:
- return NULL;
- }
-}
-
-/* glFlush */
-static void nouveauFlush( GLcontext *ctx )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (ctx->DrawBuffer->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT)
- nouveauDoSwapBuffers(nmesa, nmesa->driDrawable);
- FIRE_RING();
-}
-
-/* glFinish */
-static void nouveauFinish( GLcontext *ctx )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- nouveauFlush( ctx );
- nouveauWaitForIdle( nmesa );
-}
-
-/* glClear */
-static void nouveauClear( GLcontext *ctx, GLbitfield mask )
-{
- uint32_t clear_value;
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- /* FIXME: should we clear front buffer, even if asked to do it? */
- if (mask & (BUFFER_BIT_FRONT_LEFT|BUFFER_BIT_BACK_LEFT)) {
- GLubyte c[4];
- int color_bits = 32;
- int color_mask = 0xffffffff;
-
- UNCLAMPED_FLOAT_TO_RGBA_CHAN(c,ctx->Color.ClearColor);
- clear_value = PACK_COLOR_8888(c[3],c[0],c[1],c[2]);
-
- if (ctx->DrawBuffer) {
- /* FIXME: find correct color buffer, instead of [0] */
- if (ctx->DrawBuffer->_ColorDrawBuffers[0]) {
- color_bits = ctx->DrawBuffer->_ColorDrawBuffers[0]->RedBits;
- color_bits += ctx->DrawBuffer->_ColorDrawBuffers[0]->GreenBits;
- color_bits += ctx->DrawBuffer->_ColorDrawBuffers[0]->BlueBits;
- color_bits += ctx->DrawBuffer->_ColorDrawBuffers[0]->AlphaBits;
- }
- }
-
- if (color_bits<24) {
- clear_value = PACK_COLOR_565(c[0],c[1],c[2]);
- color_mask = 0xffff;
- }
-
- nouveauClearBuffer(ctx, nmesa->color_buffer,
- clear_value, color_mask);
- }
-
- if (mask & (BUFFER_BIT_DEPTH)) {
- int depth_bits = 24;
- int depth_mask;
- if (ctx->DrawBuffer) {
- if (ctx->DrawBuffer->_DepthBuffer) {
- depth_bits = ctx->DrawBuffer->_DepthBuffer->DepthBits;
- }
- }
-
- switch(depth_bits) {
- case 16:
- clear_value = (uint32_t) (ctx->Depth.Clear * 32767.0);
- depth_mask = 0xffff;
- break;
- default:
- clear_value = ((uint32_t) (ctx->Depth.Clear * 16777215.0)) << 8;
- depth_mask = 0xffffff00;
- break;
- }
-
- nouveauClearBuffer(ctx, nmesa->depth_buffer,
- clear_value, depth_mask);
- }
-
- if (mask & (BUFFER_BIT_STENCIL)) {
- int stencil_bits = 0;
- if (ctx->DrawBuffer) {
- if (ctx->DrawBuffer->_StencilBuffer) {
- stencil_bits = ctx->DrawBuffer->_StencilBuffer->StencilBits;
- }
- }
-
- if (stencil_bits>0) {
- nouveauClearBuffer(ctx, nmesa->depth_buffer,
- ctx->Stencil.Clear, (1<GetBufferSize = nouveauGetBufferSize;
- functions->ResizeBuffers = _mesa_resize_framebuffer;
- functions->GetString = nouveauGetString;
- functions->Flush = nouveauFlush;
- functions->Finish = nouveauFinish;
- functions->Clear = nouveauClear;
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_driver.h b/src/mesa/drivers/dri/nouveau/nouveau_driver.h
deleted file mode 100644
index 6164012b5b..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_driver.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-
-#ifndef __NOUVEAU_DRIVER_H__
-#define __NOUVEAU_DRIVER_H__
-
-#define DRIVER_DATE "20060219"
-#define DRIVER_AUTHOR "Stephane Marchesin"
-
-extern void nouveauDriverInitFunctions( struct dd_function_table *functions );
-extern GLboolean nouveauDRMGetParam(nouveauContextPtr nmesa, unsigned int param,
- uint64_t *value);
-extern GLboolean nouveauDRMSetParam(nouveauContextPtr nmesa, unsigned int param,
- uint64_t value);
-
-#endif /* __NOUVEAU_DRIVER_H__ */
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_fbo.c b/src/mesa/drivers/dri/nouveau/nouveau_fbo.c
deleted file mode 100644
index 23525509d1..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_fbo.c
+++ /dev/null
@@ -1,289 +0,0 @@
-#include "utils.h"
-#include "framebuffer.h"
-#include "renderbuffer.h"
-#include "fbobject.h"
-
-#include "nouveau_context.h"
-#include "nouveau_fbo.h"
-#include "nouveau_fifo.h"
-#include "nouveau_msg.h"
-#include "nouveau_object.h"
-#include "nouveau_reg.h"
-
-static GLboolean
-nouveau_renderbuffer_pixelformat(nouveau_renderbuffer_t * nrb,
- GLenum internalFormat)
-{
- nrb->mesa.InternalFormat = internalFormat;
-
- /*TODO: We probably want to extend this a bit, and maybe make
- * card-specific?
- */
- switch (internalFormat) {
- case GL_RGBA:
- case GL_RGBA8:
- nrb->mesa._BaseFormat = GL_RGBA;
- nrb->mesa._ActualFormat = GL_RGBA8;
- nrb->mesa.DataType = GL_UNSIGNED_BYTE;
- nrb->mesa.RedBits = 8;
- nrb->mesa.GreenBits = 8;
- nrb->mesa.BlueBits = 8;
- nrb->mesa.AlphaBits = 8;
- nrb->cpp = 4;
- break;
- case GL_RGB:
- case GL_RGB5:
- nrb->mesa._BaseFormat = GL_RGB;
- nrb->mesa._ActualFormat = GL_RGB5;
- nrb->mesa.DataType = GL_UNSIGNED_BYTE;
- nrb->mesa.RedBits = 5;
- nrb->mesa.GreenBits = 6;
- nrb->mesa.BlueBits = 5;
- nrb->mesa.AlphaBits = 0;
- nrb->cpp = 2;
- break;
- case GL_DEPTH_COMPONENT16:
- nrb->mesa._BaseFormat = GL_DEPTH_COMPONENT;
- nrb->mesa._ActualFormat = GL_DEPTH_COMPONENT16;
- nrb->mesa.DataType = GL_UNSIGNED_SHORT;
- nrb->mesa.DepthBits = 16;
- nrb->cpp = 2;
- break;
- case GL_DEPTH_COMPONENT24:
- nrb->mesa._BaseFormat = GL_DEPTH_COMPONENT;
- nrb->mesa._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
- nrb->mesa.DataType = GL_UNSIGNED_INT_24_8_EXT;
- nrb->mesa.DepthBits = 24;
- nrb->cpp = 4;
- break;
- case GL_STENCIL_INDEX8_EXT:
- nrb->mesa._BaseFormat = GL_STENCIL_INDEX;
- nrb->mesa._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
- nrb->mesa.DataType = GL_UNSIGNED_INT_24_8_EXT;
- nrb->mesa.StencilBits = 8;
- nrb->cpp = 4;
- break;
- case GL_DEPTH24_STENCIL8_EXT:
- nrb->mesa._BaseFormat = GL_DEPTH_STENCIL_EXT;
- nrb->mesa._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
- nrb->mesa.DataType = GL_UNSIGNED_INT_24_8_EXT;
- nrb->mesa.DepthBits = 24;
- nrb->mesa.StencilBits = 8;
- nrb->cpp = 4;
- break;
- default:
- return GL_FALSE;
- break;
- }
-
- return GL_TRUE;
-}
-
-static GLboolean
-nouveau_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
- GLenum internalFormat,
- GLuint width, GLuint height)
-{
- nouveau_renderbuffer_t *nrb = (nouveau_renderbuffer_t *) rb;
-
- if (!nouveau_renderbuffer_pixelformat(nrb, internalFormat)) {
- fprintf(stderr, "%s: unknown internalFormat\n", __func__);
- return GL_FALSE;
- }
-
- /* If this buffer isn't statically alloc'd, we may need to ask the
- * drm for more memory */
- if (rb->Width != width || rb->Height != height) {
- GLuint pitch;
-
- /* align pitches to 64 bytes */
- pitch = ((width * nrb->cpp) + 63) & ~63;
-
- if (nrb->mem)
- nouveau_mem_free(ctx, nrb->mem);
- nrb->mem = nouveau_mem_alloc(ctx,
- NOUVEAU_MEM_FB |
- NOUVEAU_MEM_MAPPED,
- pitch * height, 0);
- if (!nrb->mem)
- return GL_FALSE;
-
- /* update nouveau_renderbuffer info */
- nrb->offset = nouveau_mem_gpu_offset_get(ctx, nrb->mem);
- nrb->pitch = pitch;
- }
-
- rb->Width = width;
- rb->Height = height;
- rb->InternalFormat = internalFormat;
-
- nouveauSpanSetFunctions(nrb);
-
- return GL_TRUE;
-}
-
-static void
-nouveau_renderbuffer_delete(struct gl_renderbuffer *rb)
-{
- GET_CURRENT_CONTEXT(ctx);
- nouveau_renderbuffer_t *nrb = (nouveau_renderbuffer_t *) rb;
-
- if (nrb->mem)
- nouveau_mem_free(ctx, nrb->mem);
- FREE(nrb);
-}
-
-nouveau_renderbuffer_t *
-nouveau_renderbuffer_new(GLenum internalFormat)
-{
- nouveau_renderbuffer_t *nrb;
-
- nrb = CALLOC_STRUCT(nouveau_renderbuffer);
- if (!nrb)
- return NULL;
-
- _mesa_init_renderbuffer(&nrb->mesa, 0);
-
- if (!nouveau_renderbuffer_pixelformat(nrb, internalFormat)) {
- fprintf(stderr, "%s: unknown internalFormat\n", __func__);
- return GL_FALSE;
- }
-
- nrb->mesa.AllocStorage = nouveau_renderbuffer_storage;
- nrb->mesa.Delete = nouveau_renderbuffer_delete;
-
- return nrb;
-}
-
-static void
-nouveau_cliprects_renderbuffer_set(nouveauContextPtr nmesa,
- nouveau_renderbuffer_t * nrb)
-{
- nmesa->numClipRects = 1;
- nmesa->pClipRects = &nmesa->osClipRect;
- nmesa->osClipRect.x1 = 0;
- nmesa->osClipRect.y1 = 0;
- nmesa->osClipRect.x2 = nrb->mesa.Width;
- nmesa->osClipRect.y2 = nrb->mesa.Height;
- nmesa->drawX = 0;
- nmesa->drawY = 0;
- nmesa->drawW = nrb->mesa.Width;
- nmesa->drawH = nrb->mesa.Height;
-}
-
-void
-nouveau_window_moved(GLcontext * ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nouveau_renderbuffer_t *nrb;
-
- nrb = (nouveau_renderbuffer_t *) ctx->DrawBuffer->_ColorDrawBuffers[0];
- if (!nrb)
- return;
-
- nouveau_cliprects_renderbuffer_set(nmesa, nrb);
-
- /* Viewport depends on window size/position, nouveauCalcViewport
- * will take care of calling the hw-specific WindowMoved
- */
- ctx->Driver.Viewport(ctx, ctx->Viewport.X, ctx->Viewport.Y,
- ctx->Viewport.Width, ctx->Viewport.Height);
- /* Scissor depends on window position */
- ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
- ctx->Scissor.Width, ctx->Scissor.Height);
-}
-
-GLboolean
-nouveau_build_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nouveau_renderbuffer_t *color[MAX_DRAW_BUFFERS];
- nouveau_renderbuffer_t *depth;
-
- _mesa_update_framebuffer(ctx);
- _mesa_update_draw_buffer_bounds(ctx);
-
- color[0] = (nouveau_renderbuffer_t *) fb->_ColorDrawBuffers[0];
- if (fb->_DepthBuffer && fb->_DepthBuffer->Wrapped)
- depth = (nouveau_renderbuffer_t *) fb->_DepthBuffer->Wrapped;
- else
- depth = (nouveau_renderbuffer_t *) fb->_DepthBuffer;
-
- if (!nmesa->hw_func.BindBuffers(nmesa, 1, color, depth))
- return GL_FALSE;
- nouveau_window_moved(ctx);
-
- return GL_TRUE;
-}
-
-static void
-nouveauDrawBuffer(GLcontext *ctx, GLenum buffer)
-{
- nouveau_build_framebuffer(ctx, ctx->DrawBuffer);
-}
-
-static struct gl_framebuffer *
-nouveauNewFramebuffer(GLcontext *ctx, GLuint name)
-{
- return _mesa_new_framebuffer(ctx, name);
-}
-
-static struct gl_renderbuffer *
-nouveauNewRenderbuffer(GLcontext *ctx, GLuint name)
-{
- nouveau_renderbuffer_t *nrb;
-
- nrb = CALLOC_STRUCT(nouveau_renderbuffer);
- if (!nrb)
- return NULL;
-
- _mesa_init_renderbuffer(&nrb->mesa, name);
-
- nrb->mesa.AllocStorage = nouveau_renderbuffer_storage;
- nrb->mesa.Delete = nouveau_renderbuffer_delete;
- return &nrb->mesa;
-}
-
-static void
-nouveauBindFramebuffer(GLcontext *ctx, GLenum target,
- struct gl_framebuffer *fb,
- struct gl_framebuffer *fbread)
-{
- if (target == GL_FRAMEBUFFER_EXT || target == GL_DRAW_FRAMEBUFFER_EXT) {
- nouveau_build_framebuffer(ctx, fb);
- }
-}
-
-static void
-nouveauFramebufferRenderbuffer(GLcontext *ctx, struct gl_framebuffer *fb,
- GLenum attachment, struct gl_renderbuffer *rb)
-{
- _mesa_framebuffer_renderbuffer(ctx, fb, attachment, rb);
- nouveau_build_framebuffer(ctx, fb);
-}
-
-static void
-nouveauRenderTexture(GLcontext * ctx, struct gl_framebuffer *fb,
- struct gl_renderbuffer_attachment *att)
-{
-}
-
-static void
-nouveauFinishRenderTexture(GLcontext * ctx,
- struct gl_renderbuffer_attachment *att)
-{
-}
-
-void
-nouveauInitBufferFuncs(struct dd_function_table *func)
-{
- func->DrawBuffer = nouveauDrawBuffer;
-
- func->NewFramebuffer = nouveauNewFramebuffer;
- func->NewRenderbuffer = nouveauNewRenderbuffer;
- func->BindFramebuffer = nouveauBindFramebuffer;
- func->FramebufferRenderbuffer = nouveauFramebufferRenderbuffer;
- func->RenderTexture = nouveauRenderTexture;
- func->FinishRenderTexture = nouveauFinishRenderTexture;
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_fbo.h b/src/mesa/drivers/dri/nouveau/nouveau_fbo.h
deleted file mode 100644
index 787af4e9e4..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_fbo.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __NOUVEAU_BUFFERS_H__
-#define __NOUVEAU_BUFFERS_H__
-
-#include
-#include "mtypes.h"
-#include "utils.h"
-#include "renderbuffer.h"
-
-#include "nouveau_mem.h"
-
-typedef struct nouveau_renderbuffer {
- struct gl_renderbuffer mesa; /* must be first! */
-
- nouveau_mem *mem;
- void *map;
-
- int cpp;
- uint32_t offset;
- uint32_t pitch;
-} nouveau_renderbuffer_t;
-
-extern nouveau_renderbuffer_t *nouveau_renderbuffer_new(GLenum internalFormat);
-extern void nouveau_window_moved(GLcontext *);
-extern GLboolean nouveau_build_framebuffer(GLcontext *,
- struct gl_framebuffer *);
-extern nouveau_renderbuffer_t *nouveau_current_draw_buffer(GLcontext *);
-
-extern void nouveauInitBufferFuncs(struct dd_function_table *);
-
-#endif
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_fifo.c b/src/mesa/drivers/dri/nouveau/nouveau_fifo.c
deleted file mode 100644
index 5dc94e0520..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_fifo.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-#include "vblank.h"
-#include
-#include "mtypes.h"
-#include "macros.h"
-#include "dd.h"
-#include "swrast/swrast.h"
-#include "nouveau_context.h"
-#include "nouveau_msg.h"
-#include "nouveau_fifo.h"
-#include "nouveau_lock.h"
-#include "nouveau_object.h"
-#include "nouveau_sync.h"
-
-#ifdef NOUVEAU_RING_DEBUG
-int nouveau_fifo_remaining=0;
-#endif
-
-
-#define RING_SKIPS 8
-
-void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size)
-{
-#ifdef NOUVEAU_RING_DEBUG
- return;
-#endif
- u_int32_t fifo_get;
- while(nmesa->fifo.free < size+1) {
- fifo_get = NV_FIFO_READ_GET();
-
- if(nmesa->fifo.put >= fifo_get) {
- nmesa->fifo.free = nmesa->fifo.max - nmesa->fifo.current;
- if(nmesa->fifo.free < size+1) {
- OUT_RING(NV03_FIFO_CMD_JUMP |
- nmesa->fifo.drm.put_base);
- if(fifo_get <= RING_SKIPS) {
- if(nmesa->fifo.put <= RING_SKIPS) /* corner case - will be idle */
- NV_FIFO_WRITE_PUT(RING_SKIPS + 1);
- do { fifo_get = NV_FIFO_READ_GET(); }
- while(fifo_get <= RING_SKIPS);
- }
- NV_FIFO_WRITE_PUT(RING_SKIPS);
- nmesa->fifo.current = nmesa->fifo.put = RING_SKIPS;
- nmesa->fifo.free = fifo_get - (RING_SKIPS + 1);
- }
- } else
- nmesa->fifo.free = fifo_get - nmesa->fifo.current - 1;
- }
-}
-
-/*
- * Wait for the channel to be idle
- */
-void nouveauWaitForIdleLocked(nouveauContextPtr nmesa)
-{
- /* Wait for FIFO idle */
- FIRE_RING();
- while(RING_AHEAD()>0);
-
- /* Wait on notifier to indicate all commands in the channel have
- * been completed.
- */
- nouveau_notifier_wait_nop(nmesa->glCtx, nmesa->syncNotifier, NvSub3D);
-}
-
-void nouveauWaitForIdle(nouveauContextPtr nmesa)
-{
- LOCK_HARDWARE(nmesa);
- nouveauWaitForIdleLocked(nmesa);
- UNLOCK_HARDWARE(nmesa);
-}
-
-// here we call the fifo initialization ioctl and fill in stuff accordingly
-GLboolean nouveauFifoInit(nouveauContextPtr nmesa)
-{
- int i, ret;
-
-#ifdef NOUVEAU_RING_DEBUG
- return GL_TRUE;
-#endif
-
- nmesa->fifo.drm.fb_ctxdma_handle = NvDmaFB;
- nmesa->fifo.drm.tt_ctxdma_handle = NvDmaTT;
- ret = drmCommandWriteRead(nmesa->driFd, DRM_NOUVEAU_CHANNEL_ALLOC,
- &nmesa->fifo.drm, sizeof(nmesa->fifo.drm));
- if (ret) {
- FATAL("Fifo initialization ioctl failed (returned %d)\n", ret);
- return GL_FALSE;
- }
-
- ret = drmMap(nmesa->driFd, nmesa->fifo.drm.cmdbuf,
- nmesa->fifo.drm.cmdbuf_size, &nmesa->fifo.pushbuf);
- if (ret) {
- FATAL("Unable to map the fifo (returned %d)\n", ret);
- return GL_FALSE;
- }
-
- ret = drmMap(nmesa->driFd, nmesa->fifo.drm.ctrl,
- nmesa->fifo.drm.ctrl_size, &nmesa->fifo.mmio);
- if (ret) {
- FATAL("Unable to map the control regs (returned %d)\n", ret);
- return GL_FALSE;
- }
-
- ret = drmMap(nmesa->driFd, nmesa->fifo.drm.notifier,
- nmesa->fifo.drm.notifier_size,
- &nmesa->fifo.notifier_block);
- if (ret) {
- FATAL("Unable to map the notifier block (returned %d)\n", ret);
- return GL_FALSE;
- }
-
- /* Setup our initial FIFO tracking params */
- nmesa->fifo.current = 0;
- nmesa->fifo.put = 0;
- nmesa->fifo.max = (nmesa->fifo.drm.cmdbuf_size >> 2) - 1;
- nmesa->fifo.free = nmesa->fifo.max - nmesa->fifo.current;
-
- for (i=0; ififo.free -= RING_SKIPS;
-
- MESSAGE("Fifo init ok. Using context %d\n", nmesa->fifo.drm.channel);
- return GL_TRUE;
-}
-
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_fifo.h b/src/mesa/drivers/dri/nouveau/nouveau_fifo.h
deleted file mode 100644
index 3ca1560e3a..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_fifo.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-
-#ifndef __NOUVEAU_FIFO_H__
-#define __NOUVEAU_FIFO_H__
-
-#include "nouveau_context.h"
-#include "nouveau_ctrlreg.h"
-#include "nouveau_state_cache.h"
-
-//#define NOUVEAU_RING_TRACE
-//#define NOUVEAU_RING_DEBUG
-//#define NOUVEAU_STATE_CACHE_DISABLE
-
-#ifndef NOUVEAU_RING_TRACE
-#define NOUVEAU_RING_TRACE 0
-#else
-#undef NOUVEAU_RING_TRACE
-#define NOUVEAU_RING_TRACE 1
-#endif
-
-#define NV_READ(reg) *(volatile u_int32_t *)(nmesa->mmio + (reg))
-
-#define NV_FIFO_READ(reg) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg/4))
-#define NV_FIFO_WRITE(reg,value) *(volatile u_int32_t *)(nmesa->fifo.mmio + (reg/4)) = value;
-#define NV_FIFO_READ_GET() ((NV_FIFO_READ(NV03_FIFO_REGS_DMAGET) - nmesa->fifo.drm.put_base) >> 2)
-#define NV_FIFO_WRITE_PUT(val) do { \
- if (NOUVEAU_RING_TRACE) {\
- printf("FIRE_RING : 0x%08x\n", nmesa->fifo.current << 2); \
- fflush(stdout); \
- sleep(1); \
- } \
- NV_FIFO_WRITE(NV03_FIFO_REGS_DMAPUT, ((val)<<2) + nmesa->fifo.drm.put_base); \
-} while(0)
-
-/*
- * Ring/fifo interface
- *
- * - Begin a ring section with BEGIN_RING_SIZE (if you know the full size in advance)
- * - Output stuff to the ring with either OUT_RINGp (outputs a raw mem chunk), OUT_RING (1 uint32_t) or OUT_RINGf (1 float)
- * - RING_AVAILABLE returns the available fifo (in uint32_ts)
- * - RING_AHEAD returns how much ahead of the last submission point we are
- * - FIRE_RING fires whatever we have that wasn't fired before
- * - WAIT_RING waits for size (in uint32_ts) to be available in the fifo
- */
-
-/* Enable for ring debugging. Prints out writes to the ring buffer
- * but does not actually write to it.
- */
-#ifdef NOUVEAU_RING_DEBUG
-
-extern int nouveau_fifo_remaining;
-
-#define OUT_RINGp(ptr,sz) do { \
-uint32_t* p=(uint32_t*)(ptr); \
-int i; printf("OUT_RINGp: (size 0x%x dwords)\n",sz); for(i=0;ififo.free <= (size)) \
- WAIT_RING(nmesa,(size)); \
- OUT_RING( ((size)<<18) | ((subchannel) << 13) | (tag)); \
- nmesa->fifo.free -= ((size) + 1); \
- nouveau_fifo_remaining=size; \
-}while(0)
-
-#else
-
-#define OUT_RINGp(ptr,sz) do{ \
- if (NOUVEAU_RING_TRACE) { \
- uint32_t* p=(uint32_t*)(ptr); \
- int i; printf("OUT_RINGp: (size 0x%x dwords) (%s)\n",sz, __func__); for(i=0;ififo.current+i) << 2, *(p+i), *((float*)(p+i))); \
- } \
- memcpy(nmesa->fifo.pushbuf+nmesa->fifo.current,ptr,(sz)*4); \
- nmesa->fifo.current+=(sz); \
-}while(0)
-
-#define OUT_RING(n) do { \
-if (NOUVEAU_RING_TRACE) \
- printf("OUT_RINGn: [0x%08x] 0x%08x (%s)\n", nmesa->fifo.current << 2, n, __func__); \
-nmesa->fifo.pushbuf[nmesa->fifo.current++]=(n); \
-}while(0)
-
-#define OUT_RINGf(n) do { \
-if (NOUVEAU_RING_TRACE) \
- printf("OUT_RINGf: [0x%08x] %.04f (%s)\n", nmesa->fifo.current << 2, n, __func__); \
-*((float*)(nmesa->fifo.pushbuf+nmesa->fifo.current++))=(n); \
-}while(0)
-
-#define BEGIN_RING_SIZE(subchannel,tag,size) do { \
- nouveau_state_cache_flush(nmesa); \
- if (nmesa->fifo.free <= (size)) \
- WAIT_RING(nmesa,(size)); \
- OUT_RING( ((size)<<18) | ((subchannel) << 13) | (tag)); \
- nmesa->fifo.free -= ((size) + 1); \
-}while(0)
-
-#endif
-
-extern void WAIT_RING(nouveauContextPtr nmesa,u_int32_t size);
-extern void nouveau_state_cache_flush(nouveauContextPtr nmesa);
-extern void nouveau_state_cache_init(nouveauContextPtr nmesa);
-
-#ifdef NOUVEAU_STATE_CACHE_DISABLE
-#define BEGIN_RING_CACHE(subc,tag,size) BEGIN_RING_SIZE((subc), (tag), (size))
-#define OUT_RING_CACHE(n) OUT_RING((n))
-#define OUT_RING_CACHEf(n) OUT_RINGf((n))
-#define OUT_RING_CACHEp(ptr, sz) OUT_RINGp((ptr), (sz))
-#define OUT_RING_CACHE_FORCE(n) OUT_RING((n))
-#define OUT_RING_CACHE_FORCEf(n) OUT_RINGf((n))
-#define OUT_RING_CACHE_FORCEp(ptr, sz) OUT_RINGp((ptr), (sz))
-#else
-#define BEGIN_RING_CACHE(subchannel,tag,size) do { \
- nmesa->state_cache.dirty=1; \
- nmesa->state_cache.current_pos=((tag)/4); \
- assert(nmesa->state_cache.current_pos + size <= NOUVEAU_STATE_CACHE_ENTRIES); \
-}while(0)
-
-#define OUT_RING_CACHE(n) do { \
- if (nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value!=(n)) { \
- nmesa->state_cache.atoms[nmesa->state_cache.current_pos].dirty=1; \
- nmesa->state_cache.hdirty[nmesa->state_cache.current_pos/NOUVEAU_STATE_CACHE_HIER_SIZE]=1; \
- nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value=(n); \
- } \
- nmesa->state_cache.current_pos++; \
-}while(0)
-
-#define OUT_RING_CACHEf(n) do { \
- if ((*(GLfloat*)(&nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value))!=(n)){ \
- nmesa->state_cache.atoms[nmesa->state_cache.current_pos].dirty=1; \
- nmesa->state_cache.hdirty[nmesa->state_cache.current_pos/NOUVEAU_STATE_CACHE_HIER_SIZE]=1; \
- (*(GLfloat*)(&nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value))=(n);\
- } \
- nmesa->state_cache.current_pos++; \
-}while(0)
-
-#define OUT_RING_CACHEp(ptr,sz) do { \
- GLuint* p=(GLuint*)(ptr); \
- int i; \
- for(i=0;istate_cache.atoms[nmesa->state_cache.current_pos].dirty=1; \
- nmesa->state_cache.hdirty[nmesa->state_cache.current_pos/NOUVEAU_STATE_CACHE_HIER_SIZE]=1; \
- nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value=(n); \
- nmesa->state_cache.current_pos++; \
-}while(0)
-
-#define OUT_RING_CACHE_FORCEf(n) do { \
- nmesa->state_cache.atoms[nmesa->state_cache.current_pos].dirty=1; \
- nmesa->state_cache.hdirty[nmesa->state_cache.current_pos/NOUVEAU_STATE_CACHE_HIER_SIZE]=1; \
- (*(GLfloat*)(&nmesa->state_cache.atoms[nmesa->state_cache.current_pos].value))=(n);\
- nmesa->state_cache.current_pos++; \
-}while(0)
-
-#define OUT_RING_CACHE_FORCEp(ptr,sz) do { \
- GLuint* p=(GLuint*)(ptr); \
- int i; \
- for(i=0;ififo.free-1)
-
-#define RING_AHEAD() ((nmesa->fifo.put<=nmesa->fifo.current)?(nmesa->fifo.current-nmesa->fifo.put):nmesa->fifo.max-nmesa->fifo.put+nmesa->fifo.current)
-
-#define FIRE_RING() do { \
- if (nmesa->fifo.current!=nmesa->fifo.put) { \
- nmesa->fifo.put=nmesa->fifo.current; \
- NV_FIFO_WRITE_PUT(nmesa->fifo.put); \
- } \
-}while(0)
-
-extern void nouveauWaitForIdle(nouveauContextPtr nmesa);
-extern void nouveauWaitForIdleLocked(nouveauContextPtr nmesa);
-extern GLboolean nouveauFifoInit(nouveauContextPtr nmesa);
-
-#endif /* __NOUVEAU_FIFO_H__ */
-
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_lock.c b/src/mesa/drivers/dri/nouveau/nouveau_lock.c
deleted file mode 100644
index aa86c9e783..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_lock.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-#include "nouveau_context.h"
-#include "nouveau_lock.h"
-
-#include "drirenderbuffer.h"
-#include "framebuffer.h"
-
-
-/* Update the hardware state. This is called if another context has
- * grabbed the hardware lock, which includes the X server. This
- * function also updates the driver's window state after the X server
- * moves, resizes or restacks a window -- the change will be reflected
- * in the drawable position and clip rects. Since the X server grabs
- * the hardware lock when it changes the window state, this routine will
- * automatically be called after such a change.
- */
-void nouveauGetLock( nouveauContextPtr nmesa, GLuint flags )
-{
- __DRIdrawablePrivate *dPriv = nmesa->driDrawable;
- __DRIscreenPrivate *sPriv = nmesa->driScreen;
- struct drm_nouveau_sarea *sarea = nmesa->sarea;
-
- drmGetLock( nmesa->driFd, nmesa->hHWContext, flags );
-
- /* The window might have moved, so we might need to get new clip
- * rects.
- *
- * NOTE: This releases and regrabs the hw lock to allow the X server
- * to respond to the DRI protocol request for new drawable info.
- * Since the hardware state depends on having the latest drawable
- * clip rects, all state checking must be done _after_ this call.
- */
- DRI_VALIDATE_DRAWABLE_INFO( sPriv, dPriv );
-
- /* If timestamps don't match, the window has been changed */
- if (nmesa->lastStamp != dPriv->lastStamp) {
- struct gl_framebuffer *fb = (struct gl_framebuffer *)dPriv->driverPrivate;
-
- /* _mesa_resize_framebuffer will take care of calling the renderbuffer's
- * AllocStorage function if we need more memory to hold it */
- if (fb->Width != dPriv->w || fb->Height != dPriv->h) {
- _mesa_resize_framebuffer(nmesa->glCtx, fb, dPriv->w, dPriv->h);
- /* resize buffers, will call nouveau_window_moved */
- nouveau_build_framebuffer(nmesa->glCtx, fb);
- } else {
- nouveau_window_moved(nmesa->glCtx);
- }
-
- nmesa->lastStamp = dPriv->lastStamp;
- }
-
- nmesa->numClipRects = dPriv->numClipRects;
- nmesa->pClipRects = dPriv->pClipRects;
-
-}
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_lock.h b/src/mesa/drivers/dri/nouveau/nouveau_lock.h
deleted file mode 100644
index 38bb001425..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_lock.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-#ifndef __NOUVEAU_LOCK_H__
-#define __NOUVEAU_LOCK_H__
-
-#include "nouveau_context.h"
-
-extern void nouveauGetLock( nouveauContextPtr nmesa, GLuint flags );
-
-/*
- * !!! We may want to separate locks from locks with validation. This
- * could be used to improve performance for those things commands that
- * do not do any drawing !!!
- */
-
-/* Lock the hardware and validate our state.
- */
-#define LOCK_HARDWARE( nmesa ) \
- do { \
- char __ret = 0; \
- DEBUG_CHECK_LOCK(); \
- DRM_CAS( nmesa->driHwLock, nmesa->hHWContext, \
- (DRM_LOCK_HELD | nmesa->hHWContext), __ret ); \
- if ( __ret ) \
- nouveauGetLock( nmesa, 0 ); \
- DEBUG_LOCK(); \
- } while (0)
-
-/* Unlock the hardware.
- */
-#define UNLOCK_HARDWARE( nmesa ) \
- do { \
- DRM_UNLOCK( nmesa->driFd, \
- nmesa->driHwLock, \
- nmesa->hHWContext ); \
- DEBUG_RESET(); \
- } while (0)
-
-#define DEBUG_LOCK()
-#define DEBUG_RESET()
-#define DEBUG_CHECK_LOCK()
-
-
-#endif /* __NOUVEAU_LOCK_H__ */
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_mem.c b/src/mesa/drivers/dri/nouveau/nouveau_mem.c
deleted file mode 100644
index 35c53268b0..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_mem.c
+++ /dev/null
@@ -1,144 +0,0 @@
-#include "mtypes.h"
-
-#include "nouveau_context.h"
-#include "nouveau_fifo.h"
-#include "nouveau_mem.h"
-#include "nouveau_msg.h"
-#include "nouveau_object.h"
-#include "nouveau_reg.h"
-
-#define MAX_MEMFMT_LENGTH 32768
-
-/* Unstrided blit using NV_MEMORY_TO_MEMORY_FORMAT */
-GLboolean
-nouveau_memformat_flat_emit(GLcontext * ctx,
- nouveau_mem * dst, nouveau_mem * src,
- GLuint dst_offset, GLuint src_offset,
- GLuint size)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- uint32_t src_handle, dst_handle;
- GLuint count;
-
- if (src_offset + size > src->size) {
- MESSAGE("src out of nouveau_mem bounds\n");
- return GL_FALSE;
- }
- if (dst_offset + size > dst->size) {
- MESSAGE("dst out of nouveau_mem bounds\n");
- return GL_FALSE;
- }
-
- src_handle = (src->type & NOUVEAU_MEM_FB) ? NvDmaFB : NvDmaTT;
- dst_handle = (dst->type & NOUVEAU_MEM_FB) ? NvDmaFB : NvDmaTT;
- src_offset += nouveau_mem_gpu_offset_get(ctx, src);
- dst_offset += nouveau_mem_gpu_offset_get(ctx, dst);
-
- BEGIN_RING_SIZE(NvSubMemFormat,
- NV_MEMORY_TO_MEMORY_FORMAT_OBJECT_IN, 2);
- OUT_RING(src_handle);
- OUT_RING(dst_handle);
-
- count = (size / MAX_MEMFMT_LENGTH) +
- ((size % MAX_MEMFMT_LENGTH) ? 1 : 0);
-
- while (count--) {
- GLuint length =
- (size > MAX_MEMFMT_LENGTH) ? MAX_MEMFMT_LENGTH : size;
-
- BEGIN_RING_SIZE(NvSubMemFormat,
- NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
- OUT_RING(src_offset);
- OUT_RING(dst_offset);
- OUT_RING(0); /* pitch in */
- OUT_RING(0); /* pitch out */
- OUT_RING(length); /* line length */
- OUT_RING(1); /* number of lines */
- OUT_RING((1 << 8) /* dst_inc */ |(1 << 0) /* src_inc */ );
- OUT_RING(0); /* buffer notify? */
- FIRE_RING();
-
- src_offset += length;
- dst_offset += length;
- size -= length;
- }
-
- return GL_TRUE;
-}
-
-void nouveau_mem_free(GLcontext * ctx, nouveau_mem * mem)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- struct drm_nouveau_mem_free memf;
-
- if (NOUVEAU_DEBUG & DEBUG_MEM) {
- fprintf(stderr, "%s: type=0x%x, offset=0x%x, size=0x%x\n",
- __func__, mem->type, (GLuint) mem->offset,
- (GLuint) mem->size);
- }
-
- if (mem->map)
- drmUnmap(mem->map, mem->size);
- memf.flags = mem->type;
- memf.offset = mem->offset;
- drmCommandWrite(nmesa->driFd, DRM_NOUVEAU_MEM_FREE, &memf,
- sizeof(memf));
- FREE(mem);
-}
-
-nouveau_mem *nouveau_mem_alloc(GLcontext *ctx, uint32_t flags, GLuint size,
- GLuint align)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- struct drm_nouveau_mem_alloc mema;
- nouveau_mem *mem;
- int ret;
-
- if (NOUVEAU_DEBUG & DEBUG_MEM) {
- fprintf(stderr,
- "%s: requested: flags=0x%x, size=0x%x, align=0x%x\n",
- __func__, flags, (GLuint) size, align);
- }
-
- mem = CALLOC(sizeof(nouveau_mem));
- if (!mem)
- return NULL;
-
- mema.flags = flags;
- mema.size = mem->size = size;
- mema.alignment = align;
- mem->map = NULL;
- ret = drmCommandWriteRead(nmesa->driFd, DRM_NOUVEAU_MEM_ALLOC,
- &mema, sizeof(mema));
- if (ret) {
- FREE(mem);
- return NULL;
- }
- mem->offset = mema.offset;
- mem->type = mema.flags;
-
- if (NOUVEAU_DEBUG & DEBUG_MEM) {
- fprintf(stderr,
- "%s: actual: type=0x%x, offset=0x%x, size=0x%x\n",
- __func__, mem->type, (GLuint) mem->offset,
- (GLuint) mem->size);
- }
-
- if (flags & NOUVEAU_MEM_MAPPED)
- ret = drmMap(nmesa->driFd, mema.map_handle, mem->size,
- &mem->map);
- if (ret) {
- mem->map = NULL;
- nouveau_mem_free(ctx, mem);
- mem = NULL;
- }
-
- return mem;
-}
-
-uint32_t nouveau_mem_gpu_offset_get(GLcontext * ctx, nouveau_mem * mem)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- return mem->offset;
-}
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_mem.h b/src/mesa/drivers/dri/nouveau/nouveau_mem.h
deleted file mode 100644
index 6db73f4708..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_mem.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __NOUVEAU_MEM_H__
-#define __NOUVEAU_MEM_H__
-
-typedef struct nouveau_mem_t {
- int type;
- uint64_t offset;
- uint64_t size;
- void *map;
-} nouveau_mem;
-
-extern nouveau_mem *nouveau_mem_alloc(GLcontext *, uint32_t flags,
- GLuint size, GLuint align);
-extern void nouveau_mem_free(GLcontext *, nouveau_mem *);
-extern uint32_t nouveau_mem_gpu_offset_get(GLcontext *, nouveau_mem *);
-
-extern GLboolean nouveau_memformat_flat_emit(GLcontext *,
- nouveau_mem *dst,
- nouveau_mem *src,
- GLuint dst_offset,
- GLuint src_offset,
- GLuint size);
-
-#endif
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_msg.h b/src/mesa/drivers/dri/nouveau/nouveau_msg.h
deleted file mode 100644
index 5dea2189c7..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_msg.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
-Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
-Copyright 2006 Stephane Marchesin. All Rights Reserved
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell
- * Nicolai Haehnle
- */
-
-
-#ifndef __NOUVEAU_MSG_H__
-#define __NOUVEAU_MSG_H__
-
-#define WARN_ONCE(a, ...) do {\
- static int warn##__LINE__=1;\
- if(warn##__LINE__){\
- fprintf(stderr, "*********************************WARN_ONCE*********************************\n");\
- fprintf(stderr, "File %s function %s line %d\n", __FILE__, __FUNCTION__, __LINE__);\
- fprintf(stderr, a, ## __VA_ARGS__);\
- fprintf(stderr, "***************************************************************************\n");\
- warn##__LINE__=0;\
- } \
- }while(0)
-
-#define MESSAGE(a, ...) do{\
- fprintf(stderr, "************************************INFO***********************************\n");\
- fprintf(stderr, "File %s function %s line %d\n", __FILE__, __FUNCTION__, __LINE__); \
- fprintf(stderr, a, ## __VA_ARGS__);\
- fprintf(stderr, "***************************************************************************\n");\
- }while(0)
-
-#define FATAL(a, ...) do{\
- fprintf(stderr, "***********************************FATAL***********************************\n");\
- fprintf(stderr, "File %s function %s line %d\n", __FILE__, __FUNCTION__, __LINE__); \
- fprintf(stderr, a, ## __VA_ARGS__);\
- fprintf(stderr, "***************************************************************************\n");\
- }while(0)
-
-#endif /* __NOUVEAU_MSG_H__ */
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_object.c b/src/mesa/drivers/dri/nouveau/nouveau_object.c
deleted file mode 100644
index 8f33093f1a..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_object.c
+++ /dev/null
@@ -1,98 +0,0 @@
-
-#include "nouveau_fifo.h"
-#include "nouveau_object.h"
-#include "nouveau_reg.h"
-
-
-GLboolean nouveauCreateContextObject(nouveauContextPtr nmesa,
- uint32_t handle, int class)
-{
- struct drm_nouveau_grobj_alloc cto;
- int ret;
-
- cto.channel = nmesa->fifo.drm.channel;
- cto.handle = handle;
- cto.class = class;
- ret = drmCommandWrite(nmesa->driFd, DRM_NOUVEAU_GROBJ_ALLOC,
- &cto, sizeof(cto));
-
- return ret == 0;
-}
-
-void nouveauObjectOnSubchannel(nouveauContextPtr nmesa, int subchannel, int handle)
-{
- BEGIN_RING_SIZE(subchannel, 0, 1);
- OUT_RING(handle);
-}
-
-void nouveauObjectInit(nouveauContextPtr nmesa)
-{
-#ifdef NOUVEAU_RING_DEBUG
- return;
-#endif
-
- nouveauCreateContextObject(nmesa, Nv3D, nmesa->screen->card->class_3d);
- if (nmesa->screen->card->type>=NV_10) {
- nouveauCreateContextObject(nmesa, NvCtxSurf2D, NV10_CONTEXT_SURFACES_2D);
- } else {
- nouveauCreateContextObject(nmesa, NvCtxSurf2D, NV04_CONTEXT_SURFACES_2D);
- nouveauCreateContextObject(nmesa, NvCtxSurf3D, NV04_CONTEXT_SURFACES_3D);
- }
- if (nmesa->screen->card->type>=NV_11) {
- nouveauCreateContextObject(nmesa, NvImageBlit, NV11_IMAGE_BLIT);
- } else {
- nouveauCreateContextObject(nmesa, NvImageBlit, NV_IMAGE_BLIT);
- }
- if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->typescreen->card->type>=NV_10) && (nmesa->screen->card->typequery_object_max; i++)
- if (nmesa->query_alloc[i] == GL_FALSE)
- break;
- if (i==nmesa->query_object_max)
- return NULL;
-
- nq = CALLOC_STRUCT(nouveau_query_object_t);
- if (nq) {
- nq->notifier_id = i;
-
- nq->mesa.Id = id;
- nq->mesa.Result = 0;
- nq->mesa.Active = GL_FALSE;
- nq->mesa.Ready = GL_TRUE;
- }
-
- return (struct gl_query_object *)nq;
-}
-
-static void
-nouveauBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nouveau_query_object *nq = (nouveau_query_object *)q;
-
- nouveau_notifier_reset(ctx, nmesa->queryNotifier, nq->notifier_id);
-
- switch (nmesa->screen->card->type) {
- case NV_20:
- BEGIN_RING_CACHE(NvSub3D, 0x17c8, 1);
- OUT_RING_CACHE (1);
- BEGIN_RING_CACHE(NvSub3D, 0x17cc, 1);
- OUT_RING_CACHE (1);
- break;
- case NV_30:
- case NV_40:
- case NV_44:
- /* I don't think this is OCC_QUERY enable, but it *is* needed to make
- * the SET_OBJECT7 notifier block work with STORE_RESULT.
- *
- * Also, this appears to reset the pixel pass counter */
- BEGIN_RING_SIZE(NvSub3D,
- NV30_TCL_PRIMITIVE_3D_OCC_QUERY_OR_COLOR_BUFF_ENABLE,
- 1);
- OUT_RING (1);
- /* Probably OCC_QUERY_ENABLE */
- BEGIN_RING_CACHE(NvSub3D, 0x17cc, 1);
- OUT_RING_CACHE (1);
- break;
- default:
- WARN_ONCE("no support for this card\n");
- break;
- }
-}
-
-static void
-nouveauUpdateQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nouveau_query_object *nq = (nouveau_query_object *)q;
- int status;
-
- status = nouveau_notifier_status(ctx, nmesa->queryNotifier,
- nq->notifier_id);
-
- q->Ready = (status == NV_NOTIFY_STATE_STATUS_COMPLETED);
- if (q->Ready)
- q->Result = nouveau_notifier_return_val(ctx,
- nmesa->queryNotifier,
- nq->notifier_id);
-}
-
-static void
-nouveauWaitQueryResult(GLcontext *ctx, GLenum target, struct gl_query_object *q)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nouveau_query_object *nq = (nouveau_query_object *)q;
-
- nouveau_notifier_wait_status(ctx, nmesa->queryNotifier, nq->notifier_id,
- NV_NOTIFY_STATE_STATUS_COMPLETED, 0);
- nouveauUpdateQuery(ctx, target, q);
-}
-
-static void
-nouveauEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
-{
- nouveau_query_object *nq = (nouveau_query_object *)q;
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- switch (nmesa->screen->card->type) {
- case NV_20:
- BEGIN_RING_SIZE(NvSub3D, 0x17d0, 1);
- OUT_RING (0x01000000 | nq->notifier_id*32);
- break;
- case NV_30:
- case NV_40:
- case NV_44:
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STORE_RESULT, 1);
- OUT_RING (0x01000000 | nq->notifier_id*32);
- break;
- default:
- WARN_ONCE("no support for this card\n");
- break;
- }
- FIRE_RING();
-
- /*XXX: wait for query to complete, mesa doesn't give the driver
- * an interface to query the status of a query object so
- * this has to stall the channel.
- */
- nouveauWaitQueryResult(ctx, target, q);
-
- BEGIN_RING_CACHE(NvSub3D, 0x17cc, 1);
- OUT_RING_CACHE (0);
-}
-
-void
-nouveauQueryInitFuncs(GLcontext *ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (nmesa->screen->card->type < NV_20)
- return;
-
- /* Reserve half the notifier block for use as query objects */
- nmesa->query_object_max = (nmesa->fifo.drm.notifier_size / 2) / 32;
- nmesa->queryNotifier =
- nouveau_notifier_new(ctx, NvQueryNotify,
- nmesa->query_object_max);
- nmesa->query_alloc = calloc(nmesa->query_object_max, sizeof(GLboolean));
-
- switch (nmesa->screen->card->type) {
- case NV_20:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SET_OBJECT8, 1);
- OUT_RING_CACHE (NvQueryNotify);
- break;
- case NV_30:
- case NV_40:
- case NV_44:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT7, 1);
- OUT_RING_CACHE (NvQueryNotify);
- break;
- default:
- break;
- };
-
- ctx->Driver.NewQueryObject = nouveauNewQueryObject;
- ctx->Driver.BeginQuery = nouveauBeginQuery;
- ctx->Driver.EndQuery = nouveauEndQuery;
-#if 0
- ctx->Driver.UpdateQuery = nouveauUpdateQuery;
- ctx->Driver.WaitQueryResult = nouveauWaitQueryResult;
-#endif
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_query.h b/src/mesa/drivers/dri/nouveau/nouveau_query.h
deleted file mode 100644
index 3ded41417e..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_query.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (C) 2007 Ben Skeggs.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef __NOUVEAU_QUERY_H__
-#define __NOUVEAU_QUERY_H__
-
-typedef struct nouveau_query_object_t {
- struct gl_query_object mesa;
-
- int notifier_id;
-} nouveau_query_object;
-
-extern void nouveauQueryInitFuncs(GLcontext *ctx);
-#endif
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_reg.h b/src/mesa/drivers/dri/nouveau/nouveau_reg.h
deleted file mode 100644
index 6b90bab076..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_reg.h
+++ /dev/null
@@ -1,4998 +0,0 @@
-/*
- Autogenerated file, do not edit !
-
-**************************************************************************
-
- Copyright (C) 2006 :
- Dmitry Baryshkov,
- Laurent Carlier,
- Matthieu Castet,
- Dawid Gajownik,
- Jeremy Kolb,
- Stephane Loeuillet,
- Patrice Mandin,
- Stephane Marchesin,
- Serge Martin,
- Sylvain Munaut,
- Ben Skeggs,
- Erik Waling,
- koala_br,
- sturmflut.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************
-
- Created from objects.c rev. 1.440
-*/
-
-#ifndef _NOUVEAU_REG_H
-#define _NOUVEAU_REG_H
-
-/******************************************
-Object NV01_CONTEXT_CLIP_RECTANGLE used on: NV03 NV04 NV10 NV15 NV20 NV40 G70
-*/
-#define NV01_CONTEXT_CLIP_RECTANGLE 0x00000019
-# define NV01_CONTEXT_CLIP_RECTANGLE_NOP 0x00000100
-# define NV01_CONTEXT_CLIP_RECTANGLE_NOTIFY 0x00000104
-# define NV01_CONTEXT_CLIP_RECTANGLE_DMA_NOTIFY 0x00000180
-# define NV01_CONTEXT_CLIP_RECTANGLE_SET_POINT 0x00000300 /* Parameters: x y */
-# define NV01_CONTEXT_CLIP_RECTANGLE_SET_POINT_X_MASK 0x0000ffff
-# define NV01_CONTEXT_CLIP_RECTANGLE_SET_POINT_Y_MASK 0xffff0000
-# define NV01_CONTEXT_CLIP_RECTANGLE_SET_POINT_Y_SHIFT 16
-# define NV01_CONTEXT_CLIP_RECTANGLE_SET_SIZE 0x00000304 /* Parameters: width height */
-# define NV01_CONTEXT_CLIP_RECTANGLE_SET_SIZE_WIDTH_MASK 0x0000ffff
-# define NV01_CONTEXT_CLIP_RECTANGLE_SET_SIZE_HEIGHT_MASK 0xffff0000
-# define NV01_CONTEXT_CLIP_RECTANGLE_SET_SIZE_HEIGHT_SHIFT 16
-
-/******************************************
-Object NV_MEMORY_TO_MEMORY_FORMAT used on: NV04 NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039
-# define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100
-# define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
-# define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180
-# define NV_MEMORY_TO_MEMORY_FORMAT_OBJECT_IN 0x00000184
-# define NV_MEMORY_TO_MEMORY_FORMAT_OBJECT_OUT 0x00000188
-# define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
-# define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT 0x00000310
-# define NV_MEMORY_TO_MEMORY_FORMAT_PITCH_IN 0x00000314
-# define NV_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT 0x00000318
-# define NV_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN 0x0000031c
-# define NV_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT 0x00000320
-# define NV_MEMORY_TO_MEMORY_FORMAT_FORMAT 0x00000324 /* Parameters: src_inc dst_inc */
-# define NV_MEMORY_TO_MEMORY_FORMAT_FORMAT_SRC_INC_MASK 0x00000007
-# define NV_MEMORY_TO_MEMORY_FORMAT_FORMAT_DST_INC_MASK 0x00000700
-# define NV_MEMORY_TO_MEMORY_FORMAT_FORMAT_DST_INC_SHIFT 8
-# define NV_MEMORY_TO_MEMORY_FORMAT_BUF_NOTIFY 0x00000328
-
-/******************************************
-Object NV03_PRIMITIVE_RASTER_OP used on: NV03 NV04 NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV03_PRIMITIVE_RASTER_OP 0x00000043
-# define NV03_PRIMITIVE_RASTER_OP_NOP 0x00000100
-# define NV03_PRIMITIVE_RASTER_OP_NOTIFY 0x00000104
-# define NV03_PRIMITIVE_RASTER_OP_DMA_NOTIFY 0x00000180
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP 0x00000300 /* Parameters: logic_op */
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_MASK 0x000000f0
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_SHIFT 4
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_CLEAR 0x0000
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_NOR 0x0001
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_AND_INVERTED 0x0002
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_COPY_INVERTED 0x0003
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_AND_REVERSE 0x0004
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_INVERT 0x0005
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_XOR 0x0006
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_NAND 0x0007
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_AND 0x0008
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_EQUIV 0x0009
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_NOOP 0x000a
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_OR_INVERTED 0x000b
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_COPY 0x000c
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_OR_REVERSE 0x000d
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_OR 0x000e
-# define NV03_PRIMITIVE_RASTER_OP_LOGIC_OP_LOGIC_OP_SET 0x000f
-
-/******************************************
-Object NV04_GDI_RECTANGLE_TEXT used on: NV04 NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV04_GDI_RECTANGLE_TEXT 0x0000004a
-# define NV04_GDI_RECTANGLE_TEXT_NOP 0x00000100
-# define NV04_GDI_RECTANGLE_TEXT_NOTIFY 0x00000104
-# define NV04_GDI_RECTANGLE_TEXT_SET_DMA_NOTIFY 0x00000180
-# define NV04_GDI_RECTANGLE_TEXT_SET_DMA_FONTS 0x00000184
-# define NV04_GDI_RECTANGLE_TEXT_PATTERN 0x00000188
-# define NV04_GDI_RECTANGLE_TEXT_ROP5 0x0000018c
-# define NV04_GDI_RECTANGLE_TEXT_SURFACE 0x00000198
-# define NV04_GDI_RECTANGLE_TEXT_OPERATION 0x000002fc
-# define NV04_GDI_RECTANGLE_TEXT_FORMAT 0x00000300
-# define NV04_GDI_RECTANGLE_TEXT_MONO_FORMAT 0x00000304
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL 0x000005f4 /* Parameters: left top */
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL_LEFT_MASK 0x0000ffff
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL_TOP_MASK 0xffff0000
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_TL_TOP_SHIFT 16
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_BR 0x000005f8 /* Parameters: right bottom */
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_BR_RIGHT_MASK 0x0000ffff
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_BR_BOTTOM_MASK 0xffff0000
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL1_BR_BOTTOM_SHIFT 16
-# define NV04_GDI_RECTANGLE_TEXT_FILL_VALUE 0x000005fc
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_TL 0x00000600 /* Parameters: left top */
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_TL_LEFT_MASK 0x0000ffff
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_TL_TOP_MASK 0xffff0000
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_TL_TOP_SHIFT 16
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_BR 0x00000604 /* Parameters: right bottom */
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_BR_RIGHT_MASK 0x0000ffff
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_BR_BOTTOM_MASK 0xffff0000
-# define NV04_GDI_RECTANGLE_TEXT_BLOCK_LEVEL2_BR_BOTTOM_SHIFT 16
-
-/******************************************
-Object NV04_SWIZZLED_SURFACE used on: NV04 NV10 NV15
-*/
-#define NV04_SWIZZLED_SURFACE 0x00000052
-# define NV04_SWIZZLED_SURFACE_DMA_NOTIFY 0x00000180
-# define NV04_SWIZZLED_SURFACE_DMA_IMAGE 0x00000184
-# define NV04_SWIZZLED_SURFACE_FORMAT 0x00000300 /* Parameters: log2_height log2_width color */
-# define NV04_SWIZZLED_SURFACE_FORMAT_LOG2_HEIGHT_MASK 0xff000000
-# define NV04_SWIZZLED_SURFACE_FORMAT_LOG2_HEIGHT_SHIFT 24
-# define NV04_SWIZZLED_SURFACE_FORMAT_LOG2_WIDTH_MASK 0x00ff0000
-# define NV04_SWIZZLED_SURFACE_FORMAT_LOG2_WIDTH_SHIFT 16
-# define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_MASK 0x0000ffff
-# define NV04_SWIZZLED_SURFACE_OFFSET 0x00000304
-
-/******************************************
-Object NV04_CONTEXT_SURFACES_3D used on: NV04
-*/
-#define NV04_CONTEXT_SURFACES_3D 0x00000053
-# define NV04_CONTEXT_SURFACES_3D_DMA_NOTIFY 0x00000180
-# define NV04_CONTEXT_SURFACES_3D_DMA_COLOR 0x00000184
-# define NV04_CONTEXT_SURFACES_3D_DMA_ZETA 0x00000188
-# define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL 0x000002f8 /* Parameters: x width */
-# define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_MASK 0x0000ffff
-# define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_WIDTH_MASK 0xffff0000
-# define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_WIDTH_SHIFT 16
-# define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL 0x000002fc /* Parameters: y height */
-# define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_MASK 0x0000ffff
-# define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_HEIGHT_MASK 0xffff0000
-# define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_HEIGHT_SHIFT 16
-# define NV04_CONTEXT_SURFACES_3D_FORMAT 0x00000300 /* Parameters: color type width height */
-# define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_MASK 0x000000ff
-# define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_MASK 0x0000ff00
-# define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SHIFT 8
-# define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_pitch 0x0001
-# define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_swizzle 0x0002
-# define NV04_CONTEXT_SURFACES_3D_FORMAT_WIDTH_MASK 0x00ff0000
-# define NV04_CONTEXT_SURFACES_3D_FORMAT_WIDTH_SHIFT 16
-# define NV04_CONTEXT_SURFACES_3D_FORMAT_HEIGHT_MASK 0xff000000
-# define NV04_CONTEXT_SURFACES_3D_FORMAT_HEIGHT_SHIFT 24
-# define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE 0x00000304 /* Parameters: width height */
-# define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_WIDTH_MASK 0x0000ffff
-# define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_HEIGHT_MASK 0xffff8000
-# define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_HEIGHT_SHIFT 15
-# define NV04_CONTEXT_SURFACES_3D_PITCH 0x00000308 /* Parameters: color zeta */
-# define NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_MASK 0x0000ffff
-# define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_MASK 0xffff0000
-# define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_SHIFT 16
-# define NV04_CONTEXT_SURFACES_3D_OFFSET_COLOR 0x0000030c
-# define NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA 0x00000310
-
-/******************************************
-Object NV04_DX5_TEXTURED_TRIANGLE used on: NV04
-*/
-#define NV04_DX5_TEXTURED_TRIANGLE 0x00000054
-# define NV04_DX5_TEXTURED_TRIANGLE_NOP 0x00000100
-# define NV04_DX5_TEXTURED_TRIANGLE_NOTIFY 0x00000104
-# define NV04_DX5_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180
-# define NV04_DX5_TEXTURED_TRIANGLE_DMA_1 0x00000184
-# define NV04_DX5_TEXTURED_TRIANGLE_DMA_2 0x00000188
-# define NV04_DX5_TEXTURED_TRIANGLE_SURFACE 0x0000018c
-# define NV04_DX5_TEXTURED_TRIANGLE_COLOR_KEY 0x00000300
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_OFFSET 0x00000304
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT 0x00000308 /* Parameters: color mipmaps log_u log_v wrap_s wrap_t */
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_MASK 0x00000f00
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_SHIFT 8
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_Y8 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_A1R5G5B5 0x0002
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_X1R5G5B5 0x0003
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_A4R4G4B4 0x0004
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_R5G6B5 0x0005
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_A8R8G8B8 0x0006
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_X8R8G8B8 0x0007
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_MIPMAPS_MASK 0x0000f000
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_MIPMAPS_SHIFT 12
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_LOG_U_MASK 0x000f0000
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_LOG_U_SHIFT 16
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_LOG_V_MASK 0x00f00000
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_LOG_V_SHIFT 20
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_S_MASK 0x07000000
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_S_SHIFT 24
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_S_REPEAT 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_S_MIRRORED 0x0002
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_S_CLAMP 0x0003
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_T_MASK 0x70000000
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_T_SHIFT 28
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_T_REPEAT 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_T_MIRRORED 0x0002
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FORMAT_WRAP_T_CLAMP 0x0003
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER 0x0000030c /* Parameters: magfilter minfilter lodbias */
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_MASK 0x70000000
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_SHIFT 28
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_NEAREST 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_LINEAR 0x0002
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MAGFILTER_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_MASK 0x07000000
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_SHIFT 24
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_NEAREST 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_LINEAR 0x0002
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_MINFILTER_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_LODBIAS_MASK 0x00ff0000
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_FILTER_LODBIAS_SHIFT 16
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND 0x00000310 /* Parameters: texture benable dst src */
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_MASK 0x0000000f
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_BENABLE_MASK 0x00100000
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_BENABLE (1 << 20)
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_BENABLE_TRUE 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_BENABLE_FALSE 0x0000
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_MASK 0xf0000000
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_SHIFT 28
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_0 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_1 0x0002
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_src_col 0x0003
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_inv_src_col 0x0004
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_src_a 0x0005
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_inv_src_a 0x0006
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_dst_col 0x0009
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_inv_dst_col 0x000a
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_MASK 0x0f000000
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_SHIFT 24
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_0 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_1 0x0002
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_src_col 0x0003
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_inv_src_col 0x0004
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_src_a 0x0005
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_inv_src_a 0x0006
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_dst_col 0x0009
-# define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_inv_dst_col 0x000a
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL 0x00000314 /* Parameters: alpharef alphafunc alphaenable zenable zwrite zfunc cullmode */
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAREF_MASK 0x000000ff
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_MASK 0x00000f00
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_SHIFT 8
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_NEVER 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_LESS 0x0002
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_EQUAL 0x0003
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_LEQUAL 0x0004
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_GREATER 0x0005
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_NOTEQUAL 0x0006
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_GEQUAL 0x0007
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAFUNC_ALWAYS 0x0008
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAENABLE_MASK 0x00001000
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAENABLE (1 << 12)
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAENABLE_TRUE 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHAENABLE_FALSE 0x0000
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZENABLE_MASK 0x00004000
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZENABLE (1 << 14)
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZENABLE_TRUE 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZENABLE_FALSE 0x0000
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZWRITE_MASK 0x01000000
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZWRITE (1 << 24)
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZWRITE_TRUE 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZWRITE_FALSE 0x0000
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_MASK 0x000f0000
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_SHIFT 16
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_NEVER 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_LESS 0x0002
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_EQUAL 0x0003
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_LEQUAL 0x0004
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_GREATER 0x0005
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_NOTEQUAL 0x0006
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_GEQUAL 0x0007
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ZFUNC_ALWAYS 0x0008
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULLMODE_MASK 0x00300000
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULLMODE_SHIFT 20
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULLMODE_NONE 0x0001
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULLMODE_CW 0x0002
-# define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULLMODE_CCW 0x0003
-# define NV04_DX5_TEXTURED_TRIANGLE_FOG_COLOR 0x00000318
-# define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX( d) (0x00000400 + (d) * 0x0020)
-# define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SY( d) (0x00000404 + (d) * 0x0020)
-# define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SZ( d) (0x00000408 + (d) * 0x0020)
-# define NV04_DX5_TEXTURED_TRIANGLE_INV_W( d) (0x0000040c + (d) * 0x0020)
-# define NV04_DX5_TEXTURED_TRIANGLE_COLOR( d) (0x00000410 + (d) * 0x0020)
-# define NV04_DX5_TEXTURED_TRIANGLE_SPECULAR( d) (0x00000414 + (d) * 0x0020)
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_S( d) (0x00000418 + (d) * 0x0020)
-# define NV04_DX5_TEXTURED_TRIANGLE_TEXTURE_T( d) (0x0000041c + (d) * 0x0020)
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW 0x00000600 /* Parameters: v0 v1 v2 v3 v4 v5 */
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V0_MASK 0x0000000f
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V1_MASK 0x000000f0
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V1_SHIFT 4
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V2_MASK 0x00000f00
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V2_SHIFT 8
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V3_MASK 0x0000f000
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V3_SHIFT 12
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V4_MASK 0x000f0000
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V4_SHIFT 16
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V5_MASK 0x00f00000
-# define NV04_DX5_TEXTURED_TRIANGLE_DRAW_V5_SHIFT 20
-
-/******************************************
-Object NV04_DX6_MULTITEX_TRIANGLE used on: NV04 NV10 NV15
-*/
-#define NV04_DX6_MULTITEX_TRIANGLE 0x00000055
-# define NV04_DX6_MULTITEX_TRIANGLE_NOP 0x00000100
-# define NV04_DX6_MULTITEX_TRIANGLE_NOTIFY 0x00000104
-# define NV04_DX6_MULTITEX_TRIANGLE_DMA_NOTIFY 0x00000180
-# define NV04_DX6_MULTITEX_TRIANGLE_DMA_1 0x00000184
-# define NV04_DX6_MULTITEX_TRIANGLE_DMA_2 0x00000188
-# define NV04_DX6_MULTITEX_TRIANGLE_SURFACE 0x0000018c
-# define NV04_DX6_MULTITEX_TRIANGLE_OFFSET0 0x00000308
-# define NV04_DX6_MULTITEX_TRIANGLE_OFFSET1 0x0000030c
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0 0x00000310 /* Parameters: color mipmaps log_u log_v wrap_s wrap_t */
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_MASK 0x00000f00
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_SHIFT 8
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_Y8 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_A1R5G5B5 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_X1R5G5B5 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_A4R4G4B4 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_R5G6B5 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_A8R8G8B8 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_COLOR_X8R8G8B8 0x0007
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_MIPMAPS_MASK 0x0000f000
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_MIPMAPS_SHIFT 12
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_LOG_U_MASK 0x000f0000
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_LOG_U_SHIFT 16
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_LOG_V_MASK 0x00f00000
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_LOG_V_SHIFT 20
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_S_MASK 0x07000000
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_S_SHIFT 24
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_S_REPEAT 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_S_MIRRORED 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_S_CLAMP 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_T_MASK 0x70000000
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_T_SHIFT 28
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_T_REPEAT 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_T_MIRRORED 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT0_WRAP_T_CLAMP 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1 0x00000314 /* Parameters: color mipmaps log_u log_v wrap_s wrap_t */
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_MASK 0x00000f00
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_SHIFT 8
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_Y8 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_A1R5G5B5 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_X1R5G5B5 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_A4R4G4B4 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_R5G6B5 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_A8R8G8B8 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_COLOR_X8R8G8B8 0x0007
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_MIPMAPS_MASK 0x0000f000
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_MIPMAPS_SHIFT 12
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_LOG_U_MASK 0x000f0000
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_LOG_U_SHIFT 16
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_LOG_V_MASK 0x00f00000
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_LOG_V_SHIFT 20
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_S_MASK 0x07000000
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_S_SHIFT 24
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_S_REPEAT 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_S_MIRRORED 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_S_CLAMP 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_T_MASK 0x70000000
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_T_SHIFT 28
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_T_REPEAT 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_T_MIRRORED 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_FORMAT1_WRAP_T_CLAMP 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0 0x00000318 /* Parameters: magfilter minfilter lodbias */
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_MASK 0x70000000
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_SHIFT 28
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_NEAREST 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_LINEAR 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MAGFILTER_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_MASK 0x07000000
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_SHIFT 24
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_NEAREST 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_LINEAR 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_MINFILTER_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_LODBIAS_MASK 0x00ff0000
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER0_LODBIAS_SHIFT 16
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1 0x0000031c /* Parameters: magfilter minfilter lodbias */
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_MASK 0x70000000
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_SHIFT 28
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_NEAREST 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_LINEAR 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MAGFILTER_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_MASK 0x07000000
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_SHIFT 24
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_NEAREST 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_LINEAR 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_MINFILTER_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_LODBIAS_MASK 0x00ff0000
-# define NV04_DX6_MULTITEX_TRIANGLE_FILTER1_LODBIAS_SHIFT 16
-# define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA 0x00000320
-# define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR 0x00000324
-# define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA 0x0000032c
-# define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR 0x00000330
-# define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR 0x00000334
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND 0x00000338 /* Parameters: benable dst src */
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_BENABLE_MASK 0x00100000
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_BENABLE (1 << 20)
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_BENABLE_TRUE 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_BENABLE_FALSE 0x0000
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_MASK 0xf0000000
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_SHIFT 28
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_0 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_1 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_src_col 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_inv_src_col 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_src_a 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_inv_src_a 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_dst_col 0x0009
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_inv_dst_col 0x000a
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_MASK 0x0f000000
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_SHIFT 24
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_0 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_1 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_src_col 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_inv_src_col 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_src_a 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_inv_src_a 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_dst_col 0x0009
-# define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_inv_dst_col 0x000a
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0 0x0000033c /* Parameters: red_write green_write blue_write alpha_write alpha_write stencil_write alpharef alphafunc alphaenable zenable zwrite zfunc cullmode */
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE_MASK 0x08000000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE (1 << 27)
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE_TRUE 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE_FALSE 0x0000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE_MASK 0x10000000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE (1 << 28)
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE_TRUE 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE_FALSE 0x0000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE_MASK 0x20000000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE (1 << 29)
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE_TRUE 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE_FALSE 0x0000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_MASK 0x04000000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE (1 << 26)
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_TRUE 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_FALSE 0x0000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_MASK 0x04000000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE (1 << 26)
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_TRUE 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_FALSE 0x0000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE_MASK 0x02000000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE (1 << 25)
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE_TRUE 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE_FALSE 0x0000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAREF_MASK 0x000000ff
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_MASK 0x00000f00
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_SHIFT 8
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_NEVER 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_LESS 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_EQUAL 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_LEQUAL 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_GREATER 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_NOTEQUAL 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_GEQUAL 0x0007
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAFUNC_ALWAYS 0x0008
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAENABLE_MASK 0x00001000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAENABLE (1 << 12)
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAENABLE_TRUE 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHAENABLE_FALSE 0x0000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZENABLE_MASK 0x00004000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZENABLE (1 << 14)
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZENABLE_TRUE 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZENABLE_FALSE 0x0000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZWRITE_MASK 0x01000000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZWRITE (1 << 24)
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZWRITE_TRUE 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZWRITE_FALSE 0x0000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_MASK 0x000f0000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_SHIFT 16
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_NEVER 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_LESS 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_EQUAL 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_LEQUAL 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_GREATER 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_NOTEQUAL 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_GEQUAL 0x0007
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ZFUNC_ALWAYS 0x0008
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULLMODE_MASK 0x00300000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULLMODE_SHIFT 20
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULLMODE_NONE 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULLMODE_CW 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULLMODE_CCW 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1 0x00000340 /* Parameters: stencil_enable stencil_mask_write stencil_mask_read stencilref stencilfunc */
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_ENABLE_MASK 0x00000001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_MASK 0xff000000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_SHIFT 24
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_MASK 0x00ff0000
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_SHIFT 16
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILREF_MASK 0x0000ff00
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILREF_SHIFT 8
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_MASK 0x000000f0
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_SHIFT 4
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_NEVER 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_LESS 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_EQUAL 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_LEQUAL 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_GREATER 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_NOTEQUAL 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_GEQUAL 0x0007
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCILFUNC_ALWAYS 0x0008
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2 0x00000344 /* Parameters: stencil_fail stencil_zfail stencil_zpass */
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_FAIL_MASK 0x0000000f
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_MASK 0x000000f0
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_SHIFT 4
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_KEEP 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_ZERO 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_REPLACE 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_INCR 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_DECR 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_INVERT 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_INCR_WRAP 0x0007
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZFAIL_DECR_WRAP 0x0008
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_MASK 0x00000f00
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_SHIFT 8
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_KEEP 0x0001
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_ZERO 0x0002
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_REPLACE 0x0003
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_INCR 0x0004
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_DECR 0x0005
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_INVERT 0x0006
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_INCR_WRAP 0x0007
-# define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_ZPASS_DECR_WRAP 0x0008
-# define NV04_DX6_MULTITEX_TRIANGLE_FOG_COLOR 0x00000348
-# define NV04_DX6_MULTITEX_TRIANGLE_TLVERTEX_SX( d) (0x00000400 + (d) * 0x0028)
-# define NV04_DX6_MULTITEX_TRIANGLE_TLVERTEX_SY( d) (0x00000404 + (d) * 0x0028)
-# define NV04_DX6_MULTITEX_TRIANGLE_TLVERTEX_SZ( d) (0x00000408 + (d) * 0x0028)
-# define NV04_DX6_MULTITEX_TRIANGLE_INV_W( d) (0x0000040c + (d) * 0x0028)
-# define NV04_DX6_MULTITEX_TRIANGLE_COLOR( d) (0x00000410 + (d) * 0x0028)
-# define NV04_DX6_MULTITEX_TRIANGLE_SPECULAR( d) (0x00000414 + (d) * 0x0028)
-# define NV04_DX6_MULTITEX_TRIANGLE_TEXTURE0_S( d) (0x00000418 + (d) * 0x0028)
-# define NV04_DX6_MULTITEX_TRIANGLE_TEXTURE0_T( d) (0x0000041c + (d) * 0x0028)
-# define NV04_DX6_MULTITEX_TRIANGLE_TEXTURE1_S( d) (0x00000420 + (d) * 0x0028)
-# define NV04_DX6_MULTITEX_TRIANGLE_TEXTURE1_T( d) (0x00000424 + (d) * 0x0028)
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW 0x00000540 /* Parameters: v0 v1 v2 v3 v4 v5 */
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V0_MASK 0x0000000f
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V1_MASK 0x000000f0
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V1_SHIFT 4
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V2_MASK 0x00000f00
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V2_SHIFT 8
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V3_MASK 0x0000f000
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V3_SHIFT 12
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V4_MASK 0x000f0000
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V4_SHIFT 16
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V5_MASK 0x00f00000
-# define NV04_DX6_MULTITEX_TRIANGLE_DRAW_V5_SHIFT 20
-
-/******************************************
-Object NV04_COLOR_KEY used on: NV04 NV10 NV15 NV20 NV40
-*/
-#define NV04_COLOR_KEY 0x00000057
-# define NV04_COLOR_KEY_SET_DMA_NOTIFY 0x00000180
-# define NV04_COLOR_KEY_FORMAT 0x00000300
-# define NV04_COLOR_KEY_VALUE 0x00000304
-
-/******************************************
-Object NV04_SOLID_LINE used on: NV04
-*/
-#define NV04_SOLID_LINE 0x0000005c
-# define NV04_SOLID_LINE_CLIP_RECTANGLE 0x00000184
-# define NV04_SOLID_LINE_PATTERN 0x00000188
-# define NV04_SOLID_LINE_ROP 0x0000018c
-# define NV04_SOLID_LINE_SURFACE 0x00000198
-# define NV04_SOLID_LINE_OPERATION 0x000002fc
-# define NV04_SOLID_LINE_COLOR_FORMAT 0x00000300
-# define NV04_SOLID_LINE_COLOR_VALUE 0x00000304
-# define NV04_SOLID_LINE_START 0x00000400 /* Parameters: x y */
-# define NV04_SOLID_LINE_START_X_MASK 0x0000ffff
-# define NV04_SOLID_LINE_START_Y_MASK 0xffff0000
-# define NV04_SOLID_LINE_START_Y_SHIFT 16
-# define NV04_SOLID_LINE_END 0x00000400 /* Parameters: x y */
-# define NV04_SOLID_LINE_END_X_MASK 0x0000ffff
-# define NV04_SOLID_LINE_END_Y_MASK 0xffff0000
-# define NV04_SOLID_LINE_END_Y_SHIFT 16
-
-/******************************************
-Object NV04_UNK005E used on: NV04
-*/
-#define NV04_UNK005E 0x0000005e
-# define NV04_UNK005E_SET_SURFACE 0x00000198
-# define NV04_UNK005E_UNK02fc 0x000002fc
-# define NV04_UNK005E_UNK0300 0x00000300
-# define NV04_UNK005E_COUNTER 0x00000304
-
-/******************************************
-Object NV05_SCALED_IMAGE_FROM_MEMORY used on: NV04
-*/
-#define NV05_SCALED_IMAGE_FROM_MEMORY 0x00000063
-# define NV05_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198
-# define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc
-# define NV05_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304
-
-/******************************************
-Object NV04_SCALED_IMAGE_FROM_MEMORY used on: NV04
-*/
-#define NV04_SCALED_IMAGE_FROM_MEMORY 0x00000077
-# define NV04_SCALED_IMAGE_FROM_MEMORY_NOP 0x00000100
-# define NV04_SCALED_IMAGE_FROM_MEMORY_NOTIFY 0x00000104
-# define NV04_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY 0x00000180
-# define NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE 0x00000184
-# define NV04_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188
-# define NV04_SCALED_IMAGE_FROM_MEMORY_ROP 0x0000018c
-# define NV04_SCALED_IMAGE_FROM_MEMORY_BETA1 0x00000190
-# define NV04_SCALED_IMAGE_FROM_MEMORY_BETA4 0x00000194
-# define NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198
-# define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT 0x00000300
-# define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304
-# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POS 0x00000308 /* Parameters: x y */
-# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_X_MASK 0x0000ffff
-# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_Y_MASK 0xffff0000
-# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_Y_SHIFT 16
-# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c /* Parameters: width height */
-# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_WIDTH_MASK 0x0000ffff
-# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_HEIGHT_MASK 0xffff0000
-# define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_HEIGHT_SHIFT 16
-# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POS 0x00000310 /* Parameters: x y */
-# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POS_X_MASK 0x0000ffff
-# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POS_Y_MASK 0xffff0000
-# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POS_Y_SHIFT 16
-# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314 /* Parameters: width height */
-# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_WIDTH_MASK 0x0000ffff
-# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_HEIGHT_MASK 0xffff0000
-# define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_HEIGHT_SHIFT 16
-# define NV04_SCALED_IMAGE_FROM_MEMORY_DU_DX 0x00000318 /* Parameters: int frac_mul_0x100000 */
-# define NV04_SCALED_IMAGE_FROM_MEMORY_DU_DX_INT_MASK 0xfff00000
-# define NV04_SCALED_IMAGE_FROM_MEMORY_DU_DX_INT_SHIFT 20
-# define NV04_SCALED_IMAGE_FROM_MEMORY_DU_DX_FRAC_MUL_0X100000_MASK 0x000fffff
-# define NV04_SCALED_IMAGE_FROM_MEMORY_DV_DY 0x0000031c /* Parameters: int frac_mul_0x100000 */
-# define NV04_SCALED_IMAGE_FROM_MEMORY_DV_DY_INT_MASK 0xfff00000
-# define NV04_SCALED_IMAGE_FROM_MEMORY_DV_DY_INT_SHIFT 20
-# define NV04_SCALED_IMAGE_FROM_MEMORY_DV_DY_FRAC_MUL_0X100000_MASK 0x000fffff
-# define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400 /* Parameters: width height */
-# define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_WIDTH_MASK 0x0000ffff
-# define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_HEIGHT_MASK 0xffff0000
-# define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_HEIGHT_SHIFT 16
-# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404 /* Parameters: pitch origin filter */
-# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_MASK 0x0000ffff
-# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_MASK 0x00ff0000
-# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_SHIFT 16
-# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER 0x0001
-# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER 0x0002
-# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_MASK 0xff000000
-# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_SHIFT 24
-# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE 0x0001
-# define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR 0x0002
-# define NV04_SCALED_IMAGE_FROM_MEMORY_OFFSET 0x00000408
-# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c /* Parameters: u_int u_frac_mul_0x10 v_int v_frac_mul_0x10 */
-# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_U_INT_MASK 0xfff00000
-# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_U_INT_SHIFT 20
-# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_U_FRAC_MUL_0X10_MASK 0x000f0000
-# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_U_FRAC_MUL_0X10_SHIFT 16
-# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_V_INT_MASK 0x0000fff0
-# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_V_INT_SHIFT 4
-# define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_V_FRAC_MUL_0X10_MASK 0x0000000f
-
-/******************************************
-Object NV_IMAGE_FROM_CPU used on: NV04
-*/
-#define NV_IMAGE_FROM_CPU 0x00000061
-# define NV_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180
-# define NV_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x00000188
-# define NV_IMAGE_FROM_CPU_PATTERN 0x0000018c
-# define NV_IMAGE_FROM_CPU_ROP 0x00000190
-# define NV_IMAGE_FROM_CPU_SURFACE 0x0000019c
-# define NV_IMAGE_FROM_CPU_OPERATION 0x000002fc
-# define NV_IMAGE_FROM_CPU_FORMAT 0x00000300
-
-/******************************************
-Object NV05_IMAGE_FROM_CPU used on: NV04
-*/
-#define NV05_IMAGE_FROM_CPU 0x00000065
-# define NV05_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180
-# define NV05_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x00000188
-# define NV05_IMAGE_FROM_CPU_PATTERN 0x0000018c
-# define NV05_IMAGE_FROM_CPU_ROP 0x00000190
-# define NV05_IMAGE_FROM_CPU_BETA1 0x00000194
-# define NV05_IMAGE_FROM_CPU_BETA4 0x00000198
-# define NV05_IMAGE_FROM_CPU_SURFACE 0x0000019c
-# define NV05_IMAGE_FROM_CPU_OPERATION 0x000002fc
-# define NV05_IMAGE_FROM_CPU_FORMAT 0x00000300
-# define NV05_IMAGE_FROM_CPU_POINT 0x00000304 /* Parameters: x y */
-# define NV05_IMAGE_FROM_CPU_POINT_X_MASK 0x0000ffff
-# define NV05_IMAGE_FROM_CPU_POINT_Y_MASK 0xffff0000
-# define NV05_IMAGE_FROM_CPU_POINT_Y_SHIFT 16
-# define NV05_IMAGE_FROM_CPU_SIZE_OUT 0x00000308 /* Parameters: x y */
-# define NV05_IMAGE_FROM_CPU_SIZE_OUT_X_MASK 0x0000ffff
-# define NV05_IMAGE_FROM_CPU_SIZE_OUT_Y_MASK 0xffff0000
-# define NV05_IMAGE_FROM_CPU_SIZE_OUT_Y_SHIFT 16
-# define NV05_IMAGE_FROM_CPU_SIZE_IN 0x0000030c /* Parameters: x y */
-# define NV05_IMAGE_FROM_CPU_SIZE_IN_X_MASK 0x0000ffff
-# define NV05_IMAGE_FROM_CPU_SIZE_IN_Y_MASK 0xffff0000
-# define NV05_IMAGE_FROM_CPU_SIZE_IN_Y_SHIFT 16
-# define NV05_IMAGE_FROM_CPU_COLOR( d) (0x00000400 + (d) * 0x0004)
-
-/******************************************
-Object NV_IMAGE_BLIT used on: NV04 NV10 NV15 NV20
-*/
-#define NV_IMAGE_BLIT 0x0000005f
-# define NV_IMAGE_BLIT_SET_DMA_NOTIFY 0x00000180
-# define NV_IMAGE_BLIT_SET_COLOR_KEY 0x00000184
-# define NV_IMAGE_BLIT_SET_CLIP_RECTANGLE 0x00000188
-# define NV_IMAGE_BLIT_SET_PATTERN 0x0000018c
-# define NV_IMAGE_BLIT_SET_ROP5 0x00000190
-# define NV_IMAGE_BLIT_SET_SURFACES_2D 0x0000019c
-# define NV_IMAGE_BLIT_OPERATION 0x000002fc
-# define NV_IMAGE_BLIT_POINT_IN 0x00000300 /* Parameters: x y */
-# define NV_IMAGE_BLIT_POINT_IN_X_MASK 0x0000ffff
-# define NV_IMAGE_BLIT_POINT_IN_Y_MASK 0xffff0000
-# define NV_IMAGE_BLIT_POINT_IN_Y_SHIFT 16
-# define NV_IMAGE_BLIT_POINT_OUT 0x00000304 /* Parameters: x y */
-# define NV_IMAGE_BLIT_POINT_OUT_X_MASK 0x0000ffff
-# define NV_IMAGE_BLIT_POINT_OUT_Y_MASK 0xffff0000
-# define NV_IMAGE_BLIT_POINT_OUT_Y_SHIFT 16
-# define NV_IMAGE_BLIT_SIZE 0x00000308 /* Parameters: width height */
-# define NV_IMAGE_BLIT_SIZE_WIDTH_MASK 0x0000ffff
-# define NV_IMAGE_BLIT_SIZE_HEIGHT_MASK 0xffff0000
-# define NV_IMAGE_BLIT_SIZE_HEIGHT_SHIFT 16
-
-/******************************************
-Object NV11_IMAGE_BLIT used on: NV15 NV20
-*/
-#define NV11_IMAGE_BLIT 0x0000009f
-
-/******************************************
-Object NV30_IMAGE_BLIT used on: NV30 NV40 G70
-*/
-#define NV30_IMAGE_BLIT 0x0000009f
-
-/******************************************
-Object NV10_TCL_PRIMITIVE_3D used on: NV10
-*/
-#define NV10_TCL_PRIMITIVE_3D 0x00000056
-# define NV10_TCL_PRIMITIVE_3D_NOP 0x00000100
-# define NV10_TCL_PRIMITIVE_3D_NOTIFY 0x00000104
-# define NV10_TCL_PRIMITIVE_3D_SET_DMA_NOTIFY 0x00000180
-# define NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY0 0x00000184
-# define NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY1 0x00000188
-# define NV10_TCL_PRIMITIVE_3D_SET_DISPLAY_LIST 0x0000018c
-# define NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY2 0x00000194
-# define NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY3 0x00000198
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ 0x00000200 /* Parameters: width x */
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_WIDTH_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_WIDTH_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_X_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT 0x00000204 /* Parameters: height y */
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT_HEIGHT_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT_HEIGHT_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_VERT_Y_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT 0x00000208 /* Parameters: type color */
-# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_pitch 0x0001
-# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_swizzle 0x0002
-# define NV10_TCL_PRIMITIVE_3D_BUFFER_FORMAT_COLOR_MASK 0x000000ff
-# define NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH 0x0000020c /* Parameters: depth/stencil buffer pitch color buffer pitch */
-# define NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH_DEPTH_STENCIL_BUFFER_PITCH_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH_DEPTH_STENCIL_BUFFER_PITCH_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_BUFFER_PITCH_COLOR_BUFFER_PITCH_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_COLOR_OFFSET 0x00000210
-# define NV10_TCL_PRIMITIVE_3D_DEPTH_OFFSET 0x00000214
-# define NV10_TCL_PRIMITIVE_3D_TX_OFFSET(d) (0x00000218 + (d) * 0x0004)
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT(d) (0x00000220 + (d) * 0x0004) /* Parameters: wrap_t wrap_s log2_height log2_width lod npot format cube_map */
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_MASK 0xf0000000
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_SHIFT 28
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_REPEAT 0x0001
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_MIRRORED_REPEAT 0x0002
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_CLAMP_TO_EDGE 0x0003
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_CLAMP_TO_BORDER 0x0004
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_T_CLAMP 0x0005
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_MASK 0x0f000000
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_REPEAT 0x0001
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_MIRRORED_REPEAT 0x0002
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_CLAMP_TO_EDGE 0x0003
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_CLAMP_TO_BORDER 0x0004
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_WRAP_S_CLAMP 0x0005
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_HEIGHT_MASK 0x00f00000
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_HEIGHT_SHIFT 20
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_WIDTH_MASK 0x000f0000
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_WIDTH_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOD_MASK 0x0000f000
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_LOD_SHIFT 12
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_NPOT_MASK 0x00000800
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_NPOT (1 << 11)
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_NPOT_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_NPOT_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_MASK 0x00000780
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_SHIFT 7
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8 0x0000
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8 0x0001
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R5G5B5A1 0x0002
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8_RECT 0x0003
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R4G4B4A4 0x0004
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R8G8B8A8 0x0006
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_INDEX8 0x000b
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT1 0x000c
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT3 0x000e
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT5 0x000f
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R5G5B5A1_RECT 0x0010
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R8G8B8A8_RECT 0x0012
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8_RECT 0x0013
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8A8 0x001a
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8_RECT_2 0x001b
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R4G4B4A4_RECT 0x001d
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8A8_RECT 0x0020
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_MASK 0x00000004
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP (1 << 2)
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE(d) (0x00000228 + (d) * 0x0004) /* Parameters: enable anisotropy */
-# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_MASK 0x40000000
-# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE (1 << 30)
-# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_MASK 0x00000030
-# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_1 0x0000
-# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_2 0x0001
-# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_4 0x0002
-# define NV10_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_8 0x0003
-# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_PITCH(d) (0x00000230 + (d) * 0x0004) /* Parameters: pitch */
-# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_PITCH_PITCH_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_PITCH_PITCH_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE(d) (0x00000240 + (d) * 0x0004) /* Parameters: width height */
-# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_WIDTH_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_WIDTH_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_HEIGHT_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER(d) (0x00000248 + (d) * 0x0004) /* Parameters: mag_filter min_filter */
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_MASK 0xf0000000
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_SHIFT 28
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST 0x0001
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR 0x0002
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_MASK 0x0f000000
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST 0x0001
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR 0x0002
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV10_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV10_TCL_PRIMITIVE_3D_TX_PALETTE_OFFSET(d) (0x00000250 + (d) * 0x0004)
-# define NV10_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE(d) (0x000003e0 + (d) * 0x0004)
-# define NV10_TCL_PRIMITIVE_3D_TX_MATRIX(x,y) (0x00000540 + (y) * 0x0010 + (x) * 0x0004)
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA(d) (0x00000260 + (d) * 0x0004) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_MASK 0xe0000000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SHIFT 29
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_MASK 0x10000000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE (1 << 28)
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_BLUE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_MASK 0x0f000000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_MASK 0x00e00000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SHIFT 21
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_MASK 0x00100000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE (1 << 20)
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_BLUE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_MASK 0x000f0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_MASK 0x0000e000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SHIFT 13
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_MASK 0x00001000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE (1 << 12)
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_BLUE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_MASK 0x00000f00
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_MASK 0x000000e0
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SHIFT 5
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_MASK 0x00000010
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE (1 << 4)
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_BLUE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_INPUT_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB(d) (0x00000268 + (d) * 0x0004) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_MASK 0xe0000000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SHIFT 29
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_MASK 0x10000000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE (1 << 28)
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_RGB 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_MASK 0x0f000000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_MASK 0x00e00000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SHIFT 21
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_MASK 0x00100000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE (1 << 20)
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_RGB 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_MASK 0x000f0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_MASK 0x0000e000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SHIFT 13
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_MASK 0x00001000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE (1 << 12)
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_RGB 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_MASK 0x00000f00
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_MASK 0x000000e0
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SHIFT 5
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_MASK 0x00000010
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE (1 << 4)
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_RGB 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_INPUT_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA(d) (0x00000278 + (d) * 0x0004) /* Parameters: scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_MASK 0x00030000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_NONE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_MASK 0x00008000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS (1 << 15)
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_NONE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_MASK 0x00004000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM (1 << 14)
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_MASK 0x00002000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13)
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_MASK 0x00001000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12)
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB(d) (0x00000280 + (d) * 0x0004) /* Parameters: rc1_tx_units_enabled rc1_rc_enabled scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_TX_UNITS_ENABLED_MASK 0x30000000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_TX_UNITS_ENABLED_SHIFT 28
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_RC_ENABLED_MASK 0x08000000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_RC_ENABLED (1 << 27)
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_RC_ENABLED_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_RC1_RC_ENABLED_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_MASK 0x00030000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_NONE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_MASK 0x00008000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS (1 << 15)
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_NONE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_MASK 0x00004000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM (1 << 14)
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_MASK 0x00002000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13)
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_MASK 0x00001000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12)
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0 0x00000270 /* Parameters: a r g b */
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_A_MASK 0xff000000
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_A_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_R_MASK 0x00ff0000
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_R_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_G_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_G_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR0_B_MASK 0x000000ff
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1 0x00000274 /* Parameters: a r g b */
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_A_MASK 0xff000000
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_A_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_R_MASK 0x00ff0000
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_R_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_G_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_G_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_RC_COLOR1_B_MASK 0x000000ff
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0 0x00000288 /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_MASK 0xe0000000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SHIFT 29
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_MASK 0x10000000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE (1 << 28)
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_RGB 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_MASK 0x0f000000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_MASK 0x00e00000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SHIFT 21
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_MASK 0x00100000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE (1 << 20)
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_RGB 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_MASK 0x000f0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_MASK 0x0000e000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SHIFT 13
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_MASK 0x00001000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE (1 << 12)
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_RGB 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_MASK 0x00000f00
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_MASK 0x000000e0
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SHIFT 5
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_MASK 0x00000010
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE (1 << 4)
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_RGB 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_INPUT_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1 0x0000028c /* Parameters: vare_mapping vare_component_usage vare_input varf_mapping varf_component_usage varf_input varg_mapping varg_component_usage varg_input color_sum_clamp */
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_MASK 0xe0000000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SHIFT 29
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_MASK 0x10000000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE (1 << 28)
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_RGB 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_MASK 0x0f000000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_MASK 0x00e00000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SHIFT 21
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_MASK 0x00100000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE (1 << 20)
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_RGB 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_MASK 0x000f0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_MASK 0x0000e000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SHIFT 13
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_MASK 0x00001000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE (1 << 12)
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_RGB 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_ALPHA 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_MASK 0x00000f00
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_ZERO 0x0000
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_FOG 0x0003
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE1_ARB 0x0008
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE0_ARB 0x0009
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_NV 0x000c
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE1_NV 0x000d
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_E_TIMES_F_NV 0x000f
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_MASK 0x00000080
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7)
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL 0x00000294 /* Parameters: local_viewer color_control */
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_LOCAL_VIEWER_MASK 0x00010000
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_LOCAL_VIEWER (1 << 16)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_LOCAL_VIEWER_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_LOCAL_VIEWER_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_COLOR_CONTROL_MASK 0x00000002
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_COLOR_CONTROL 1 // Nothing to shift
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_COLOR_CONTROL_SINGLE_COLOR 0x0000
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_COLOR_CONTROL_SEPARATE_SPECULAR_COLOR 0x0001
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE 0x00000298 /* Parameters: specular diffuse ambient emission */
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_SPECULAR_MASK 0x00000008
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_SPECULAR (1 << 3)
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_SPECULAR_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_SPECULAR_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_DIFFUSE_MASK 0x00000004
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_DIFFUSE (1 << 2)
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_DIFFUSE_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_DIFFUSE_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_AMBIENT_MASK 0x00000002
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_AMBIENT 1 // Nothing to shift
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_AMBIENT_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_AMBIENT_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_ENABLE_EMISSION_MASK 0x00000001
-# define NV10_TCL_PRIMITIVE_3D_FOG_MODE 0x0000029c
-# define NV10_TCL_PRIMITIVE_3D_FOG_COORD_DIST 0x000002a0
-# define NV10_TCL_PRIMITIVE_3D_FOG_ENABLE 0x000002a4
-# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR 0x000002a8 /* Parameters: a b g r */
-# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_A_MASK 0xff000000
-# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_A_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_B_MASK 0x00ff0000
-# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_B_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_G_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_G_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_FOG_COLOR_R_MASK 0x000000ff
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_MODE 0x000002b4
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(d) (0x000002c0 + (d) * 0x0004) /* Parameters: enable clip at x2 x2 enable clip at x1 x1 */
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X2_MASK 0x08000000
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X2 (1 << 27)
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X2_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X2_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_MASK 0x07ff0000
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X1_MASK 0x00000800
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X1 (1 << 11)
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X1_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_ENABLE_CLIP_AT_X1_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X1_MASK 0x000007ff
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(d) (0x000002e0 + (d) * 0x0004) /* Parameters: enable clip at y2 y2 enable clip at y1 y1 */
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y2_MASK 0x08000000
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y2 (1 << 27)
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y2_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y2_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_MASK 0x07ff0000
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y1_MASK 0x00000800
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y1 (1 << 11)
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y1_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_ENABLE_CLIP_AT_Y1_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y1_MASK 0x000007ff
-# define NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE 0x00000300
-# define NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE 0x00000304
-# define NV10_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE 0x00000308
-# define NV10_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE 0x0000030c
-# define NV10_TCL_PRIMITIVE_3D_DITHER_ENABLE 0x00000310
-# define NV10_TCL_PRIMITIVE_3D_LIGHTING_ENABLE 0x00000314
-# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETERS_ENABLE 0x00000318
-# define NV10_TCL_PRIMITIVE_3D_POINT_SMOOTH_ENABLE 0x0000031c
-# define NV10_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE 0x00000320
-# define NV10_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE 0x00000324
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_WEIGHT_ENABLE 0x00000328
-# define NV10_TCL_PRIMITIVE_3D_STENCIL_ENABLE 0x0000032c
-# define NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE 0x00000330
-# define NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE 0x00000334
-# define NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE 0x00000338
-# define NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC 0x0000033c
-# define NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF 0x00000340
-# define NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC 0x00000344
-# define NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_DST 0x00000348
-# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR 0x0000034c /* Parameters: a r g b */
-# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_A_MASK 0xff000000
-# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_A_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_R_MASK 0x00ff0000
-# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_R_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_G_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_G_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_BLEND_COLOR_B_MASK 0x000000ff
-# define NV10_TCL_PRIMITIVE_3D_BLEND_EQUATION 0x00000350
-# define NV10_TCL_PRIMITIVE_3D_DEPTH_FUNC 0x00000354
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK 0x00000358 /* Parameters: a r g b */
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_A_MASK 0xff000000
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_A_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_A_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_A_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_R_MASK 0x00ff0000
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_R_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_R_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_R_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_G_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_G_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_G_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_G_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MASK_B_MASK 0x000000ff
-# define NV10_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE 0x0000035c
-# define NV10_TCL_PRIMITIVE_3D_STENCIL_MASK 0x00000360
-# define NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC 0x00000364
-# define NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_REF 0x00000368
-# define NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_MASK 0x0000036c
-# define NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL 0x00000370
-# define NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL 0x00000374
-# define NV10_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS 0x00000378
-# define NV10_TCL_PRIMITIVE_3D_SHADE_MODEL 0x0000037c
-# define NV10_TCL_PRIMITIVE_3D_LINE_WIDTH 0x00000380
-# define NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR 0x00000384
-# define NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS 0x00000388
-# define NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT 0x0000038c
-# define NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK 0x00000390
-# define NV10_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR 0x00000394
-# define NV10_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR 0x00000398
-# define NV10_TCL_PRIMITIVE_3D_CULL_FACE 0x0000039c
-# define NV10_TCL_PRIMITIVE_3D_FRONT_FACE 0x000003a0
-# define NV10_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE 0x000003a4
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_R 0x000003a8
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_G 0x000003ac
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_B 0x000003b0
-# define NV10_TCL_PRIMITIVE_3D_COLOR_MATERIAL_A 0x000003b4
-# define NV10_TCL_PRIMITIVE_3D_COLOR_CONTROL 0x000003b8 /* Parameters: color_control */
-# define NV10_TCL_PRIMITIVE_3D_COLOR_CONTROL_COLOR_CONTROL_MASK 0x00000001
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS 0x000003bc /* Parameters: light 7 light 6 light 5 light 4 light 3 light 2 light 1 light 0 */
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_MASK 0x00004000
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7 (1 << 14)
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_MASK 0x00001000
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6 (1 << 12)
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_MASK 0x00000400
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5 (1 << 10)
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_MASK 0x00000100
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4 (1 << 8)
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_MASK 0x00000040
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3 (1 << 6)
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_MASK 0x00000010
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2 (1 << 4)
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_MASK 0x00000004
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1 (1 << 2)
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0_MASK 0x00000001
-# define NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE( d) (0x000003c0 + (d) * 0x0004)
-# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE 0x000003e8 /* Parameters: projection modelview0 modelview1 */
-# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_PROJECTION_MASK 0x00000004
-# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_PROJECTION (1 << 2)
-# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_PROJECTION_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_PROJECTION_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW0_MASK 0x00000002
-# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW0 1 // Nothing to shift
-# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW0_TRUE 0x0001
-# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW0_FALSE 0x0000
-# define NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE_MODELVIEW1_MASK 0x00000001
-# define NV10_TCL_PRIMITIVE_3D_POINT_SIZE 0x000003ec
-# define NV10_TCL_PRIMITIVE_3D_MODELVIEW0_MATRIX( d) (0x00000400 + (d) * 0x0004)
-# define NV10_TCL_PRIMITIVE_3D_MODELVIEW1_MATRIX( d) (0x00000440 + (d) * 0x0004)
-# define NV10_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW0_MATRIX( d) (0x00000480 + (d) * 0x0004)
-# define NV10_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW1_MATRIX( d) (0x000004c0 + (d) * 0x0004)
-# define NV10_TCL_PRIMITIVE_3D_PROJECTION_MATRIX( d) (0x00000500 + (d) * 0x0004)
-# define NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_A(d) (0x00000600 + (d) * 0x0010)
-# define NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_B(d) (0x00000604 + (d) * 0x0010)
-# define NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_C(d) (0x00000608 + (d) * 0x0010)
-# define NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_D(d) (0x0000060c + (d) * 0x0010)
-# define NV10_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT 0x00000680
-# define NV10_TCL_PRIMITIVE_3D_FOG_EQUATION_LINEAR 0x00000684
-# define NV10_TCL_PRIMITIVE_3D_FOG_EQUATION_QUADRATIC 0x00000688
-# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_A 0x000006a0
-# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_B 0x000006a4
-# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_C 0x000006a8
-# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_D 0x000006ac
-# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_E 0x000006b0
-# define NV10_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_F 0x000006b4
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000006c4
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000006c8
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000006cc
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_X 0x000006e8
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_Y 0x000006ec
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_Z 0x000006f0
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_W 0x000006f4
-# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_A 0x000006f8
-# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_B 0x000006fc
-# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_C 0x00000700
-# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_D 0x00000704
-# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_E 0x00000708
-# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_F 0x0000070c
-# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_G 0x00000710
-# define NV10_TCL_PRIMITIVE_3D_POINT_PARAMETER_H 0x00000714
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(d) (0x00000800 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(d) (0x00000804 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(d) (0x00000808 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(d) (0x0000080c + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(d) (0x00000810 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(d) (0x00000814 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(d) (0x00000818 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(d) (0x0000081c + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(d) (0x00000820 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_X(d) (0x00000828 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Y(d) (0x0000082c + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Z(d) (0x00000830 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_X(d) (0x00000834 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Y(d) (0x00000838 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Z(d) (0x0000083c + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(d) (0x00000840 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_EXPONENT(d) (0x00000844 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_B(d) (0x00000848 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(d) (0x0000084c + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Y(d) (0x00000850 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Z(d) (0x00000854 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_C(d) (0x00000858 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(d) (0x0000085c + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_Y(d) (0x00000860 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_Z(d) (0x00000864 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(d) (0x00000868 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(d) (0x0000086c + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(d) (0x00000870 + (d) * 0x0080)
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_3F_X 0x00000c00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Y 0x00000c04
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Z 0x00000c08
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_X 0x00000c18
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Y 0x00000c1c
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Z 0x00000c20
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_POS_4F_W 0x00000c24
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_X 0x00000c30
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Y 0x00000c34
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Z 0x00000c38
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY 0x00000c40 /* Parameters: y x */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z 0x00000c44 /* Parameters: z */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_R 0x00000c50
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_G 0x00000c54
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_B 0x00000c58
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_A 0x00000c5c
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_3F_R 0x00000c60
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_3F_G 0x00000c64
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_3F_B 0x00000c68
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I 0x00000c6c /* Parameters: a b g r */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_MASK 0xff000000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_MASK 0x00ff0000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_MASK 0x000000ff
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_R 0x00000c80
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_G 0x00000c84
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_B 0x00000c88
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I 0x00000c8c /* Parameters: a b g r */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_MASK 0xff000000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_MASK 0x00ff0000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_R_MASK 0x000000ff
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_S 0x00000c90
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_T 0x00000c94
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I 0x00000c98 /* Parameters: t s */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_S_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_S 0x00000ca0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_T 0x00000ca4
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_R 0x00000ca8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_Q 0x00000cac
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST 0x00000cb0 /* Parameters: t s */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ 0x00000cb4 /* Parameters: q r */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_S 0x00000cb8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_T 0x00000cbc
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I 0x00000cc0 /* Parameters: t s */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_S_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_S 0x00000cc8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_T 0x00000ccc
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_R 0x00000cd0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_Q 0x00000cd4
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST 0x00000cd8 /* Parameters: t s */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ 0x00000cdc /* Parameters: q r */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_FOG_1F 0x00000ce0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_WGH_1F 0x00000ce4
-# define NV10_TCL_PRIMITIVE_3D_EDGEFLAG_ENABLE 0x00000cec
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR( d) (0x00000d04 + (d) * 0x0008) /* Parameters: stride fields type */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR_STRIDE_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR_STRIDE_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR_FIELDS_MASK 0x000000f0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR_FIELDS_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR_TYPE_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_VALIDATE 0x00000cf0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_POS 0x00000d00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS 0x00000d04 /* Parameters: stride fields type */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_STRIDE_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_STRIDE_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_FIELDS_MASK 0x000000f0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_FIELDS_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_POS_TYPE_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_COL 0x00000d08
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL 0x00000d0c /* Parameters: stride fields type */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_STRIDE_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_STRIDE_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_FIELDS_MASK 0x000000f0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_FIELDS_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL_TYPE_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_COL2 0x00000d10
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2 0x00000d14 /* Parameters: stride fields type */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_STRIDE_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_STRIDE_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_FIELDS_MASK 0x000000f0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_FIELDS_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_COL2_TYPE_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_TX0 0x00000d18
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0 0x00000d1c /* Parameters: stride fields type */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_STRIDE_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_STRIDE_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_FIELDS_MASK 0x000000f0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_FIELDS_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX0_TYPE_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_TX1 0x00000d20
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1 0x00000d24 /* Parameters: stride fields type */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_STRIDE_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_STRIDE_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_FIELDS_MASK 0x000000f0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_FIELDS_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_TX1_TYPE_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_NOR 0x00000d28
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR 0x00000d2c /* Parameters: stride fields type */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_STRIDE_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_STRIDE_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_FIELDS_MASK 0x000000f0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_FIELDS_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_NOR_TYPE_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_WGH 0x00000d30
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH 0x00000d34 /* Parameters: stride fields type */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_STRIDE_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_STRIDE_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_FIELDS_MASK 0x000000f0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_FIELDS_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_WGH_TYPE_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_OFFSET_FOG 0x00000d38
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG 0x00000d3c /* Parameters: stride fields type */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_STRIDE_MASK 0x0000ff00
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_STRIDE_SHIFT 8
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_FIELDS_MASK 0x000000f0
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_FIELDS_SHIFT 4
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_FORMAT_FOG_TYPE_MASK 0x0000000f
-# define NV10_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE 0x00000d40
-# define NV10_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP 0x00000d44
-# define NV10_TCL_PRIMITIVE_3D_BEGIN_END 0x00000dfc
-# define NV10_TCL_PRIMITIVE_3D_INDEX_DATA 0x00000e00 /* Parameters: index1 index0 */
-# define NV10_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX1_MASK 0xffff0000
-# define NV10_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX1_SHIFT 16
-# define NV10_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX0_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_BEGIN_END 0x000013fc
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS 0x00001400 /* Parameters: count_minus_1 first */
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS_COUNT_MINUS_1_MASK 0xff000000
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS_COUNT_MINUS_1_SHIFT 24
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_MASK 0x0000ffff
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_X 0x00001638
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_Y 0x0000163c
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_Z 0x00001640
-# define NV10_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_W 0x00001644
-# define NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_DATA 0x00001800
-
-/******************************************
-Object NV11_TCL_PRIMITIVE_3D used on: NV15
-*/
-#define NV11_TCL_PRIMITIVE_3D 0x00000096
-
-/******************************************
-Object NV17_TCL_PRIMITIVE_3D used on: NV15
-*/
-#define NV17_TCL_PRIMITIVE_3D 0x00000099
-# define NV17_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY4 0x000001ac
-# define NV17_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY5 0x000001b0
-# define NV17_TCL_PRIMITIVE_3D_COLOR_MASK_ENABLE 0x000002bc
-# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH 0x00000d5c /* Parameters: pitch */
-# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH_PITCH_MASK 0x0000ffff
-# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_OFFSET 0x00000d60
-# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_FILL_VALUE 0x00000d68
-# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_CLEAR_ENABLE 0x00000d6c
-# define NV17_TCL_PRIMITIVE_3D_LMA_DEPTH_ENABLE 0x00001658
-
-/******************************************
-Object NV10_IMAGE_FROM_CPU used on: NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV10_IMAGE_FROM_CPU 0x0000008a
-# define NV10_IMAGE_FROM_CPU_SET_DMA_NOTIFY 0x00000180
-# define NV10_IMAGE_FROM_CPU_SET_CONTEXT_CLIP_RECTANGLE 0x00000188
-# define NV10_IMAGE_FROM_CPU_SET_IMAGE_PATTERN 0x0000018c
-# define NV10_IMAGE_FROM_CPU_SET_RASTER_OP 0x00000190
-# define NV10_IMAGE_FROM_CPU_SET_CONTEXT_SURFACES_2D 0x0000019c
-# define NV10_IMAGE_FROM_CPU_OPERATION 0x000002fc
-# define NV10_IMAGE_FROM_CPU_FORMAT 0x00000300
-# define NV10_IMAGE_FROM_CPU_POINT 0x00000304 /* Parameters: x y */
-# define NV10_IMAGE_FROM_CPU_POINT_X_MASK 0x0000ffff
-# define NV10_IMAGE_FROM_CPU_POINT_Y_MASK 0xffff0000
-# define NV10_IMAGE_FROM_CPU_POINT_Y_SHIFT 16
-# define NV10_IMAGE_FROM_CPU_SIZE_OUT 0x00000308 /* Parameters: width height */
-# define NV10_IMAGE_FROM_CPU_SIZE_OUT_WIDTH_MASK 0x0000ffff
-# define NV10_IMAGE_FROM_CPU_SIZE_OUT_HEIGHT_MASK 0xffff0000
-# define NV10_IMAGE_FROM_CPU_SIZE_OUT_HEIGHT_SHIFT 16
-# define NV10_IMAGE_FROM_CPU_SIZE_IN 0x0000030c /* Parameters: width height */
-# define NV10_IMAGE_FROM_CPU_SIZE_IN_WIDTH_MASK 0x0000ffff
-# define NV10_IMAGE_FROM_CPU_SIZE_IN_HEIGHT_MASK 0xffff0000
-# define NV10_IMAGE_FROM_CPU_SIZE_IN_HEIGHT_SHIFT 16
-# define NV10_IMAGE_FROM_CPU_HLINE 0x00000400
-
-/******************************************
-Object NV10_PRIMITIVE_2D used on: NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV10_PRIMITIVE_2D 0x0000007b
-# define NV10_PRIMITIVE_2D_SET_DMA_NOTIFY 0x00000180
-# define NV10_PRIMITIVE_2D_SET_SURFACE 0x00000184
-# define NV10_PRIMITIVE_2D_SET_FORMAT 0x00000300
-# define NV10_PRIMITIVE_2D_SET_POINT 0x00000304 /* Parameters: x y */
-# define NV10_PRIMITIVE_2D_SET_POINT_X_MASK 0x0000ffff
-# define NV10_PRIMITIVE_2D_SET_POINT_Y_MASK 0xffff0000
-# define NV10_PRIMITIVE_2D_SET_POINT_Y_SHIFT 16
-# define NV10_PRIMITIVE_2D_SET_SIZE 0x00000308 /* Parameters: width height */
-# define NV10_PRIMITIVE_2D_SET_SIZE_WIDTH_MASK 0x0000ffff
-# define NV10_PRIMITIVE_2D_SET_SIZE_HEIGHT_MASK 0xffff0000
-# define NV10_PRIMITIVE_2D_SET_SIZE_HEIGHT_SHIFT 16
-# define NV10_PRIMITIVE_2D_SET_CLIP_HORIZ 0x0000030c /* Parameters: width x */
-# define NV10_PRIMITIVE_2D_SET_CLIP_HORIZ_WIDTH_MASK 0xffff0000
-# define NV10_PRIMITIVE_2D_SET_CLIP_HORIZ_WIDTH_SHIFT 16
-# define NV10_PRIMITIVE_2D_SET_CLIP_HORIZ_X_MASK 0x0000ffff
-# define NV10_PRIMITIVE_2D_SET_CLIP_VERT 0x00000310 /* Parameters: height y */
-# define NV10_PRIMITIVE_2D_SET_CLIP_VERT_HEIGHT_MASK 0xffff0000
-# define NV10_PRIMITIVE_2D_SET_CLIP_VERT_HEIGHT_SHIFT 16
-# define NV10_PRIMITIVE_2D_SET_CLIP_VERT_Y_MASK 0x0000ffff
-# define NV10_PRIMITIVE_2D_SET_DATA( d) (0x00000400 + (d) * 0x0004)
-
-/******************************************
-Object NV10_VIDEO_DISPLAY used on: NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV10_VIDEO_DISPLAY 0x0000007c
-# define NV10_VIDEO_DISPLAY_COUNTER 0x00000050
-# define NV10_VIDEO_DISPLAY_SET_DMA_FROM_MEMORY 0x00000180
-# define NV10_VIDEO_DISPLAY_SET_DMA_IN_MEMORY0 0x00000184
-# define NV10_VIDEO_DISPLAY_SET_DMA_IN_MEMORY1 0x00000188
-# define NV10_VIDEO_DISPLAY_SET_OBJECT3 0x0000019c
-# define NV10_VIDEO_DISPLAY_SIZE 0x000002f8 /* Parameters: height width */
-# define NV10_VIDEO_DISPLAY_SIZE_HEIGHT_MASK 0xffff0000
-# define NV10_VIDEO_DISPLAY_SIZE_HEIGHT_SHIFT 16
-# define NV10_VIDEO_DISPLAY_SIZE_WIDTH_MASK 0x0000ffff
-# define NV10_VIDEO_DISPLAY_OFFSET 0x00000300
-
-/******************************************
-Object NV10_UNK0072 used on: NV10 NV15 NV20 NV40 G70
-*/
-#define NV10_UNK0072 0x00000072
-# define NV10_UNK0072_COUNTER 0x00000050
-# define NV40_UNK0072_SET_OBJECT 0x00000060
-# define NV10_UNK0072_SET_DMA_NOTIFY 0x00000180
-
-/******************************************
-Object NV10_SCALED_IMAGE_FROM_MEMORY used on: NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV10_SCALED_IMAGE_FROM_MEMORY 0x00000089
-# define NV10_SCALED_IMAGE_FROM_MEMORY_COUNTER 0x00000050
-# define NV10_SCALED_IMAGE_FROM_MEMORY_SET_DMA_IN_MEMORY 0x00000184
-# define NV10_SCALED_IMAGE_FROM_MEMORY_SET_RASTER_OP 0x0000018c
-# define NV10_SCALED_IMAGE_FROM_MEMORY_SET_IMAGE_PATTERN 0x00000188
-# define NV10_SCALED_IMAGE_FROM_MEMORY_SET_SURFACE 0x00000198
-# define NV10_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304
-# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_POS 0x00000308 /* Parameters: x y */
-# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_X_MASK 0x0000ffff
-# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_Y_MASK 0xffff0000
-# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_POS_Y_SHIFT 16
-# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c /* Parameters: width height */
-# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_WIDTH_MASK 0x0000ffff
-# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_HEIGHT_MASK 0xffff0000
-# define NV10_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_HEIGHT_SHIFT 16
-# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_POS 0x00000310 /* Parameters: x y */
-# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_POS_X_MASK 0x0000ffff
-# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_POS_Y_MASK 0xffff0000
-# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_POS_Y_SHIFT 16
-# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314 /* Parameters: width height */
-# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_WIDTH_MASK 0x0000ffff
-# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_HEIGHT_MASK 0xffff0000
-# define NV10_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_HEIGHT_SHIFT 16
-# define NV10_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400 /* Parameters: width height */
-# define NV10_SCALED_IMAGE_FROM_MEMORY_SIZE_WIDTH_MASK 0x0000ffff
-# define NV10_SCALED_IMAGE_FROM_MEMORY_SIZE_HEIGHT_MASK 0xffff0000
-# define NV10_SCALED_IMAGE_FROM_MEMORY_SIZE_HEIGHT_SHIFT 16
-# define NV10_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404 /* Parameters: pitch */
-# define NV10_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_MASK 0x0000ffff
-# define NV10_SCALED_IMAGE_FROM_MEMORY_OFFSET 0x00000408
-# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c /* Parameters: u_int u_frac_mul_0x10 v_int v_frac_mul_0x10 */
-# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_U_INT_MASK 0xfff00000
-# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_U_INT_SHIFT 20
-# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_U_FRAC_MUL_0X10_MASK 0x000f0000
-# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_U_FRAC_MUL_0X10_SHIFT 16
-# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_V_INT_MASK 0x0000fff0
-# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_V_INT_SHIFT 4
-# define NV10_SCALED_IMAGE_FROM_MEMORY_POINT_V_FRAC_MUL_0X10_MASK 0x0000000f
-
-/******************************************
-Object NV10_CONTEXT_SURFACES_2D used on: NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV10_CONTEXT_SURFACES_2D 0x00000062
-# define NV10_CONTEXT_SURFACES_2D_SET_DMA_NOTIFY 0x00000180
-# define NV10_CONTEXT_SURFACES_2D_SET_DMA_IN_MEMORY0 0x00000184
-# define NV10_CONTEXT_SURFACES_2D_SET_DMA_IN_MEMORY1 0x00000188
-# define NV10_CONTEXT_SURFACES_2D_FORMAT 0x00000300 /* Parameters: color type width height */
-# define NV10_CONTEXT_SURFACES_2D_FORMAT_COLOR_MASK 0x000000ff
-# define NV10_CONTEXT_SURFACES_2D_FORMAT_TYPE_MASK 0x0000ff80
-# define NV10_CONTEXT_SURFACES_2D_FORMAT_TYPE_SHIFT 7
-# define NV10_CONTEXT_SURFACES_2D_FORMAT_TYPE_pitch 0x0001
-# define NV10_CONTEXT_SURFACES_2D_FORMAT_TYPE_swizzle 0x0002
-# define NV10_CONTEXT_SURFACES_2D_FORMAT_WIDTH_MASK 0x00ff0000
-# define NV10_CONTEXT_SURFACES_2D_FORMAT_WIDTH_SHIFT 16
-# define NV10_CONTEXT_SURFACES_2D_FORMAT_HEIGHT_MASK 0xff000000
-# define NV10_CONTEXT_SURFACES_2D_FORMAT_HEIGHT_SHIFT 24
-# define NV10_CONTEXT_SURFACES_2D_PITCH 0x00000304 /* Parameters: src dst */
-# define NV10_CONTEXT_SURFACES_2D_PITCH_SRC_MASK 0x0000ffff
-# define NV10_CONTEXT_SURFACES_2D_PITCH_DST_MASK 0xffff0000
-# define NV10_CONTEXT_SURFACES_2D_PITCH_DST_SHIFT 16
-# define NV10_CONTEXT_SURFACES_2D_OFFSET_SRC 0x00000308
-# define NV10_CONTEXT_SURFACES_2D_OFFSET_DST 0x0000030c
-
-/******************************************
-Object NV04_CONTEXT_SURFACES_2D used on: NV04 NV10 NV15
-*/
-#define NV04_CONTEXT_SURFACES_2D 0x00000042
-# define NV04_CONTEXT_SURFACES_2D_NOTIFY 0x00000104
-# define NV04_CONTEXT_SURFACES_2D_SET_DMA_NOTIFY 0x00000180
-# define NV04_CONTEXT_SURFACES_2D_SET_DMA_IMAGE_SRC 0x00000184
-# define NV04_CONTEXT_SURFACES_2D_SET_DMA_IMAGE_DST 0x00000188
-# define NV04_CONTEXT_SURFACES_2D_FORMAT 0x00000300
-# define NV04_CONTEXT_SURFACES_2D_PITCH 0x00000304 /* Parameters: src dst */
-# define NV04_CONTEXT_SURFACES_2D_PITCH_SRC_MASK 0x0000ffff
-# define NV04_CONTEXT_SURFACES_2D_PITCH_DST_MASK 0xffff0000
-# define NV04_CONTEXT_SURFACES_2D_PITCH_DST_SHIFT 16
-# define NV04_CONTEXT_SURFACES_2D_OFFSET_SRC 0x00000308
-# define NV04_CONTEXT_SURFACES_2D_OFFSET_DST 0x0000030c
-
-/******************************************
-Object NV04_IMAGE_PATTERN used on: NV04 NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV04_IMAGE_PATTERN 0x00000044
-# define NV04_IMAGE_PATTERN_COLOR_FORMAT 0x00000300
-# define NV04_IMAGE_PATTERN_MONO_FORMAT 0x00000304
-# define NV04_IMAGE_PATTERN_SELECT 0x0000030c
-# define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE 0x00000308
-# define NV04_IMAGE_PATTERN_MONOCHROME_COLOR0 0x00000310
-# define NV04_IMAGE_PATTERN_MONOCHROME_COLOR1 0x00000314
-# define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN0 0x00000318
-# define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN1 0x0000031c
-
-/******************************************
-Object NV20_SWIZZLED_SURFACE used on: NV20 NV30 NV40 G70
-*/
-#define NV20_SWIZZLED_SURFACE 0x0000009e
-# define NV20_SWIZZLED_SURFACE_SET_OBJECT0 0x00000180
-# define NV20_SWIZZLED_SURFACE_SET_OBJECT1 0x00000184
-# define NV20_SWIZZLED_SURFACE_FORMAT 0x00000300 /* Parameters: log2_height log2_width color */
-# define NV20_SWIZZLED_SURFACE_FORMAT_LOG2_HEIGHT_MASK 0xff000000
-# define NV20_SWIZZLED_SURFACE_FORMAT_LOG2_HEIGHT_SHIFT 24
-# define NV20_SWIZZLED_SURFACE_FORMAT_LOG2_WIDTH_MASK 0x00ff0000
-# define NV20_SWIZZLED_SURFACE_FORMAT_LOG2_WIDTH_SHIFT 16
-# define NV20_SWIZZLED_SURFACE_FORMAT_COLOR_MASK 0x0000ffff
-# define NV20_SWIZZLED_SURFACE_OFFSET 0x00000304
-
-/******************************************
-Object NV20_TCL_PRIMITIVE_3D used on: NV20
-*/
-#define NV20_TCL_PRIMITIVE_3D 0x00000097
-# define NV20_TCL_PRIMITIVE_3D_NOP 0x00000100
-# define NV20_TCL_PRIMITIVE_3D_NOTIFY 0x00000104
-# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT0 0x00000180
-# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT1 0x00000184
-# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT2 0x00000188
-# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT3 0x00000194
-# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT4 0x00000198
-# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT5 0x0000019c
-# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT6 0x000001a0
-# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT7 0x000001a4
-# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT8 0x000001a8
-# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT9 0x000001ac
-# define NV20_TCL_PRIMITIVE_3D_SET_OBJECT10 0x000001b0
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ 0x00000200 /* Parameters: width x */
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_WIDTH_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_WIDTH_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ_X_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_VERT 0x00000204 /* Parameters: height y */
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_VERT_HEIGHT_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_VERT_HEIGHT_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_VERT_Y_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT 0x00000208 /* Parameters: type color */
-# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_pitch 0x0001
-# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT_TYPE_swizzle 0x0002
-# define NV20_TCL_PRIMITIVE_3D_BUFFER_FORMAT_COLOR_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_BUFFER_PITCH 0x0000020c /* Parameters: zs_pitch color_pitch */
-# define NV20_TCL_PRIMITIVE_3D_BUFFER_PITCH_ZS_PITCH_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_BUFFER_PITCH_ZS_PITCH_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_BUFFER_PITCH_COLOR_PITCH_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_COLOR_OFFSET 0x00000210
-# define NV20_TCL_PRIMITIVE_3D_DEPTH_OFFSET 0x00000214
-# define NV20_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH 0x0000022c /* Parameters: pitch */
-# define NV20_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH_PITCH_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_OFFSET 0x00000230
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_CONTROL 0x00000294
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL 0x00000298 /* Parameters: back_specular back_ambient back_diffuse back_emission front_specular front_ambient front_diffuse front_emission */
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_SPECULAR_MASK 0x00004000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_SPECULAR (1 << 14)
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_SPECULAR_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_SPECULAR_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_AMBIENT_MASK 0x00001000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_AMBIENT (1 << 12)
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_AMBIENT_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_AMBIENT_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_DIFFUSE_MASK 0x00000400
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_DIFFUSE (1 << 10)
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_DIFFUSE_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_DIFFUSE_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_EMISSION_MASK 0x00000100
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_EMISSION (1 << 8)
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_EMISSION_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_BACK_EMISSION_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_SPECULAR_MASK 0x00000040
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_SPECULAR (1 << 6)
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_SPECULAR_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_SPECULAR_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_AMBIENT_MASK 0x00000010
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_AMBIENT (1 << 4)
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_AMBIENT_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_AMBIENT_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_DIFFUSE_MASK 0x00000004
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_DIFFUSE (1 << 2)
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_DIFFUSE_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_DIFFUSE_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_CONTROL_FRONT_EMISSION_MASK 0x00000001
-# define NV20_TCL_PRIMITIVE_3D_FOG_MODE 0x0000029c
-# define NV20_TCL_PRIMITIVE_3D_FOG_COORD_DIST 0x000002a0
-# define NV20_TCL_PRIMITIVE_3D_FOG_ENABLE 0x000002a4
-# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR 0x000002a8 /* Parameters: a b g r */
-# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_A_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_A_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_B_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_B_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_G_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_G_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_FOG_COLOR_R_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_MODE 0x000002b4
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(d) (0x000002c0 + (d) * 0x0004) /* Parameters: x2 x1 */
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X1_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(d) (0x000002e0 + (d) * 0x0004) /* Parameters: y2 y1 */
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y1_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE 0x00000300
-# define NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE 0x00000304
-# define NV20_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE 0x00000308
-# define NV20_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE 0x0000030c
-# define NV20_TCL_PRIMITIVE_3D_DITHER_ENABLE 0x00000310
-# define NV20_TCL_PRIMITIVE_3D_LIGHTING_ENABLE 0x00000314
-# define NV20_TCL_PRIMITIVE_3D_POINT_SMOOTH_ENABLE 0x0000031c
-# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETERS_ENABLE 0x00000318
-# define NV20_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE 0x00000320
-# define NV20_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE 0x00000324
-# define NV20_TCL_PRIMITIVE_3D_STENCIL_ENABLE 0x0000032c
-# define NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE 0x00000330
-# define NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE 0x00000334
-# define NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE 0x00000338
-# define NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC 0x0000033c
-# define NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF 0x00000340
-# define NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC 0x00000344
-# define NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_DST 0x00000348
-# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR 0x0000034c /* Parameters: a r g b */
-# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_A_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_A_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_R_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_R_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_G_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_G_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_BLEND_COLOR_B_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_BLEND_EQUATION 0x00000350
-# define NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC 0x00000354
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK 0x00000358 /* Parameters: a r g b */
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_A_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_A_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_A_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_A_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_R_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_R_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_R_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_R_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_G_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_G_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_G_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_G_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MASK_B_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE 0x0000035c
-# define NV20_TCL_PRIMITIVE_3D_STENCIL_MASK 0x00000360
-# define NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC 0x00000364
-# define NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_REF 0x00000368
-# define NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_MASK 0x0000036c
-# define NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL 0x00000370
-# define NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZFAIL 0x00000374
-# define NV20_TCL_PRIMITIVE_3D_STENCIL_OP_ZPASS 0x00000378
-# define NV20_TCL_PRIMITIVE_3D_SHADE_MODEL 0x0000037c
-# define NV20_TCL_PRIMITIVE_3D_LINE_WIDTH 0x00000380
-# define NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR 0x00000384
-# define NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS 0x00000388
-# define NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT 0x0000038c
-# define NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK 0x00000390
-# define NV20_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR 0x00000394
-# define NV20_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR 0x00000398
-# define NV20_TCL_PRIMITIVE_3D_CULL_FACE 0x0000039c
-# define NV20_TCL_PRIMITIVE_3D_FRONT_FACE 0x000003a0
-# define NV20_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE 0x000003a4
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_R 0x000003a8
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_G 0x000003ac
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_B 0x000003b0
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_A 0x000003b4
-# define NV20_TCL_PRIMITIVE_3D_SEPARATE_SPECULAR_ENABLE 0x000003b8
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS 0x000003bc /* Parameters: light 7 light 6 light 5 light 4 light 3 light 2 light 1 light 0 */
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_MASK 0x00002000
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7 (1 << 13)
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_MASK 0x00008000
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6 (1 << 15)
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_MASK 0x00000200
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5 (1 << 9)
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_MASK 0x00000800
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4 (1 << 11)
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_MASK 0x00000020
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3 (1 << 5)
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_MASK 0x00000080
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2 (1 << 7)
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_MASK 0x00000002
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1 1 // Nothing to shift
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0_MASK 0x00000008
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0 (1 << 3)
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(d) (0x000003c0 + (d) * 0x0004)
-# define NV20_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE(d) (0x00000420 + (d) * 0x0004)
-# define NV20_TCL_PRIMITIVE_3D_POINT_SIZE 0x0000043c
-# define NV20_TCL_PRIMITIVE_3D_MODELVIEW_MATRIX( d) (0x00000480 + (d) * 0x0004)
-# define NV20_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW_MATRIX( d) (0x00000580 + (d) * 0x0004)
-# define NV20_TCL_PRIMITIVE_3D_PROJECTION_MATRIX( d) (0x00000680 + (d) * 0x0004)
-# define NV20_TCL_PRIMITIVE_3D_TX_MATRIX(x,y) (0x000006c0 + (y) * 0x0010 + (x) * 0x0004)
-# define NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_A(d) (0x00000840 + (d) * 0x0010)
-# define NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_B(d) (0x00000844 + (d) * 0x0010)
-# define NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_C(d) (0x00000848 + (d) * 0x0010)
-# define NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_D(d) (0x0000084c + (d) * 0x0010)
-# define NV20_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT 0x000009c0
-# define NV20_TCL_PRIMITIVE_3D_FOG_EQUATION_LINEAR 0x000009c4
-# define NV20_TCL_PRIMITIVE_3D_FOG_EQUATION_QUADRATIC 0x000009c8
-# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_A 0x000009e0
-# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_B 0x000009e4
-# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_C 0x000009e8
-# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_D 0x000009ec
-# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_E 0x000009f0
-# define NV20_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_F 0x000009f4
-# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE 0x00000a1c /* Parameters: coord_replace r_mode enable */
-# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_MASK 0x00000800
-# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE (1 << 11)
-# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_MASK 0x00000006
-# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_SHIFT 1
-# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_R 0x0001
-# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_S 0x0002
-# define NV20_TCL_PRIMITIVE_3D_POINT_SPRITE_ENABLE_MASK 0x00000001
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_OX 0x00000a20
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_OY 0x00000a24
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_DEPTH_AVG_S 0x00000a28
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_UNKNOWN_A 0x00000a2c
-# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_A 0x00000a30
-# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_B 0x00000a34
-# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_C 0x00000a38
-# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_D 0x00000a3c
-# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_E 0x00000a40
-# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_F 0x00000a44
-# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_G 0x00000a48
-# define NV20_TCL_PRIMITIVE_3D_POINT_PARAMETER_H 0x00000a4c
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_PX_DIV2 0x00000af0
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_PY_DIV2 0x00000af4
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_DEPTH_HALF_S 0x00000af8
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_UNKNOWN_B 0x00000afc
-# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST0 0x00000b00
-# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST1 0x00000b04
-# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST2 0x00000b08
-# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST3 0x00000b0c
-# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_X 0x00000b80
-# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_Y 0x00000b84
-# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_Z 0x00000b88
-# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_W 0x00000b8c
-# define NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID 0x00001ea4
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x00000a10
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x00000a14
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x00000a18
-# define NV20_TCL_PRIMITIVE_3D_TX_OFFSET(d) (0x00001b00 + (d) * 0x0040)
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT(d) (0x00001b04 + (d) * 0x0040) /* Parameters: log2_height log2_width lod format cube_map */
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_HEIGHT_MASK 0x0f000000
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_HEIGHT_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_WIDTH_MASK 0x00f00000
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOG2_WIDTH_SHIFT 20
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOD_MASK 0x000f0000
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_LOD_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R5G5B5A1 0x0002
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8_RECT 0x0003
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R4G4B4A4 0x0004
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R8G8B8A8 0x0006
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_INDEX8 0x000b
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT1 0x000c
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT3 0x000e
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_DXT5 0x000f
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R5G5B5A1_RECT 0x0010
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R8G8B8A8_RECT 0x0012
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8_RECT 0x0013
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8A8 0x001a
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_A8_RECT_2 0x001b
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_R4G4B4A4_RECT 0x001d
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_FORMAT_L8A8_RECT 0x0020
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_MASK 0x00000004
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP (1 << 2)
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_FORMAT_CUBE_MAP_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP(d) (0x00001b08 + (d) * 0x0040) /* Parameters: wrap_s wrap_t wrap_r */
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_S_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_REPEAT 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_MIRRORED_REPEAT 0x0002
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_CLAMP_TO_EDGE 0x0003
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_CLAMP_TO_BORDER 0x0004
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_T_CLAMP 0x0005
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_REPEAT 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_MIRRORED_REPEAT 0x0002
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_CLAMP_TO_EDGE 0x0003
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_CLAMP_TO_BORDER 0x0004
-# define NV20_TCL_PRIMITIVE_3D_TX_WRAP_WRAP_R_CLAMP 0x0005
-# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE(d) (0x00001b0c + (d) * 0x0040) /* Parameters: enable anisotropy */
-# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_MASK 0x40000000
-# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE (1 << 30)
-# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ENABLE_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_MASK 0x00000030
-# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_1 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_2 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_4 0x0002
-# define NV20_TCL_PRIMITIVE_3D_TX_ENABLE_ANISOTROPY_8 0x0003
-# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_PITCH(d) (0x00001b10 + (d) * 0x0040) /* Parameters: pitch */
-# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_PITCH_PITCH_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_PITCH_PITCH_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER(d) (0x00001b14 + (d) * 0x0040) /* Parameters: mag_filter min_filter */
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR 0x0002
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MAG_FILTER_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR 0x0002
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV20_TCL_PRIMITIVE_3D_TX_FILTER_MIN_FILTER_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_SIZE(d) (0x00001b1c + (d) * 0x0040) /* Parameters: width height */
-# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_WIDTH_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_WIDTH_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_TX_NPOT_SIZE_HEIGHT_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_TX_PALETTE_OFFSET(d) (0x00001b20 + (d) * 0x0040)
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR(d) (0x00001b24 + (d) * 0x0040) /* Parameters: a r g b */
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_A_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_A_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_A_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_A_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_R_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_R_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_R_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_R_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_G_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_G_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_G_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_G_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_B_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_RC_ENABLE 0x00001e60 /* Parameters: number of rc enabled */
-# define NV20_TCL_PRIMITIVE_3D_RC_ENABLE_NUMBER_OF_RC_ENABLED_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP 0x00001e70 /* Parameters: op0 op1 op2 op3 */
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP0_MASK 0x0000001f
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_MASK 0x000003e0
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_SHIFT 5
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_NONE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_TEXTURE_2D 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_PASS_THROUGH 0x0004
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_CULL_FRAGMENT 0x0005
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_DOT_PRODUCT_TEXTURE_2D 0x0009
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_DEPENDANT_AR 0x000f
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_DEPENDANT_GB 0x0010
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP1_DOT_PRODUCT 0x0011
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_MASK 0x00007c00
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_SHIFT 10
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_NONE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_TEXTURE_2D 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_PASS_THROUGH 0x0004
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_CULL_FRAGMENT 0x0005
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_DOT_PRODUCT_TEXTURE_2D 0x0009
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_DEPENDANT_AR 0x000f
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_DEPENDANT_GB 0x0010
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP2_DOT_PRODUCT 0x0011
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_MASK 0x000f8000
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_SHIFT 15
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_NONE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_TEXTURE_2D 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_PASS_THROUGH 0x0004
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_CULL_FRAGMENT 0x0005
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_DOT_PRODUCT_TEXTURE_2D 0x0009
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_DEPENDANT_AR 0x000f
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_DEPENDANT_GB 0x0010
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_OP_OP3_DOT_PRODUCT 0x0011
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE 0x000017f8 /* Parameters: cull0 cull1 cull2 cull3 */
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL0_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_gggg 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_lggg 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_glgg 0x0002
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_llgg 0x0003
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_gglg 0x0004
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_lglg 0x0005
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_gllg 0x0006
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_lllg 0x0007
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_gggl 0x0008
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_lggl 0x0009
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_glgl 0x000a
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_llgl 0x000b
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_ggll 0x000c
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_lgll 0x000d
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_glll 0x000e
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL1_llll 0x000f
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_MASK 0x00000f00
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_gggg 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_lggg 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_glgg 0x0002
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_llgg 0x0003
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_gglg 0x0004
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_lglg 0x0005
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_gllg 0x0006
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_lllg 0x0007
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_gggl 0x0008
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_lggl 0x0009
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_glgl 0x000a
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_llgl 0x000b
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_ggll 0x000c
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_lgll 0x000d
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_glll 0x000e
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL2_llll 0x000f
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_MASK 0x0000f000
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_SHIFT 12
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_gggg 0x0000
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_lggg 0x0001
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_glgg 0x0002
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_llgg 0x0003
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_gglg 0x0004
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_lglg 0x0005
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_gllg 0x0006
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_lllg 0x0007
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_gggl 0x0008
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_lggl 0x0009
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_glgl 0x000a
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_llgl 0x000b
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_ggll 0x000c
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_lgll 0x000d
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_glll 0x000e
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_CULL_MODE_CULL3_llll 0x000f
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_PREVIOUS 0x00001e78 /* Parameters: prev2 prev3 */
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_PREVIOUS_PREV2_MASK 0x00030000
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_PREVIOUS_PREV2_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_PREVIOUS_PREV3_MASK 0x00300000
-# define NV20_TCL_PRIMITIVE_3D_TX_SHADER_PREVIOUS_PREV3_SHIFT 20
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0 0x00001e20 /* Parameters: a r g b */
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_A_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_A_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_R_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_R_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_G_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_G_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR0_B_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1 0x00001e24 /* Parameters: a r g b */
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_A_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_A_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_R_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_R_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_G_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_G_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_RC_COLOR1_B_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0 0x00000288 /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_MASK 0xe0000000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SHIFT 29
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_MASK 0x10000000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE (1 << 28)
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_RGB 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_MASK 0x0f000000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_MASK 0x00e00000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SHIFT 21
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_MASK 0x00100000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE (1 << 20)
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_RGB 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_MASK 0x000f0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_MASK 0x0000e000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SHIFT 13
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_MASK 0x00001000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE (1 << 12)
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_RGB 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_MASK 0x00000f00
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_MASK 0x000000e0
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SHIFT 5
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_MASK 0x00000010
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE (1 << 4)
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_RGB 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_INPUT_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1 0x0000028c /* Parameters: vare_mapping vare_component_usage vare_input varf_mapping varf_component_usage varf_input varg_mapping varg_component_usage varg_input color_sum_clamp */
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_MASK 0xe0000000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SHIFT 29
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_MASK 0x10000000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE (1 << 28)
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_RGB 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_MASK 0x0f000000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_MASK 0x00e00000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SHIFT 21
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_MASK 0x00100000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE (1 << 20)
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_RGB 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_MASK 0x000f0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_MASK 0x0000e000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SHIFT 13
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_MASK 0x00001000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE (1 << 12)
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_RGB 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_MASK 0x00000f00
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_MASK 0x00000080
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7)
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA(d) (0x00000260 + (d) * 0x0004) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_MASK 0xe0000000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SHIFT 29
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_MASK 0x10000000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE (1 << 28)
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_BLUE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_MASK 0x0f000000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_MASK 0x00e00000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SHIFT 21
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_MASK 0x00100000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE (1 << 20)
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_BLUE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_MASK 0x000f0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_MASK 0x0000e000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SHIFT 13
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_MASK 0x00001000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE (1 << 12)
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_BLUE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_MASK 0x00000f00
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_MASK 0x000000e0
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SHIFT 5
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_MASK 0x00000010
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE (1 << 4)
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_BLUE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_INPUT_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB(d) (0x00000ac0 + (d) * 0x0004) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_MASK 0xe0000000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SHIFT 29
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_MASK 0x10000000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE (1 << 28)
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_RGB 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_MASK 0x0f000000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_MASK 0x00e00000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SHIFT 21
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_MASK 0x00100000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE (1 << 20)
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_RGB 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_MASK 0x000f0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_MASK 0x0000e000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SHIFT 13
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_MASK 0x00001000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE (1 << 12)
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_RGB 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_MASK 0x00000f00
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_MASK 0x000000e0
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SHIFT 5
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_MASK 0x00000010
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE (1 << 4)
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_RGB 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_ALPHA 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_INPUT_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0(d) (0x00000a60 + (d) * 0x0004) /* Parameters: a r g b */
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_A_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_A_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_R_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_R_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_G_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_G_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_B_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1(d) (0x00000a80 + (d) * 0x0004) /* Parameters: a r g b */
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_A_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_A_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_R_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_R_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_G_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_G_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_B_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA(d) (0x00000aa0 + (d) * 0x0004) /* Parameters: scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_MASK 0x00030000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_NONE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_MASK 0x00008000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS (1 << 15)
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_NONE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_MASK 0x00004000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM (1 << 14)
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_MASK 0x00002000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13)
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_MASK 0x00001000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12)
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB(d) (0x00001e40 + (d) * 0x0004) /* Parameters: scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_MASK 0x00030000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_NONE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_MASK 0x00008000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS (1 << 15)
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_NONE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_MASK 0x00004000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM (1 << 14)
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_MASK 0x00002000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13)
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_MASK 0x00001000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12)
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_ZERO 0x0000
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_FOG 0x0003
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000c
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000d
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV20_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(d) (0x0000105c + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_POSITION_Y(d) (0x00001060 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_POSITION_Z(d) (0x00001064 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_X(d) (0x00001028 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Y(d) (0x0000102c + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Z(d) (0x00001030 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_X(d) (0x00001034 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Y(d) (0x00001038 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Z(d) (0x0000103c + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(d) (0x00001000 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(d) (0x00001004 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(d) (0x00001008 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(d) (0x0000100c + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(d) (0x00001010 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(d) (0x00001014 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(d) (0x00001018 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(d) (0x0000101c + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(d) (0x00001020 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_BACK_SIDE_PRODUCT_AMBIENT(d) (0x00000c00 + (d) * 0x0040)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_BACK_SIDE_PRODUCT_DIFFUSE(d) (0x00000c0c + (d) * 0x0040)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_BACK_SIDE_PRODUCT_SPECULAR(d) (0x00000c18 + (d) * 0x0040)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(d) (0x00001068 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(d) (0x0000106c + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(d) (0x00001070 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(d) (0x00001040 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_EXPONENT(d) (0x00001044 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_B(d) (0x00001048 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(d) (0x0000104c + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Y(d) (0x00001050 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Z(d) (0x00001054 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_C(d) (0x00001058 + (d) * 0x0080)
-# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_A 0x00001e28
-# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_B 0x00001e2c
-# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_C 0x00001e30
-# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_D 0x00001e34
-# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_E 0x00001e38
-# define NV20_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_F 0x00001e3c
-# define NV20_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE 0x0000147c
-# define NV20_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN(d) (0x00001480 + (d) * 0x0004)
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3F_X 0x00001500
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Y 0x00001504
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Z 0x00001508
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4F_X 0x00001518
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Y 0x0000151c
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Z 0x00001520
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4F_W 0x00001524
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY 0x00001528 /* Parameters: y x */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_Y_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_Y_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_X_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW 0x0000152c /* Parameters: w z */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_W_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_W_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_Z_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_X 0x00001530
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Y 0x00001534
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Z 0x00001538
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY 0x00001540 /* Parameters: y x */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z 0x00001544 /* Parameters: z */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_R 0x00001550
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_G 0x00001554
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_B 0x00001558
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4F_A 0x0000155c
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_3F_R 0x00001560
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_3F_G 0x00001564
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_3F_B 0x00001568
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I 0x0000156c /* Parameters: a b g r */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_R 0x00001580
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_G 0x00001584
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_B 0x00001588
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I 0x0000158c /* Parameters: a b g r */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_MASK 0x00ff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_R_MASK 0x000000ff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_S 0x00001590
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_T 0x00001594
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I 0x00001598 /* Parameters: t s */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_S_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_S 0x000015a0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_T 0x000015a4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_R 0x000015a8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_Q 0x000015ac
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST 0x000015b0 /* Parameters: t s */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ 0x000015b4 /* Parameters: q r */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_S 0x000015b8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_T 0x000015bc
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I 0x000015c0 /* Parameters: t s */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_S_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_S 0x000015c8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_T 0x000015cc
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_R 0x000015d0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_Q 0x000015d4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST 0x000015d8 /* Parameters: t s */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ 0x000015dc /* Parameters: q r */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2F_S 0x000015e0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2F_T 0x000015e4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I 0x000015e8 /* Parameters: t s */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_T_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_T_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_S_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_S 0x000015f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_T 0x000015f4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_R 0x000015f8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_Q 0x000015fc
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST 0x00001600 /* Parameters: t s */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_S_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ 0x00001604 /* Parameters: q r */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_R_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2F_S 0x00001608
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2F_T 0x0000160c
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I 0x00001610 /* Parameters: t s */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_T_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_T_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_S_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_S 0x00001620
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_T 0x00001624
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_R 0x00001628
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_Q 0x0000162c
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST 0x00001630 /* Parameters: t s */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_S_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ 0x00001634 /* Parameters: q r */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_R_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_FOG_1F 0x00001698
-# define NV20_TCL_PRIMITIVE_3D_EDGE_FLAG 0x000016bc
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS 0x00001720 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR0_POS_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH 0x00001724 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR1_WGH_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR 0x00001728 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR2_NOR_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL 0x0000172c /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR3_COL_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2 0x00001730 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR4_COL2_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG 0x00001734 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR5_FOG_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6 0x00001738 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR6_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7 0x0000173c /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR7_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0 0x00001740 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1 0x00001744 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR9_TX1_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2 0x00001748 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR10_TX2_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3 0x0000174c /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR11_TX3_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4 0x00001750 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR12_TX4_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5 0x00001754 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR13_TX5_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6 0x00001758 /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR14_TX6_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7 0x0000175c /* Parameters: enabled offset */
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7_ENABLED_MASK 0x80000000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7_ENABLED (1 << 31)
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7_ENABLED_TRUE 0x0001
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7_ENABLED_FALSE 0x0000
-# define NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR15_TX7_OFFSET_MASK 0x1fffffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR( d) (0x00001760 + (d) * 0x0004)
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS 0x00001760 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR0_POS_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH 0x00001764 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR1_WGH_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR 0x00001768 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR2_NOR_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL 0x0000176c /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR3_COL_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2 0x00001770 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR4_COL2_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG 0x00001774 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR5_FOG_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6 0x00001778 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR6_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7 0x0000177c /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR7_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0 0x00001780 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR8_TX0_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1 0x00001784 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR9_TX1_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2 0x00001788 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR10_TX2_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3 0x0000178c /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR11_TX3_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4 0x00001790 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR12_TX4_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5 0x00001794 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR13_TX5_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6 0x00001798 /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR14_TX6_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7 0x0000179c /* Parameters: stride fields type */
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7_STRIDE_MASK 0x0000ff00
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7_STRIDE_SHIFT 8
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7_FIELDS_MASK 0x000000f0
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7_FIELDS_SHIFT 4
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR15_TX7_TYPE_MASK 0x0000000f
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000017a0
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000017a4
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000017a8
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_A 0x000017ac
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_R 0x000017b0
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_G 0x000017b4
-# define NV20_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_B 0x000017b8
-# define NV20_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE 0x000017bc
-# define NV20_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP 0x000017c0
-# define NV20_TCL_PRIMITIVE_3D_LIGHT_MODEL_TWO_SIDE_ENABLE 0x000017c4
-# define NV20_TCL_PRIMITIVE_3D_BEGIN_END 0x000017fc
-# define NV20_TCL_PRIMITIVE_3D_SCISSOR_X2_X1 0x00001c30 /* Parameters: x2 x1 */
-# define NV20_TCL_PRIMITIVE_3D_SCISSOR_X2_X1_X2_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_SCISSOR_X2_X1_X2_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_SCISSOR_X2_X1_X1_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_SCISSOR_Y2_Y1 0x00001c50 /* Parameters: y2 y1 */
-# define NV20_TCL_PRIMITIVE_3D_SCISSOR_Y2_Y1_Y2_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_SCISSOR_Y2_Y1_Y2_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_SCISSOR_Y2_Y1_Y1_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH 0x00001d8c
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB 0x00001d90
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS 0x00001d94 /* Parameters: clear color a clear color b clear color g clear color r clear depth clear stencil */
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_A_MASK 0x00000080
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_A (1 << 7)
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_B_MASK 0x00000040
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_B (1 << 6)
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_G_MASK 0x00000020
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_G (1 << 5)
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_R_MASK 0x00000010
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_COLOR_R (1 << 4)
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_DEPTH_MASK 0x00000002
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_DEPTH 1 // Nothing to shift
-# define NV20_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS_CLEAR_STENCIL_MASK 0x00000001
-# define NV20_TCL_PRIMITIVE_3D_INDEX_DATA 0x00001800 /* Parameters: index1 index0 */
-# define NV20_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX1_MASK 0xffff0000
-# define NV20_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX1_SHIFT 16
-# define NV20_TCL_PRIMITIVE_3D_INDEX_DATA_INDEX0_MASK 0x0000ffff
-# define NV20_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH 0x00001810 /* Parameters: count_vertices offset_vertices */
-# define NV20_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_COUNT_VERTICES_MASK 0xff000000
-# define NV20_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_COUNT_VERTICES_SHIFT 24
-# define NV20_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_OFFSET_VERTICES_MASK 0x00ffffff
-# define NV20_TCL_PRIMITIVE_3D_VERTEX_DATA 0x00001818
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_X 0x00001f00
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_Y 0x00001f04
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_Z 0x00001f08
-# define NV20_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_W 0x00001f0c
-
-/******************************************
-Object NV30_TCL_PRIMITIVE_3D used on: NV30
-*/
-#define NV30_TCL_PRIMITIVE_3D 0x00000097
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT0 0x00000180
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT1 0x00000184
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT2 0x00000188
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT3 0x0000018c
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT4 0x00000194
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT5 0x00000198
-# define NV30_TCL_PRIMITIVE_3D_SET_VB_SRC0_OBJECT 0x0000019c
-# define NV30_TCL_PRIMITIVE_3D_SET_VB_SRC1_OBJECT 0x000001a0
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT6 0x000001a4
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT7 0x000001a8
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT8 0x000001ac
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT8B 0x000001b0
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT9 0x000001b4
-# define NV30_TCL_PRIMITIVE_3D_SET_OBJECT10 0x000001b8
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM0 0x00000200 /* Parameters: width x_offset */
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM0_WIDTH_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM0_WIDTH_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM0_X_OFFSET_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM1 0x00000204 /* Parameters: height y_offset */
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM1_HEIGHT_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM1_HEIGHT_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM1_Y_OFFSET_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_BUFFER0_PITCH 0x0000020c /* Parameters: zs_pitch color0_pitch */
-# define NV30_TCL_PRIMITIVE_3D_BUFFER0_PITCH_ZS_PITCH_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_BUFFER0_PITCH_ZS_PITCH_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_BUFFER0_PITCH_COLOR0_PITCH_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_COLOR0_OFFSET 0x00000210
-# define NV30_TCL_PRIMITIVE_3D_DEPTH_OFFSET 0x00000214
-# define NV30_TCL_PRIMITIVE_3D_COLOR1_OFFSET 0x00000218
-# define NV30_TCL_PRIMITIVE_3D_BUFFER1_PITCH 0x0000021c /* Parameters: color1 buffer pitch */
-# define NV30_TCL_PRIMITIVE_3D_BUFFER1_PITCH_COLOR1_BUFFER_PITCH_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS 0x00000220 /* Parameters: BUF0 BUF1 BUF2 BUF3 */
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF0_MASK 0x00000001
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF1_MASK 0x00000002
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF1 1 // Nothing to shift
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF1_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF1_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF2_MASK 0x00000004
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF2 (1 << 2)
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF2_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF2_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF3_MASK 0x00000008
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF3 (1 << 3)
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF3_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_BUFFERS_BUF3_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH 0x0000022c /* Parameters: pitch */
-# define NV30_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH_PITCH_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_OFFSET 0x00000230
-# define NV30_TCL_PRIMITIVE_3D_TX_MATRIX_ENABLE(d) (0x00000240 + (d) * 0x0004)
-# define NV30_TCL_PRIMITIVE_3D_BUFFER2_PITCH 0x00000280
-# define NV30_TCL_PRIMITIVE_3D_BUFFER3_PITCH 0x00000284
-# define NV30_TCL_PRIMITIVE_3D_BUFFER2_OFFSET 0x00000288
-# define NV30_TCL_PRIMITIVE_3D_BUFFER3_OFFSET 0x0000028c
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS0 0x000002c0 /* Parameters: width x_offset */
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS0_WIDTH_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS0_WIDTH_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS0_X_OFFSET_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS1 0x000002c4 /* Parameters: height y_offset */
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS1_HEIGHT_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS1_HEIGHT_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS1_Y_OFFSET_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_DITHER_ENABLE 0x00000300
-# define NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE 0x00000304
-# define NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC 0x00000308
-# define NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF 0x0000030c
-# define NV30_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE 0x00000310
-# define NV30_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC 0x00000314
-# define NV30_TCL_PRIMITIVE_3D_BLEND_FUNC_DST 0x00000318
-# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR 0x0000031c /* Parameters: a r g b */
-# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_A_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_A_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_R_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_R_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_G_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_G_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_BLEND_COLOR_B_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_BLEND_EQUATION 0x00000320
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK 0x00000324 /* Parameters: a r g b */
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_A_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_A_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_A_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_A_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_R_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_R_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_R_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_R_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_G_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_G_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_G_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_G_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MASK_B_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_ENABLE 0x00000328
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_MASK 0x0000032c
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC 0x00000330
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_REF 0x00000334
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_MASK 0x00000338
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL 0x0000033c
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL 0x00000340
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS 0x00000344
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_ENABLE 0x00000348
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_MASK 0x0000034c
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC 0x00000350
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_REF 0x00000354
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_MASK 0x00000358
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL 0x0000035c
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL 0x00000360
-# define NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS 0x00000364
-# define NV30_TCL_PRIMITIVE_3D_SHADE_MODEL 0x00000368
-# define NV30_TCL_PRIMITIVE_3D_FOG_ENABLE 0x0000036c
-# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR 0x00000370 /* Parameters: a b g r */
-# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_A_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_A_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_B_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_B_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_G_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_G_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_FOG_COLOR_R_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE 0x00000374
-# define NV30_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP 0x00000378
-# define NV30_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE 0x0000037c
-# define NV30_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR 0x00000394
-# define NV30_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR 0x00000398
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_R 0x000003a0
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_G 0x000003a4
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_B 0x000003a8
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_FRONT_A 0x000003b4
-# define NV30_TCL_PRIMITIVE_3D_LINE_WIDTH_SMOOTH 0x000003b8
-# define NV30_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE 0x000003bc
-# define NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(d) (0x00000400 + (d) * 0x0004)
-# define NV30_TCL_PRIMITIVE_3D_MODELVIEW_MATRIX( d) (0x00000480 + (d) * 0x0004)
-# define NV30_TCL_PRIMITIVE_3D_INVERSE_MODELVIEW_MATRIX( d) (0x00000580 + (d) * 0x0004)
-# define NV30_TCL_PRIMITIVE_3D_PROJECTION_MATRIX( d) (0x00000680 + (d) * 0x0004)
-# define NV30_TCL_PRIMITIVE_3D_TX_MATRIX(x,y) (0x000006c0 + (y) * 0x0010 + (x) * 0x0004)
-# define NV30_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS 0x000008c0 /* Parameters: width x_offset */
-# define NV30_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_WIDTH_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_WIDTH_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_X_OFFSET_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS 0x000008c4 /* Parameters: height y_offset */
-# define NV30_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_HEIGHT_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_HEIGHT_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_Y_OFFSET_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_FOG_COORD_DIST 0x000008c8
-# define NV30_TCL_PRIMITIVE_3D_FOG_MODE 0x000008cc
-# define NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT 0x000008d0
-# define NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_LINEAR 0x000008d4
-# define NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_QUADRATIC 0x000008d8
-# define NV30_TCL_PRIMITIVE_3D_FP_ACTIVE_PROGRAM 0x000008e4
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0 0x000008ec /* Parameters: a r g b */
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_A_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_A_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_R_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_R_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_G_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_G_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR0_B_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1 0x000008f0 /* Parameters: a r g b */
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_A_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_A_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_R_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_R_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_G_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_G_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_RC_COLOR1_B_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0 0x000008f4 /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_MASK 0xe0000000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SHIFT 29
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_MASK 0x10000000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE (1 << 28)
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_RGB 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_MASK 0x0f000000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARA_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_MASK 0x00e00000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SHIFT 21
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_MASK 0x00100000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE (1 << 20)
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_RGB 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_MASK 0x000f0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARB_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_MASK 0x0000e000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SHIFT 13
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_MASK 0x00001000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE (1 << 12)
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_RGB 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_MASK 0x00000f00
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARC_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_MASK 0x000000e0
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SHIFT 5
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_MASK 0x00000010
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE (1 << 4)
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_RGB 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL0_VARD_INPUT_MASK 0x0000000f
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1 0x000008f8 /* Parameters: vare_mapping vare_component_usage vare_input varf_mapping varf_component_usage varf_input varg_mapping varg_component_usage varg_input color_sum_clamp */
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_MASK 0xe0000000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SHIFT 29
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_MASK 0x10000000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE (1 << 28)
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_RGB 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_MASK 0x0f000000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARE_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_MASK 0x00e00000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SHIFT 21
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_MASK 0x00100000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE (1 << 20)
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_RGB 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_MASK 0x000f0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARF_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_MASK 0x0000e000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SHIFT 13
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_MASK 0x00001000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE (1 << 12)
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_RGB 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_MASK 0x00000f00
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_VARG_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_MASK 0x00000080
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7)
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_FINAL1_COLOR_SUM_CLAMP_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_ENABLE 0x000008fc /* Parameters: number of rc enabled */
-# define NV30_TCL_PRIMITIVE_3D_RC_ENABLE_NUMBER_OF_RC_ENABLED_MASK 0x0000000f
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA(d) (0x00000900 + (d) * 0x0020) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_MASK 0xe0000000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SHIFT 29
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_MASK 0x10000000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE (1 << 28)
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_BLUE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_MASK 0x0f000000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARA_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_MASK 0x00e00000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SHIFT 21
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_MASK 0x00100000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE (1 << 20)
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_BLUE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_MASK 0x000f0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARB_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_MASK 0x0000e000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SHIFT 13
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_MASK 0x00001000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE (1 << 12)
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_BLUE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_MASK 0x00000f00
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARC_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_MASK 0x000000e0
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SHIFT 5
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_MASK 0x00000010
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE (1 << 4)
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_BLUE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_ALPHA_VARD_INPUT_MASK 0x0000000f
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB(d) (0x00000904 + (d) * 0x0020) /* Parameters: vara_mapping vara_component_usage vara_input varb_mapping varb_component_usage varb_input varc_mapping varc_component_usage varc_input vard_mapping vard_component_usage vard_input */
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_MASK 0xe0000000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SHIFT 29
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_MASK 0x10000000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE (1 << 28)
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_RGB 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_MASK 0x0f000000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARA_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_MASK 0x00e00000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SHIFT 21
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_MASK 0x00100000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE (1 << 20)
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_RGB 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_MASK 0x000f0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARB_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_MASK 0x0000e000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SHIFT 13
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_MASK 0x00001000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE (1 << 12)
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_RGB 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_MASK 0x00000f00
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARC_INPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_MASK 0x000000e0
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SHIFT 5
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_IDENTITY_NV 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_UNSIGNED_INVERT_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NORMAL_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_EXPAND_NEGATE_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NORMAL_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_HALF_BIAS_NEGATE_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_IDENTITY_NV 0x0006
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_MAPPING_SIGNED_NEGATE_NV 0x0007
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_MASK 0x00000010
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE (1 << 4)
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_RGB 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_COMPONENT_USAGE_ALPHA 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_IN_RGB_VARD_INPUT_MASK 0x0000000f
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0(d) (0x00000908 + (d) * 0x0020) /* Parameters: a r g b */
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_A_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_A_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_R_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_R_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_G_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_G_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR0_B_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1(d) (0x0000090c + (d) * 0x0020) /* Parameters: a r g b */
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_A_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_A_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_R_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_R_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_G_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_G_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_RC_CONSTANT_COLOR1_B_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA(d) (0x00000910 + (d) * 0x0020) /* Parameters: scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_MASK 0x00030000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_NONE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_MASK 0x00008000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS (1 << 15)
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_NONE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_MASK 0x00004000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM (1 << 14)
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_MUX_SUM_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_MASK 0x00002000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13)
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_MASK 0x00001000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12)
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB(d) (0x00000914 + (d) * 0x0020) /* Parameters: scale bias mux_sum ab_dot_product cd_dot_product sum_output ab_output cd_output */
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_MASK 0x00030000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_NONE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_MASK 0x00008000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS (1 << 15)
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_NONE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_MASK 0x00004000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM (1 << 14)
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_MUX_SUM_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_MASK 0x00002000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13)
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_DOT_PRODUCT_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_MASK 0x00001000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12)
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_DOT_PRODUCT_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SHIFT 4
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x0001
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x0002
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_FOG 0x0003
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x0004
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x0005
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x0008
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x0009
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000c
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000d
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000f
-# define NV30_TCL_PRIMITIVE_3D_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0 0x00000a00 /* Parameters: width x_offset */
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_WIDTH_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_WIDTH_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_X_OFFSET_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1 0x00000a04 /* Parameters: height y_offset */
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_HEIGHT_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_HEIGHT_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_Y_OFFSET_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x00000a10
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x00000a14
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x00000a18
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_OX 0x00000a20
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_OY 0x00000a24
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_NPF_DIV2 0x00000a28
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_UNK0_0x0 0x00000a2c
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_PX_DIV2 0x00000a30
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_PY_DIV2 0x00000a34
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_FMN_DIV2 0x00000a38
-# define NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_UNK1_0x0 0x00000a3c
-# define NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE 0x00000a60
-# define NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE 0x00000a64
-# define NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE 0x00000a68
-# define NV30_TCL_PRIMITIVE_3D_DEPTH_FUNC 0x00000a6c
-# define NV30_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE 0x00000a70
-# define NV30_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE 0x00000a74
-# define NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR 0x00000a78
-# define NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS 0x00000a7c
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY 0x00000a90 /* Parameters: y x */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z 0x00000a94 /* Parameters: z */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_INST0 0x00000b80
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_INST1 0x00000b84
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_INST2 0x00000b88
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_INST3 0x00000b8c
-# define NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_A(d) (0x00000e00 + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_B(d) (0x00000e04 + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_C(d) (0x00000e08 + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_D(d) (0x00000e0c + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(d) (0x00001000 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(d) (0x00001004 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(d) (0x00001008 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(d) (0x0000100c + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(d) (0x00001010 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(d) (0x00001014 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(d) (0x00001018 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(d) (0x0000101c + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(d) (0x00001020 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_X(d) (0x00001028 + (d) * 0x0080)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Y(d) (0x0000102c + (d) * 0x0080)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_HALF_VECTOR_Z(d) (0x00001030 + (d) * 0x0080)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_X(d) (0x00001034 + (d) * 0x0080)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Y(d) (0x00001038 + (d) * 0x0080)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_DIRECTION_Z(d) (0x0000103c + (d) * 0x0080)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(d) (0x00001200 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_EXPONENT(d) (0x00001204 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_B(d) (0x00001208 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(d) (0x0000120c + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Y(d) (0x00001210 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_Z(d) (0x00001214 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_C(d) (0x00001218 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(d) (0x0000121c + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_POSITION_Y(d) (0x00001220 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_POSITION_Z(d) (0x00001224 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(d) (0x00001228 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(d) (0x0000122c + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(d) (0x00001230 + (d) * 0x0040)
-# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_A 0x00001400
-# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_B 0x00001404
-# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_C 0x00001408
-# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_D 0x0000140c
-# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_E 0x00001410
-# define NV30_TCL_PRIMITIVE_3D_FRONT_MATERIAL_SHININESS_F 0x00001414
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS 0x00001420 /* Parameters: light 7 light 6 light 5 light 4 light 3 light 2 light 1 light 0 */
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_MASK 0x00008000
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7 (1 << 15)
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_7_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_MASK 0x00002000
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6 (1 << 13)
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_6_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_MASK 0x00000800
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5 (1 << 11)
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_5_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_MASK 0x00000200
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4 (1 << 9)
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_4_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_MASK 0x00000080
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3 (1 << 7)
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_3_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_MASK 0x00000020
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2 (1 << 5)
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_2_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_MASK 0x00000008
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1 (1 << 3)
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_1_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS_LIGHT_0_MASK 0x00000001
-# define NV30_TCL_PRIMITIVE_3D_SET_CLIPPING_PLANES 0x00001478
-# define NV30_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE 0x0000147c
-# define NV30_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN( d) (0x00001480 + (d) * 0x0004)
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_3F_X( d) (0x00001500 + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_3F_Y( d) (0x00001504 + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_3F_Z( d) (0x00001508 + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_3F_W( d) (0x0000150c + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_VB_POINTER( d) (0x00001680 + (d) * 0x0004) /* Parameters: source offset */
-# define NV30_TCL_PRIMITIVE_3D_VB_POINTER_SOURCE_MASK 0x80000000
-# define NV30_TCL_PRIMITIVE_3D_VB_POINTER_SOURCE (1 << 31)
-# define NV30_TCL_PRIMITIVE_3D_VB_POINTER_OFFSET_MASK 0x1fffffff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_UNK_0 0x00001718
-# define NV30_TCL_PRIMITIVE_3D_VTXFMT( d) (0x00001740 + (d) * 0x0004) /* Parameters: stride ncomp type */
-# define NV30_TCL_PRIMITIVE_3D_VTXFMT_STRIDE_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_VTXFMT_STRIDE_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_VTXFMT_NCOMP_MASK 0x000000f0
-# define NV30_TCL_PRIMITIVE_3D_VTXFMT_NCOMP_SHIFT 4
-# define NV30_TCL_PRIMITIVE_3D_VTXFMT_TYPE_MASK 0x0000000f
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000017a0
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000017a4
-# define NV30_TCL_PRIMITIVE_3D_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000017a8
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_R 0x000017b0
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_G 0x000017b4
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_B 0x000017b8
-# define NV30_TCL_PRIMITIVE_3D_COLOR_MATERIAL_BACK_A 0x000017c0
-# define NV30_TCL_PRIMITIVE_3D_OCC_QUERY_OR_COLOR_BUFF_ENABLE 0x000017c8
-# define NV30_TCL_PRIMITIVE_3D_STORE_RESULT 0x00001800
-# define NV30_TCL_PRIMITIVE_3D_BEGIN_END 0x00001808
-# define NV30_TCL_PRIMITIVE_3D_VB_ELEMENT_U16 0x0000180c /* Parameters: 1 0 */
-# define NV30_TCL_PRIMITIVE_3D_VB_ELEMENT_U16_1_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_VB_ELEMENT_U16_1_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_VB_ELEMENT_U16_0_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VB_ELEMENT_U32 0x00001810
-# define NV30_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH 0x00001814 /* Parameters: count_vertices offset_vertices */
-# define NV30_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_COUNT_VERTICES_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_COUNT_VERTICES_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_VB_VERTEX_BATCH_OFFSET_VERTICES_MASK 0x00ffffff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_DATA 0x00001818
-# define NV30_TCL_PRIMITIVE_3D_SET_DISPLAY_LIST_MEM_OFFSET 0x0000181c
-# define NV30_TCL_PRIMITIVE_3D_EXECUTE_DISPLAY_LIST 0x00001824 /* Parameters: length start offset */
-# define NV30_TCL_PRIMITIVE_3D_EXECUTE_DISPLAY_LIST_LENGTH_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_EXECUTE_DISPLAY_LIST_LENGTH_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_EXECUTE_DISPLAY_LIST_START_OFFSET_MASK 0x00ffffff
-# define NV30_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT 0x00001828
-# define NV30_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK 0x0000182c
-# define NV30_TCL_PRIMITIVE_3D_CULL_FACE 0x00001830
-# define NV30_TCL_PRIMITIVE_3D_FRONT_FACE 0x00001834
-# define NV30_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE 0x00001838
-# define NV30_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE 0x0000183c
-# define NV30_TCL_PRIMITIVE_3D_TX_DEPTH_UNIT( d) (0x00001840 + (d) * 0x0004) /* Parameters: depth NPOT pitch */
-# define NV30_TCL_PRIMITIVE_3D_TX_DEPTH_UNIT_DEPTH_MASK 0xfff00000
-# define NV30_TCL_PRIMITIVE_3D_TX_DEPTH_UNIT_DEPTH_SHIFT 20
-# define NV30_TCL_PRIMITIVE_3D_TX_DEPTH_UNIT_NPOT_PITCH_MASK 0x000fffff
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2F_X( d) (0x00001880 + (d) * 0x0008)
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2F_Y( d) (0x00001884 + (d) * 0x0008)
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2I( d) (0x00001900 + (d) * 0x0004) /* Parameters: x y */
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2I_X_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2I_Y_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_2I_Y_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I 0x0000194c /* Parameters: a b g r */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I 0x00001950 /* Parameters: a b g r */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_R_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST 0x000019c0 /* Parameters: t s */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ 0x000019c4 /* Parameters: q r */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST 0x000019c8 /* Parameters: t s */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ 0x000019cc /* Parameters: q r */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST 0x000019d0 /* Parameters: t s */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_S_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ 0x000019d4 /* Parameters: q r */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_R_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST 0x000019d8 /* Parameters: t s */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_S_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ 0x000019dc /* Parameters: q r */
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_R_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_TX_ADDRESS_UNIT( d) (0x00001a00 + (d) * 0x0020)
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT( d) (0x00001a04 + (d) * 0x0020) /* Parameters: mipmap type format ncomp cubic */
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_MIPMAP_MASK 0x000f0000
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_MIPMAP_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_TYPE_MASK 0x00006000
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_TYPE_SHIFT 13
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_TYPE_POT 0x0000
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_TYPE_NPOT 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_TYPE_RECT 0x0003
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_MASK 0x00001f00
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_L8 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_A1R5G5B5 0x0002
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_A4R4G4B4 0x0003
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_R5G6B5 0x0004
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_A8R8G8B8 0x0005
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_DXT1 0x0006
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_DXT3 0x0007
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_DXT5 0x0008
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_L16 0x0014
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_L16A16 0x0015
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_L8A8 0x0018
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_SL8A8 0x0019
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_RGBA_F16 0x001a
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_RGBA_F32 0x001b
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_L_F32 0x001c
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_FORMAT_LA_F16 0x001f
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_NCOMP_MASK 0x000000f0
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_NCOMP_SHIFT 4
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_CUBIC_MASK 0x00000004
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_CUBIC (1 << 2)
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_CUBIC_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_FORMAT_UNIT_CUBIC_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT( d) (0x00001a08 + (d) * 0x0020) /* Parameters: wrap_s wrap_t wrap_r */
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_S_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_REPEAT 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_MIRRORED_REPEAT 0x0002
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_CLAMP_TO_EDGE 0x0003
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_CLAMP_TO_BORDER 0x0004
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_T_CLAMP 0x0005
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_REPEAT 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_MIRRORED_REPEAT 0x0002
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_CLAMP_TO_EDGE 0x0003
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_CLAMP_TO_BORDER 0x0004
-# define NV30_TCL_PRIMITIVE_3D_TX_WRAP_UNIT_WRAP_R_CLAMP 0x0005
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT( d) (0x00001a0c + (d) * 0x0020) /* Parameters: nv40_enable nv30_enable anisotropy */
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV40_ENABLE_MASK 0x80000000
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV40_ENABLE (1 << 31)
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV40_ENABLE_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV40_ENABLE_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV30_ENABLE_MASK 0x40000000
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV30_ENABLE (1 << 30)
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV30_ENABLE_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_NV30_ENABLE_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_MASK 0x00000070
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_SHIFT 4
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_1 0x0000
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_2 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_4 0x0002
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_NV40_6_NV30_8 0x0003
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_8 0x0004
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_10 0x0005
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_12 0x0006
-# define NV30_TCL_PRIMITIVE_3D_TX_ENABLE_UNIT_ANISOTROPY_16 0x0007
-# define NV30_TCL_PRIMITIVE_3D_TX_SWIZZLE_UNIT( d) (0x00001a10 + (d) * 0x0020)
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT( d) (0x00001a14 + (d) * 0x0020) /* Parameters: filter_min filter_mag */
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_MASK 0x000f0000
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_NEAREST 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_LINEAR 0x0002
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MIN_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_MASK 0x0f000000
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_NEAREST 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_LINEAR 0x0002
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_NEAREST_MIPMAP_NEAREST 0x0003
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_LINEAR_MIPMAP_NEAREST 0x0004
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_NEAREST_MIPMAP_LINEAR 0x0005
-# define NV30_TCL_PRIMITIVE_3D_TX_FILTER_UNIT_FILTER_MAG_LINEAR_MIPMAP_LINEAR 0x0006
-# define NV30_TCL_PRIMITIVE_3D_TX_XY_DIM_UNIT( d) (0x00001a18 + (d) * 0x0020) /* Parameters: width height */
-# define NV30_TCL_PRIMITIVE_3D_TX_XY_DIM_UNIT_WIDTH_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_TX_XY_DIM_UNIT_WIDTH_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_TX_XY_DIM_UNIT_HEIGHT_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT( d) (0x00001a1c + (d) * 0x0020) /* Parameters: a r g b */
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_A_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_A_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_A_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_A_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_R_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_R_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_R_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_R_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_G_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_G_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_G_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_G_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_TX_BORDER_COLOR_UNIT_B_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_4F_X( d) (0x00001c00 + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_4F_Y( d) (0x00001c04 + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_4F_Z( d) (0x00001c08 + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_VTX_ATTR_4F_W( d) (0x00001c0c + (d) * 0x0010)
-# define NV30_TCL_PRIMITIVE_3D_FP_CONTROL 0x00001d60 /* Parameters: uses_kil */
-# define NV30_TCL_PRIMITIVE_3D_FP_CONTROL_USES_KIL_MASK 0x00000080
-# define NV30_TCL_PRIMITIVE_3D_FP_CONTROL_USES_KIL (1 << 7)
-# define NV30_TCL_PRIMITIVE_3D_FP_CONTROL_USES_KIL_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_FP_CONTROL_USES_KIL_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_UNK1D6C_OFFSET 0x00001d6c
-# define NV30_TCL_PRIMITIVE_3D_UNK1D70_VALUE 0x00001d70
-# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH 0x00001d8c
-# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB 0x00001d90 /* Parameters: a r g b */
-# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_A_MASK 0xff000000
-# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_A_SHIFT 24
-# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_R_MASK 0x00ff0000
-# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_R_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_G_MASK 0x0000ff00
-# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_G_SHIFT 8
-# define NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB_B_MASK 0x000000ff
-# define NV30_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS 0x00001d94
-# define NV30_TCL_PRIMITIVE_3D_DO_VERTICES 0x00001dac
-# define NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_ENABLE 0x00001db4
-# define NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN 0x00001db8 /* Parameters: factor pattern */
-# define NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_FACTOR_MASK 0x0000ffff
-# define NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_PATTERN_MASK 0xffff0000
-# define NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_PATTERN_SHIFT 16
-# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_A 0x00001e20
-# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_B 0x00001e24
-# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_C 0x00001e28
-# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_D 0x00001e2c
-# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_E 0x00001e30
-# define NV30_TCL_PRIMITIVE_3D_BACK_MATERIAL_SHININESS_F 0x00001e34
-# define NV30_TCL_PRIMITIVE_3D_VERTEX_FOG_1F 0x00001e54
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_FROM_ID 0x00001e9c
-# define NV30_TCL_PRIMITIVE_3D_VP_PROGRAM_START_ID 0x00001ea0
-# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_A 0x00001ec0
-# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_B 0x00001ec4
-# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_C 0x00001ec8
-# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_D 0x00001ecc
-# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_E 0x00001ed0
-# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_F 0x00001ed4
-# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_G 0x00001ed8
-# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETER_H 0x00001edc
-# define NV30_TCL_PRIMITIVE_3D_POINT_SIZE 0x00001ee0
-# define NV30_TCL_PRIMITIVE_3D_POINT_PARAMETERS_ENABLE 0x00001ee4
-# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE 0x00001ee8 /* Parameters: coord_replace r_mode enable */
-# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_MASK 0x00000800
-# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE (1 << 11)
-# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_COORD_REPLACE_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_MASK 0x00000006
-# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_SHIFT 1
-# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_ZERO 0x0000
-# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_R 0x0001
-# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_R_MODE_GL_S 0x0002
-# define NV30_TCL_PRIMITIVE_3D_POINT_SPRITE_ENABLE_MASK 0x00000001
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID 0x00001efc
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P0_X 0x00001f00
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P0_Y 0x00001f04
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P0_Z 0x00001f08
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P0_W 0x00001f0c
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P1_X 0x00001f10
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P1_Y 0x00001f14
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P1_Z 0x00001f18
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P1_W 0x00001f1c
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P2_X 0x00001f20
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P2_Y 0x00001f24
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P2_Z 0x00001f28
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P2_W 0x00001f2c
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P3_X 0x00001f30
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P3_Y 0x00001f34
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P3_Z 0x00001f38
-# define NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_P3_W 0x00001f3c
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG 0x00001ff0 /* Parameters: POS WEIGHT NORMAL COL0 COL1 FOGC TEX0 TEX1 TEX2 TEX3 TEX4 TEX5 TEX6 TEX7 */
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_POS_MASK 0x00000001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_WEIGHT_MASK 0x00000002
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_WEIGHT 1 // Nothing to shift
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_WEIGHT_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_WEIGHT_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_NORMAL_MASK 0x00000004
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_NORMAL (1 << 2)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_NORMAL_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_NORMAL_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL0_MASK 0x00000008
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL0 (1 << 3)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL0_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL0_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL1_MASK 0x00000010
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL1 (1 << 4)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL1_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_COL1_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_FOGC_MASK 0x00000020
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_FOGC (1 << 5)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_FOGC_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_FOGC_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX0_MASK 0x00000100
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX0 (1 << 8)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX0_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX0_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX1_MASK 0x00000200
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX1 (1 << 9)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX1_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX1_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX2_MASK 0x00000400
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX2 (1 << 10)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX2_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX2_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX3_MASK 0x00000800
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX3 (1 << 11)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX3_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX3_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX4_MASK 0x00001000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX4 (1 << 12)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX4_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX4_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX5_MASK 0x00002000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX5 (1 << 13)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX5_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX5_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX6_MASK 0x00004000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX6 (1 << 14)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX6_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX6_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX7_MASK 0x00008000
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX7 (1 << 15)
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX7_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_IN_REG_TEX7_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG 0x00001ff4 /* Parameters: COL0 COL1 BFC0 BFC1 FOGC PSZ CLP0 CLP1 CLP2 CLP3 CLP4 CLP5 TEX0 TEX1 TEX2 TEX3 TEX4 TEX5 TEX6 TEX7 */
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL0_MASK 0x00000001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1_MASK 0x00000002
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1 1 // Nothing to shift
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0_MASK 0x00000004
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0 (1 << 2)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1_MASK 0x00000008
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1 (1 << 3)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC_MASK 0x00000010
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC (1 << 4)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ_MASK 0x00000020
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ (1 << 5)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0_MASK 0x00000040
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0 (1 << 6)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1_MASK 0x00000080
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1 (1 << 7)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2_MASK 0x00000100
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2 (1 << 8)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3_MASK 0x00000200
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3 (1 << 9)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4_MASK 0x00000400
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4 (1 << 10)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5_MASK 0x00000800
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5 (1 << 11)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0_MASK 0x00004000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0 (1 << 14)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX1_MASK 0x00008000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX1 (1 << 15)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX1_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX1_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX2_MASK 0x00010000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX2 (1 << 16)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX2_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX2_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX3_MASK 0x00020000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX3 (1 << 17)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX3_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX3_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX4_MASK 0x00040000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX4 (1 << 18)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX4_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX4_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX5_MASK 0x00080000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX5 (1 << 19)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX5_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX5_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX6_MASK 0x00100000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX6 (1 << 20)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX6_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX6_FALSE 0x0000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX7_MASK 0x00200000
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX7 (1 << 21)
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX7_TRUE 0x0001
-# define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX7_FALSE 0x0000
-
-/******************************************
-Object NV40_TCL_PRIMITIVE_3D used on: NV40 G70
-*/
-#define NV40_TCL_PRIMITIVE_3D 0x00000097
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123 0x00000370 /* Parameters: buffer3 b buffer3 g buffer3 r buffer3 a buffer2 b buffer2 g buffer2 r buffer2 a buffer1 b buffer1 g buffer1 r buffer1 a */
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_B_MASK 0x00008000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_B (1 << 15)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_B_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_B_FALSE 0x0000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_G_MASK 0x00004000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_G (1 << 14)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_G_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_G_FALSE 0x0000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_R_MASK 0x00002000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_R (1 << 13)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_R_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_R_FALSE 0x0000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_A_MASK 0x00001000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_A (1 << 12)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_A_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER3_A_FALSE 0x0000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_B_MASK 0x00000800
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_B (1 << 11)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_B_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_B_FALSE 0x0000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_G_MASK 0x00000400
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_G (1 << 10)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_G_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_G_FALSE 0x0000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_R_MASK 0x00000200
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_R (1 << 9)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_R_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_R_FALSE 0x0000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_A_MASK 0x00000100
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_A (1 << 8)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_A_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER2_A_FALSE 0x0000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_B_MASK 0x00000080
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_B (1 << 7)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_B_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_B_FALSE 0x0000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_G_MASK 0x00000040
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_G (1 << 6)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_G_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_G_FALSE 0x0000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_R_MASK 0x00000020
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_R (1 << 5)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_R_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_R_FALSE 0x0000
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_A_MASK 0x00000010
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_A (1 << 4)
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_A_TRUE 0x0001
-# define NV40_TCL_PRIMITIVE_3D_COLOR_MASK_BUFFER123_BUFFER1_A_FALSE 0x0000
-
-/******************************************
-Object NV30_CLEAR_BUFFER used on: NV30 NV40 G70
-*/
-#define NV30_CLEAR_BUFFER 0x00000066
-# define NV30_CLEAR_BUFFER_SET_DMA_NOTIFY 0x00000180
-# define NV30_CLEAR_BUFFER_SET_IMAGE_PATTERN 0x00000188
-# define NV30_CLEAR_BUFFER_SET_RASTER_OP 0x0000018c
-# define NV30_CLEAR_BUFFER_SET_CONTEXT_SURFACE_2D 0x00000198
-# define NV30_CLEAR_BUFFER_UNK002fc 0x000002fc
-
-/******************************************
-Object NV50_TCL_PRIMITIVE_3D used on:
-*/
-#define NV50_TCL_PRIMITIVE_3D 0x00000097
-# define NV50_TCL_PRIMITIVE_3D_SET_OBJECT_0( d) (0x00000180 + (d) * 0x0004)
-# define NV50_TCL_PRIMITIVE_3D_SET_OBJECT_1( d) (0x000001c0 + (d) * 0x0004)
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_FOG_1F 0x00000314
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_2F_X 0x00000380
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_2F_Y 0x00000384
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_S 0x000003c0
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2F_T 0x000003c4
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_S 0x000003c8
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2F_T 0x000003cc
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2F_S 0x000003d0
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2F_T 0x000003d4
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2F_S 0x000003d8
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2F_T 0x000003dc
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_3F_X 0x00000400
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Y 0x00000404
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_3F_Z 0x00000408
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_X 0x00000420
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Y 0x00000424
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_Z 0x00000428
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_3F_R 0x00000430
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_3F_G 0x00000434
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_3F_B 0x00000438
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_R 0x00000440
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_G 0x00000444
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_B 0x00000448
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4F_X 0x00000500
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Y 0x00000504
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4F_Z 0x00000508
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4F_W 0x0000050c
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4F_R 0x00000530
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4F_G 0x00000534
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4F_B 0x00000538
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4F_A 0x0000053c
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_S 0x00000580
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_T 0x00000584
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_R 0x00000588
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_Q 0x0000058c
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_S 0x00000590
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_T 0x00000594
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_R 0x00000598
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_Q 0x0000059c
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_S 0x000005a0
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_T 0x000005a4
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_R 0x000005a8
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4F_Q 0x000005ac
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_S 0x000005b0
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_T 0x000005b4
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_R 0x000005b8
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4F_Q 0x000005bc
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2I 0x000006a0 /* Parameters: t s */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_T_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_2I_S_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2I 0x000006a4 /* Parameters: t s */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_T_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_2I_S_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2I 0x000006a8 /* Parameters: t s */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_T_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_T_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_2I_S_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2I 0x000006ac /* Parameters: t s */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_T_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_T_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_2I_S_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY 0x00000700 /* Parameters: y x */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_Y_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_Y_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_XY_X_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW 0x00000704 /* Parameters: w z */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_W_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_W_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_POS_4I_ZW_Z_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST 0x00000740 /* Parameters: t s */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_T_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_ST_S_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ 0x00000744 /* Parameters: q r */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_Q_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX0_4I_RQ_R_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST 0x00000748 /* Parameters: t s */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_T_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_ST_S_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ 0x0000074c /* Parameters: q r */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_Q_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX1_4I_RQ_R_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST 0x00000750 /* Parameters: t s */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_T_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_ST_S_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ 0x00000754 /* Parameters: q r */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_Q_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX2_4I_RQ_R_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST 0x00000758 /* Parameters: t s */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_T_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_ST_S_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ 0x0000075c /* Parameters: q r */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_Q_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_TX3_4I_RQ_R_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY 0x00000790 /* Parameters: y x */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_Y_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_XY_X_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z 0x00000794 /* Parameters: z */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_NOR_3I_Z_Z_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I 0x0000088c /* Parameters: a b g r */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_MASK 0xff000000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_A_SHIFT 24
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_MASK 0x00ff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_B_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_MASK 0x0000ff00
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_G_SHIFT 8
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL_4I_R_MASK 0x000000ff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I 0x00000890 /* Parameters: a b g r */
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_MASK 0xff000000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_A_SHIFT 24
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_MASK 0x00ff0000
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_B_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_MASK 0x0000ff00
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_G_SHIFT 8
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_COL2_3I_R_MASK 0x000000ff
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK0_X 0x00000a00
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK0_Y 0x00000a04
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK0_Z 0x00000a08
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK1_X 0x00000a0c
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK1_Y 0x00000a10
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_UNK1_Z 0x00000a14
-# define NV50_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR 0x00000c08
-# define NV50_TCL_PRIMITIVE_3D_DEPTH_RANGE_FAR 0x00000c0c
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(d) (0x00000d00 + (d) * 0x0008) /* Parameters: x2 x1 */
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X2_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ_X1_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(d) (0x00000d04 + (d) * 0x0008) /* Parameters: y2 y1 */
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y2_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT_Y1_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_BUFFER_FIRST 0x00000d74
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_BUFFER_COUNT 0x00000d78
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR_R 0x00000d80
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR_G 0x00000d84
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR_B 0x00000d88
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR_A 0x00000d8c
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_DEPTH 0x00000d90
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_STENCIL 0x00000da0
-# define NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT 0x00000dac
-# define NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK 0x00000db0
-# define NV50_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE 0x00000db4
-# define NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE 0x00000dc0
-# define NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE 0x00000dc4
-# define NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE 0x00000dc8
-# define NV50_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS 0x00000e04 /* Parameters: w x */
-# define NV50_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_W_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_W_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS_X_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS 0x00000e08 /* Parameters: h y */
-# define NV50_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_H_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_H_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_SCISSOR_HEIGHT_YPOS_Y_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID 0x00000f00
-# define NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_X 0x00000f04
-# define NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_Y 0x00000f08
-# define NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_Z 0x00000f0c
-# define NV50_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_W 0x00000f10
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_REF 0x00000f54
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_MASK 0x00000f58
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_MASK 0x00000f5c
-# define NV50_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE 0x000012cc
-# define NV50_TCL_PRIMITIVE_3D_SHADE_MODEL 0x000012d4
-# define NV50_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE 0x000012e8
-# define NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE 0x000012ec
-# define NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC 0x0000130c
-# define NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF 0x00001310
-# define NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC 0x00001314
-# define NV50_TCL_PRIMITIVE_3D_BLEND_COLOR_R 0x0000131c
-# define NV50_TCL_PRIMITIVE_3D_BLEND_COLOR_G 0x00001320
-# define NV50_TCL_PRIMITIVE_3D_BLEND_COLOR_B 0x00001324
-# define NV50_TCL_PRIMITIVE_3D_BLEND_COLOR_A 0x00001328
-# define NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_RGB 0x00001340
-# define NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB 0x00001344
-# define NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_RGB 0x00001348
-# define NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_ALPHA 0x0000134c
-# define NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA 0x00001350
-# define NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_DST_ALPHA 0x00001358
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_ENABLE 0x00001380
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL 0x00001384
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZFAIL 0x00001388
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_ZPASS 0x0000138c
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC 0x00001390
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_REF 0x00001394
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_MASK 0x00001398
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_MASK 0x0000139c
-# define NV50_TCL_PRIMITIVE_3D_LINE_WIDTH 0x000013b0
-# define NV50_TCL_PRIMITIVE_3D_POINT_SIZE 0x00001518
-# define NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR 0x0000156c
-# define NV50_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE 0x00001570
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_ENABLE 0x00001594
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL 0x00001598
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZFAIL 0x0000159c
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_ZPASS 0x000015a0
-# define NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC 0x000015a4
-# define NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS 0x000015bc
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_BEGIN 0x000015dc
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_END 0x000015e0
-# define NV50_TCL_PRIMITIVE_3D_VERTEX_DATA 0x00001640
-# define NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_ENABLE 0x0000166c
-# define NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN 0x00001680 /* Parameters: pattern factor */
-# define NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_PATTERN_MASK 0x00ffff00
-# define NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_PATTERN_SHIFT 8
-# define NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN_FACTOR_MASK 0x000000ff
-# define NV50_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE 0x0000168c
-# define NV50_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN( d) (0x00001700 + (d) * 0x0004)
-# define NV50_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE 0x00001918
-# define NV50_TCL_PRIMITIVE_3D_FRONT_FACE 0x0000191c
-# define NV50_TCL_PRIMITIVE_3D_CULL_FACE 0x00001920
-# define NV50_TCL_PRIMITIVE_3D_LOGIC_OP_ENABLE 0x000019c4
-# define NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP 0x000019c8
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS 0x000019d0 /* Parameters: color stencil depth */
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS_COLOR_MASK 0x0000003c
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS_COLOR_SHIFT 2
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS_STENCIL_MASK 0x00000002
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS_STENCIL 1 // Nothing to shift
-# define NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS_DEPTH_MASK 0x00000001
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK( d) (0x00001a00 + (d) * 0x0004) /* Parameters: a b g r */
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_A_MASK 0x0000f000
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_A_SHIFT 12
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_A_TRUE 0x0001
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_A_FALSE 0x0000
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_B_MASK 0x00000f00
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_B_SHIFT 8
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_B_TRUE 0x0001
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_B_FALSE 0x0000
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_G_MASK 0x000000f0
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_G_SHIFT 4
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_G_TRUE 0x0001
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_G_FALSE 0x0000
-# define NV50_TCL_PRIMITIVE_3D_COLOR_MASK_R_MASK 0x0000000f
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0 0x00000c00 /* Parameters: width x_offset */
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_WIDTH_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_WIDTH_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0_X_OFFSET_MASK 0x0000ffff
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1 0x00000c04 /* Parameters: height y_offset */
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_HEIGHT_MASK 0xffff0000
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_HEIGHT_SHIFT 16
-# define NV50_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_1_Y_OFFSET_MASK 0x0000ffff
-
-/******************************************
-Object NV_DMA_FROM_MEMORY used on: NV03 NV04 NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV_DMA_FROM_MEMORY 0x00000002
-
-/******************************************
-Object NV_DMA_TO_MEMORY used on: NV03 NV04 NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV_DMA_TO_MEMORY 0x00000003
-
-/******************************************
-Object NV_DMA_IN_MEMORY used on: NV03 NV04 NV10 NV15 NV20 NV30 NV40 G70
-*/
-#define NV_DMA_IN_MEMORY 0x0000003d
-
-/******************************************
-Object NvType0046 used on: NV04
-*/
-#define NvType0046 0x00000046
-# define NvType0046_DMA_NOTIFY 0x00000180
-# define NvType0046_DMA_MEM_1 0x00000184
-# define NvType0046_DMA_MEM_2 0x00000188
-# define NvType0046_DMA_3 0x0000018c
-# define NvType0046_DMA_4 0x00000190
-# define NvType0046_OBJ_5 0x00000194
-# define NvType0046_OBJ_6 0x00000198
-# define NvType0046_PITCH1 0x00000304
-# define NvType0046_PITCH2 0x0000030c
-# define NvType0046_SIZE 0x00000340 /* Parameters: width height */
-# define NvType0046_SIZE_WIDTH_MASK 0x0000ffff
-# define NvType0046_SIZE_HEIGHT_MASK 0xffff0000
-# define NvType0046_SIZE_HEIGHT_SHIFT 16
-# define NvType0046_WIDTH 0x00000344 /* Parameters: visible_width blank_width */
-# define NvType0046_WIDTH_VISIBLE_WIDTH_MASK 0x0000ffff
-# define NvType0046_WIDTH_BLANK_WIDTH_MASK 0xffff0000
-# define NvType0046_WIDTH_BLANK_WIDTH_SHIFT 16
-# define NvType0046_HSYNC 0x00000348 /* Parameters: hsync_start hsync_len */
-# define NvType0046_HSYNC_HSYNC_START_MASK 0x0000ffff
-# define NvType0046_HSYNC_HSYNC_LEN_MASK 0xffff0000
-# define NvType0046_HSYNC_HSYNC_LEN_SHIFT 16
-# define NvType0046_HEIGHT 0x0000034c /* Parameters: visible_height blank_height */
-# define NvType0046_HEIGHT_VISIBLE_HEIGHT_MASK 0x0000ffff
-# define NvType0046_HEIGHT_BLANK_HEIGHT_MASK 0xffff0000
-# define NvType0046_HEIGHT_BLANK_HEIGHT_SHIFT 16
-# define NvType0046_VSYNC 0x00000350 /* Parameters: vsync_start vsync_len */
-# define NvType0046_VSYNC_VSYNC_START_MASK 0x0000ffff
-# define NvType0046_VSYNC_VSYNC_LEN_MASK 0xffff0000
-# define NvType0046_VSYNC_VSYNC_LEN_SHIFT 16
-# define NvType0046_FULL_SIZE 0x00000354 /* Parameters: full_width full_height */
-# define NvType0046_FULL_SIZE_FULL_WIDTH_MASK 0x0000ffff
-# define NvType0046_FULL_SIZE_FULL_HEIGHT_MASK 0xffff0000
-# define NvType0046_FULL_SIZE_FULL_HEIGHT_SHIFT 16
-# define NvType0046_PIXEL_CLK 0x00000358
-# define NvType0046_FLAGS 0x0000035c /* Parameters: doublescan neg_hsync neg_vsync depth */
-# define NvType0046_FLAGS_DOUBLESCAN_MASK 0x00000002
-# define NvType0046_FLAGS_DOUBLESCAN 1 // Nothing to shift
-# define NvType0046_FLAGS_DOUBLESCAN_TRUE 0x0001
-# define NvType0046_FLAGS_DOUBLESCAN_FALSE 0x0000
-# define NvType0046_FLAGS_NEG_HSYNC_MASK 0x00000008
-# define NvType0046_FLAGS_NEG_HSYNC (1 << 3)
-# define NvType0046_FLAGS_NEG_HSYNC_TRUE 0x0001
-# define NvType0046_FLAGS_NEG_HSYNC_FALSE 0x0000
-# define NvType0046_FLAGS_NEG_VSYNC_MASK 0x00000010
-# define NvType0046_FLAGS_NEG_VSYNC (1 << 4)
-# define NvType0046_FLAGS_NEG_VSYNC_TRUE 0x0001
-# define NvType0046_FLAGS_NEG_VSYNC_FALSE 0x0000
-# define NvType0046_FLAGS_DEPTH_MASK 0x00030000
-# define NvType0046_FLAGS_DEPTH_SHIFT 16
-# define NvType0046_FLAGS_DEPTH_8 bpp 0x0000
-# define NvType0046_FLAGS_DEPTH_16 bpp 0x0001
-# define NvType0046_FLAGS_DEPTH_15 bpp 0x0002
-# define NvType0046_FLAGS_DEPTH_24 bpp 0x0003
-
-/******************************************
-Object NvType0047 used on: NV04
-*/
-#define NvType0047 0x00000047
-# define NvType0047_DMA_NOTIFY 0x00000180
-# define NvType0047_UNK19C 0x0000019c
-# define NvType0047_UNK1A0 0x000001a0
-
-/******************************************
-Object NvType0049 used on: NV04
-*/
-#define NvType0049 0x00000049
-# define NvType0049_DMA_NOTIFY 0x00000180
-# define NvType0049_DMA_MEM_1 0x00000184
-# define NvType0049_DMA_MEM_2 0x00000188
-
-/******************************************
-Object NvType004D used on: NV04
-*/
-#define NvType004D 0x0000004d
-# define NvType004D_DMA_NOTIFY 0x00000180
-# define NvType004D_DMA_MEM_1 0x00000184
-# define NvType004D_DMA_MEM_2 0x00000188
-# define NvType004D_DMA_MEM_3 0x0000018c
-# define NvType004D_DMA_MEM_4 0x00000190
-
-#endif /* _NOUVEAU_REG_H */
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_screen.c b/src/mesa/drivers/dri/nouveau/nouveau_screen.c
deleted file mode 100644
index e4463fb31a..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_screen.c
+++ /dev/null
@@ -1,325 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-#include "glheader.h"
-#include "imports.h"
-#include "mtypes.h"
-#include "framebuffer.h"
-#include "renderbuffer.h"
-
-#include "nouveau_context.h"
-#include "nouveau_screen.h"
-#include "nouveau_object.h"
-#include "nouveau_span.h"
-#include "nouveau_msg.h"
-
-#include "utils.h"
-#include "context.h"
-#include "vblank.h"
-#include "drirenderbuffer.h"
-
-#include "GL/internal/dri_interface.h"
-
-#include "xmlpool.h"
-
-PUBLIC const char __driConfigOptions[] =
-DRI_CONF_BEGIN
- DRI_CONF_SECTION_DEBUG
- DRI_CONF_NO_RAST(false)
- DRI_CONF_SECTION_END
-DRI_CONF_END;
-static const GLuint __driNConfigOptions = 1;
-
-extern const struct dri_extension common_extensions[];
-extern const struct dri_extension nv10_extensions[];
-extern const struct dri_extension nv20_extensions[];
-extern const struct dri_extension nv30_extensions[];
-extern const struct dri_extension nv40_extensions[];
-extern const struct dri_extension nv50_extensions[];
-
-static nouveauScreenPtr nouveauCreateScreen(__DRIscreenPrivate *sPriv)
-{
- nouveauScreenPtr screen;
- NOUVEAUDRIPtr dri_priv=(NOUVEAUDRIPtr)sPriv->pDevPriv;
-
- /* allocate screen */
- screen = (nouveauScreenPtr) CALLOC( sizeof(*screen) );
- if ( !screen ) {
- __driUtilMessage("%s: Could not allocate memory for screen structure",__FUNCTION__);
- return NULL;
- }
-
- screen->card=nouveau_card_lookup(dri_priv->device_id);
- if (!screen->card) {
- __driUtilMessage("%s: Unknown card type 0x%04x:0x%04x\n",
- __func__, dri_priv->device_id >> 16, dri_priv->device_id & 0xFFFF);
- FREE(screen);
- return NULL;
- }
-
- /* parse information in __driConfigOptions */
- driParseOptionInfo (&screen->optionCache,__driConfigOptions, __driNConfigOptions);
-
- screen->fbFormat = dri_priv->bpp / 8;
- screen->frontOffset = dri_priv->front_offset;
- screen->frontPitch = dri_priv->front_pitch;
- screen->backOffset = dri_priv->back_offset;
- screen->backPitch = dri_priv->back_pitch;
- screen->depthOffset = dri_priv->depth_offset;
- screen->depthPitch = dri_priv->depth_pitch;
-
- screen->driScreen = sPriv;
- return screen;
-}
-
-static void
-nouveauDestroyScreen(__DRIscreenPrivate *sPriv)
-{
- nouveauScreenPtr screen = (nouveauScreenPtr)sPriv->private;
-
- if (!screen) return;
-
- /* free all option information */
- driDestroyOptionInfo (&screen->optionCache);
-
- FREE(screen);
- sPriv->private = NULL;
-}
-
-static GLboolean nouveauInitDriver(__DRIscreenPrivate *sPriv)
-{
- sPriv->private = (void *) nouveauCreateScreen( sPriv );
- if ( !sPriv->private ) {
- nouveauDestroyScreen( sPriv );
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-/**
- * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
- *
- * \todo This function (and its interface) will need to be updated to support
- * pbuffers.
- */
-static GLboolean
-nouveauCreateBuffer(__DRIscreenPrivate *driScrnPriv,
- __DRIdrawablePrivate *driDrawPriv,
- const __GLcontextModes *mesaVis,
- GLboolean isPixmap)
-{
- nouveauScreenPtr screen = (nouveauScreenPtr) driScrnPriv->private;
- nouveau_renderbuffer_t *nrb;
- struct gl_framebuffer *fb;
- const GLboolean swAccum = mesaVis->accumRedBits > 0;
- const GLboolean swStencil = (mesaVis->stencilBits > 0 &&
- mesaVis->depthBits != 24);
- GLenum color_format = screen->fbFormat == 4 ? GL_RGBA8 : GL_RGB5;
-
- if (isPixmap)
- return GL_FALSE; /* not implemented */
-
- fb = _mesa_create_framebuffer(mesaVis);
- if (!fb)
- return GL_FALSE;
-
- /* Front buffer */
- nrb = nouveau_renderbuffer_new(color_format);
- _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &nrb->mesa);
-
- if (mesaVis->doubleBufferMode) {
- nrb = nouveau_renderbuffer_new(color_format);
- _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &nrb->mesa);
- }
-
- if (mesaVis->depthBits == 24 && mesaVis->stencilBits == 8) {
- nrb = nouveau_renderbuffer_new(GL_DEPTH24_STENCIL8_EXT);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &nrb->mesa);
- _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &nrb->mesa);
- } else
- if (mesaVis->depthBits == 24) {
- nrb = nouveau_renderbuffer_new(GL_DEPTH_COMPONENT24);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &nrb->mesa);
- } else
- if (mesaVis->depthBits == 16) {
- nrb = nouveau_renderbuffer_new(GL_DEPTH_COMPONENT16);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &nrb->mesa);
- }
-
- _mesa_add_soft_renderbuffers(fb,
- GL_FALSE, /* color */
- GL_FALSE, /* depth */
- swStencil,
- swAccum,
- GL_FALSE, /* alpha */
- GL_FALSE /* aux */);
-
- driDrawPriv->driverPrivate = (void *) fb;
- return (driDrawPriv->driverPrivate != NULL);
-}
-
-
-static void
-nouveauDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
-{
- _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
-}
-
-static int
-nouveauGetSwapInfo(__DRIdrawablePrivate *dpriv, __DRIswapInfo *sInfo)
-{
- return -1;
-}
-
-static __DRIconfig **
-nouveauFillInModes( __DRIscreenPrivate *psp,
- unsigned pixel_bits, unsigned depth_bits,
- unsigned stencil_bits, GLboolean have_back_buffer )
-{
- unsigned depth_buffer_factor;
- unsigned back_buffer_factor;
-
- /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
- * support pageflipping at all.
- */
- static const GLenum back_buffer_modes[] = {
- GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
- };
-
- u_int8_t depth_bits_array[4] = { 0, 16, 24, 24 };
- u_int8_t stencil_bits_array[4] = { 0, 0, 0, 8 };
-
- depth_buffer_factor = 4;
- back_buffer_factor = (have_back_buffer) ? 3 : 1;
-
- if (pixel_bits == 16)
- return driCreateConfigs(GL_RGB,
- GL_UNSIGNED_SHORT_5_6_5,
- depth_bits_array,
- stencil_bits_array,
- depth_buffer_factor,
- back_buffer_modes,
- back_buffer_factor);
- else
- return driCreateConfigs(GL_RGBA,
- GL_UNSIGNED_INT_8_8_8_8_REV,
- depth_bits_array,
- stencil_bits_array,
- depth_buffer_factor,
- back_buffer_modes,
- back_buffer_factor);
-}
-
-
-/**
- * This is the driver specific part of the createNewScreen entry point.
- *
- * \todo maybe fold this into intelInitDriver
- *
- * \return the __GLcontextModes supported by this driver
- */
-static const __DRIconfig **
-nouveauInitScreen(__DRIscreenPrivate *psp)
-{
- static const __DRIversion ddx_expected = { 0, 0, NOUVEAU_DRM_HEADER_PATCHLEVEL };
- static const __DRIversion dri_expected = { 4, 0, 0 };
- static const __DRIversion drm_expected = { 0, 0, NOUVEAU_DRM_HEADER_PATCHLEVEL };
- NOUVEAUDRIPtr dri_priv = (NOUVEAUDRIPtr)psp->pDevPriv;
-
- WARN_ONCE("\nThis driver is not currently maintained\n\n"
- "Current work on 3D is in the gallium-0.1 branch of:\n"
- " git://anongit.freedesktop.org/git/nouveau/mesa\n");
-
-#if NOUVEAU_DRM_HEADER_PATCHLEVEL != 10
-#error nouveau_drm.h version does not match expected version
-#endif
-
- if (!driCheckDriDdxDrmVersions2("nouveau",
- &psp->dri_version, & dri_expected,
- &psp->ddx_version, & ddx_expected,
- &psp->drm_version, & drm_expected))
- return NULL;
-
- // temporary lock step versioning
- if (drm_expected.patch != psp->drm_version.patch) {
- __driUtilMessage("%s: wrong DRM version, expected %d, got %d\n",
- __func__,
- drm_expected.patch, psp->drm_version.patch);
- return NULL;
- }
-
- /* Calling driInitExtensions here, with a NULL context
- * pointer, does not actually enable the extensions. It just
- * makes sure that all the dispatch offsets for all the
- * extensions that *might* be enables are known. This is
- * needed because the dispatch offsets need to be known when
- * _mesa_context_create is called, but we can't enable the
- * extensions until we have a context pointer.
- *
- * Hello chicken. Hello egg. How are you two today?
- */
- driInitExtensions( NULL, common_extensions, GL_FALSE );
- driInitExtensions( NULL, nv10_extensions, GL_FALSE );
- driInitExtensions( NULL, nv10_extensions, GL_FALSE );
- driInitExtensions( NULL, nv30_extensions, GL_FALSE );
- driInitExtensions( NULL, nv40_extensions, GL_FALSE );
- driInitExtensions( NULL, nv50_extensions, GL_FALSE );
-
- if (!nouveauInitDriver(psp))
- return NULL;
-
- return (const __DRIconfig **)
- nouveauFillInModes(psp,
- dri_priv->bpp,
- (dri_priv->bpp == 16) ? 16 : 24,
- (dri_priv->bpp == 16) ? 0 : 8,
- 1);
-}
-
-const struct __DriverAPIRec driDriverAPI = {
- .InitScreen = nouveauInitScreen,
- .DestroyScreen = nouveauDestroyScreen,
- .CreateContext = nouveauCreateContext,
- .DestroyContext = nouveauDestroyContext,
- .CreateBuffer = nouveauCreateBuffer,
- .DestroyBuffer = nouveauDestroyBuffer,
- .SwapBuffers = nouveauSwapBuffers,
- .MakeCurrent = nouveauMakeCurrent,
- .UnbindContext = nouveauUnbindContext,
- .GetSwapInfo = nouveauGetSwapInfo,
- .GetDrawableMSC = driDrawableGetMSC32,
- .WaitForMSC = driWaitForMSC32,
- .WaitForSBC = NULL,
- .SwapBuffersMSC = NULL,
- .CopySubBuffer = nouveauCopySubBuffer
-};
-
-const __DRIextension *__driDriverExtensions[] = {
- &driCoreExtension.base,
- &driLegacyExtension.base,
- NULL
-};
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_screen.h b/src/mesa/drivers/dri/nouveau/nouveau_screen.h
deleted file mode 100644
index decdafa86d..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_screen.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-#ifndef __NOUVEAU_SCREEN_H__
-#define __NOUVEAU_SCREEN_H__
-
-#include "xmlconfig.h"
-
-#include "nouveau_dri.h"
-#include "nouveau_card.h"
-
-typedef struct {
- nouveau_card* card;
- u_int32_t bus_type;
- u_int32_t agp_mode;
-
- GLint fbFormat;
-
- GLuint frontOffset;
- GLuint frontPitch;
- GLuint backOffset;
- GLuint backPitch;
-
- GLuint depthOffset;
- GLuint depthPitch;
- GLuint spanOffset;
-
- __DRIscreenPrivate *driScreen;
- unsigned int sarea_priv_offset;
-
- /* Configuration cache with default values for all contexts */
- driOptionCache optionCache;
-
-} nouveauScreenRec, *nouveauScreenPtr;
-
-
-#endif /* __NOUVEAU_SCREEN_H__ */
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader.c b/src/mesa/drivers/dri/nouveau/nouveau_shader.c
deleted file mode 100644
index b6837c5de1..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_shader.c
+++ /dev/null
@@ -1,833 +0,0 @@
-/*
- * Copyright (C) 2006 Ben Skeggs.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-/*
- * Authors:
- * Ben Skeggs
- */
-
-#include "glheader.h"
-#include "macros.h"
-#include "enums.h"
-#include "extensions.h"
-
-#include "shader/program.h"
-#include "shader/prog_instruction.h"
-/*#include "shader/arbprogparse.h"*/
-#include "tnl/tnl.h"
-
-#include "nouveau_context.h"
-#include "nouveau_shader.h"
-
-/*****************************************************************************
- * Mesa entry points
- */
-static void
-nouveauBindProgram(GLcontext *ctx, GLenum target, struct gl_program *prog)
-{
- NVSDBG("target=%s, prog=%p\n", _mesa_lookup_enum_by_nr(target), prog);
-}
-
-static struct gl_program *
-nouveauNewProgram(GLcontext *ctx, GLenum target, GLuint id)
-{
- nouveauShader *nvs;
-
- NVSDBG("target=%s, id=%d\n", _mesa_lookup_enum_by_nr(target), id);
-
- nvs = CALLOC_STRUCT(_nouveauShader);
- NVSDBG("prog=%p\n", nvs);
- switch (target) {
- case GL_VERTEX_PROGRAM_ARB:
- return _mesa_init_vertex_program(ctx, &nvs->mesa.vp, target, id);
- case GL_FRAGMENT_PROGRAM_ARB:
- return _mesa_init_fragment_program(ctx, &nvs->mesa.fp, target, id);
- default:
- _mesa_problem(ctx, "Unsupported shader target");
- break;
- }
-
- FREE(nvs);
- return NULL;
-}
-
-static void
-nouveauDeleteProgram(GLcontext *ctx, struct gl_program *prog)
-{
- nouveauShader *nvs = (nouveauShader *)prog;
-
- NVSDBG("prog=%p\n", prog);
-
- if (nvs->translated)
- FREE(nvs->program);
- _mesa_delete_program(ctx, prog);
-}
-
-static void
-nouveauProgramStringNotify(GLcontext *ctx, GLenum target,
- struct gl_program *prog)
-{
- nouveauShader *nvs = (nouveauShader *)prog;
-
- NVSDBG("target=%s, prog=%p\n", _mesa_lookup_enum_by_nr(target), prog);
-
- if (nvs->translated)
- FREE(nvs->program);
-
- nvs->error = GL_FALSE;
- nvs->translated = GL_FALSE;
-
- _tnl_program_string(ctx, target, prog);
-}
-
-static GLboolean
-nouveauIsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog)
-{
- nouveauShader *nvs = (nouveauShader *)prog;
-
- NVSDBG("target=%s, prog=%p\n", _mesa_lookup_enum_by_nr(target), prog);
-
- return nvs->translated;
-}
-
-GLboolean
-nvsUpdateShader(GLcontext *ctx, nouveauShader *nvs)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- struct gl_program_parameter_list *plist;
- int i;
-
- NVSDBG("prog=%p\n", nvs);
-
- /* Translate to HW format now if necessary */
- if (!nvs->translated) {
- /* Mesa ASM shader -> nouveauShader */
- if (!nouveau_shader_pass0(ctx, nvs))
- return GL_FALSE;
- /* Basic dead code elimination + register usage info */
- if (!nouveau_shader_pass1(nvs))
- return GL_FALSE;
- /* nouveauShader -> HW bytecode, HW register alloc */
- if (!nouveau_shader_pass2(nvs))
- return GL_FALSE;
- assert(nvs->translated);
- assert(nvs->program);
- }
-
- /* Update state parameters */
- plist = nvs->mesa.vp.Base.Parameters;
- _mesa_load_state_parameters(ctx, plist);
- for (i=0; iparam_high; i++) {
- if (!nvs->params[i].in_use)
- continue;
-
- if (!nvs->on_hardware) {
- /* if we've been kicked off the hardware there's no guarantee our
- * consts are still there.. reupload them all
- */
- nvs->func->UpdateConst(ctx, nvs, i);
- } else if (nvs->params[i].source_val) {
- /* update any changed state parameters */
- if (!TEST_EQ_4V(nvs->params[i].val, nvs->params[i].source_val))
- nvs->func->UpdateConst(ctx, nvs, i);
- }
- }
-
- /* Upload program to hardware, this must come after state param update
- * as >=NV30 fragprogs inline consts into the bytecode.
- */
- if (!nvs->on_hardware) {
- nouveauShader **current;
-
- if (nvs->mesa.vp.Base.Target == GL_VERTEX_PROGRAM_ARB)
- current = &nmesa->current_vertprog;
- else
- current = &nmesa->current_fragprog;
- if (*current) (*current)->on_hardware = 0;
-
- nvs->func->UploadToHW(ctx, nvs);
- nvs->on_hardware = 1;
-
- *current = nvs;
- }
-
- return GL_TRUE;
-}
-
-nouveauShader *
-nvsBuildTextShader(GLcontext *ctx, GLenum target, const char *text)
-{
- nouveauShader *nvs;
-
- nvs = CALLOC_STRUCT(_nouveauShader);
- if (!nvs)
- return NULL;
-
- if (target == GL_VERTEX_PROGRAM_ARB) {
- _mesa_init_vertex_program(ctx, &nvs->mesa.vp, GL_VERTEX_PROGRAM_ARB, 0);
- _mesa_parse_arb_vertex_program(ctx,
- GL_VERTEX_PROGRAM_ARB,
- text,
- strlen(text),
- &nvs->mesa.vp);
- } else if (target == GL_FRAGMENT_PROGRAM_ARB) {
- _mesa_init_fragment_program(ctx, &nvs->mesa.fp, GL_FRAGMENT_PROGRAM_ARB, 0);
- _mesa_parse_arb_fragment_program(ctx,
- GL_FRAGMENT_PROGRAM_ARB,
- text,
- strlen(text),
- &nvs->mesa.fp);
- }
-
- nouveau_shader_pass0(ctx, nvs);
- nouveau_shader_pass1(nvs);
- nouveau_shader_pass2(nvs);
-
- return nvs;
-}
-
-static void
-nvsBuildPassthroughVP(GLcontext *ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- const char *vp_text =
- "!!ARBvp1.0\n"
- "OPTION ARB_position_invariant;"
- ""
- "MOV result.color, vertex.color;\n"
- "MOV result.texcoord[0], vertex.texcoord[0];\n"
- "MOV result.texcoord[1], vertex.texcoord[1];\n"
- "MOV result.texcoord[2], vertex.texcoord[2];\n"
- "MOV result.texcoord[3], vertex.texcoord[3];\n"
- "MOV result.texcoord[4], vertex.texcoord[4];\n"
- "MOV result.texcoord[5], vertex.texcoord[5];\n"
- "MOV result.texcoord[6], vertex.texcoord[6];\n"
- "MOV result.texcoord[7], vertex.texcoord[7];\n"
- "END";
-
- nmesa->passthrough_vp = nvsBuildTextShader(ctx,
- GL_VERTEX_PROGRAM_ARB,
- vp_text);
-}
-
-static void
-nvsBuildPassthroughFP(GLcontext *ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- const char *fp_text =
- "!!ARBfp1.0\n"
- "MOV result.color, fragment.color;\n"
- "END";
-
- nmesa->passthrough_fp = nvsBuildTextShader(ctx,
- GL_FRAGMENT_PROGRAM_ARB,
- fp_text);
-}
-
-void
-nouveauShaderInitFuncs(GLcontext * ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- switch (nmesa->screen->card->type) {
- case NV_20:
- NV20VPInitShaderFuncs(&nmesa->VPfunc);
- break;
- case NV_30:
- NV30VPInitShaderFuncs(&nmesa->VPfunc);
- NV30FPInitShaderFuncs(&nmesa->FPfunc);
- break;
- case NV_40:
- case NV_44:
- NV40VPInitShaderFuncs(&nmesa->VPfunc);
- NV40FPInitShaderFuncs(&nmesa->FPfunc);
- break;
- case NV_50:
- default:
- return;
- }
-
- /* Build a vertex program that simply passes through all attribs.
- * Needed to do swtcl on nv40
- */
- if (nmesa->screen->card->type >= NV_40)
- nvsBuildPassthroughVP(ctx);
-
- /* Needed on NV30, even when using swtcl, if you want to get colours */
- if (nmesa->screen->card->type >= NV_30)
- nvsBuildPassthroughFP(ctx);
-
- ctx->Const.VertexProgram.MaxNativeInstructions = nmesa->VPfunc.MaxInst;
- ctx->Const.VertexProgram.MaxNativeAluInstructions = nmesa->VPfunc.MaxInst;
- ctx->Const.VertexProgram.MaxNativeTexInstructions = nmesa->VPfunc.MaxInst;
- ctx->Const.VertexProgram.MaxNativeTexIndirections =
- ctx->Const.VertexProgram.MaxNativeTexInstructions;
- ctx->Const.VertexProgram.MaxNativeAttribs = nmesa->VPfunc.MaxAttrib;
- ctx->Const.VertexProgram.MaxNativeTemps = nmesa->VPfunc.MaxTemp;
- ctx->Const.VertexProgram.MaxNativeAddressRegs = nmesa->VPfunc.MaxAddress;
- ctx->Const.VertexProgram.MaxNativeParameters = nmesa->VPfunc.MaxConst;
-
- if (nmesa->screen->card->type >= NV_30) {
- ctx->Const.FragmentProgram.MaxNativeInstructions = nmesa->FPfunc.MaxInst;
- ctx->Const.FragmentProgram.MaxNativeAluInstructions = nmesa->FPfunc.MaxInst;
- ctx->Const.FragmentProgram.MaxNativeTexInstructions = nmesa->FPfunc.MaxInst;
- ctx->Const.FragmentProgram.MaxNativeTexIndirections =
- ctx->Const.FragmentProgram.MaxNativeTexInstructions;
- ctx->Const.FragmentProgram.MaxNativeAttribs = nmesa->FPfunc.MaxAttrib;
- ctx->Const.FragmentProgram.MaxNativeTemps = nmesa->FPfunc.MaxTemp;
- ctx->Const.FragmentProgram.MaxNativeAddressRegs = nmesa->FPfunc.MaxAddress;
- ctx->Const.FragmentProgram.MaxNativeParameters = nmesa->FPfunc.MaxConst;
- }
-
- ctx->Driver.NewProgram = nouveauNewProgram;
- ctx->Driver.BindProgram = nouveauBindProgram;
- ctx->Driver.DeleteProgram = nouveauDeleteProgram;
- ctx->Driver.ProgramStringNotify = nouveauProgramStringNotify;
- ctx->Driver.IsProgramNative = nouveauIsProgramNative;
-}
-
-
-/*****************************************************************************
- * Disassembly support structs
- */
-#define CHECK_RANGE(idx, arr) ((idx)= (sizeof(ops) / sizeof(struct _opcode_info)))
- return NULL;
- if (ops[op].name == NULL)
- return NULL;
- return &ops[op];
-}
-
-static const char *_SFR_STRING[] = {
- [NVS_FR_POSITION] = "position",
- [NVS_FR_WEIGHT] = "weight",
- [NVS_FR_NORMAL] = "normal",
- [NVS_FR_COL0] = "color",
- [NVS_FR_COL1] = "color.secondary",
- [NVS_FR_BFC0] = "bfc",
- [NVS_FR_BFC1] = "bfc.secondary",
- [NVS_FR_FOGCOORD] = "fogcoord",
- [NVS_FR_POINTSZ] = "pointsize",
- [NVS_FR_TEXCOORD0] = "texcoord[0]",
- [NVS_FR_TEXCOORD1] = "texcoord[1]",
- [NVS_FR_TEXCOORD2] = "texcoord[2]",
- [NVS_FR_TEXCOORD3] = "texcoord[3]",
- [NVS_FR_TEXCOORD4] = "texcoord[4]",
- [NVS_FR_TEXCOORD5] = "texcoord[5]",
- [NVS_FR_TEXCOORD6] = "texcoord[6]",
- [NVS_FR_TEXCOORD7] = "texcoord[7]",
- [NVS_FR_FRAGDATA0] = "data[0]",
- [NVS_FR_FRAGDATA1] = "data[1]",
- [NVS_FR_FRAGDATA2] = "data[2]",
- [NVS_FR_FRAGDATA3] = "data[3]",
- [NVS_FR_CLIP0] = "clip_plane[0]",
- [NVS_FR_CLIP1] = "clip_plane[1]",
- [NVS_FR_CLIP2] = "clip_plane[2]",
- [NVS_FR_CLIP3] = "clip_plane[3]",
- [NVS_FR_CLIP4] = "clip_plane[4]",
- [NVS_FR_CLIP5] = "clip_plane[5]",
- [NVS_FR_CLIP6] = "clip_plane[6]",
- [NVS_FR_FACING] = "facing",
-};
-
-#define SFR_STRING(idx) CHECK_RANGE((idx), SFR_STRING)
-
-static const char *_SWZ_STRING[] = {
- [NVS_SWZ_X] = "x",
- [NVS_SWZ_Y] = "y",
- [NVS_SWZ_Z] = "z",
- [NVS_SWZ_W] = "w"
-};
-
-#define SWZ_STRING(idx) CHECK_RANGE((idx), SWZ_STRING)
-
-static const char *_NVS_PREC_STRING[] = {
- [NVS_PREC_FLOAT32] = "R",
- [NVS_PREC_FLOAT16] = "H",
- [NVS_PREC_FIXED12] = "X",
- [NVS_PREC_UNKNOWN] = "?"
-};
-
-#define NVS_PREC_STRING(idx) CHECK_RANGE((idx), NVS_PREC_STRING)
-
-static const char *_NVS_COND_STRING[] = {
- [NVS_COND_FL] = "FL",
- [NVS_COND_LT] = "LT",
- [NVS_COND_EQ] = "EQ",
- [NVS_COND_LE] = "LE",
- [NVS_COND_GT] = "GT",
- [NVS_COND_NE] = "NE",
- [NVS_COND_GE] = "GE",
- [NVS_COND_TR] = "TR",
- [NVS_COND_UNKNOWN] = "??"
-};
-
-#define NVS_COND_STRING(idx) CHECK_RANGE((idx), NVS_COND_STRING)
-
-/*****************************************************************************
- * ShaderFragment dumping
- */
-static void
-nvsDumpIndent(int lvl)
-{
- while (lvl--)
- printf(" ");
-}
-
-static void
-nvsDumpSwizzle(nvsSwzComp *swz)
-{
- printf(".%s%s%s%s",
- SWZ_STRING(swz[0]),
- SWZ_STRING(swz[1]), SWZ_STRING(swz[2]), SWZ_STRING(swz[3])
- );
-}
-
-static void
-nvsDumpReg(nvsInstruction * inst, nvsRegister * reg)
-{
- if (reg->negate)
- printf("-");
- if (reg->abs)
- printf("abs(");
-
- switch (reg->file) {
- case NVS_FILE_TEMP:
- printf("R%d", reg->index);
- nvsDumpSwizzle(reg->swizzle);
- break;
- case NVS_FILE_ATTRIB:
- printf("attrib.%s", SFR_STRING(reg->index));
- nvsDumpSwizzle(reg->swizzle);
- break;
- case NVS_FILE_ADDRESS:
- printf("A%d", reg->index);
- break;
- case NVS_FILE_CONST:
- if (reg->indexed)
- printf("const[A%d.%s + %d]",
- reg->addr_reg, SWZ_STRING(reg->addr_comp), reg->index);
- else
- printf("const[%d]", reg->index);
- nvsDumpSwizzle(reg->swizzle);
- break;
- default:
- printf("UNKNOWN_FILE");
- break;
- }
-
- if (reg->abs)
- printf(")");
-}
-
-static void
-nvsDumpInstruction(nvsInstruction * inst, int slot, int lvl)
-{
- struct _opcode_info *opr = &ops[inst->op];
- int i;
-
- nvsDumpIndent(lvl);
- printf("%s ", opr->name);
-
- if (!opr->flags & NODS) {
- switch (inst->dest.file) {
- case NVS_FILE_RESULT:
- printf("result.%s", SFR_STRING(inst->dest.index));
- break;
- case NVS_FILE_TEMP:
- printf("R%d", inst->dest.index);
- break;
- case NVS_FILE_ADDRESS:
- printf("A%d", inst->dest.index);
- break;
- default:
- printf("UNKNOWN_DST_FILE");
- break;
- }
-
- if (inst->mask != SMASK_ALL) {
- printf(".");
- if (inst->mask & SMASK_X)
- printf("x");
- if (inst->mask & SMASK_Y)
- printf("y");
- if (inst->mask & SMASK_Z)
- printf("z");
- if (inst->mask & SMASK_W)
- printf("w");
- }
-
- if (opr->numsrc)
- printf(", ");
- }
-
- for (i = 0; i < opr->numsrc; i++) {
- nvsDumpReg(inst, &inst->src[i]);
- if (i != opr->numsrc - 1)
- printf(", ");
- }
- if (opr->flags & TI_UNIT)
- printf(", texture[%d]", inst->tex_unit);
-
- printf("\n");
-}
-
-void
-nvsDumpFragmentList(nvsFragmentHeader *f, int lvl)
-{
- while (f) {
- switch (f->type) {
- case NVS_INSTRUCTION:
- nvsDumpInstruction((nvsInstruction*)f, 0, lvl);
- break;
- default:
- fprintf(stderr, "%s: Only NVS_INSTRUCTION fragments can be in"
- "nvsFragmentList!\n", __func__);
- return;
- }
- f = f->next;
- }
-}
-
-/*****************************************************************************
- * HW shader disassembly
- */
-static void
-nvsDisasmHWShaderOp(nvsFunc * shader, int merged)
-{
- struct _opcode_info *opi;
- nvsOpcode op;
- nvsRegFile file;
- nvsSwzComp swz[4];
- int i;
-
- op = shader->GetOpcode(shader, merged);
- opi = _get_op_info(op);
- if (!opi) {
- printf("NO OPINFO!");
- return;
- }
-
- printf("%s", opi->name);
- if (shader->GetPrecision &&
- (!(opi->flags & BRANCH_ALL)) && (!(opi->flags * NODS)) &&
- (op != NVS_OP_NOP))
- printf("%s", NVS_PREC_STRING(shader->GetPrecision(shader)));
- if (shader->SupportsConditional && shader->SupportsConditional(shader)) {
- if (shader->GetConditionUpdate(shader)) {
- printf("C%d", shader->GetCondRegID(shader));
- }
- }
- if (shader->GetSaturate && shader->GetSaturate(shader))
- printf("_SAT");
-
- if (!(opi->flags & NODS)) {
- int mask = shader->GetDestMask(shader, merged);
-
- switch (shader->GetDestFile(shader, merged)) {
- case NVS_FILE_ADDRESS:
- printf(" A%d", shader->GetDestID(shader, merged));
- break;
- case NVS_FILE_TEMP:
- printf(" R%d", shader->GetDestID(shader, merged));
- break;
- case NVS_FILE_RESULT:
- printf(" result.%s", (SFR_STRING(shader->GetDestID(shader, merged))));
- break;
- default:
- printf(" BAD_RESULT_FILE");
- break;
- }
-
- if (mask != SMASK_ALL) {
- printf(".");
- if (mask & SMASK_X) printf("x");
- if (mask & SMASK_Y) printf("y");
- if (mask & SMASK_Z) printf("z");
- if (mask & SMASK_W) printf("w");
- }
- }
-
- if (shader->SupportsConditional && shader->SupportsConditional(shader) &&
- shader->GetConditionTest(shader)) {
- shader->GetCondRegSwizzle(shader, swz);
-
- printf(" (%s%d.%s%s%s%s)",
- NVS_COND_STRING(shader->GetCondition(shader)),
- shader->GetCondRegID(shader),
- SWZ_STRING(swz[NVS_SWZ_X]),
- SWZ_STRING(swz[NVS_SWZ_Y]),
- SWZ_STRING(swz[NVS_SWZ_Z]),
- SWZ_STRING(swz[NVS_SWZ_W])
- );
- }
-
- /* looping */
- if (opi->flags & COUNT_ALL) {
- printf(" { ");
- if (opi->flags & COUNT_NUM) {
- printf("%d", shader->GetLoopCount(shader));
- }
- if (opi->flags & COUNT_IND) {
- printf(", %d", shader->GetLoopInitial(shader));
- }
- if (opi->flags & COUNT_INC) {
- printf(", %d", shader->GetLoopIncrement(shader));
- }
- printf(" }");
- }
-
- /* branching */
- if (opi->flags & BRANCH_TR)
- printf(" %d", shader->GetBranch(shader));
- if (opi->flags & BRANCH_EL)
- printf(" ELSE %d", shader->GetBranchElse(shader));
- if (opi->flags & BRANCH_EN)
- printf(" END %d", shader->GetBranchEnd(shader));
-
- if (!(opi->flags & NODS) && opi->numsrc)
- printf(",");
- printf(" ");
-
- for (i = 0; i < opi->numsrc; i++) {
- if (shader->GetSourceAbs(shader, merged, i))
- printf("abs(");
- if (shader->GetSourceNegate(shader, merged, i))
- printf("-");
-
- file = shader->GetSourceFile(shader, merged, i);
- switch (file) {
- case NVS_FILE_TEMP:
- printf("R%d", shader->GetSourceID(shader, merged, i));
- break;
- case NVS_FILE_CONST:
- if (shader->GetSourceIndexed(shader, merged, i)) {
- printf("c[A%d.%s + 0x%x]",
- shader->GetRelAddressRegID(shader),
- SWZ_STRING(shader->GetRelAddressSwizzle(shader)),
- shader->GetSourceID(shader, merged, i)
- );
- } else {
- float val[4];
-
- if (shader->GetSourceConstVal) {
- shader->GetSourceConstVal(shader, merged, i, val);
- printf("{ %.02f, %.02f, %.02f, %.02f }",
- val[0], val[1], val[2], val[3]);
- } else {
- printf("c[0x%x]", shader->GetSourceID(shader, merged, i));
- }
- }
- break;
- case NVS_FILE_ATTRIB:
- if (shader->GetSourceIndexed(shader, merged, i)) {
- printf("attrib[A%d.%s + %d]",
- shader->GetRelAddressRegID(shader),
- SWZ_STRING(shader->GetRelAddressSwizzle(shader)),
- shader->GetSourceID(shader, merged, i)
- );
- }
- else {
- printf("attrib.%s",
- SFR_STRING(shader->GetSourceID(shader, merged, i))
- );
- }
- break;
- case NVS_FILE_ADDRESS:
- printf("A%d", shader->GetRelAddressRegID(shader));
- break;
- default:
- printf("UNKNOWN_SRC_FILE");
- break;
- }
-
- shader->GetSourceSwizzle(shader, merged, i, swz);
- if (file != NVS_FILE_ADDRESS &&
- (swz[NVS_SWZ_X] != NVS_SWZ_X || swz[NVS_SWZ_Y] != NVS_SWZ_Y ||
- swz[NVS_SWZ_Z] != NVS_SWZ_Z || swz[NVS_SWZ_W] != NVS_SWZ_W)) {
- printf(".%s%s%s%s", SWZ_STRING(swz[NVS_SWZ_X]),
- SWZ_STRING(swz[NVS_SWZ_Y]),
- SWZ_STRING(swz[NVS_SWZ_Z]),
- SWZ_STRING(swz[NVS_SWZ_W]));
- }
-
- if (shader->GetSourceAbs(shader, merged, i))
- printf(")");
- if (shader->GetSourceScale) {
- int scale = shader->GetSourceScale(shader, merged, i);
- if (scale > 1)
- printf("{scaled %dx}", scale);
- }
- if (i < (opi->numsrc - 1))
- printf(", ");
- }
-
- if (shader->IsLastInst(shader))
- printf(" + END");
-}
-
-void
-nvsDisasmHWShader(nvsPtr nvs)
-{
- nvsFunc *shader = nvs->func;
- unsigned int iaddr = 0;
-
- if (!nvs->program) {
- fprintf(stderr, "No HW program present");
- return;
- }
-
- shader->inst = nvs->program;
- while (1) {
- if (shader->inst >= (nvs->program + nvs->program_size)) {
- fprintf(stderr, "Reached end of program, but HW inst has no END");
- break;
- }
-
- printf("\t0x%08x:\n", shader->inst[0]);
- printf("\t0x%08x:\n", shader->inst[1]);
- printf("\t0x%08x:\n", shader->inst[2]);
- printf("\t0x%08x:", shader->inst[3]);
-
- printf("\n\t\tINST %d.0: ", iaddr);
- nvsDisasmHWShaderOp(shader, 0);
- if (shader->HasMergedInst(shader)) {
- printf("\n\t\tINST %d.1: ", iaddr);
- nvsDisasmHWShaderOp(shader, 1);
- }
- printf("\n");
-
- if (shader->IsLastInst(shader))
- break;
-
- shader->inst += shader->GetOffsetNext(shader);
- iaddr++;
- }
-
- printf("\n");
-}
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader.h b/src/mesa/drivers/dri/nouveau/nouveau_shader.h
deleted file mode 100644
index 636bcaa72b..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_shader.h
+++ /dev/null
@@ -1,454 +0,0 @@
-#ifndef __SHADER_COMMON_H__
-#define __SHADER_COMMON_H__
-
-#include "mtypes.h"
-#include "bufferobj.h"
-
-#define NVSDBG(fmt, args...) do { \
- if (NOUVEAU_DEBUG & DEBUG_SHADERS) { \
- fprintf(stderr, "%s: "fmt, __func__, ##args); \
- } \
-} while(0)
-
-typedef struct _nvsFunc nvsFunc;
-
-#define NVS_MAX_TEMPS 32
-#define NVS_MAX_ATTRIBS 16
-#define NVS_MAX_CONSTS 256
-#define NVS_MAX_ADDRESS 2
-#define NVS_MAX_INSNS 4096
-
-typedef struct _nvs_fragment_header {
- struct _nvs_fragment_header *parent;
- struct _nvs_fragment_header *prev;
- struct _nvs_fragment_header *next;
- enum {
- NVS_INSTRUCTION,
- NVS_BRANCH,
- NVS_LOOP,
- NVS_SUBROUTINE
- } type;
-} nvsFragmentHeader;
-
-typedef union {
- struct {
- GLboolean uses_kil;
- GLuint num_regs;
- } NV30FP;
- struct {
- uint32_t vp_in_reg;
- uint32_t vp_out_reg;
- uint32_t clip_enables;
- } NV30VP;
-} nvsCardPriv;
-
-typedef struct _nouveauShader {
- union {
- struct gl_vertex_program vp;
- struct gl_fragment_program fp;
- } mesa;
- GLcontext *ctx;
- nvsFunc *func;
-
- /* State of the final program */
- GLboolean error;
- GLboolean translated;
- GLboolean on_hardware;
- unsigned int *program;
- unsigned int program_size;
- unsigned int program_alloc_size;
- unsigned int program_start_id;
- unsigned int program_current;
- struct gl_buffer_object *program_buffer;
- int inst_count;
-
- nvsCardPriv card_priv;
- int vp_attrib_map[NVS_MAX_ATTRIBS];
-
- struct {
- GLboolean in_use;
-
- GLfloat *source_val; /* NULL if invariant */
- float val[4];
- /* Hardware-specific tracking, currently only nv30_fragprog
- * makes use of it.
- */
- int *hw_index;
- int hw_index_cnt;
- } params[NVS_MAX_CONSTS];
- int param_high;
-
- /* Pass-private data */
- void *pass_rec;
-
- nvsFragmentHeader *program_tree;
-} nouveauShader, *nvsPtr;
-
-typedef enum {
- NVS_FILE_NONE,
- NVS_FILE_TEMP,
- NVS_FILE_ATTRIB,
- NVS_FILE_CONST,
- NVS_FILE_RESULT,
- NVS_FILE_ADDRESS,
- NVS_FILE_UNKNOWN
-} nvsRegFile;
-
-typedef enum {
- NVS_OP_UNKNOWN = 0,
- NVS_OP_NOP,
- NVS_OP_ABS, NVS_OP_ADD, NVS_OP_ARA, NVS_OP_ARL, NVS_OP_ARR,
- NVS_OP_BRA, NVS_OP_BRK,
- NVS_OP_CAL, NVS_OP_CMP, NVS_OP_COS,
- NVS_OP_DDX, NVS_OP_DDY, NVS_OP_DIV, NVS_OP_DP2, NVS_OP_DP2A, NVS_OP_DP3,
- NVS_OP_DP4, NVS_OP_DPH, NVS_OP_DST,
- NVS_OP_EX2, NVS_OP_EXP,
- NVS_OP_FLR, NVS_OP_FRC,
- NVS_OP_IF,
- NVS_OP_KIL,
- NVS_OP_LG2, NVS_OP_LIT, NVS_OP_LOG, NVS_OP_LOOP, NVS_OP_LRP,
- NVS_OP_MAD, NVS_OP_MAX, NVS_OP_MIN, NVS_OP_MOV, NVS_OP_MUL,
- NVS_OP_NRM,
- NVS_OP_PK2H, NVS_OP_PK2US, NVS_OP_PK4B, NVS_OP_PK4UB, NVS_OP_POW,
- NVS_OP_POPA, NVS_OP_PUSHA,
- NVS_OP_RCC, NVS_OP_RCP, NVS_OP_REP, NVS_OP_RET, NVS_OP_RFL, NVS_OP_RSQ,
- NVS_OP_SCS, NVS_OP_SEQ, NVS_OP_SFL, NVS_OP_SGE, NVS_OP_SGT, NVS_OP_SIN,
- NVS_OP_SLE, NVS_OP_SLT, NVS_OP_SNE, NVS_OP_SSG, NVS_OP_STR, NVS_OP_SUB,
- NVS_OP_SWZ,
- NVS_OP_TEX, NVS_OP_TXB, NVS_OP_TXD, NVS_OP_TXL, NVS_OP_TXP,
- NVS_OP_UP2H, NVS_OP_UP2US, NVS_OP_UP4B, NVS_OP_UP4UB,
- NVS_OP_X2D, NVS_OP_XPD,
- NVS_OP_EMUL
-} nvsOpcode;
-
-typedef enum {
- NVS_PREC_FLOAT32,
- NVS_PREC_FLOAT16,
- NVS_PREC_FIXED12,
- NVS_PREC_UNKNOWN
-} nvsPrecision;
-
-typedef enum {
- NVS_SWZ_X = 0,
- NVS_SWZ_Y = 1,
- NVS_SWZ_Z = 2,
- NVS_SWZ_W = 3
-} nvsSwzComp;
-
-typedef enum {
- NVS_FR_POSITION = 0,
- NVS_FR_WEIGHT = 1,
- NVS_FR_NORMAL = 2,
- NVS_FR_COL0 = 3,
- NVS_FR_COL1 = 4,
- NVS_FR_FOGCOORD = 5,
- NVS_FR_TEXCOORD0 = 8,
- NVS_FR_TEXCOORD1 = 9,
- NVS_FR_TEXCOORD2 = 10,
- NVS_FR_TEXCOORD3 = 11,
- NVS_FR_TEXCOORD4 = 12,
- NVS_FR_TEXCOORD5 = 13,
- NVS_FR_TEXCOORD6 = 14,
- NVS_FR_TEXCOORD7 = 15,
- NVS_FR_BFC0 = 16,
- NVS_FR_BFC1 = 17,
- NVS_FR_POINTSZ = 18,
- NVS_FR_FRAGDATA0 = 19,
- NVS_FR_FRAGDATA1 = 20,
- NVS_FR_FRAGDATA2 = 21,
- NVS_FR_FRAGDATA3 = 22,
- NVS_FR_CLIP0 = 23,
- NVS_FR_CLIP1 = 24,
- NVS_FR_CLIP2 = 25,
- NVS_FR_CLIP3 = 26,
- NVS_FR_CLIP4 = 27,
- NVS_FR_CLIP5 = 28,
- NVS_FR_CLIP6 = 29,
- NVS_FR_FACING = 30,
- NVS_FR_UNKNOWN
-} nvsFixedReg;
-
-typedef enum {
- NVS_COND_FL, NVS_COND_LT, NVS_COND_EQ, NVS_COND_LE, NVS_COND_GT,
- NVS_COND_NE, NVS_COND_GE, NVS_COND_TR, NVS_COND_UN,
- NVS_COND_UNKNOWN
-} nvsCond;
-
-typedef struct {
- nvsRegFile file;
- unsigned int index;
-
- unsigned int indexed;
- unsigned int addr_reg;
- nvsSwzComp addr_comp;
-
- nvsSwzComp swizzle[4];
- int negate;
- int abs;
-} nvsRegister;
-
-static const nvsRegister nvr_unused = {
- .file = NVS_FILE_ATTRIB,
- .index = 0,
- .indexed = 0,
- .addr_reg = 0,
- .addr_comp = NVS_SWZ_X,
- .swizzle = {NVS_SWZ_X, NVS_SWZ_Y, NVS_SWZ_Z, NVS_SWZ_W},
- .negate = 0,
- .abs = 0,
-};
-
-typedef enum {
- NVS_TEX_TARGET_1D,
- NVS_TEX_TARGET_2D,
- NVS_TEX_TARGET_3D,
- NVS_TEX_TARGET_CUBE,
- NVS_TEX_TARGET_RECT,
- NVS_TEX_TARGET_UNKNOWN = 0
-} nvsTexTarget;
-
-typedef enum {
- NVS_SCALE_1X = 0,
- NVS_SCALE_2X = 1,
- NVS_SCALE_4X = 2,
- NVS_SCALE_8X = 3,
- NVS_SCALE_INV_2X = 5,
- NVS_SCALE_INV_4X = 6,
- NVS_SCALE_INV_8X = 7,
-} nvsScale;
-
-/* Arith/TEX instructions */
-typedef struct nvs_instruction {
- nvsFragmentHeader header;
-
- nvsOpcode op;
- unsigned int saturate;
-
- nvsRegister dest;
- unsigned int mask;
- nvsScale dest_scale;
-
- nvsRegister src[3];
-
- unsigned int tex_unit;
- nvsTexTarget tex_target;
-
- nvsCond cond;
- nvsSwzComp cond_swizzle[4];
- int cond_reg;
- int cond_test;
- int cond_update;
-} nvsInstruction;
-
-/* BRA, CAL, IF */
-typedef struct nvs_branch {
- nvsFragmentHeader header;
-
- nvsOpcode op;
-
- nvsCond cond;
- nvsSwzComp cond_swizzle[4];
- int cond_test;
-
- nvsFragmentHeader *target_head;
- nvsFragmentHeader *target_tail;
- nvsFragmentHeader *else_head;
- nvsFragmentHeader *else_tail;
-} nvsBranch;
-
-/* LOOP+ENDLOOP */
-typedef struct {
- nvsFragmentHeader header;
-
- int count;
- int initial;
- int increment;
-
- nvsFragmentHeader *insn_head;
- nvsFragmentHeader *insn_tail;
-} nvsLoop;
-
-/* label+following instructions */
-typedef struct nvs_subroutine {
- nvsFragmentHeader header;
-
- char * label;
- nvsFragmentHeader *insn_head;
- nvsFragmentHeader *insn_tail;
-} nvsSubroutine;
-
-#define SMASK_X (1<<0)
-#define SMASK_Y (1<<1)
-#define SMASK_Z (1<<2)
-#define SMASK_W (1<<3)
-#define SMASK_ALL (SMASK_X|SMASK_Y|SMASK_Z|SMASK_W)
-
-#define SPOS_ADDRESS 3
-struct _op_xlat {
- unsigned int NV;
- nvsOpcode SOP;
- int srcpos[3];
-};
-#define MOD_OPCODE(t,hw,sop,s0,s1,s2) do { \
- t[hw].NV = hw; \
- t[hw].SOP = sop; \
- t[hw].srcpos[0] = s0; \
- t[hw].srcpos[1] = s1; \
- t[hw].srcpos[2] = s2; \
-} while(0)
-
-extern unsigned int NVVP_TX_VOP_COUNT;
-extern unsigned int NVVP_TX_NVS_OP_COUNT;
-extern struct _op_xlat NVVP_TX_VOP[];
-extern struct _op_xlat NVVP_TX_SOP[];
-
-extern unsigned int NVFP_TX_AOP_COUNT;
-extern unsigned int NVFP_TX_BOP_COUNT;
-extern struct _op_xlat NVFP_TX_AOP[];
-extern struct _op_xlat NVFP_TX_BOP[];
-
-extern void NV20VPTXSwizzle(int hwswz, nvsSwzComp *swz);
-extern nvsSwzComp NV20VP_TX_SWIZZLE[4];
-
-#define SCAP_SRC_ABS (1<<0)
-
-struct _nvsFunc {
- nvsCardPriv *card_priv;
-
- unsigned int MaxInst;
- unsigned int MaxAttrib;
- unsigned int MaxTemp;
- unsigned int MaxAddress;
- unsigned int MaxConst;
- unsigned int caps;
-
- unsigned int *inst;
- void (*UploadToHW) (GLcontext *, nouveauShader *);
- void (*UpdateConst) (GLcontext *, nouveauShader *, int);
-
- struct _op_xlat*(*GetOPTXRec) (nvsFunc *, int merged);
- struct _op_xlat*(*GetOPTXFromSOP) (nvsOpcode, int *id);
-
- void (*InitInstruction) (nvsFunc *);
- int (*SupportsOpcode) (nvsFunc *, nvsOpcode);
- int (*SupportsResultScale) (nvsFunc *, nvsScale);
- void (*SetOpcode) (nvsFunc *, unsigned int opcode,
- int slot);
- void (*SetCCUpdate) (nvsFunc *);
- void (*SetCondition) (nvsFunc *, int on, nvsCond, int reg,
- nvsSwzComp *swizzle);
- void (*SetResult) (nvsFunc *, nvsRegister *,
- unsigned int mask, int slot);
- void (*SetResultScale) (nvsFunc *, nvsScale);
- void (*SetSource) (nvsFunc *, nvsRegister *, int pos);
- void (*SetTexImageUnit) (nvsFunc *, int unit);
- void (*SetSaturate) (nvsFunc *);
- void (*SetLastInst) (nvsFunc *);
-
- void (*SetBranchTarget) (nvsFunc *, int addr);
- void (*SetBranchElse) (nvsFunc *, int addr);
- void (*SetBranchEnd) (nvsFunc *, int addr);
- void (*SetLoopParams) (nvsFunc *, int cnt, int init, int inc);
-
- int (*HasMergedInst) (nvsFunc *);
- int (*IsLastInst) (nvsFunc *);
- int (*GetOffsetNext) (nvsFunc *);
-
- int (*GetOpcodeSlot) (nvsFunc *, int merged);
- unsigned int (*GetOpcodeHW) (nvsFunc *, int slot);
- nvsOpcode (*GetOpcode) (nvsFunc *, int merged);
-
- nvsPrecision (*GetPrecision) (nvsFunc *);
- int (*GetSaturate) (nvsFunc *);
-
- nvsRegFile (*GetDestFile) (nvsFunc *, int merged);
- unsigned int (*GetDestID) (nvsFunc *, int merged);
- unsigned int (*GetDestMask) (nvsFunc *, int merged);
-
- unsigned int (*GetSourceHW) (nvsFunc *, int merged, int pos);
- nvsRegFile (*GetSourceFile) (nvsFunc *, int merged, int pos);
- int (*GetSourceID) (nvsFunc *, int merged, int pos);
- int (*GetTexImageUnit) (nvsFunc *);
- int (*GetSourceNegate) (nvsFunc *, int merged, int pos);
- int (*GetSourceAbs) (nvsFunc *, int merged, int pos);
- void (*GetSourceSwizzle) (nvsFunc *, int merged, int pos,
- nvsSwzComp *swz);
- int (*GetSourceIndexed) (nvsFunc *, int merged, int pos);
- void (*GetSourceConstVal) (nvsFunc *, int merged, int pos,
- float *val);
- int (*GetSourceScale) (nvsFunc *, int merged, int pos);
-
- int (*GetRelAddressRegID) (nvsFunc *);
- nvsSwzComp (*GetRelAddressSwizzle) (nvsFunc *);
-
- int (*SupportsConditional) (nvsFunc *);
- int (*GetConditionUpdate) (nvsFunc *);
- int (*GetConditionTest) (nvsFunc *);
- nvsCond (*GetCondition) (nvsFunc *);
- void (*GetCondRegSwizzle) (nvsFunc *, nvsSwzComp *swz);
- int (*GetCondRegID) (nvsFunc *);
- int (*GetBranch) (nvsFunc *);
- int (*GetBranchElse) (nvsFunc *);
- int (*GetBranchEnd) (nvsFunc *);
-
- int (*GetLoopCount) (nvsFunc *);
- int (*GetLoopInitial) (nvsFunc *);
- int (*GetLoopIncrement) (nvsFunc *);
-};
-
-static INLINE nvsRegister
-nvsNegate(nvsRegister reg)
-{
- reg.negate = !reg.negate;
- return reg;
-}
-
-static INLINE nvsRegister
-nvsAbs(nvsRegister reg)
-{
- reg.abs = 1;
- return reg;
-}
-
-static INLINE nvsRegister
-nvsSwizzle(nvsRegister reg, nvsSwzComp x, nvsSwzComp y,
- nvsSwzComp z, nvsSwzComp w)
-{
- nvsSwzComp sc[4] = { x, y, z, w };
- nvsSwzComp oc[4];
- int i;
-
- for (i=0;i<4;i++)
- oc[i] = reg.swizzle[i];
- for (i=0;i<4;i++)
- reg.swizzle[i] = oc[sc[i]];
- return reg;
-}
-
-#define nvsProgramError(nvs,fmt,args...) do { \
- fprintf(stderr, "nvsProgramError (%s): "fmt, __func__, ##args); \
- (nvs)->error = GL_TRUE; \
- (nvs)->translated = GL_FALSE; \
-} while(0)
-
-extern GLboolean nvsUpdateShader(GLcontext *ctx, nouveauShader *nvs);
-extern void nvsDisasmHWShader(nvsPtr);
-extern void nvsDumpFragmentList(nvsFragmentHeader *f, int lvl);
-extern nouveauShader *nvsBuildTextShader(GLcontext *ctx, GLenum target,
- const char *text);
-
-extern void NV20VPInitShaderFuncs(nvsFunc *);
-extern void NV30VPInitShaderFuncs(nvsFunc *);
-extern void NV40VPInitShaderFuncs(nvsFunc *);
-
-extern void NV30FPInitShaderFuncs(nvsFunc *);
-extern void NV40FPInitShaderFuncs(nvsFunc *);
-
-extern void nouveauShaderInitFuncs(GLcontext *ctx);
-
-extern GLboolean nouveau_shader_pass0(GLcontext *ctx, nouveauShader *nvs);
-extern GLboolean nouveau_shader_pass1(nvsPtr nvs);
-extern GLboolean nouveau_shader_pass2(nvsPtr nvs);
-
-#endif
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c b/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c
deleted file mode 100644
index 8c203cc664..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c
+++ /dev/null
@@ -1,1050 +0,0 @@
-/*
- * Copyright (C) 2006 Ben Skeggs.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-/*
- * Authors:
- * Ben Skeggs
- */
-
-#include "glheader.h"
-#include "macros.h"
-#include "enums.h"
-
-#include "shader/prog_instruction.h"
-#include "shader/prog_parameter.h"
-#include "shader/prog_statevars.h"
-#include "shader/programopt.h"
-
-#include "nouveau_context.h"
-#include "nouveau_shader.h"
-#include "nouveau_msg.h"
-
-static nvsFixedReg _tx_mesa_vp_dst_reg[VERT_RESULT_MAX] = {
- NVS_FR_POSITION, NVS_FR_COL0, NVS_FR_COL1, NVS_FR_FOGCOORD,
- NVS_FR_TEXCOORD0, NVS_FR_TEXCOORD1, NVS_FR_TEXCOORD2, NVS_FR_TEXCOORD3,
- NVS_FR_TEXCOORD4, NVS_FR_TEXCOORD5, NVS_FR_TEXCOORD6, NVS_FR_TEXCOORD7,
- NVS_FR_POINTSZ, NVS_FR_BFC0, NVS_FR_BFC1, NVS_FR_UNKNOWN /* EDGE */
-};
-
-static nvsFixedReg _tx_mesa_fp_dst_reg[FRAG_RESULT_MAX] = {
- NVS_FR_FRAGDATA0 /* COLR */, NVS_FR_FRAGDATA0 /* COLH */,
- NVS_FR_UNKNOWN /* DEPR */
-};
-
-static nvsFixedReg _tx_mesa_fp_src_reg[FRAG_ATTRIB_MAX] = {
- NVS_FR_POSITION, NVS_FR_COL0, NVS_FR_COL1, NVS_FR_FOGCOORD,
- NVS_FR_TEXCOORD0, NVS_FR_TEXCOORD1, NVS_FR_TEXCOORD2, NVS_FR_TEXCOORD3,
- NVS_FR_TEXCOORD4, NVS_FR_TEXCOORD5, NVS_FR_TEXCOORD6, NVS_FR_TEXCOORD7
-};
-
-static nvsSwzComp _tx_mesa_swizzle[4] = {
- NVS_SWZ_X, NVS_SWZ_Y, NVS_SWZ_Z, NVS_SWZ_W
-};
-
-static nvsOpcode _tx_mesa_opcode[] = {
- [OPCODE_ABS] = NVS_OP_ABS, [OPCODE_ADD] = NVS_OP_ADD,
- [OPCODE_ARA] = NVS_OP_ARA, [OPCODE_ARL] = NVS_OP_ARL,
- [OPCODE_ARL_NV] = NVS_OP_ARL, [OPCODE_ARR] = NVS_OP_ARR,
- [OPCODE_CMP] = NVS_OP_CMP, [OPCODE_COS] = NVS_OP_COS,
- [OPCODE_DDX] = NVS_OP_DDX, [OPCODE_DDY] = NVS_OP_DDY,
- [OPCODE_DP3] = NVS_OP_DP3, [OPCODE_DP4] = NVS_OP_DP4,
- [OPCODE_DPH] = NVS_OP_DPH, [OPCODE_DST] = NVS_OP_DST,
- [OPCODE_EX2] = NVS_OP_EX2, [OPCODE_EXP] = NVS_OP_EXP,
- [OPCODE_FLR] = NVS_OP_FLR, [OPCODE_FRC] = NVS_OP_FRC,
- [OPCODE_KIL] = NVS_OP_EMUL, [OPCODE_KIL_NV] = NVS_OP_KIL,
- [OPCODE_LG2] = NVS_OP_LG2, [OPCODE_LIT] = NVS_OP_LIT,
- [OPCODE_LOG] = NVS_OP_LOG,
- [OPCODE_LRP] = NVS_OP_LRP,
- [OPCODE_MAD] = NVS_OP_MAD, [OPCODE_MAX] = NVS_OP_MAX,
- [OPCODE_MIN] = NVS_OP_MIN, [OPCODE_MOV] = NVS_OP_MOV,
- [OPCODE_MUL] = NVS_OP_MUL,
- [OPCODE_PK2H] = NVS_OP_PK2H, [OPCODE_PK2US] = NVS_OP_PK2US,
- [OPCODE_PK4B] = NVS_OP_PK4B, [OPCODE_PK4UB] = NVS_OP_PK4UB,
- [OPCODE_POW] = NVS_OP_POW, [OPCODE_POPA] = NVS_OP_POPA,
- [OPCODE_PUSHA] = NVS_OP_PUSHA,
- [OPCODE_RCC] = NVS_OP_RCC, [OPCODE_RCP] = NVS_OP_RCP,
- [OPCODE_RFL] = NVS_OP_RFL, [OPCODE_RSQ] = NVS_OP_RSQ,
- [OPCODE_SCS] = NVS_OP_SCS, [OPCODE_SEQ] = NVS_OP_SEQ,
- [OPCODE_SFL] = NVS_OP_SFL, [OPCODE_SGE] = NVS_OP_SGE,
- [OPCODE_SGT] = NVS_OP_SGT, [OPCODE_SIN] = NVS_OP_SIN,
- [OPCODE_SLE] = NVS_OP_SLE, [OPCODE_SLT] = NVS_OP_SLT,
- [OPCODE_SNE] = NVS_OP_SNE, [OPCODE_SSG] = NVS_OP_SSG,
- [OPCODE_STR] = NVS_OP_STR, [OPCODE_SUB] = NVS_OP_SUB,
- [OPCODE_SWZ] = NVS_OP_MOV,
- [OPCODE_TEX] = NVS_OP_TEX, [OPCODE_TXB] = NVS_OP_TXB,
- [OPCODE_TXD] = NVS_OP_TXD,
- [OPCODE_TXL] = NVS_OP_TXL, [OPCODE_TXP] = NVS_OP_TXP,
- [OPCODE_TXP_NV] = NVS_OP_TXP,
- [OPCODE_UP2H] = NVS_OP_UP2H, [OPCODE_UP2US] = NVS_OP_UP2US,
- [OPCODE_UP4B] = NVS_OP_UP4B, [OPCODE_UP4UB] = NVS_OP_UP4UB,
- [OPCODE_X2D] = NVS_OP_X2D,
- [OPCODE_XPD] = NVS_OP_XPD
-};
-
-static nvsCond _tx_mesa_condmask[] = {
- NVS_COND_TR, /* workaround mesa not filling a valid value */
- NVS_COND_GT, NVS_COND_LT, NVS_COND_UN, NVS_COND_GE,
- NVS_COND_LE, NVS_COND_NE, NVS_COND_NE, NVS_COND_TR, NVS_COND_FL
-};
-
-struct pass0_rec {
- int nvs_ipos;
- int next_temp;
-
- int mesa_const_base;
- int mesa_const_last;
-
- int swzconst_done;
- int swzconst_id;
- nvsRegister const_half;
-};
-
-#define X NVS_SWZ_X
-#define Y NVS_SWZ_Y
-#define Z NVS_SWZ_Z
-#define W NVS_SWZ_W
-
-#define FILL_CONDITION_FLAGS(fragment) do { \
- (fragment)->cond = \
- pass0_make_condmask(inst->DstReg.CondMask); \
- if ((fragment)->cond != NVS_COND_TR) \
- (fragment)->cond_test = 1; \
- (fragment)->cond_reg = inst->CondDst; \
- pass0_make_swizzle((fragment)->cond_swizzle, inst->DstReg.CondSwizzle);\
-} while(0)
-
-#define ARITH(op,dest,mask,sat,s0,s1,s2) do { \
- nvsinst = pass0_emit(nvs, parent, fpos, (op), \
- (dest), (mask), (sat), (s0), (s1), (s2));\
- FILL_CONDITION_FLAGS(nvsinst); \
-} while(0)
-
-#define ARITHu(op,dest,mask,sat,s0,s1,s2) do { \
- nvsinst = pass0_emit(nvs, parent, fpos, (op), \
- (dest), (mask), (sat), (s0), (s1), (s2));\
-} while(0)
-
-static void
-pass0_append_fragment(nvsFragmentHeader *parent,
- nvsFragmentHeader *fragment,
- int pos)
-{
- nvsFragmentHeader **head, **tail;
- assert(parent && fragment);
-
- switch (parent->type) {
- case NVS_BRANCH:
- if (pos == 0) {
- head = &((nvsBranch *)parent)->target_head;
- tail = &((nvsBranch *)parent)->target_tail;
- } else {
- head = &((nvsBranch *)parent)->else_head;
- tail = &((nvsBranch *)parent)->else_tail;
- }
- break;
- case NVS_LOOP:
- head = &((nvsLoop *)parent)->insn_head;
- tail = &((nvsLoop *)parent)->insn_tail;
- break;
- case NVS_SUBROUTINE:
- head = &((nvsSubroutine *)parent)->insn_head;
- tail = &((nvsSubroutine *)parent)->insn_tail;
- break;
- default:
- assert(0);
- break;
- }
-
- fragment->parent = parent;
- fragment->prev = *tail;
- fragment->next = NULL;
- if (!(*head))
- *head = fragment;
- else
- (*tail)->next = fragment;
- *tail = fragment;
-
-}
-
-static nvsSubroutine *
-pass0_create_subroutine(nouveauShader *nvs, const char *label)
-{
- nvsSubroutine *sub;
-
- sub = CALLOC_STRUCT(nvs_subroutine);
- if (sub) {
- sub->header.type = NVS_SUBROUTINE;
- sub->label = strdup(label);
- if (!nvs->program_tree)
- nvs->program_tree = &sub->header;
- else
- pass0_append_fragment(nvs->program_tree,
- &sub->header, 0);
- }
-
- return sub;
-}
-
-static void
-pass0_make_reg(nouveauShader *nvs, nvsRegister *reg,
- nvsRegFile file, unsigned int index)
-{
- struct pass0_rec *rec = nvs->pass_rec;
-
- /* defaults */
- *reg = nvr_unused;
- /* -1 == quick-and-dirty temp alloc */
- if (file == NVS_FILE_TEMP && index == -1) {
- index = rec->next_temp++;
- assert(index < NVS_MAX_TEMPS);
- }
- reg->file = file;
- reg->index = index;
-}
-
-static void
-pass0_make_swizzle(nvsSwzComp *swz, unsigned int mesa)
-{
- int i;
-
- for (i=0;i<4;i++)
- swz[i] = _tx_mesa_swizzle[GET_SWZ(mesa, i)];
-}
-
-static nvsOpcode
-pass0_make_opcode(enum prog_opcode op)
-{
- if (op > MAX_OPCODE)
- return NVS_OP_UNKNOWN;
- return _tx_mesa_opcode[op];
-}
-
-static nvsCond
-pass0_make_condmask(GLuint mesa)
-{
- if (mesa > COND_FL)
- return NVS_COND_UNKNOWN;
- return _tx_mesa_condmask[mesa];
-}
-
-static unsigned int
-pass0_make_mask(GLuint mesa_mask)
-{
- unsigned int mask = 0;
-
- if (mesa_mask & WRITEMASK_X) mask |= SMASK_X;
- if (mesa_mask & WRITEMASK_Y) mask |= SMASK_Y;
- if (mesa_mask & WRITEMASK_Z) mask |= SMASK_Z;
- if (mesa_mask & WRITEMASK_W) mask |= SMASK_W;
-
- return mask;
-}
-
-static GLboolean
-pass0_opcode_is_tex(enum prog_opcode op)
-{
- switch (op) {
- case OPCODE_TEX:
- case OPCODE_TXB:
- case OPCODE_TXD:
- case OPCODE_TXL:
- case OPCODE_TXP:
- return GL_TRUE;
- default:
- break;
- }
-
- return GL_FALSE;
-}
-
-static nvsTexTarget
-pass0_make_tex_target(GLuint mesa)
-{
- switch (mesa) {
- case TEXTURE_1D_INDEX: return NVS_TEX_TARGET_1D;
- case TEXTURE_2D_INDEX: return NVS_TEX_TARGET_2D;
- case TEXTURE_3D_INDEX: return NVS_TEX_TARGET_3D;
- case TEXTURE_CUBE_INDEX: return NVS_TEX_TARGET_CUBE;
- case TEXTURE_RECT_INDEX: return NVS_TEX_TARGET_RECT;
- default:
- return NVS_TEX_TARGET_UNKNOWN;
- }
-}
-
-static void
-pass0_make_dst_reg(nvsPtr nvs, nvsRegister *reg,
- struct prog_dst_register *dst)
-{
- struct gl_program *mesa = (struct gl_program*)&nvs->mesa.vp;
- nvsFixedReg sfr;
-
- switch (dst->File) {
- case PROGRAM_OUTPUT:
- if (mesa->Target == GL_VERTEX_PROGRAM_ARB) {
- sfr = (dst->Index < VERT_RESULT_MAX) ?
- _tx_mesa_vp_dst_reg[dst->Index] :
- NVS_FR_UNKNOWN;
- } else {
- sfr = (dst->Index < FRAG_RESULT_MAX) ?
- _tx_mesa_fp_dst_reg[dst->Index] :
- NVS_FR_UNKNOWN;
- }
- pass0_make_reg(nvs, reg, NVS_FILE_RESULT, sfr);
- break;
- case PROGRAM_TEMPORARY:
- pass0_make_reg(nvs, reg, NVS_FILE_TEMP, dst->Index);
- break;
- case PROGRAM_ADDRESS:
- pass0_make_reg(nvs, reg, NVS_FILE_ADDRESS, dst->Index);
- break;
- default:
- fprintf(stderr, "Unknown dest file %d\n", dst->File);
- assert(0);
- }
-}
-
-static void
-pass0_make_src_reg(nvsPtr nvs, nvsRegister *reg, struct prog_src_register *src)
-{
- struct pass0_rec *rec = nvs->pass_rec;
- struct gl_program *mesa = (struct gl_program *)&nvs->mesa.vp.Base;
- int i;
-
- *reg = nvr_unused;
-
- switch (src->File) {
- case PROGRAM_INPUT:
- reg->file = NVS_FILE_ATTRIB;
- if (mesa->Target == GL_VERTEX_PROGRAM_ARB) {
- for (i=0; ivp_attrib_map[i] == src->Index) {
- reg->index = i;
- break;
- }
- }
- if (i==NVS_MAX_ATTRIBS)
- reg->index = NVS_FR_UNKNOWN;
- } else {
- reg->index = (src->Index < FRAG_ATTRIB_MAX) ?
- _tx_mesa_fp_src_reg[src->Index] :
- NVS_FR_UNKNOWN;
- }
- break;
- case PROGRAM_STATE_VAR:
- case PROGRAM_NAMED_PARAM:
- case PROGRAM_CONSTANT:
- reg->file = NVS_FILE_CONST;
- reg->index = src->Index + rec->mesa_const_base;
- reg->indexed = src->RelAddr;
- if (reg->indexed) {
- reg->addr_reg = 0;
- reg->addr_comp = NVS_SWZ_X;
- }
- break;
- case PROGRAM_TEMPORARY:
- reg->file = NVS_FILE_TEMP;
- reg->index = src->Index;
- break;
- default:
- fprintf(stderr, "Unknown source type %d\n", src->File);
- assert(0);
- }
-
- /* per-component negate handled elsewhere */
- reg->negate = src->NegateBase != 0;
- reg->abs = src->Abs;
- pass0_make_swizzle(reg->swizzle, src->Swizzle);
-}
-
-static nvsInstruction *
-pass0_emit(nouveauShader *nvs, nvsFragmentHeader *parent, int fpos,
- nvsOpcode op, nvsRegister dst,
- unsigned int mask, int saturate,
- nvsRegister src0, nvsRegister src1, nvsRegister src2)
-{
- nvsInstruction *sif;
-
- sif = CALLOC_STRUCT(nvs_instruction);
- if (!sif)
- return NULL;
-
- /* Seems mesa doesn't explicitly 0 this.. */
- if (nvs->mesa.vp.Base.Target == GL_VERTEX_PROGRAM_ARB)
- saturate = 0;
-
- sif->op = op;
- sif->saturate = saturate;
- sif->dest = dst;
- sif->mask = mask;
- sif->dest_scale = NVS_SCALE_1X;
- sif->src[0] = src0;
- sif->src[1] = src1;
- sif->src[2] = src2;
- sif->cond = COND_TR;
- sif->cond_reg = 0;
- sif->cond_test = 0;
- sif->cond_update= 0;
- pass0_make_swizzle(sif->cond_swizzle, SWIZZLE_NOOP);
- pass0_append_fragment(parent, &sif->header, fpos);
-
- return sif;
-}
-
-static void
-pass0_fixup_swizzle(nvsPtr nvs, nvsFragmentHeader *parent, int fpos,
- struct prog_src_register *src,
- unsigned int sm1,
- unsigned int sm2)
-{
- static const float sc[4] = { 1.0, 0.0, -1.0, 0.0 };
- struct pass0_rec *rec = nvs->pass_rec;
- int fixup_1, fixup_2;
- nvsInstruction *nvsinst;
- nvsRegister sr, dr = nvr_unused;
- nvsRegister sm1const, sm2const;
-
- if (!rec->swzconst_done) {
- struct gl_program *prog = &nvs->mesa.vp.Base;
- GLuint swizzle;
- rec->swzconst_id = _mesa_add_unnamed_constant(prog->Parameters,
- sc, 4, &swizzle);
- /* XXX what about swizzle? */
- rec->swzconst_done = 1;
- COPY_4V(nvs->params[rec->swzconst_id].val, sc);
- }
-
- fixup_1 = (sm1 != MAKE_SWIZZLE4(0,0,0,0) &&
- sm2 != MAKE_SWIZZLE4(2,2,2,2));
- fixup_2 = (sm2 != MAKE_SWIZZLE4(2,2,2,2));
-
- if (src->File != PROGRAM_TEMPORARY && src->File != PROGRAM_INPUT) {
- /* We can't use more than one const in an instruction,
- * so move the const into a temp, and swizzle from there.
- *
- * TODO: should just emit the swizzled const, instead of
- * swizzling it in the shader.. would need to reswizzle
- * any state params when they change however..
- */
- pass0_make_reg(nvs, &dr, NVS_FILE_TEMP, -1);
- pass0_make_src_reg(nvs, &sr, src);
- ARITHu(NVS_OP_MOV, dr, SMASK_ALL, 0,
- sr, nvr_unused, nvr_unused);
- pass0_make_reg(nvs, &sr, NVS_FILE_TEMP, dr.index);
- } else {
- if (fixup_1)
- src->NegateBase = 0;
- pass0_make_src_reg(nvs, &sr, src);
- pass0_make_reg(nvs, &dr, NVS_FILE_TEMP, -1);
- }
-
- pass0_make_reg(nvs, &sm1const, NVS_FILE_CONST, rec->swzconst_id);
- pass0_make_swizzle(sm1const.swizzle, sm1);
- if (fixup_1 && fixup_2) {
- /* Any combination with SWIZZLE_ONE */
- pass0_make_reg(nvs, &sm2const,
- NVS_FILE_CONST, rec->swzconst_id);
- pass0_make_swizzle(sm2const.swizzle, sm2);
- ARITHu(NVS_OP_MAD, dr, SMASK_ALL, 0, sr, sm1const, sm2const);
- } else {
- /* SWIZZLE_ZERO || arbitrary negate */
- ARITHu(NVS_OP_MUL, dr, SMASK_ALL, 0, sr, sm1const, nvr_unused);
- }
-
- src->File = PROGRAM_TEMPORARY;
- src->Index = dr.index;
- src->Swizzle = SWIZZLE_NOOP;
-}
-
-#define SET_SWZ(fs, cp, c) fs = (fs & ~(0x7<<(cp*3))) | (c<<(cp*3))
-static void
-pass0_check_sources(nvsPtr nvs, nvsFragmentHeader *parent, int fpos,
- struct prog_instruction *inst)
-{
- unsigned int insrc = -1, constsrc = -1;
- int i;
-
- for (i=0;i<_mesa_num_inst_src_regs(inst->Opcode);i++) {
- struct prog_src_register *src = &inst->SrcReg[i];
- unsigned int sm_1 = 0, sm_2 = 0;
- nvsRegister sr, dr;
- int do_mov = 0, c;
-
- /* Build up swizzle masks as if we were going to use
- * "MAD new, src, const1, const2" to support arbitrary negation
- * and SWIZZLE_ZERO/SWIZZLE_ONE.
- */
- for (c=0;c<4;c++) {
- if (GET_SWZ(src->Swizzle, c) == SWIZZLE_ZERO) {
- SET_SWZ(sm_1, c, SWIZZLE_Y); /* 0.0 */
- SET_SWZ(sm_2, c, SWIZZLE_Y);
- SET_SWZ(src->Swizzle, c, SWIZZLE_X);
- } else if (GET_SWZ(src->Swizzle, c) == SWIZZLE_ONE) {
- SET_SWZ(sm_1, c, SWIZZLE_Y);
- if (src->NegateBase & (1<Swizzle, c, SWIZZLE_X);
- } else {
- if (src->NegateBase & (1<File) {
- case PROGRAM_INPUT:
- if (insrc != -1 && insrc != src->Index)
- do_mov = 1;
- else insrc = src->Index;
- break;
- case PROGRAM_STATE_VAR:
- if (constsrc != -1 && constsrc != src->Index)
- do_mov = 1;
- else constsrc = src->Index;
- break;
- default:
- break;
- }
-
- /* Emit any extra ATTRIB/CONST to a temp, and modify the Mesa
- * instruction to point at the temp.
- */
- if (do_mov) {
- pass0_make_src_reg(nvs, &sr, src);
- pass0_make_reg(nvs, &dr, NVS_FILE_TEMP, -1);
- pass0_emit(nvs, parent, fpos, NVS_OP_MOV,
- dr, SMASK_ALL, 0,
- sr, nvr_unused, nvr_unused);
-
- src->File = PROGRAM_TEMPORARY;
- src->Index = dr.index;
- src->Swizzle= SWIZZLE_NOOP;
- }
- }
-}
-
-static GLboolean
-pass0_emulate_instruction(nouveauShader *nvs,
- nvsFragmentHeader *parent, int fpos,
- struct prog_instruction *inst)
-{
- nvsFunc *shader = nvs->func;
- nvsRegister src[3], dest, temp;
- nvsInstruction *nvsinst;
- unsigned int mask = pass0_make_mask(inst->DstReg.WriteMask);
- int i, sat;
-
- sat = (inst->SaturateMode == SATURATE_ZERO_ONE);
-
- /* Build all the "real" regs for the instruction */
- for (i=0; i<_mesa_num_inst_src_regs(inst->Opcode); i++)
- pass0_make_src_reg(nvs, &src[i], &inst->SrcReg[i]);
- if (inst->Opcode != OPCODE_KIL)
- pass0_make_dst_reg(nvs, &dest, &inst->DstReg);
-
- switch (inst->Opcode) {
- case OPCODE_ABS:
- if (shader->caps & SCAP_SRC_ABS)
- ARITH(NVS_OP_MOV, dest, mask, sat,
- nvsAbs(src[0]), nvr_unused, nvr_unused);
- else
- ARITH(NVS_OP_MAX, dest, mask, sat,
- src[0], nvsNegate(src[0]), nvr_unused);
- break;
- case OPCODE_CMP:
- /*XXX: this will clobber CC0... */
- ARITH (NVS_OP_MOV, dest, mask, sat,
- src[2], nvr_unused, nvr_unused);
- pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1);
- ARITHu(NVS_OP_MOV, temp, SMASK_ALL, 0,
- src[0], nvr_unused, nvr_unused);
- nvsinst->cond_update = 1;
- nvsinst->cond_reg = 0;
- ARITH (NVS_OP_MOV, dest, mask, sat,
- src[1], nvr_unused, nvr_unused);
- nvsinst->cond = COND_LT;
- nvsinst->cond_reg = 0;
- nvsinst->cond_test = 1;
- break;
- case OPCODE_DPH:
- pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1);
- ARITHu(NVS_OP_DP3, temp, SMASK_X, 0,
- src[0], src[1], nvr_unused);
- ARITH (NVS_OP_ADD, dest, mask, sat,
- nvsSwizzle(temp, X, X, X, X),
- nvsSwizzle(src[1], W, W, W, W),
- nvr_unused);
- break;
- case OPCODE_KIL:
- /* This is only in ARB shaders, so we don't have to worry
- * about clobbering a CC reg as they aren't supported anyway.
- *XXX: might have to worry with GLSL however...
- */
- /* MOVC0 temp, src */
- pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1);
- ARITHu(NVS_OP_MOV, temp, SMASK_ALL, 0,
- src[0], nvr_unused, nvr_unused);
- nvsinst->cond_update = 1;
- nvsinst->cond_reg = 0;
- /* KIL_NV (LT0.xyzw) temp */
- ARITHu(NVS_OP_KIL, nvr_unused, 0, 0,
- nvr_unused, nvr_unused, nvr_unused);
- nvsinst->cond = COND_LT;
- nvsinst->cond_reg = 0;
- nvsinst->cond_test = 1;
- pass0_make_swizzle(nvsinst->cond_swizzle, SWIZZLE_NOOP);
- break;
- case OPCODE_LRP:
- pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1);
- ARITHu(NVS_OP_MAD, temp, mask, 0,
- nvsNegate(src[0]), src[2], src[2]);
- ARITH (NVS_OP_MAD, dest, mask, sat, src[0], src[1], temp);
- break;
- case OPCODE_POW:
- if (shader->SupportsOpcode(shader, NVS_OP_LG2) &&
- shader->SupportsOpcode(shader, NVS_OP_EX2)) {
- pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1);
- /* LG2 temp.x, src0.c */
- ARITHu(NVS_OP_LG2, temp, SMASK_X, 0,
- nvsSwizzle(src[0], X, X, X, X),
- nvr_unused, nvr_unused);
- /* MUL temp.x, temp.x, src1.c */
- ARITHu(NVS_OP_MUL, temp, SMASK_X, 0,
- nvsSwizzle(temp, X, X, X, X),
- nvsSwizzle(src[1], X, X, X, X),
- nvr_unused);
- /* EX2 dest, temp.x */
- ARITH (NVS_OP_EX2, dest, mask, sat,
- nvsSwizzle(temp, X, X, X, X),
- nvr_unused, nvr_unused);
- } else {
- /* can we use EXP/LOG instead of EX2/LG2?? */
- fprintf(stderr, "Implement POW for NV20 vtxprog!\n");
- return GL_FALSE;
- }
- break;
- case OPCODE_RSQ:
- pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1);
- ARITHu(NVS_OP_LG2, temp, SMASK_X, 0,
- nvsAbs(nvsSwizzle(src[0], X, X, X, X)),
- nvr_unused, nvr_unused);
- nvsinst->dest_scale = NVS_SCALE_INV_2X;
- ARITH (NVS_OP_EX2, dest, mask, sat,
- nvsNegate(nvsSwizzle(temp, X, X, X, X)),
- nvr_unused, nvr_unused);
- break;
- case OPCODE_SCS:
- if (mask & SMASK_X)
- ARITH(NVS_OP_COS, dest, SMASK_X, sat,
- nvsSwizzle(src[0], X, X, X, X),
- nvr_unused, nvr_unused);
- if (mask & SMASK_Y)
- ARITH(NVS_OP_SIN, dest, SMASK_Y, sat,
- nvsSwizzle(src[0], X, X, X, X),
- nvr_unused, nvr_unused);
- break;
- case OPCODE_SUB:
- ARITH(NVS_OP_ADD, dest, mask, sat,
- src[0], nvsNegate(src[1]), nvr_unused);
- break;
- case OPCODE_XPD:
- pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1);
- ARITHu(NVS_OP_MUL, temp, SMASK_ALL, 0,
- nvsSwizzle(src[0], Z, X, Y, Y),
- nvsSwizzle(src[1], Y, Z, X, X),
- nvr_unused);
- ARITH (NVS_OP_MAD, dest, (mask & ~SMASK_W), sat,
- nvsSwizzle(src[0], Y, Z, X, X),
- nvsSwizzle(src[1], Z, X, Y, Y),
- nvsNegate(temp));
- break;
- default:
- WARN_ONCE("hw doesn't support opcode \"%s\","
- "and no emulation found\n",
- _mesa_opcode_string(inst->Opcode));
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-static GLboolean
-pass0_translate_arith(nouveauShader *nvs, struct gl_program *prog,
- int ipos, int fpos,
- nvsFragmentHeader *parent)
-{
- struct prog_instruction *inst = &prog->Instructions[ipos];
- nvsFunc *shader = nvs->func;
- nvsInstruction *nvsinst;
- GLboolean ret;
-
- /* Deal with multiple ATTRIB/PARAM in a single instruction */
- pass0_check_sources(nvs, parent, fpos, inst);
-
- /* Now it's safe to do the prog_instruction->nvsInstruction
- * conversion
- */
- if (shader->SupportsOpcode(shader,
- pass0_make_opcode(inst->Opcode))) {
- nvsRegister src[3], dest;
- int i;
-
- for (i=0; i<_mesa_num_inst_src_regs(inst->Opcode); i++)
- pass0_make_src_reg(nvs, &src[i], &inst->SrcReg[i]);
- pass0_make_dst_reg(nvs, &dest, &inst->DstReg);
-
- ARITH(pass0_make_opcode(inst->Opcode), dest,
- pass0_make_mask(inst->DstReg.WriteMask),
- (inst->SaturateMode != SATURATE_OFF),
- src[0], src[1], src[2]);
- nvsinst->tex_unit = inst->TexSrcUnit;
- if (pass0_opcode_is_tex(inst->Opcode))
- nvsinst->tex_target =
- pass0_make_tex_target(inst->TexSrcTarget);
- else
- nvsinst->tex_target = NVS_TEX_TARGET_UNKNOWN;
-
- ret = GL_TRUE;
- } else
- ret = pass0_emulate_instruction(nvs, parent, fpos, inst);
-
- return ret;
-}
-
-static GLboolean
-pass0_translate_instructions(nouveauShader *nvs, int ipos, int fpos,
- nvsFragmentHeader *parent)
-{
- struct gl_program *prog = (struct gl_program *)&nvs->mesa.vp;
-
- while (1) {
- struct prog_instruction *inst = &prog->Instructions[ipos];
-
- switch (inst->Opcode) {
- case OPCODE_END:
- return GL_TRUE;
- case OPCODE_BRA:
- case OPCODE_CAL:
- case OPCODE_RET:
- //case OPCODE_LOOP:
- //case OPCODE_ENDLOOP:
- //case OPCODE_IF:
- //case OPCODE_ELSE:
- //case OPCODE_ENDIF:
- WARN_ONCE("branch ops unimplemented\n");
- return GL_FALSE;
- break;
- default:
- if (!pass0_translate_arith(nvs, prog,
- ipos, fpos, parent))
- return GL_FALSE;
- break;
- }
-
- ipos++;
- }
-
- return GL_TRUE;
-}
-
-static void
-pass0_build_attrib_map(nouveauShader *nvs, struct gl_vertex_program *vp)
-{
- GLuint inputs_read = vp->Base.InputsRead;
- GLuint input_alloc = ~0xFFFF;
- int i;
-
- for (i=0; ivp_attrib_map[i] = -1;
-
- while (inputs_read) {
- int in = ffs(inputs_read) - 1;
- int hw;
- inputs_read &= ~(1<IsNVProgram) {
- /* NVvp: must alias */
- if (in >= VERT_ATTRIB_GENERIC0)
- hw = in - VERT_ATTRIB_GENERIC0;
- else
- hw = in;
- } else {
- /* ARBvp: may alias (but we won't)
- * GL2.0: must not alias
- */
- if (in >= VERT_ATTRIB_GENERIC0)
- hw = ffs(~input_alloc) - 1;
- else
- hw = in;
- input_alloc |= (1<vp_attrib_map[hw] = in;
- }
-
- if (NOUVEAU_DEBUG & DEBUG_SHADERS) {
- printf("vtxprog attrib map:\n");
- for (i=0; ivp_attrib_map[i]);
- }
- }
-}
-
-static void
-pass0_vp_insert_ff_clip_planes(GLcontext *ctx, nouveauShader *nvs)
-{
- struct gl_program *prog = &nvs->mesa.vp.Base;
- nvsFragmentHeader *parent = nvs->program_tree;
- nvsInstruction *nvsinst;
- GLuint fpos = 0;
- nvsRegister opos, epos, eqn, mv[4];
- gl_state_index tokens[STATE_LENGTH]
- = { STATE_MODELVIEW_MATRIX, 0, 0, 0, 0 };
- GLint id;
- int i;
-
- /* modelview transform */
- pass0_make_reg(nvs, &opos, NVS_FILE_ATTRIB, NVS_FR_POSITION);
- pass0_make_reg(nvs, &epos, NVS_FILE_TEMP , -1);
- for (i=0; i<4; i++) {
- tokens[2] = tokens[3] = i;
- id = _mesa_add_state_reference(prog->Parameters, tokens);
- pass0_make_reg(nvs, &mv[i], NVS_FILE_CONST, id);
- }
- ARITHu(NVS_OP_DP4, epos, SMASK_X, 0, opos, mv[0], nvr_unused);
- ARITHu(NVS_OP_DP4, epos, SMASK_Y, 0, opos, mv[1], nvr_unused);
- ARITHu(NVS_OP_DP4, epos, SMASK_Z, 0, opos, mv[2], nvr_unused);
- ARITHu(NVS_OP_DP4, epos, SMASK_W, 0, opos, mv[3], nvr_unused);
-
- /* Emit code to emulate fixed-function glClipPlane */
- for (i=0; i<6; i++) {
- GLuint clipmask = SMASK_X;
- nvsRegister clip;
-
- if (!(ctx->Transform.ClipPlanesEnabled & (1<Parameters, tokens);
- pass0_make_reg(nvs, &eqn , NVS_FILE_CONST , id);
- pass0_make_reg(nvs, &clip, NVS_FILE_RESULT, NVS_FR_CLIP0 + i);
-
- /*XXX: something else needs to take care of modifying the
- * instructions to write to the correct hw clip register.
- */
- switch (i) {
- case 0: case 3: clipmask = SMASK_Y; break;
- case 1: case 4: clipmask = SMASK_Z; break;
- case 2: case 5: clipmask = SMASK_W; break;
- }
-
- /* Emit transform */
- ARITHu(NVS_OP_DP4, clip, clipmask, 0, epos, eqn, nvr_unused);
- }
-}
-
-static void
-pass0_rebase_mesa_consts(nouveauShader *nvs)
-{
- struct pass0_rec *rec = nvs->pass_rec;
- struct gl_program *prog = &nvs->mesa.vp.Base;
- struct prog_instruction *inst = prog->Instructions;
- int i;
-
- /*XXX: not a good idea, params->hw_index is malloc'd */
- memset(nvs->params, 0x00, sizeof(nvs->params));
-
- /* When doing relative addressing on constants, the hardware needs us
- * to fill the "const id" field with a positive value. Determine the
- * most negative index that is used so that all accesses to a
- * mesa-provided constant can be rebased to a positive index.
- */
- while (inst->Opcode != OPCODE_END) {
- for (i=0; i<_mesa_num_inst_src_regs(inst->Opcode); i++) {
- struct prog_src_register *src = &inst->SrcReg[i];
-
- switch (src->File) {
- case PROGRAM_STATE_VAR:
- case PROGRAM_CONSTANT:
- case PROGRAM_NAMED_PARAM:
- if (src->RelAddr && src->Index < 0) {
- int base = src->Index * -1;
- if (rec->mesa_const_base < base)
- rec->mesa_const_base = base;
- }
- break;
- default:
- break;
- }
- }
-
- inst++;
- }
-}
-
-static GLboolean
-pass0_resolve_mesa_consts(nouveauShader *nvs)
-{
- struct pass0_rec *rec = nvs->pass_rec;
- struct gl_program *prog = &nvs->mesa.vp.Base;
- struct gl_program_parameter_list *plist = prog->Parameters;
- int i;
-
- /* Init all const tracking/alloc info from the parameter list, rather
- * than doing it as we translate the program. Otherwise:
- * 1) we can't get at the correct constant info when relative
- * addressing is being used due to src->Index not pointing
- * at the exact const;
- * 2) as we add extra consts to the program, mesa will call realloc()
- * and we get invalid pointers to the const data.
- */
- rec->mesa_const_last = plist->NumParameters + rec->mesa_const_base;
- nvs->param_high = rec->mesa_const_last;
- for (i=0; iNumParameters; i++) {
- int hw = rec->mesa_const_base + i;
-
- if (hw > NVS_MAX_CONSTS) {
- nvsProgramError(nvs, "hw = %d > NVS_MAX_CONSTS!\n", hw);
- return GL_FALSE;
- }
-
- switch (plist->Parameters[i].Type) {
- case PROGRAM_NAMED_PARAM:
- case PROGRAM_STATE_VAR:
- nvs->params[hw].in_use = GL_TRUE;
- nvs->params[hw].source_val = plist->ParameterValues[i];
- COPY_4V(nvs->params[hw].val, plist->ParameterValues[i]);
- break;
- case PROGRAM_CONSTANT:
- nvs->params[hw].in_use = GL_TRUE;
- nvs->params[hw].source_val = NULL;
- COPY_4V(nvs->params[hw].val, plist->ParameterValues[i]);
- break;
- default:
- nvsProgramError(nvs, "hit bad type=%d on param %d\n",
- plist->Parameters[i].Type, i);
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
-}
-
-GLboolean
-nouveau_shader_pass0(GLcontext *ctx, nouveauShader *nvs)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- struct gl_program *prog = (struct gl_program*)nvs;
- struct gl_vertex_program *vp = (struct gl_vertex_program *)prog;
- struct gl_fragment_program *fp = (struct gl_fragment_program *)prog;
- struct pass0_rec *rec;
- int ret = GL_FALSE;
-
- NVSDBG("start: nvs=%p\n", nvs);
-
- /* Previously detected an error, and haven't recieved new program
- * string, so fail immediately.
- */
- if (nvs->error) {
- NVSDBG("failed previous compile attempt, not retrying\n");
- return GL_FALSE;
- }
-
- rec = CALLOC_STRUCT(pass0_rec);
- if (!rec)
- return GL_FALSE;
-
- rec->next_temp = prog->NumTemporaries;
- nvs->pass_rec = rec;
-
- nvs->program_tree = (nvsFragmentHeader*)
- pass0_create_subroutine(nvs, "program body");
- if (!nvs->program_tree) {
- FREE(rec);
- return GL_FALSE;
- }
-
- switch (prog->Target) {
- case GL_VERTEX_PROGRAM_ARB:
- nvs->func = &nmesa->VPfunc;
-
- if (vp->IsPositionInvariant)
- _mesa_insert_mvp_code(ctx, vp);
- pass0_rebase_mesa_consts(nvs);
-
- if (!prog->String && ctx->Transform.ClipPlanesEnabled)
- pass0_vp_insert_ff_clip_planes(ctx, nvs);
-
- pass0_build_attrib_map(nvs, vp);
- break;
- case GL_FRAGMENT_PROGRAM_ARB:
- nvs->func = &nmesa->FPfunc;
-
- if (fp->FogOption != GL_NONE)
- _mesa_append_fog_code(ctx, fp);
- pass0_rebase_mesa_consts(nvs);
- break;
- default:
- fprintf(stderr, "Unknown program type %d", prog->Target);
- FREE(rec);
- /* DESTROY TREE!! */
- return GL_FALSE;
- }
- nvs->func->card_priv = &nvs->card_priv;
-
- ret = pass0_translate_instructions(nvs, 0, 0, nvs->program_tree);
- if (ret)
- ret = pass0_resolve_mesa_consts(nvs);
-
- /*XXX: if (!ret) DESTROY TREE!!! */
-
- FREE(rec);
- return ret;
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader_1.c b/src/mesa/drivers/dri/nouveau/nouveau_shader_1.c
deleted file mode 100644
index 78c1401f7d..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_shader_1.c
+++ /dev/null
@@ -1,16 +0,0 @@
-#include "glheader.h"
-#include "macros.h"
-#include "enums.h"
-
-#include "nouveau_context.h"
-#include "nouveau_shader.h"
-
-GLboolean
-nouveau_shader_pass1(nvsPtr nvs)
-{
- NVSDBG("start: nvs=%p\n", nvs);
-
- return GL_TRUE;
-}
-
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader_2.c b/src/mesa/drivers/dri/nouveau/nouveau_shader_2.c
deleted file mode 100644
index cd27daca88..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_shader_2.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * Copyright (C) 2006 Ben Skeggs.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-/*
- * Authors:
- * Ben Skeggs
- */
-
-#include "glheader.h"
-#include "macros.h"
-#include "enums.h"
-
-#include "shader/prog_parameter.h"
-#include "shader/prog_print.h"
-
-#include "nouveau_context.h"
-#include "nouveau_shader.h"
-#include "nouveau_msg.h"
-
-struct pass2_rec {
- /* Map nvsRegister temp ID onto hw temp ID */
- unsigned int temps[NVS_MAX_TEMPS];
- /* Track free hw registers */
- unsigned int hw_temps[NVS_MAX_TEMPS];
-};
-
-static int
-pass2_alloc_hw_temp(nvsPtr nvs)
-{
- struct pass2_rec *rec = nvs->pass_rec;
- int i;
-
- for (i=0; ifunc->MaxTemp; i++) {
- /* This is a *horrible* hack.. R0 is both temp0 and result.color
- * in NV30/40 fragprogs, we can use R0 as a temp before result
- * is written however..
- */
- if (nvs->mesa.vp.Base.Target == GL_FRAGMENT_PROGRAM_ARB && i==0)
- continue;
- if (rec->hw_temps[i] == 0) {
- rec->hw_temps[i] = 1;
- return i;
- }
- }
-
- return -1;
-}
-
-static nvsRegister
-pass2_mangle_reg(nvsPtr nvs, nvsInstruction *inst, nvsRegister reg)
-{
- struct pass2_rec *rec = nvs->pass_rec;
-
- if (reg.file == NVS_FILE_TEMP) {
- if (rec->temps[reg.index] == -1)
- rec->temps[reg.index] = pass2_alloc_hw_temp(nvs);
- reg.index = rec->temps[reg.index];
- }
-
- return reg;
-}
-
-static void
-pass2_add_instruction(nvsPtr nvs, nvsInstruction *inst,
- struct _op_xlat *op, int slot)
-{
- nvsSwzComp default_swz[4] = { NVS_SWZ_X, NVS_SWZ_Y,
- NVS_SWZ_Z, NVS_SWZ_W };
- nvsFunc *shader = nvs->func;
- nvsRegister reg;
- int i;
-
- shader->SetOpcode(shader, op->NV, slot);
- if (inst->saturate ) shader->SetSaturate(shader);
- if (inst->cond_update ) shader->SetCCUpdate(shader);
- if (inst->cond_test ) shader->SetCondition(shader, 1, inst->cond,
- inst->cond_reg,
- inst->cond_swizzle);
- else shader->SetCondition(shader, 0, NVS_COND_TR,
- 0,
- default_swz);
- switch (inst->op) {
- case NVS_OP_TEX:
- case NVS_OP_TXB:
- case NVS_OP_TXL:
- case NVS_OP_TXP:
- case NVS_OP_TXD:
- shader->SetTexImageUnit(shader, inst->tex_unit);
- break;
- default:
- break;
- }
-
- for (i = 0; i < 3; i++) {
- if (op->srcpos[i] != -1) {
- reg = pass2_mangle_reg(nvs, inst, inst->src[i]);
-
- shader->SetSource(shader, ®, op->srcpos[i]);
-
- if (reg.file == NVS_FILE_CONST &&
- shader->GetSourceConstVal) {
- int idx_slot =
- nvs->params[reg.index].hw_index_cnt++;
- nvs->params[reg.index].hw_index = realloc(
- nvs->params[reg.index].hw_index,
- sizeof(int) * idx_slot+1);
- nvs->params[reg.index].hw_index[idx_slot] =
- nvs->program_current + 4;
- }
- }
- }
-
- reg = pass2_mangle_reg(nvs, inst, inst->dest);
- shader->SetResult(shader, ®, inst->mask, slot);
-
- if (inst->dest_scale != NVS_SCALE_1X) {
- shader->SetResultScale(shader, inst->dest_scale);
- }
-}
-
-static int
-pass2_assemble_instruction(nvsPtr nvs, nvsInstruction *inst, int last)
-{
- nvsFunc *shader = nvs->func;
- struct _op_xlat *op;
- unsigned int hw_inst[8];
- int slot;
- int instsz;
- int i;
-
- shader->inst = hw_inst;
-
- /* Assemble this instruction */
- if (!(op = shader->GetOPTXFromSOP(inst->op, &slot)))
- return 0;
- shader->InitInstruction(shader);
- pass2_add_instruction(nvs, inst, op, slot);
- if (last)
- shader->SetLastInst(shader);
-
- instsz = shader->GetOffsetNext(nvs->func);
- if (nvs->program_size + instsz >= nvs->program_alloc_size) {
- nvs->program_alloc_size *= 2;
- nvs->program = realloc(nvs->program,
- nvs->program_alloc_size *
- sizeof(uint32_t));
- }
-
- for (i=0; iprogram[nvs->program_current++] = hw_inst[i];
- nvs->program_size = nvs->program_current;
- return 1;
-}
-
-static GLboolean
-pass2_translate(nvsPtr nvs, nvsFragmentHeader *f)
-{
- nvsFunc *shader = nvs->func;
- GLboolean last;
-
- while (f) {
- last = (f == ((nvsSubroutine*)nvs->program_tree)->insn_tail);
-
- switch (f->type) {
- case NVS_INSTRUCTION:
- if (!pass2_assemble_instruction(nvs,
- (nvsInstruction *)f,
- last))
- return GL_FALSE;
- break;
- default:
- WARN_ONCE("Unimplemented fragment type\n");
- return GL_FALSE;
- }
-
- f = f->next;
- }
-
- return GL_TRUE;
-}
-
-/* Translate program into hardware format */
-GLboolean
-nouveau_shader_pass2(nvsPtr nvs)
-{
- struct pass2_rec *rec;
- int i;
-
- NVSDBG("start: nvs=%p\n", nvs);
-
- rec = calloc(1, sizeof(struct pass2_rec));
- for (i=0; itemps[i] = -1;
- nvs->pass_rec = rec;
-
- /* Start off with allocating 4 uint32_t's for each inst, will be grown
- * if necessary..
- */
- nvs->program_alloc_size = nvs->mesa.vp.Base.NumInstructions * 4;
- nvs->program = calloc(nvs->program_alloc_size, sizeof(uint32_t));
- nvs->program_size = 0;
- nvs->program_current = 0;
-
- if (!pass2_translate(nvs,
- ((nvsSubroutine*)nvs->program_tree)->insn_head)) {
- free(nvs->program);
- nvs->program = NULL;
- return GL_FALSE;
- }
-
- /* Shrink allocated memory to only what we need */
- nvs->program = realloc(nvs->program,
- nvs->program_size * sizeof(uint32_t));
- nvs->program_alloc_size = nvs->program_size;
-
- nvs->translated = 1;
- nvs->on_hardware = 0;
-
- if (NOUVEAU_DEBUG & DEBUG_SHADERS) {
- fflush(stdout); fflush(stderr);
- fprintf(stderr, "-----------MESA PROGRAM target=%s, id=0x%x\n",
- _mesa_lookup_enum_by_nr(
- nvs->mesa.vp.Base.Target),
- nvs->mesa.vp.Base.Id);
- fflush(stdout); fflush(stderr);
- _mesa_print_program(&nvs->mesa.vp.Base);
- fflush(stdout); fflush(stderr);
- fprintf(stderr, "^^^^^^^^^^^^^^^^MESA PROGRAM\n");
- fflush(stdout); fflush(stderr);
- fprintf(stderr, "----------------NV PROGRAM\n");
- fflush(stdout); fflush(stderr);
- nvsDisasmHWShader(nvs);
- fflush(stdout); fflush(stderr);
- fprintf(stderr, "^^^^^^^^^^^^^^^^NV PROGRAM\n");
- fflush(stdout); fflush(stderr);
- }
-
- return GL_TRUE;
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_span.c b/src/mesa/drivers/dri/nouveau/nouveau_span.c
deleted file mode 100644
index d62830ff53..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_span.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-#include "nouveau_context.h"
-#include "nouveau_span.h"
-#include "nouveau_fifo.h"
-#include "nouveau_lock.h"
-
-#include "swrast/swrast.h"
-
-#define HAVE_HW_DEPTH_SPANS 0
-#define HAVE_HW_DEPTH_PIXELS 0
-#define HAVE_HW_STENCIL_SPANS 0
-#define HAVE_HW_STENCIL_PIXELS 0
-
-#define HW_CLIPLOOP() \
- do { \
- int _nc = nmesa->numClipRects; \
- while ( _nc-- ) { \
- int minx = nmesa->pClipRects[_nc].x1 - nmesa->drawX; \
- int miny = nmesa->pClipRects[_nc].y1 - nmesa->drawY; \
- int maxx = nmesa->pClipRects[_nc].x2 - nmesa->drawX; \
- int maxy = nmesa->pClipRects[_nc].y2 - nmesa->drawY;
-
-#define LOCAL_VARS \
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); \
- nouveau_renderbuffer_t *nrb = (nouveau_renderbuffer_t *)rb; \
- GLuint height = nrb->mesa.Height; \
- GLubyte *map = (GLubyte *)(nrb->map ? nrb->map : nrb->mem->map) + \
- (nmesa->drawY * nrb->pitch) + (nmesa->drawX * nrb->cpp); \
- GLuint p; \
- (void) p;
-
-#define Y_FLIP( _y ) (height - _y - 1)
-
-#define HW_LOCK()
-
-#define HW_UNLOCK()
-
-
-
-/* ================================================================
- * Color buffers
- */
-
-/* RGB565 */
-#define SPANTMP_PIXEL_FMT GL_RGB
-#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
-
-#define TAG(x) nouveau##x##_RGB565
-#define TAG2(x,y) nouveau##x##_RGB565##y
-#define GET_PTR(X,Y) (map + (Y)*nrb->pitch + (X)*nrb->cpp)
-#include "spantmp2.h"
-
-
-/* ARGB8888 */
-#define SPANTMP_PIXEL_FMT GL_BGRA
-#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
-
-#define TAG(x) nouveau##x##_ARGB8888
-#define TAG2(x,y) nouveau##x##_ARGB8888##y
-#define GET_PTR(X,Y) (map + (Y)*nrb->pitch + (X)*nrb->cpp)
-#include "spantmp2.h"
-
-static void nouveauSpanRenderStart(GLcontext * ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- FIRE_RING();
- LOCK_HARDWARE(nmesa);
- nouveauWaitForIdleLocked(nmesa);
-}
-
-static void nouveauSpanRenderFinish(GLcontext * ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- _swrast_flush(ctx);
- nouveauWaitForIdleLocked(nmesa);
- UNLOCK_HARDWARE(nmesa);
-}
-
-void nouveauSpanInitFunctions(GLcontext * ctx)
-{
- struct swrast_device_driver *swdd =
- _swrast_GetDeviceDriverReference(ctx);
- swdd->SpanRenderStart = nouveauSpanRenderStart;
- swdd->SpanRenderFinish = nouveauSpanRenderFinish;
-}
-
-
-/**
- * Plug in the Get/Put routines for the given driRenderbuffer.
- */
-void nouveauSpanSetFunctions(nouveau_renderbuffer_t * nrb)
-{
- if (nrb->mesa._ActualFormat == GL_RGBA8)
- nouveauInitPointers_ARGB8888(&nrb->mesa);
- else // if (nrb->mesa._ActualFormat == GL_RGB5)
- nouveauInitPointers_RGB565(&nrb->mesa);
-}
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_span.h b/src/mesa/drivers/dri/nouveau/nouveau_span.h
deleted file mode 100644
index d3f31c9cb2..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_span.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-
-#ifndef __NOUVEAU_SPAN_H__
-#define __NOUVEAU_SPAN_H__
-
-#include "drirenderbuffer.h"
-#include "nouveau_fbo.h"
-
-extern void nouveauSpanInitFunctions(GLcontext *ctx);
-extern void nouveauSpanSetFunctions(nouveau_renderbuffer_t *nrb);
-
-#endif /* __NOUVEAU_SPAN_H__ */
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_state.c b/src/mesa/drivers/dri/nouveau/nouveau_state.c
deleted file mode 100644
index 1eb6069e34..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_state.c
+++ /dev/null
@@ -1,368 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Jeremy Kolb
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-#include "nouveau_context.h"
-#include "nouveau_state.h"
-#include "nouveau_swtcl.h"
-#include "nouveau_fifo.h"
-
-#include "swrast/swrast.h"
-#include "tnl/tnl.h"
-#include "swrast_setup/swrast_setup.h"
-
-#include "tnl/t_pipeline.h"
-
-#include "mtypes.h"
-#include "colormac.h"
-
-static INLINE GLuint nouveauPackColor(GLuint format,
- GLubyte r, GLubyte g,
- GLubyte b, GLubyte a)
-{
- switch (format) {
- case 2:
- return PACK_COLOR_565( r, g, b );
- case 4:
- return PACK_COLOR_8888( r, g, b, a);
- default:
- fprintf(stderr, "unknown format %d\n", (int)format);
- return 0;
- }
-}
-
-static void nouveauCalcViewport(GLcontext *ctx)
-{
- /* Calculate the Viewport Matrix */
-
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- const GLfloat *v = ctx->Viewport._WindowMap.m;
- GLfloat *m = nmesa->viewport.m;
- GLfloat xoffset = nmesa->drawX, yoffset = nmesa->drawY + nmesa->drawH;
-
- nmesa->depth_scale = 1.0 / ctx->DrawBuffer->_DepthMaxF;
-
- m[MAT_SX] = v[MAT_SX];
- m[MAT_TX] = v[MAT_TX] + xoffset + SUBPIXEL_X;
- m[MAT_SY] = - v[MAT_SY];
- m[MAT_TY] = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y;
- m[MAT_SZ] = v[MAT_SZ] * nmesa->depth_scale;
- m[MAT_TZ] = v[MAT_TZ] * nmesa->depth_scale;
-
- nmesa->hw_func.WindowMoved(nmesa);
-}
-
-static void nouveauViewport(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h)
-{
- /*
- * Need to send (at least on an nv35 the following:
- * cons = 4 (this may be bytes per pixel)
- *
- * The viewport:
- * 445 0x0000bee0 {size: 0x0 channel: 0x1 cmd: 0x00009ee0} <-- VIEWPORT_SETUP/HEADER ?
- * 446 0x00000000 {size: 0x0 channel: 0x0 cmd: 0x00000000} <-- x * cons
- * 447 0x00000c80 {size: 0x0 channel: 0x0 cmd: 0x00000c80} <-- (height + x) * cons
- * 448 0x00000000 {size: 0x0 channel: 0x0 cmd: 0x00000000} <-- y * cons
- * 449 0x00000960 {size: 0x0 channel: 0x0 cmd: 0x00000960} <-- (width + y) * cons
- * 44a 0x00082a00 {size: 0x2 channel: 0x1 cmd: 0x00000a00} <-- VIEWPORT_DIMS
- * 44b 0x04000000 <-- (Width_from_glViewport << 16) | x
- * 44c 0x03000000 <-- (Height_from_glViewport << 16) | (win_height - height - y)
- *
- */
-
- nouveauCalcViewport(ctx);
-}
-
-static void nouveauDepthRange(GLcontext *ctx, GLclampd near, GLclampd far)
-{
- nouveauCalcViewport(ctx);
-}
-
-static void nouveauUpdateProjectionMatrix(GLcontext *ctx)
-{
-}
-
-static void nouveauUpdateModelviewMatrix(GLcontext *ctx)
-{
-}
-
-static void nouveauDDUpdateHWState(GLcontext *ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- int new_state = nmesa->new_state;
-
- if ( new_state || nmesa->new_render_state & _NEW_TEXTURE )
- {
- nmesa->new_state = 0;
-
- /* Update the various parts of the context's state.
- */
- /*
- if ( new_state & NOUVEAU_NEW_ALPHA )
- nouveauUpdateAlphaMode( ctx );
-
- if ( new_state & NOUVEAU_NEW_DEPTH )
- nouveauUpdateZMode( ctx );
-
- if ( new_state & NOUVEAU_NEW_FOG )
- nouveauUpdateFogAttrib( ctx );
-
- if ( new_state & NOUVEAU_NEW_CLIP )
- nouveauUpdateClipping( ctx );
-
- if ( new_state & NOUVEAU_NEW_CULL )
- nouveauUpdateCull( ctx );
-
- if ( new_state & NOUVEAU_NEW_MASKS )
- nouveauUpdateMasks( ctx );
-
- if ( new_state & NOUVEAU_NEW_WINDOW )
- nouveauUpdateWindow( ctx );
-
- if ( nmesa->new_render_state & _NEW_TEXTURE ) {
- nouveauUpdateTextureState( ctx );
- }*/
- }
-}
-
-static void nouveauDDInvalidateState(GLcontext *ctx, GLuint new_state)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if ( new_state & _NEW_PROJECTION ) {
- nmesa->hw_func.UpdateProjectionMatrix(ctx);
- }
- if ( new_state & _NEW_MODELVIEW ) {
- nmesa->hw_func.UpdateModelviewMatrix(ctx);
- }
-
- _swrast_InvalidateState( ctx, new_state );
- _swsetup_InvalidateState( ctx, new_state );
- _vbo_InvalidateState( ctx, new_state );
- _tnl_InvalidateState( ctx, new_state );
- NOUVEAU_CONTEXT(ctx)->new_render_state |= new_state;
-}
-
-/* Initialize the context's hardware state. */
-void nouveauDDInitState(nouveauContextPtr nmesa)
-{
- uint32_t type = nmesa->screen->card->type;
- switch(type)
- {
- case NV_04:
- case NV_05:
- nv04InitStateFuncs(nmesa->glCtx, &nmesa->glCtx->Driver);
- break;
- case NV_10:
- case NV_11:
- case NV_17:
- nv10InitStateFuncs(nmesa->glCtx, &nmesa->glCtx->Driver);
- break;
- case NV_20:
- nv20InitStateFuncs(nmesa->glCtx, &nmesa->glCtx->Driver);
- break;
- case NV_30:
- case NV_40:
- case NV_44:
- nv30InitStateFuncs(nmesa->glCtx, &nmesa->glCtx->Driver);
- break;
- case NV_50:
- nv50InitStateFuncs(nmesa->glCtx, &nmesa->glCtx->Driver);
- break;
- default:
- break;
- }
- nouveau_state_cache_init(nmesa);
-}
-
-/* Initialize the driver's state functions */
-void nouveauDDInitStateFuncs(GLcontext *ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- ctx->Driver.UpdateState = nouveauDDInvalidateState;
-
- ctx->Driver.ClearIndex = NULL;
- ctx->Driver.ClearColor = NULL; //nouveauDDClearColor;
- ctx->Driver.ClearStencil = NULL; //nouveauDDClearStencil;
- ctx->Driver.DrawBuffer = NULL; //nouveauDDDrawBuffer;
- ctx->Driver.ReadBuffer = NULL; //nouveauDDReadBuffer;
-
- ctx->Driver.IndexMask = NULL;
- ctx->Driver.ColorMask = NULL; //nouveauDDColorMask;
- ctx->Driver.AlphaFunc = NULL; //nouveauDDAlphaFunc;
- ctx->Driver.BlendEquationSeparate = NULL; //nouveauDDBlendEquationSeparate;
- ctx->Driver.BlendFuncSeparate = NULL; //nouveauDDBlendFuncSeparate;
- ctx->Driver.ClearDepth = NULL; //nouveauDDClearDepth;
- ctx->Driver.CullFace = NULL; //nouveauDDCullFace;
- ctx->Driver.FrontFace = NULL; //nouveauDDFrontFace;
- ctx->Driver.DepthFunc = NULL; //nouveauDDDepthFunc;
- ctx->Driver.DepthMask = NULL; //nouveauDDDepthMask;
- ctx->Driver.Enable = NULL; //nouveauDDEnable;
- ctx->Driver.Fogfv = NULL; //nouveauDDFogfv;
- ctx->Driver.Hint = NULL;
- ctx->Driver.Lightfv = NULL;
- ctx->Driver.LightModelfv = NULL; //nouveauDDLightModelfv;
- ctx->Driver.LogicOpcode = NULL; //nouveauDDLogicOpCode;
- ctx->Driver.PolygonMode = NULL;
- ctx->Driver.PolygonStipple = NULL; //nouveauDDPolygonStipple;
- ctx->Driver.RenderMode = NULL; //nouveauDDRenderMode;
- ctx->Driver.Scissor = NULL; //nouveauDDScissor;
- ctx->Driver.ShadeModel = NULL; //nouveauDDShadeModel;
- ctx->Driver.StencilFuncSeparate = NULL; //nouveauDDStencilFuncSeparate;
- ctx->Driver.StencilMaskSeparate = NULL; //nouveauDDStencilMaskSeparate;
- ctx->Driver.StencilOpSeparate = NULL; //nouveauDDStencilOpSeparate;
-
- ctx->Driver.DepthRange = nouveauDepthRange;
- ctx->Driver.Viewport = nouveauViewport;
-
- /* Pixel path fallbacks.
- */
- ctx->Driver.Accum = _swrast_Accum;
- ctx->Driver.Bitmap = _swrast_Bitmap;
- ctx->Driver.CopyPixels = _swrast_CopyPixels;
- ctx->Driver.DrawPixels = _swrast_DrawPixels;
- ctx->Driver.ReadPixels = _swrast_ReadPixels;
-
- /* Swrast hooks for imaging extensions:
- */
- ctx->Driver.CopyColorTable = _swrast_CopyColorTable;
- ctx->Driver.CopyColorSubTable = _swrast_CopyColorSubTable;
- ctx->Driver.CopyConvolutionFilter1D = _swrast_CopyConvolutionFilter1D;
- ctx->Driver.CopyConvolutionFilter2D = _swrast_CopyConvolutionFilter2D;
-
- /* Matrix updates */
- nmesa->hw_func.UpdateProjectionMatrix = nouveauUpdateProjectionMatrix;
- nmesa->hw_func.UpdateModelviewMatrix = nouveauUpdateModelviewMatrix;
-}
-
-#define STATE_INIT(a) if (ctx->Driver.a) ctx->Driver.a
-
-void nouveauInitState(GLcontext *ctx)
-{
- /*
- * Mesa should do this for us:
- */
-
- STATE_INIT(AlphaFunc)( ctx,
- ctx->Color.AlphaFunc,
- ctx->Color.AlphaRef);
-
- STATE_INIT(BlendColor)( ctx,
- ctx->Color.BlendColor );
-
- STATE_INIT(BlendEquationSeparate)( ctx,
- ctx->Color.BlendEquationRGB,
- ctx->Color.BlendEquationA);
-
- STATE_INIT(BlendFuncSeparate)( ctx,
- ctx->Color.BlendSrcRGB,
- ctx->Color.BlendDstRGB,
- ctx->Color.BlendSrcA,
- ctx->Color.BlendDstA);
-
- STATE_INIT(ClearColor)( ctx, ctx->Color.ClearColor);
- STATE_INIT(ClearDepth)( ctx, ctx->Depth.Clear);
- STATE_INIT(ClearStencil)( ctx, ctx->Stencil.Clear);
-
- STATE_INIT(ColorMask)( ctx,
- ctx->Color.ColorMask[RCOMP],
- ctx->Color.ColorMask[GCOMP],
- ctx->Color.ColorMask[BCOMP],
- ctx->Color.ColorMask[ACOMP]);
-
- STATE_INIT(CullFace)( ctx, ctx->Polygon.CullFaceMode );
- STATE_INIT(DepthFunc)( ctx, ctx->Depth.Func );
- STATE_INIT(DepthMask)( ctx, ctx->Depth.Mask );
- STATE_INIT(DepthRange)( ctx, ctx->Viewport.Near, ctx->Viewport.Far );
-
- STATE_INIT(Enable)( ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled );
- STATE_INIT(Enable)( ctx, GL_BLEND, ctx->Color.BlendEnabled );
- STATE_INIT(Enable)( ctx, GL_COLOR_LOGIC_OP, ctx->Color.ColorLogicOpEnabled );
- STATE_INIT(Enable)( ctx, GL_COLOR_SUM, ctx->Fog.ColorSumEnabled );
- STATE_INIT(Enable)( ctx, GL_CULL_FACE, ctx->Polygon.CullFlag );
- STATE_INIT(Enable)( ctx, GL_DEPTH_TEST, ctx->Depth.Test );
- STATE_INIT(Enable)( ctx, GL_DITHER, ctx->Color.DitherFlag );
- STATE_INIT(Enable)( ctx, GL_FOG, ctx->Fog.Enabled );
- STATE_INIT(Enable)( ctx, GL_LIGHTING, ctx->Light.Enabled );
- STATE_INIT(Enable)( ctx, GL_LINE_SMOOTH, ctx->Line.SmoothFlag );
- STATE_INIT(Enable)( ctx, GL_LINE_STIPPLE, ctx->Line.StippleFlag );
- STATE_INIT(Enable)( ctx, GL_POINT_SMOOTH, ctx->Point.SmoothFlag );
- STATE_INIT(Enable)( ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
- STATE_INIT(Enable)( ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
- STATE_INIT(Enable)( ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
- STATE_INIT(Enable)( ctx, GL_POLYGON_SMOOTH, ctx->Polygon.SmoothFlag );
- STATE_INIT(Enable)( ctx, GL_POLYGON_STIPPLE, ctx->Polygon.StippleFlag );
- STATE_INIT(Enable)( ctx, GL_SCISSOR_TEST, ctx->Scissor.Enabled );
- STATE_INIT(Enable)( ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled );
- STATE_INIT(Enable)( ctx, GL_TEXTURE_1D, GL_FALSE );
- STATE_INIT(Enable)( ctx, GL_TEXTURE_2D, GL_FALSE );
- STATE_INIT(Enable)( ctx, GL_TEXTURE_RECTANGLE_NV, GL_FALSE );
- STATE_INIT(Enable)( ctx, GL_TEXTURE_3D, GL_FALSE );
- STATE_INIT(Enable)( ctx, GL_TEXTURE_CUBE_MAP, GL_FALSE );
-
- STATE_INIT(Fogfv)( ctx, GL_FOG_COLOR, ctx->Fog.Color );
- STATE_INIT(Fogfv)( ctx, GL_FOG_MODE, 0 );
- STATE_INIT(Fogfv)( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
- STATE_INIT(Fogfv)( ctx, GL_FOG_START, &ctx->Fog.Start );
- STATE_INIT(Fogfv)( ctx, GL_FOG_END, &ctx->Fog.End );
-
- STATE_INIT(FrontFace)( ctx, ctx->Polygon.FrontFace );
-
- {
- GLfloat f = (GLfloat)ctx->Light.Model.ColorControl;
- STATE_INIT(LightModelfv)( ctx, GL_LIGHT_MODEL_COLOR_CONTROL, &f );
- }
-
- STATE_INIT(LineStipple)( ctx, ctx->Line.StippleFactor, ctx->Line.StipplePattern );
- STATE_INIT(LineWidth)( ctx, ctx->Line.Width );
- STATE_INIT(LogicOpcode)( ctx, ctx->Color.LogicOp );
- STATE_INIT(PointSize)( ctx, ctx->Point.Size );
- STATE_INIT(PolygonMode)( ctx, GL_FRONT, ctx->Polygon.FrontMode );
- STATE_INIT(PolygonMode)( ctx, GL_BACK, ctx->Polygon.BackMode );
- STATE_INIT(PolygonOffset)( ctx,
- ctx->Polygon.OffsetFactor,
- ctx->Polygon.OffsetUnits );
- STATE_INIT(PolygonStipple)( ctx, (const GLubyte *)ctx->PolygonStipple );
- STATE_INIT(ShadeModel)( ctx, ctx->Light.ShadeModel );
- STATE_INIT(StencilFuncSeparate)( ctx, GL_FRONT,
- ctx->Stencil.Function[0],
- ctx->Stencil.Ref[0],
- ctx->Stencil.ValueMask[0] );
- STATE_INIT(StencilFuncSeparate)( ctx, GL_BACK,
- ctx->Stencil.Function[1],
- ctx->Stencil.Ref[1],
- ctx->Stencil.ValueMask[1] );
- STATE_INIT(StencilMaskSeparate)( ctx, GL_FRONT, ctx->Stencil.WriteMask[0] );
- STATE_INIT(StencilMaskSeparate)( ctx, GL_BACK, ctx->Stencil.WriteMask[1] );
- STATE_INIT(StencilOpSeparate)( ctx, GL_FRONT,
- ctx->Stencil.FailFunc[0],
- ctx->Stencil.ZFailFunc[0],
- ctx->Stencil.ZPassFunc[0]);
- STATE_INIT(StencilOpSeparate)( ctx, GL_BACK,
- ctx->Stencil.FailFunc[1],
- ctx->Stencil.ZFailFunc[1],
- ctx->Stencil.ZPassFunc[1]);
-}
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_state.h b/src/mesa/drivers/dri/nouveau/nouveau_state.h
deleted file mode 100644
index dbac71760b..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_state.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Jeremy Kolb
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-#ifndef __NOUVEAU_STATE_H__
-#define __NOUVEAU_STATE_H__
-
-#include "nouveau_context.h"
-
-extern void nouveauDDInitState(nouveauContextPtr nmesa);
-extern void nouveauDDInitStateFuncs(GLcontext *ctx);
-
-extern void nv04InitStateFuncs(GLcontext *ctx, struct dd_function_table *func);
-extern void nv10InitStateFuncs(GLcontext *ctx, struct dd_function_table *func);
-extern void nv20InitStateFuncs(GLcontext *ctx, struct dd_function_table *func);
-extern void nv30InitStateFuncs(GLcontext *ctx, struct dd_function_table *func);
-extern void nv50InitStateFuncs(GLcontext *ctx, struct dd_function_table *func);
-
-extern void nouveauInitState(GLcontext *ctx);
-
-/*
-extern void nouveauDDUpdateState(GLcontext *ctx);
-extern void nouveauDDUpdateHWState(GLcontext *ctx);
-
-extern void nouveauEmitHwStateLocked(nouveauContextPtr nmesa);
-*/
-#endif
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_state_cache.c b/src/mesa/drivers/dri/nouveau/nouveau_state_cache.c
deleted file mode 100644
index cb4b9d3027..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_state_cache.c
+++ /dev/null
@@ -1,69 +0,0 @@
-
-#include "nouveau_state_cache.h"
-#include "nouveau_context.h"
-#include "nouveau_object.h"
-#include "nouveau_fifo.h"
-
-#define BEGIN_RING_NOFLUSH(subchannel,tag,size) do { \
- if (nmesa->fifo.free <= (size)) \
- WAIT_RING(nmesa,(size)); \
- OUT_RING( ((size)<<18) | ((subchannel) << 13) | (tag)); \
- nmesa->fifo.free -= ((size) + 1); \
-}while(0)
-
-// flush all the dirty state
-void nouveau_state_cache_flush(nouveauContextPtr nmesa)
-{
- int i=0;
- int run=0;
-
- // fast-path no state changes
- if (!nmesa->state_cache.dirty)
- return;
- nmesa->state_cache.dirty=0;
-
- do
- {
- // jump to a dirty state
- while((nmesa->state_cache.hdirty[i/NOUVEAU_STATE_CACHE_HIER_SIZE]==0)&&(istate_cache.atoms[i].dirty==0)&&(istate_cache.atoms[i+run].dirty)&&(i+run0) {
- int j;
-
- BEGIN_RING_NOFLUSH(NvSub3D, i*4, run);
- for(j=0;jstate_cache.atoms[i+j].value);
- nmesa->state_cache.atoms[i+j].dirty=0;
- if ((i+j)%NOUVEAU_STATE_CACHE_HIER_SIZE==0)
- nmesa->state_cache.hdirty[(i+j)/NOUVEAU_STATE_CACHE_HIER_SIZE-1]=0;
- }
- i+=run;
- }
- }
- while(istate_cache.hdirty[NOUVEAU_STATE_CACHE_HIER_SIZE/NOUVEAU_STATE_CACHE_HIER_SIZE-1]=0;
-}
-
-
-// inits the state cache
-void nouveau_state_cache_init(nouveauContextPtr nmesa)
-{
- int i;
- for(i=0;istate_cache.atoms[i].dirty=0;
- nmesa->state_cache.atoms[i].value=0xDEADBEEF; // nvidia cards like beef
- }
- nmesa->state_cache.dirty=0;
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_state_cache.h b/src/mesa/drivers/dri/nouveau/nouveau_state_cache.h
deleted file mode 100644
index 5f9d426450..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_state_cache.h
+++ /dev/null
@@ -1,29 +0,0 @@
-
-#ifndef __NOUVEAU_STATE_CACHE_H__
-#define __NOUVEAU_STATE_CACHE_H__
-
-#include "mtypes.h"
-
-#define NOUVEAU_STATE_CACHE_ENTRIES 2048
-// size of a dirty requests block
-// you can play with that and tune the value to increase/decrease performance
-// but keep it a power of 2 !
-#define NOUVEAU_STATE_CACHE_HIER_SIZE 32
-
-typedef struct nouveau_state_atom_t{
- uint32_t value;
- uint32_t dirty;
-}nouveau_state_atom;
-
-typedef struct nouveau_state_cache_t{
- nouveau_state_atom atoms[NOUVEAU_STATE_CACHE_ENTRIES];
- uint32_t current_pos;
- // hierarchical dirty flags
- uint8_t hdirty[NOUVEAU_STATE_CACHE_ENTRIES/NOUVEAU_STATE_CACHE_HIER_SIZE];
- // master dirty flag
- uint8_t dirty;
-}nouveau_state_cache;
-
-
-#endif
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_swtcl.c b/src/mesa/drivers/dri/nouveau/nouveau_swtcl.c
deleted file mode 100644
index 8a013bd999..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_swtcl.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/* Common software TCL code */
-
-#include "nouveau_context.h"
-#include "nouveau_swtcl.h"
-#include "nv10_swtcl.h"
-#include "nouveau_span.h"
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "tnl/tnl.h"
-#include "tnl/t_pipeline.h"
-
-/* Common tri functions */
-
-/* The fallbacks */
-void nouveau_fallback_tri(struct nouveau_context *nmesa,
- nouveauVertex *v0,
- nouveauVertex *v1,
- nouveauVertex *v2)
-{
- GLcontext *ctx = nmesa->glCtx;
- SWvertex v[3];
- _swsetup_Translate(ctx, v0, &v[0]);
- _swsetup_Translate(ctx, v1, &v[1]);
- _swsetup_Translate(ctx, v2, &v[2]);
- _swrast_Triangle(ctx, &v[0], &v[1], &v[2]);
-}
-
-
-void nouveau_fallback_line(struct nouveau_context *nmesa,
- nouveauVertex *v0,
- nouveauVertex *v1)
-{
- GLcontext *ctx = nmesa->glCtx;
- SWvertex v[2];
- _swsetup_Translate(ctx, v0, &v[0]);
- _swsetup_Translate(ctx, v1, &v[1]);
- _swrast_Line(ctx, &v[0], &v[1]);
-}
-
-
-void nouveau_fallback_point(struct nouveau_context *nmesa,
- nouveauVertex *v0)
-{
- GLcontext *ctx = nmesa->glCtx;
- SWvertex v[1];
- _swsetup_Translate(ctx, v0, &v[0]);
- _swrast_Point(ctx, &v[0]);
-}
-
-void nouveauFallback(struct nouveau_context *nmesa, GLuint bit, GLboolean mode)
-{
- GLcontext *ctx = nmesa->glCtx;
- GLuint oldfallback = nmesa->Fallback;
-
- if (mode) {
- nmesa->Fallback |= bit;
- if (oldfallback == 0) {
- if (nmesa->screen->card->typerender_index = ~0;
- }
- }
- else {
- nmesa->Fallback &= ~bit;
- if (oldfallback == bit) {
- _swrast_flush( ctx );
-
- if (nmesa->screen->card->typevertex_attrs,
- nmesa->vertex_attr_count,
- nmesa->viewport.m, 0 );
- }
- }
-}
-
-
-void nouveauRunPipeline( GLcontext *ctx )
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (nmesa->new_state) {
- nmesa->new_render_state |= nmesa->new_state;
- }
-
- _tnl_run_pipeline( ctx );
-}
-
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_swtcl.h b/src/mesa/drivers/dri/nouveau/nouveau_swtcl.h
deleted file mode 100644
index ba4d8725a6..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_swtcl.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-
-#ifndef __NOUVEAU_SWTCL_H__
-#define __NOUVEAU_SWTCL_H__
-
-#include "nouveau_context.h"
-
-extern void nouveau_fallback_tri(struct nouveau_context *nmesa,
- nouveauVertex *v0,
- nouveauVertex *v1,
- nouveauVertex *v2);
-
-extern void nouveau_fallback_line(struct nouveau_context *nmesa,
- nouveauVertex *v0,
- nouveauVertex *v1);
-
-extern void nouveau_fallback_point(struct nouveau_context *nmesa,
- nouveauVertex *v0);
-
-extern void nouveauFallback(struct nouveau_context *nmesa, GLuint bit, GLboolean mode);
-
-extern void nouveauRunPipeline( GLcontext *ctx );
-
-extern void nouveauTriInitFunctions( GLcontext *ctx );
-
-
-#endif /* __NOUVEAU_SWTCL_H__ */
-
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_sync.c b/src/mesa/drivers/dri/nouveau/nouveau_sync.c
deleted file mode 100644
index 2ca038f4f8..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_sync.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright (C) 2007 Ben Skeggs.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include "vblank.h" /* for DO_USLEEP */
-
-#include "nouveau_context.h"
-#include "nouveau_fifo.h"
-#include "nouveau_mem.h"
-#include "nouveau_msg.h"
-#include "nouveau_object.h"
-#include "nouveau_reg.h"
-#include "nouveau_sync.h"
-
-#define NOTIFIER(__v) \
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx); \
- volatile uint32_t *__v = (void*)nmesa->fifo.notifier_block + \
- notifier->offset
-
-struct drm_nouveau_notifierobj_alloc *
-nouveau_notifier_new(GLcontext *ctx, GLuint handle, GLuint count)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- struct drm_nouveau_notifierobj_alloc *notifier;
- int ret;
-
-#ifdef NOUVEAU_RING_DEBUG
- return NULL;
-#endif
- notifier = CALLOC_STRUCT(drm_nouveau_notifierobj_alloc);
- if (!notifier)
- return NULL;
-
- notifier->channel = nmesa->fifo.drm.channel;
- notifier->handle = handle;
- notifier->count = count;
- ret = drmCommandWriteRead(nmesa->driFd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC,
- notifier, sizeof(*notifier));
- if (ret) {
- MESSAGE("Failed to create notifier 0x%08x: %d\n", handle, ret);
- FREE(notifier);
- return NULL;
- }
-
- return notifier;
-}
-
-void
-nouveau_notifier_destroy(GLcontext *ctx,
- struct drm_nouveau_notifierobj_alloc *notifier)
-{
- /*XXX: free notifier object.. */
- FREE(notifier);
-}
-
-void
-nouveau_notifier_reset(GLcontext *ctx,
- struct drm_nouveau_notifierobj_alloc *notifier,
- GLuint id)
-{
- NOTIFIER(n);
-
-#ifdef NOUVEAU_RING_DEBUG
- return;
-#endif
-
- n[NV_NOTIFY_TIME_0 /4] = 0x00000000;
- n[NV_NOTIFY_TIME_1 /4] = 0x00000000;
- n[NV_NOTIFY_RETURN_VALUE/4] = 0x00000000;
- n[NV_NOTIFY_STATE /4] = (NV_NOTIFY_STATE_STATUS_IN_PROCESS <<
- NV_NOTIFY_STATE_STATUS_SHIFT);
-}
-
-GLuint
-nouveau_notifier_status(GLcontext *ctx,
- struct drm_nouveau_notifierobj_alloc *notifier,
- GLuint id)
-{
- NOTIFIER(n);
-
- return n[NV_NOTIFY_STATE/4] >> NV_NOTIFY_STATE_STATUS_SHIFT;
-}
-
-GLuint
-nouveau_notifier_return_val(GLcontext *ctx,
- struct drm_nouveau_notifierobj_alloc *notifier,
- GLuint id)
-{
- NOTIFIER(n);
-
- return n[NV_NOTIFY_RETURN_VALUE/4];
-}
-
-GLboolean
-nouveau_notifier_wait_status(GLcontext *ctx,
- struct drm_nouveau_notifierobj_alloc *notifier,
- GLuint id, GLuint status, GLuint timeout)
-{
- NOTIFIER(n);
- unsigned int time = 0;
-
-#ifdef NOUVEAU_RING_DEBUG
- return GL_TRUE;
-#endif
-
- while (time <= timeout) {
- if (n[NV_NOTIFY_STATE/4] & NV_NOTIFY_STATE_ERROR_CODE_MASK) {
- MESSAGE("Notifier returned error: 0x%04x\n",
- n[NV_NOTIFY_STATE/4] &
- NV_NOTIFY_STATE_ERROR_CODE_MASK);
- return GL_FALSE;
- }
-
- if (((n[NV_NOTIFY_STATE/4] & NV_NOTIFY_STATE_STATUS_MASK) >>
- NV_NOTIFY_STATE_STATUS_SHIFT) == status)
- return GL_TRUE;
-
- if (timeout) {
- DO_USLEEP(1);
- time++;
- }
- }
-
- MESSAGE("Notifier timed out\n");
- return GL_FALSE;
-}
-
-void
-nouveau_notifier_wait_nop(GLcontext *ctx,
- struct drm_nouveau_notifierobj_alloc *notifier,
- GLuint subc)
-{
- NOTIFIER(n);
- GLboolean ret;
-
- nouveau_notifier_reset(ctx, notifier, 0);
-
- BEGIN_RING_SIZE(subc, NV_NOTIFY, 1);
- OUT_RING (NV_NOTIFY_STYLE_WRITE_ONLY);
- BEGIN_RING_SIZE(subc, NV_NOP, 1);
- OUT_RING (0);
- FIRE_RING();
-
- ret = nouveau_notifier_wait_status(ctx, notifier, 0,
- NV_NOTIFY_STATE_STATUS_COMPLETED,
- 0 /* no timeout */);
- if (ret == GL_FALSE) MESSAGE("wait on notifier failed\n");
-}
-
-GLboolean nouveauSyncInitFuncs(GLcontext *ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
-#ifdef NOUVEAU_RING_DEBUG
- return GL_TRUE;
-#endif
-
- nmesa->syncNotifier = nouveau_notifier_new(ctx, NvSyncNotify, 1);
- if (!nmesa->syncNotifier) {
- MESSAGE("Failed to create channel sync notifier\n");
- return GL_FALSE;
- }
-
- /* 0x180 is SET_DMA_NOTIFY, should be correct for all supported 3D
- * object classes
- */
- BEGIN_RING_CACHE(NvSub3D, 0x180, 1);
- OUT_RING_CACHE (NvSyncNotify);
- BEGIN_RING_SIZE(NvSubMemFormat,
- NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
- OUT_RING (NvSyncNotify);
-
- return GL_TRUE;
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_sync.h b/src/mesa/drivers/dri/nouveau/nouveau_sync.h
deleted file mode 100644
index fc37efbe6b..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_sync.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2007 Ben Skeggs.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef __NOUVEAU_SYNC_H__
-#define __NOUVEAU_SYNC_H__
-
-#define NV_NOTIFIER_SIZE 32
-#define NV_NOTIFY_TIME_0 0x00000000
-#define NV_NOTIFY_TIME_1 0x00000004
-#define NV_NOTIFY_RETURN_VALUE 0x00000008
-#define NV_NOTIFY_STATE 0x0000000C
-#define NV_NOTIFY_STATE_STATUS_MASK 0xFF000000
-#define NV_NOTIFY_STATE_STATUS_SHIFT 24
-#define NV_NOTIFY_STATE_STATUS_COMPLETED 0x00
-#define NV_NOTIFY_STATE_STATUS_IN_PROCESS 0x01
-#define NV_NOTIFY_STATE_ERROR_CODE_MASK 0x0000FFFF
-#define NV_NOTIFY_STATE_ERROR_CODE_SHIFT 0
-
-/* Methods that (hopefully) all objects have */
-#define NV_NOP 0x00000100
-#define NV_NOTIFY 0x00000104
-#define NV_NOTIFY_STYLE_WRITE_ONLY 0
-
-extern struct drm_nouveau_notifierobj_alloc *
-nouveau_notifier_new(GLcontext *, GLuint handle, GLuint count);
-extern void
-nouveau_notifier_destroy(GLcontext *, struct drm_nouveau_notifierobj_alloc *);
-extern void
-nouveau_notifier_reset(GLcontext *, struct drm_nouveau_notifierobj_alloc *,
- GLuint id);
-extern GLuint
-nouveau_notifier_status(GLcontext *, struct drm_nouveau_notifierobj_alloc *,
- GLuint id);
-extern GLuint
-nouveau_notifier_return_val(GLcontext *, struct drm_nouveau_notifierobj_alloc *,
- GLuint id);
-extern GLboolean
-nouveau_notifier_wait_status(GLcontext *, struct drm_nouveau_notifierobj_alloc *,
- GLuint id, GLuint status, GLuint timeout);
-extern void
-nouveau_notifier_wait_nop(GLcontext *ctx, struct drm_nouveau_notifierobj_alloc *,
- GLuint subc);
-
-extern GLboolean nouveauSyncInitFuncs(GLcontext *ctx);
-#endif
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_tex.c b/src/mesa/drivers/dri/nouveau/nouveau_tex.c
deleted file mode 100644
index 0a8d279669..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_tex.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-#include "nouveau_tex.h"
-
-// XXX needs some love
-void nouveauTexInitFunctions( struct dd_function_table *functions )
-{
-/*
- functions->TexEnv = nouveauTexEnv;
- functions->ChooseTextureFormat = nouveauChooseTextureFormat;
- functions->TexImage1D = nouveauTexImage1D;
- functions->TexSubImage1D = nouveauTexSubImage1D;
- functions->TexImage2D = nouveauTexImage2D;
- functions->TexSubImage2D = nouveauTexSubImage2D;
- functions->TexParameter = nouveauTexParameter;
- functions->BindTexture = nouveauBindTexture;
- functions->NewTextureObject = nouveauNewTextureObject;
- functions->DeleteTexture = nouveauDeleteTexture;
- functions->IsTextureResident = driIsTextureResident;
-
- driInitTextureFormats();
-*/
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_tex.h b/src/mesa/drivers/dri/nouveau/nouveau_tex.h
deleted file mode 100644
index 7ac71f8300..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_tex.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-#ifndef __NOUVEAU_TEX_H__
-#define __NOUVEAU_TEX_H__
-
-#include
-#include "mtypes.h"
-#include "macros.h"
-#include "dd.h"
-
-extern void nouveauTexInitFunctions( struct dd_function_table *functions );
-
-#endif /* __NOUVEAU_TEX_H__ */
diff --git a/src/mesa/drivers/dri/nouveau/nv04_state.c b/src/mesa/drivers/dri/nouveau/nv04_state.c
deleted file mode 100644
index d3031aa5b1..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv04_state.c
+++ /dev/null
@@ -1,540 +0,0 @@
-/**************************************************************************
-
-Copyright 2007 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-#include "nouveau_context.h"
-#include "nouveau_object.h"
-#include "nouveau_fifo.h"
-#include "nouveau_reg.h"
-#include "nouveau_msg.h"
-
-#include "tnl/t_pipeline.h"
-
-#include "mtypes.h"
-#include "colormac.h"
-
-static uint32_t nv04_compare_func(GLuint f)
-{
- switch ( f ) {
- case GL_NEVER: return 1;
- case GL_LESS: return 2;
- case GL_EQUAL: return 3;
- case GL_LEQUAL: return 4;
- case GL_GREATER: return 5;
- case GL_NOTEQUAL: return 6;
- case GL_GEQUAL: return 7;
- case GL_ALWAYS: return 8;
- }
- WARN_ONCE("Unable to find the function\n");
- return 0;
-}
-
-static uint32_t nv04_blend_func(GLuint f)
-{
- switch ( f ) {
- case GL_ZERO: return 0x1;
- case GL_ONE: return 0x2;
- case GL_SRC_COLOR: return 0x3;
- case GL_ONE_MINUS_SRC_COLOR: return 0x4;
- case GL_SRC_ALPHA: return 0x5;
- case GL_ONE_MINUS_SRC_ALPHA: return 0x6;
- case GL_DST_ALPHA: return 0x7;
- case GL_ONE_MINUS_DST_ALPHA: return 0x8;
- case GL_DST_COLOR: return 0x9;
- case GL_ONE_MINUS_DST_COLOR: return 0xA;
- case GL_SRC_ALPHA_SATURATE: return 0xB;
- }
- WARN_ONCE("Unable to find the function 0x%x\n",f);
- return 0;
-}
-
-static void nv04_emit_control(GLcontext *ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- uint32_t control,cull;
- GLubyte alpha_ref;
-
- CLAMPED_FLOAT_TO_UBYTE(alpha_ref, ctx->Color.AlphaRef);
- control=alpha_ref;
- control|=(nv04_compare_func(ctx->Color.AlphaFunc)<<8);
- control|=(ctx->Color.AlphaEnabled<<12);
- control|=(1<<13);
- control|=(ctx->Depth.Test<<14);
- control|=(nv04_compare_func(ctx->Depth.Func)<<16);
- if ((ctx->Polygon.CullFlag)&&(ctx->Polygon.CullFaceMode!=GL_FRONT_AND_BACK))
- {
- if ((ctx->Polygon.FrontFace==GL_CW)&&(ctx->Polygon.CullFaceMode==GL_FRONT))
- cull=2;
- if ((ctx->Polygon.FrontFace==GL_CW)&&(ctx->Polygon.CullFaceMode==GL_BACK))
- cull=3;
- if ((ctx->Polygon.FrontFace==GL_CCW)&&(ctx->Polygon.CullFaceMode==GL_FRONT))
- cull=3;
- if ((ctx->Polygon.FrontFace==GL_CCW)&&(ctx->Polygon.CullFaceMode==GL_BACK))
- cull=2;
- }
- else
- if (ctx->Polygon.CullFaceMode==GL_FRONT_AND_BACK)
- cull=0;
- else
- cull=1;
- control|=(cull<<20);
- control|=(ctx->Color.DitherFlag<<22);
- if ((ctx->Depth.Test)&&(ctx->Depth.Mask))
- control|=(1<<24);
-
- control|=(1<<30); // integer zbuffer format
-
- BEGIN_RING_CACHE(NvSub3D, NV04_DX5_TEXTURED_TRIANGLE_CONTROL, 1);
- OUT_RING_CACHE(control);
-}
-
-static void nv04_emit_blend(GLcontext *ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- uint32_t blend;
-
- blend=0x4; // texture MODULATE_ALPHA
- blend|=0x20; // alpha is MSB
- switch(ctx->Light.ShadeModel) {
- case GL_SMOOTH:blend|=(1<<6);break;
- case GL_FLAT: blend|=(2<<6);break;
- default:break;
- }
- if (ctx->Hint.PerspectiveCorrection!=GL_FASTEST)
- blend|=(1<<8);
- blend|=(ctx->Fog.Enabled<<16);
- blend|=(ctx->Color.BlendEnabled<<20);
- blend|=(nv04_blend_func(ctx->Color.BlendSrcRGB)<<24);
- blend|=(nv04_blend_func(ctx->Color.BlendDstRGB)<<28);
-
- BEGIN_RING_CACHE(NvSub3D, NV04_DX5_TEXTURED_TRIANGLE_BLEND, 1);
- OUT_RING_CACHE(blend);
-}
-
-static void nv04_emit_fog_color(GLcontext *ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte c[4];
- c[0] = FLOAT_TO_UBYTE( ctx->Fog.Color[0] );
- c[1] = FLOAT_TO_UBYTE( ctx->Fog.Color[1] );
- c[2] = FLOAT_TO_UBYTE( ctx->Fog.Color[2] );
- c[3] = FLOAT_TO_UBYTE( ctx->Fog.Color[3] );
- BEGIN_RING_CACHE(NvSub3D, NV04_DX5_TEXTURED_TRIANGLE_FOG_COLOR, 1);
- OUT_RING_CACHE(PACK_COLOR_8888_REV(c[0],c[1],c[2],c[3]));
-}
-
-static void nv04AlphaFunc(GLcontext *ctx, GLenum func, GLfloat ref)
-{
- nv04_emit_control(ctx);
-}
-
-static void nv04BlendColor(GLcontext *ctx, const GLfloat color[4])
-{
- nv04_emit_blend(ctx);
-}
-
-static void nv04BlendEquationSeparate(GLcontext *ctx, GLenum modeRGB, GLenum modeA)
-{
- nv04_emit_blend(ctx);
-}
-
-
-static void nv04BlendFuncSeparate(GLcontext *ctx, GLenum sfactorRGB, GLenum dfactorRGB,
- GLenum sfactorA, GLenum dfactorA)
-{
- nv04_emit_blend(ctx);
-}
-
-static void nv04Clear(GLcontext *ctx, GLbitfield mask)
-{
- /* TODO */
-}
-
-static void nv04ClearColor(GLcontext *ctx, const GLfloat color[4])
-{
- /* TODO */
-}
-
-static void nv04ClearDepth(GLcontext *ctx, GLclampd d)
-{
- /* TODO */
-}
-
-static void nv04ClearStencil(GLcontext *ctx, GLint s)
-{
- /* TODO */
-}
-
-static void nv04ClipPlane(GLcontext *ctx, GLenum plane, const GLfloat *equation)
-{
- /* TODO */
-}
-
-static void nv04ColorMask(GLcontext *ctx, GLboolean rmask, GLboolean gmask,
- GLboolean bmask, GLboolean amask )
-{
- /* TODO */
-}
-
-static void nv04ColorMaterial(GLcontext *ctx, GLenum face, GLenum mode)
-{
- /* TODO I need love */
-}
-
-static void nv04CullFace(GLcontext *ctx, GLenum mode)
-{
- nv04_emit_control(ctx);
-}
-
-static void nv04FrontFace(GLcontext *ctx, GLenum mode)
-{
- /* TODO */
-}
-
-static void nv04DepthFunc(GLcontext *ctx, GLenum func)
-{
- nv04_emit_control(ctx);
-}
-
-static void nv04DepthMask(GLcontext *ctx, GLboolean flag)
-{
- /* TODO */
-}
-
-static void nv04DepthRange(GLcontext *ctx, GLclampd nearval, GLclampd farval)
-{
- /* TODO */
-}
-
-/** Specify the current buffer for writing */
-//void (*DrawBuffer)( GLcontext *ctx, GLenum buffer );
-/** Specify the buffers for writing for fragment programs*/
-//void (*DrawBuffers)( GLcontext *ctx, GLsizei n, const GLenum *buffers );
-
-static void nv04Enable(GLcontext *ctx, GLenum cap, GLboolean state)
-{
- switch(cap)
- {
- case GL_ALPHA_TEST:
- nv04_emit_control(ctx);
- break;
-// case GL_AUTO_NORMAL:
- case GL_BLEND:
- nv04_emit_blend(ctx);
- break;
-// case GL_CLIP_PLANE0:
-// case GL_CLIP_PLANE1:
-// case GL_CLIP_PLANE2:
-// case GL_CLIP_PLANE3:
-// case GL_CLIP_PLANE4:
-// case GL_CLIP_PLANE5:
-// case GL_COLOR_LOGIC_OP:
-// case GL_COLOR_MATERIAL:
-// case GL_COLOR_SUM_EXT:
-// case GL_COLOR_TABLE:
-// case GL_CONVOLUTION_1D:
-// case GL_CONVOLUTION_2D:
- case GL_CULL_FACE:
- nv04_emit_control(ctx);
- break;
- case GL_DEPTH_TEST:
- nv04_emit_control(ctx);
- break;
- case GL_DITHER:
- nv04_emit_control(ctx);
- break;
- case GL_FOG:
- nv04_emit_blend(ctx);
- nv04_emit_fog_color(ctx);
- break;
-// case GL_HISTOGRAM:
-// case GL_INDEX_LOGIC_OP:
-// case GL_LIGHT0:
-// case GL_LIGHT1:
-// case GL_LIGHT2:
-// case GL_LIGHT3:
-// case GL_LIGHT4:
-// case GL_LIGHT5:
-// case GL_LIGHT6:
-// case GL_LIGHT7:
-// case GL_LIGHTING:
-// case GL_LINE_SMOOTH:
-// case GL_LINE_STIPPLE:
-// case GL_MAP1_COLOR_4:
-// case GL_MAP1_INDEX:
-// case GL_MAP1_NORMAL:
-// case GL_MAP1_TEXTURE_COORD_1:
-// case GL_MAP1_TEXTURE_COORD_2:
-// case GL_MAP1_TEXTURE_COORD_3:
-// case GL_MAP1_TEXTURE_COORD_4:
-// case GL_MAP1_VERTEX_3:
-// case GL_MAP1_VERTEX_4:
-// case GL_MAP2_COLOR_4:
-// case GL_MAP2_INDEX:
-// case GL_MAP2_NORMAL:
-// case GL_MAP2_TEXTURE_COORD_1:
-// case GL_MAP2_TEXTURE_COORD_2:
-// case GL_MAP2_TEXTURE_COORD_3:
-// case GL_MAP2_TEXTURE_COORD_4:
-// case GL_MAP2_VERTEX_3:
-// case GL_MAP2_VERTEX_4:
-// case GL_MINMAX:
-// case GL_NORMALIZE:
-// case GL_POINT_SMOOTH:
-// case GL_POLYGON_OFFSET_POINT:
-// case GL_POLYGON_OFFSET_LINE:
-// case GL_POLYGON_OFFSET_FILL:
-// case GL_POLYGON_SMOOTH:
-// case GL_POLYGON_STIPPLE:
-// case GL_POST_COLOR_MATRIX_COLOR_TABLE:
-// case GL_POST_CONVOLUTION_COLOR_TABLE:
-// case GL_RESCALE_NORMAL:
-// case GL_SCISSOR_TEST:
-// case GL_SEPARABLE_2D:
-// case GL_STENCIL_TEST:
-// case GL_TEXTURE_GEN_Q:
-// case GL_TEXTURE_GEN_R:
-// case GL_TEXTURE_GEN_S:
-// case GL_TEXTURE_GEN_T:
-// case GL_TEXTURE_1D:
-// case GL_TEXTURE_2D:
-// case GL_TEXTURE_3D:
- }
-}
-
-static void nv04Fogfv(GLcontext *ctx, GLenum pname, const GLfloat *params)
-{
- nv04_emit_blend(ctx);
- nv04_emit_fog_color(ctx);
-}
-
-static void nv04Hint(GLcontext *ctx, GLenum target, GLenum mode)
-{
- switch(target)
- {
- case GL_PERSPECTIVE_CORRECTION_HINT:nv04_emit_blend(ctx);break;
- default:break;
- }
-}
-
-static void nv04LineStipple(GLcontext *ctx, GLint factor, GLushort pattern )
-{
- /* TODO not even in your dreams */
-}
-
-static void nv04LineWidth(GLcontext *ctx, GLfloat width)
-{
- /* TODO */
-}
-
-static void nv04LogicOpcode(GLcontext *ctx, GLenum opcode)
-{
- /* TODO */
-}
-
-static void nv04PointParameterfv(GLcontext *ctx, GLenum pname, const GLfloat *params)
-{
- /* TODO */
-}
-
-static void nv04PointSize(GLcontext *ctx, GLfloat size)
-{
- /* TODO */
-}
-
-static void nv04PolygonMode(GLcontext *ctx, GLenum face, GLenum mode)
-{
- /* TODO */
-}
-
-/** Set the scale and units used to calculate depth values */
-static void nv04PolygonOffset(GLcontext *ctx, GLfloat factor, GLfloat units)
-{
- /* TODO */
-}
-
-/** Set the polygon stippling pattern */
-static void nv04PolygonStipple(GLcontext *ctx, const GLubyte *mask )
-{
- /* TODO */
-}
-
-/* Specifies the current buffer for reading */
-void (*ReadBuffer)( GLcontext *ctx, GLenum buffer );
-/** Set rasterization mode */
-void (*RenderMode)(GLcontext *ctx, GLenum mode );
-
-/** Define the scissor box */
-static void nv04Scissor(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h)
-{
- /* TODO */
-}
-
-/** Select flat or smooth shading */
-static void nv04ShadeModel(GLcontext *ctx, GLenum mode)
-{
- nv04_emit_blend(ctx);
-}
-
-/** OpenGL 2.0 two-sided StencilFunc */
-static void nv04StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func,
- GLint ref, GLuint mask)
-{
- /* TODO */
-}
-
-/** OpenGL 2.0 two-sided StencilMask */
-static void nv04StencilMaskSeparate(GLcontext *ctx, GLenum face, GLuint mask)
-{
- /* TODO */
-}
-
-/** OpenGL 2.0 two-sided StencilOp */
-static void nv04StencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail,
- GLenum zfail, GLenum zpass)
-{
- /* TODO */
-}
-
-/** Control the generation of texture coordinates */
-void (*TexGen)(GLcontext *ctx, GLenum coord, GLenum pname,
- const GLfloat *params);
-/** Set texture environment parameters */
-void (*TexEnv)(GLcontext *ctx, GLenum target, GLenum pname,
- const GLfloat *param);
-/** Set texture parameters */
-void (*TexParameter)(GLcontext *ctx, GLenum target,
- struct gl_texture_object *texObj,
- GLenum pname, const GLfloat *params);
-
-/* Update anything that depends on the window position/size */
-static void nv04WindowMoved(nouveauContextPtr nmesa)
-{
-}
-
-/* Initialise any card-specific non-GL related state */
-static GLboolean nv04InitCard(nouveauContextPtr nmesa)
-{
- nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D);
- nouveauObjectOnSubchannel(nmesa, NvSubCtxSurf3D, NvCtxSurf3D);
-
- BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_DMA_NOTIFY, 3);
- OUT_RING(NvDmaFB);
- OUT_RING(NvDmaFB);
- OUT_RING(NvDmaFB);
- BEGIN_RING_SIZE(NvSub3D, NV04_DX5_TEXTURED_TRIANGLE_SURFACE, 1);
- OUT_RING(NvCtxSurf3D);
- return GL_TRUE;
-}
-
-/* Update buffer offset/pitch/format */
-static GLboolean nv04BindBuffers(nouveauContextPtr nmesa, int num_color,
- nouveau_renderbuffer_t **color,
- nouveau_renderbuffer_t *depth)
-{
- GLuint x, y, w, h;
- uint32_t depth_pitch=(depth?depth->pitch:0+15)&~15+16;
- if (depth_pitch<256) depth_pitch=256;
-
- w = color[0]->mesa.Width;
- h = color[0]->mesa.Height;
- x = nmesa->drawX;
- y = nmesa->drawY;
-
- BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_FORMAT, 1);
- if (color[0]->mesa._ActualFormat == GL_RGBA8)
- OUT_RING(0x108/*A8R8G8B8*/);
- else
- OUT_RING(0x103/*R5G6B5*/);
-
- /* FIXME pitches have to be aligned ! */
- BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_PITCH, 2);
- OUT_RING(color[0]->pitch|(depth_pitch<<16));
- OUT_RING(color[0]->offset);
- if (depth) {
- BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA, 1);
- OUT_RING(depth->offset);
- }
-
-// BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL, 2);
-// OUT_RING((w<<16)|x);
-// OUT_RING((h<<16)|y);
-
-
- /* FIXME not sure... */
-/* BEGIN_RING_SIZE(NvSubCtxSurf3D, NV04_CONTEXT_SURFACES_3D_CLIP_SIZE, 1);
- OUT_RING((h<<16)|w);*/
-
- return GL_TRUE;
-}
-
-void nv04InitStateFuncs(GLcontext *ctx, struct dd_function_table *func)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- func->AlphaFunc = nv04AlphaFunc;
- func->BlendColor = nv04BlendColor;
- func->BlendEquationSeparate = nv04BlendEquationSeparate;
- func->BlendFuncSeparate = nv04BlendFuncSeparate;
- func->Clear = nv04Clear;
- func->ClearColor = nv04ClearColor;
- func->ClearDepth = nv04ClearDepth;
- func->ClearStencil = nv04ClearStencil;
- func->ClipPlane = nv04ClipPlane;
- func->ColorMask = nv04ColorMask;
- func->ColorMaterial = nv04ColorMaterial;
- func->CullFace = nv04CullFace;
- func->FrontFace = nv04FrontFace;
- func->DepthFunc = nv04DepthFunc;
- func->DepthMask = nv04DepthMask;
- func->DepthRange = nv04DepthRange;
- func->Enable = nv04Enable;
- func->Fogfv = nv04Fogfv;
- func->Hint = nv04Hint;
-/* func->Lightfv = nv04Lightfv;*/
-/* func->LightModelfv = nv04LightModelfv; */
- func->LineStipple = nv04LineStipple; /* Not for NV04 */
- func->LineWidth = nv04LineWidth;
- func->LogicOpcode = nv04LogicOpcode;
- func->PointParameterfv = nv04PointParameterfv;
- func->PointSize = nv04PointSize;
- func->PolygonMode = nv04PolygonMode;
- func->PolygonOffset = nv04PolygonOffset;
- func->PolygonStipple = nv04PolygonStipple; /* Not for NV04 */
-/* func->ReadBuffer = nv04ReadBuffer;*/
-/* func->RenderMode = nv04RenderMode;*/
- func->Scissor = nv04Scissor;
- func->ShadeModel = nv04ShadeModel;
- func->StencilFuncSeparate = nv04StencilFuncSeparate;
- func->StencilMaskSeparate = nv04StencilMaskSeparate;
- func->StencilOpSeparate = nv04StencilOpSeparate;
-/* func->TexGen = nv04TexGen;*/
-/* func->TexParameter = nv04TexParameter;*/
-/* func->TextureMatrix = nv04TextureMatrix;*/
-
- nmesa->hw_func.InitCard = nv04InitCard;
- nmesa->hw_func.BindBuffers = nv04BindBuffers;
- nmesa->hw_func.WindowMoved = nv04WindowMoved;
-}
diff --git a/src/mesa/drivers/dri/nouveau/nv04_swtcl.c b/src/mesa/drivers/dri/nouveau/nv04_swtcl.c
deleted file mode 100644
index 1b73d0be6f..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv04_swtcl.c
+++ /dev/null
@@ -1,619 +0,0 @@
-/*
- * Copyright 2007 Stephane Marchesin. All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/* Software TCL for NV04, NV05, NV06 */
-
-#include
-#include
-
-#include "glheader.h"
-#include "context.h"
-#include "mtypes.h"
-#include "macros.h"
-#include "colormac.h"
-#include "enums.h"
-
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "tnl/t_context.h"
-#include "tnl/t_pipeline.h"
-
-#include "nouveau_swtcl.h"
-#include "nv04_swtcl.h"
-#include "nouveau_context.h"
-#include "nouveau_span.h"
-#include "nouveau_reg.h"
-#include "nouveau_tex.h"
-#include "nouveau_fifo.h"
-#include "nouveau_msg.h"
-#include "nouveau_object.h"
-
-static void nv04RasterPrimitive( GLcontext *ctx, GLenum rprim, GLuint hwprim );
-static void nv04RenderPrimitive( GLcontext *ctx, GLenum prim );
-static void nv04ResetLineStipple( GLcontext *ctx );
-
-
-static INLINE void nv04_2triangles(struct nouveau_context *nmesa,nouveauVertex* v0,nouveauVertex* v1,nouveauVertex* v2,nouveauVertex* v3,nouveauVertex* v4,nouveauVertex* v5)
-{
- BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0xA),49);
- OUT_RINGp(v0,8);
- OUT_RINGp(v1,8);
- OUT_RINGp(v2,8);
- OUT_RINGp(v3,8);
- OUT_RINGp(v4,8);
- OUT_RINGp(v5,8);
- OUT_RING(0xFEDCBA);
-}
-
-static INLINE void nv04_1triangle(struct nouveau_context *nmesa,nouveauVertex* v0,nouveauVertex* v1,nouveauVertex* v2)
-{
- BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0xD),25);
- OUT_RINGp(v0,8);
- OUT_RINGp(v1,8);
- OUT_RINGp(v2,8);
- OUT_RING(0xFED);
-}
-
-static INLINE void nv04_1quad(struct nouveau_context *nmesa,nouveauVertex* v0,nouveauVertex* v1,nouveauVertex* v2,nouveauVertex* v3)
-{
- BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0xC),33);
- OUT_RINGp(v0,8);
- OUT_RINGp(v1,8);
- OUT_RINGp(v2,8);
- OUT_RINGp(v3,8);
- OUT_RING(0xFECEDC);
-}
-
-static INLINE void nv04_render_points(GLcontext *ctx,GLuint first,GLuint last)
-{
- WARN_ONCE("Unimplemented\n");
-}
-
-static INLINE void nv04_render_line(GLcontext *ctx,GLuint v1,GLuint v2)
-{
- WARN_ONCE("Unimplemented\n");
-}
-
-static INLINE void nv04_render_triangle(GLcontext *ctx,GLuint v1,GLuint v2,GLuint v3)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte *vertptr = (GLubyte *)nmesa->verts;
- GLuint vertsize = nmesa->vertex_size;
-
- nv04_1triangle(nmesa,
- (nouveauVertex*)(vertptr+v1*vertsize),
- (nouveauVertex*)(vertptr+v2*vertsize),
- (nouveauVertex*)(vertptr+v3*vertsize)
- );
-}
-
-static INLINE void nv04_render_quad(GLcontext *ctx,GLuint v1,GLuint v2,GLuint v3,GLuint v4)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte *vertptr = (GLubyte *)nmesa->verts;
- GLuint vertsize = nmesa->vertex_size;
-
- nv04_1quad(nmesa,
- (nouveauVertex*)(vertptr+v1*vertsize),
- (nouveauVertex*)(vertptr+v2*vertsize),
- (nouveauVertex*)(vertptr+v3*vertsize),
- (nouveauVertex*)(vertptr+v4*vertsize)
- );
-}
-
-/**********************************************************************/
-/* Render unclipped begin/end objects */
-/**********************************************************************/
-
-static void nv04_render_points_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- // erm
-}
-
-static void nv04_render_lines_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- // umm
-}
-
-static void nv04_render_line_strip_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- // yeah
-}
-
-static void nv04_render_line_loop_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- // right
-}
-
-static void nv04_render_triangles_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte *vertptr = (GLubyte *)nmesa->verts;
- GLuint vertsize = nmesa->vertex_size;
- int i;
-
- for(i=start;iverts;
- GLuint vertsize = nmesa->vertex_size;
- uint32_t striptbl[]={0x321210,0x543432,0x765654,0x987876,0xBA9A98,0xDCBCBA,0xFEDEDC};
- int i,j;
-
- for(i=start;iverts;
- GLuint vertsize = nmesa->vertex_size;
- uint32_t fantbl[]={0x320210,0x540430,0x760650,0x980870,0xBA0A90,0xDC0CB0,0xFE0ED0};
- int i,j;
-
- BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0),8);
- OUT_RINGp((nouveauVertex*)(vertptr+start*vertsize),8);
-
- for(i=start+1;iverts;
- GLuint vertsize = nmesa->vertex_size;
- int i;
-
- for(i=start;iverts;
- GLuint vertsize = nmesa->vertex_size;
- const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;
- int i;
-
- for(i=start;iverts;
- GLuint vertsize = nmesa->vertex_size;
- uint32_t striptbl[]={0x321210,0x543432,0x765654,0x987876,0xBA9A98,0xDCBCBA,0xFEDEDC};
- const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;
- int i,j;
-
- for(i=start;iverts;
- GLuint vertsize = nmesa->vertex_size;
- uint32_t fantbl[]={0x320210,0x540430,0x760650,0x980870,0xBA0A90,0xDC0CB0,0xFE0ED0};
- const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;
- int i,j;
-
- BEGIN_RING_SIZE(NvSub3D,NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(0x0),8);
- OUT_RINGp((nouveauVertex*)(vertptr+elt[start]*vertsize),8);
-
- for(i=start+1;iverts;
- GLuint vertsize = nmesa->vertex_size;
- const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;
- int i;
-
- for(i=start;ivertex_attrs[nmesa->vertex_attr_count].attrib = (ATTR); \
- nmesa->vertex_attrs[nmesa->vertex_attr_count].format = (STYLE); \
- nmesa->vertex_attr_count++; \
-} while (0)
-
-#define EMIT_PAD( N ) \
-do { \
- nmesa->vertex_attrs[nmesa->vertex_attr_count].attrib = 0; \
- nmesa->vertex_attrs[nmesa->vertex_attr_count].format = EMIT_PAD; \
- nmesa->vertex_attrs[nmesa->vertex_attr_count].offset = (N); \
- nmesa->vertex_attr_count++; \
-} while (0)
-
-static void nv04_render_clipped_line(GLcontext *ctx,GLuint ii,GLuint jj)
-{
-}
-
-static void nv04_render_clipped_poly(GLcontext *ctx,const GLuint *elts,GLuint n)
-{
-}
-
-static void nv04ChooseRenderState(GLcontext *ctx)
-{
- TNLcontext *tnl = TNL_CONTEXT(ctx);
-
- tnl->Driver.Render.PrimTabVerts = nv04_render_tab_verts;
- tnl->Driver.Render.PrimTabElts = nv04_render_tab_elts;
- tnl->Driver.Render.ClippedLine = nv04_render_clipped_line;
- tnl->Driver.Render.ClippedPolygon = nv04_render_clipped_poly;
- tnl->Driver.Render.Points = nv04_render_points;
- tnl->Driver.Render.Line = nv04_render_line;
- tnl->Driver.Render.Triangle = nv04_render_triangle;
- tnl->Driver.Render.Quad = nv04_render_quad;
-}
-
-
-
-static INLINE void nv04OutputVertexFormat(struct nouveau_context* nmesa)
-{
- GLcontext* ctx=nmesa->glCtx;
- DECLARE_RENDERINPUTS(index);
-
- /*
- * Tell t_vertex about the vertex format
- */
- nmesa->vertex_attr_count = 0;
- RENDERINPUTS_COPY(index, nmesa->render_inputs_bitset);
-
- // SX SY SZ INVW
- // FIXME : we use W instead of INVW, but since W=1 it doesn't matter
- if (RENDERINPUTS_TEST(index, _TNL_ATTRIB_POS))
- EMIT_ATTR(_TNL_ATTRIB_POS,EMIT_4F_VIEWPORT);
- else
- EMIT_PAD(4*sizeof(float));
-
- // COLOR
- if (RENDERINPUTS_TEST(index, _TNL_ATTRIB_COLOR0))
- EMIT_ATTR(_TNL_ATTRIB_COLOR0,EMIT_4UB_4F_ABGR);
- else
- EMIT_PAD(4);
-
- // SPECULAR
- if (RENDERINPUTS_TEST(index, _TNL_ATTRIB_COLOR1))
- EMIT_ATTR(_TNL_ATTRIB_COLOR1,EMIT_4UB_4F_ABGR);
- else
- EMIT_PAD(4);
-
- // TEXTURE
- if (RENDERINPUTS_TEST(index, _TNL_ATTRIB_TEX0))
- EMIT_ATTR(_TNL_ATTRIB_TEX0,EMIT_2F);
- else
- EMIT_PAD(2*sizeof(float));
-
- nmesa->vertex_size=_tnl_install_attrs( ctx,
- nmesa->vertex_attrs,
- nmesa->vertex_attr_count,
- nmesa->viewport.m, 0 );
-}
-
-
-static void nv04ChooseVertexState( GLcontext *ctx )
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- DECLARE_RENDERINPUTS(index);
-
- RENDERINPUTS_COPY(index, tnl->render_inputs_bitset);
- if (!RENDERINPUTS_EQUAL(index, nmesa->render_inputs_bitset))
- {
- RENDERINPUTS_COPY(nmesa->render_inputs_bitset, index);
- nv04OutputVertexFormat(nmesa);
- }
-}
-
-
-/**********************************************************************/
-/* High level hooks for t_vb_render.c */
-/**********************************************************************/
-
-
-static void nv04RenderStart(GLcontext *ctx)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (nmesa->new_state) {
- nmesa->new_render_state |= nmesa->new_state;
- }
-
- if (nmesa->new_render_state) {
- nv04ChooseVertexState(ctx);
- nv04ChooseRenderState(ctx);
- nmesa->new_render_state = 0;
- }
-}
-
-static void nv04RenderFinish(GLcontext *ctx)
-{
-}
-
-
-/* System to flush dma and emit state changes based on the rasterized
- * primitive.
- */
-void nv04RasterPrimitive(GLcontext *ctx,
- GLenum glprim,
- GLuint hwprim)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
-
- assert (!nmesa->new_state);
-
- if (hwprim != nmesa->current_primitive)
- {
- nmesa->current_primitive=hwprim;
-
- }
-}
-
-static const GLuint hw_prim[GL_POLYGON+1] = {
- GL_POINTS+1,
- GL_LINES+1,
- GL_LINE_STRIP+1,
- GL_LINE_LOOP+1,
- GL_TRIANGLES+1,
- GL_TRIANGLE_STRIP+1,
- GL_TRIANGLE_FAN+1,
- GL_QUADS+1,
- GL_QUAD_STRIP+1,
- GL_POLYGON+1
-};
-
-/* Callback for mesa:
- */
-static void nv04RenderPrimitive( GLcontext *ctx, GLuint prim )
-{
- nv04RasterPrimitive( ctx, prim, hw_prim[prim] );
-}
-
-static void nv04ResetLineStipple( GLcontext *ctx )
-{
- /* FIXME do something here */
- WARN_ONCE("Unimplemented nv04ResetLineStipple\n");
-}
-
-
-/**********************************************************************/
-/* Initialization. */
-/**********************************************************************/
-
-void nv04TriInitFunctions(GLcontext *ctx)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- TNLcontext *tnl = TNL_CONTEXT(ctx);
-
- tnl->Driver.RunPipeline = nouveauRunPipeline;
- tnl->Driver.Render.Start = nv04RenderStart;
- tnl->Driver.Render.Finish = nv04RenderFinish;
- tnl->Driver.Render.PrimitiveNotify = nv04RenderPrimitive;
- tnl->Driver.Render.ResetLineStipple = nv04ResetLineStipple;
- tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
- tnl->Driver.Render.CopyPV = _tnl_copy_pv;
- tnl->Driver.Render.Interp = _tnl_interp;
-
- _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 32 );
-
- nmesa->verts = (GLubyte *)tnl->clipspace.vertex_buf;
-}
-
-
diff --git a/src/mesa/drivers/dri/nouveau/nv04_swtcl.h b/src/mesa/drivers/dri/nouveau/nv04_swtcl.h
deleted file mode 100644
index 42dde5383e..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv04_swtcl.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __NV04_SWTCL_H__
-#define __NV04_SWTCL_H__
-
-#include "mtypes.h"
-
-extern void nv04Fallback( GLcontext *ctx, GLuint bit, GLboolean mode );
-extern void nv04FinishPrimitive(struct nouveau_context *nmesa);
-extern void nv04TriInitFunctions(GLcontext *ctx);
-#define FALLBACK( nmesa, bit, mode ) nouveauFallback( nmesa->glCtx, bit, mode )
-
-#endif /* __NV04_SWTCL_H__ */
-
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state.c b/src/mesa/drivers/dri/nouveau/nv10_state.c
deleted file mode 100644
index 3e5bfe093f..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv10_state.c
+++ /dev/null
@@ -1,1009 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Nouveau
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-#include "nouveau_context.h"
-#include "nouveau_object.h"
-#include "nouveau_fifo.h"
-#include "nouveau_reg.h"
-
-#include "tnl/t_pipeline.h"
-
-#include "mtypes.h"
-#include "colormac.h"
-
-static void nv10ViewportScale(nouveauContextPtr nmesa)
-{
- GLcontext *ctx = nmesa->glCtx;
- GLfloat w = ((GLfloat) ctx->Viewport.Width) * 0.5;
- GLfloat h = ((GLfloat) ctx->Viewport.Height) * 0.5;
- GLfloat max_depth = (ctx->Viewport.Near + ctx->Viewport.Far) * 0.5;
-
- if (ctx->DrawBuffer) {
- if (ctx->DrawBuffer->_DepthBuffer) {
- switch (ctx->DrawBuffer->_DepthBuffer->DepthBits) {
- case 16:
- max_depth *= 32767.0;
- break;
- case 24:
- max_depth *= 16777215.0;
- break;
- }
- }
- }
-
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_X, 4);
- OUT_RINGf (w - 2048.0);
- OUT_RINGf (h - 2048.0);
- OUT_RINGf (max_depth);
- OUT_RINGf (0.0);
-}
-
-static void nv10AlphaFunc(GLcontext *ctx, GLenum func, GLfloat ref)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte ubRef;
- CLAMPED_FLOAT_TO_UBYTE(ubRef, ref);
-
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC, 2);
- OUT_RING_CACHE(func);
- OUT_RING_CACHE(ubRef);
-}
-
-static void nv10BlendColor(GLcontext *ctx, const GLfloat color[4])
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte cf[4];
-
- CLAMPED_FLOAT_TO_UBYTE(cf[0], color[0]);
- CLAMPED_FLOAT_TO_UBYTE(cf[1], color[1]);
- CLAMPED_FLOAT_TO_UBYTE(cf[2], color[2]);
- CLAMPED_FLOAT_TO_UBYTE(cf[3], color[3]);
-
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_BLEND_COLOR, 1);
- OUT_RING_CACHE(PACK_COLOR_8888(cf[3], cf[1], cf[2], cf[0]));
-}
-
-static void nv10BlendEquationSeparate(GLcontext *ctx, GLenum modeRGB, GLenum modeA)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- assert( modeRGB == modeA );
-
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_BLEND_EQUATION, 1);
- OUT_RING_CACHE(modeRGB);
-}
-
-
-static void nv10BlendFuncSeparate(GLcontext *ctx, GLenum sfactorRGB, GLenum dfactorRGB,
- GLenum sfactorA, GLenum dfactorA)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- assert( sfactorRGB == sfactorA );
- assert( dfactorRGB == dfactorA );
-
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC, 2);
- OUT_RING_CACHE(sfactorRGB);
- OUT_RING_CACHE(dfactorRGB);
-}
-
-static void nv10ClearColor(GLcontext *ctx, const GLfloat color[4])
-{
- /* Not for NV10 */
-}
-
-static void nv10ClearDepth(GLcontext *ctx, GLclampd d)
-{
- /* Not for NV10 */
-}
-
-static void nv10ClearStencil(GLcontext *ctx, GLint s)
-{
- /* Not for NV10 */
-}
-
-static void nv10ClipPlane(GLcontext *ctx, GLenum plane, const GLfloat *equation)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_A(plane - GL_CLIP_PLANE0), 4);
- OUT_RING_CACHEf(equation[0]);
- OUT_RING_CACHEf(equation[1]);
- OUT_RING_CACHEf(equation[2]);
- OUT_RING_CACHEf(equation[3]);
-}
-
-static void nv10ColorMask(GLcontext *ctx, GLboolean rmask, GLboolean gmask,
- GLboolean bmask, GLboolean amask )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_COLOR_MASK, 1);
- OUT_RING_CACHE(((amask && 0x01) << 24) | ((rmask && 0x01) << 16) | ((gmask && 0x01)<< 8) | ((bmask && 0x01) << 0));
-}
-
-static void nv10ColorMaterial(GLcontext *ctx, GLenum face, GLenum mode)
-{
- /* TODO I need love */
-}
-
-static void nv10CullFace(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_CULL_FACE, 1);
- OUT_RING_CACHE(mode);
-}
-
-static void nv10FrontFace(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FRONT_FACE, 1);
- OUT_RING_CACHE(mode);
-}
-
-static void nv10DepthFunc(GLcontext *ctx, GLenum func)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DEPTH_FUNC, 1);
- OUT_RING_CACHE(func);
-}
-
-static void nv10DepthMask(GLcontext *ctx, GLboolean flag)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE, 1);
- OUT_RING_CACHE(flag);
-}
-
-static void nv10DepthRange(GLcontext *ctx, GLclampd nearval, GLclampd farval)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- GLfloat depth_scale = 16777216.0;
- if (ctx->DrawBuffer) {
- if (ctx->DrawBuffer->_DepthBuffer) {
- if (ctx->DrawBuffer->_DepthBuffer->DepthBits == 16) {
- depth_scale = 32768.0;
- }
- }
- }
-
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR, 2);
- OUT_RING_CACHEf(nearval * depth_scale);
- OUT_RING_CACHEf(farval * depth_scale);
-
- nv10ViewportScale(nmesa);
-}
-
-/** Specify the current buffer for writing */
-//void (*DrawBuffer)( GLcontext *ctx, GLenum buffer );
-/** Specify the buffers for writing for fragment programs*/
-//void (*DrawBuffers)( GLcontext *ctx, GLsizei n, const GLenum *buffers );
-
-static void nv10Enable(GLcontext *ctx, GLenum cap, GLboolean state)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- switch(cap)
- {
- case GL_ALPHA_TEST:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_AUTO_NORMAL:
- case GL_BLEND:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_CLIP_PLANE0:
- case GL_CLIP_PLANE1:
- case GL_CLIP_PLANE2:
- case GL_CLIP_PLANE3:
- case GL_CLIP_PLANE4:
- case GL_CLIP_PLANE5:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(cap-GL_CLIP_PLANE0), 1);
- OUT_RING_CACHE(state);
- break;
- case GL_COLOR_LOGIC_OP:
- if (nmesa->screen->card->type >= NV_11) {
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE, 1);
- OUT_RING_CACHE(state);
- }
- break;
-// case GL_COLOR_MATERIAL:
-// case GL_COLOR_SUM_EXT:
-// case GL_COLOR_TABLE:
-// case GL_CONVOLUTION_1D:
-// case GL_CONVOLUTION_2D:
- case GL_CULL_FACE:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_DEPTH_TEST:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_DITHER:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DITHER_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_FOG:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FOG_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_HISTOGRAM:
-// case GL_INDEX_LOGIC_OP:
-#if 0
- /* light is broken, the hardware seem to only allow to use light
- * in order : ie GL_LIGHT0 & GL_LIGHT2 is invalid
- * In this case the blob remap GL_LIGHT2 to hw light 1
- */
- case GL_LIGHT0:
- case GL_LIGHT1:
- case GL_LIGHT2:
- case GL_LIGHT3:
- case GL_LIGHT4:
- case GL_LIGHT5:
- case GL_LIGHT6:
- case GL_LIGHT7:
- {
- uint32_t mask=1<<(2*(cap-GL_LIGHT0));
- if (state)
- nmesa->enabled_lights |= mask;
- else
- nmesa->enabled_lights &= ~mask;
-
- if (nmesa->lighting_enabled)
- {
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1);
- OUT_RING_CACHE(nmesa->enabled_lights);
- }
- break;
- }
- case GL_LIGHTING:
- nmesa->lighting_enabled=state;
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1);
- if (nmesa->lighting_enabled)
- OUT_RING_CACHE(nmesa->enabled_lights);
- else
- OUT_RING_CACHE(0x0);
- break;
-#endif
- case GL_LINE_SMOOTH:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_LINE_STIPPLE:
-// case GL_MAP1_COLOR_4:
-// case GL_MAP1_INDEX:
-// case GL_MAP1_NORMAL:
-// case GL_MAP1_TEXTURE_COORD_1:
-// case GL_MAP1_TEXTURE_COORD_2:
-// case GL_MAP1_TEXTURE_COORD_3:
-// case GL_MAP1_TEXTURE_COORD_4:
-// case GL_MAP1_VERTEX_3:
-// case GL_MAP1_VERTEX_4:
-// case GL_MAP2_COLOR_4:
-// case GL_MAP2_INDEX:
-// case GL_MAP2_NORMAL:
-// case GL_MAP2_TEXTURE_COORD_1:
-// case GL_MAP2_TEXTURE_COORD_2:
-// case GL_MAP2_TEXTURE_COORD_3:
-// case GL_MAP2_TEXTURE_COORD_4:
-// case GL_MAP2_VERTEX_3:
-// case GL_MAP2_VERTEX_4:
-// case GL_MINMAX:
- case GL_NORMALIZE:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_POINT_SMOOTH:
- case GL_POLYGON_OFFSET_POINT:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_OFFSET_LINE:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_OFFSET_FILL:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_SMOOTH:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_POLYGON_STIPPLE:
-// case GL_POST_COLOR_MATRIX_COLOR_TABLE:
-// case GL_POST_CONVOLUTION_COLOR_TABLE:
-// case GL_RESCALE_NORMAL:
-// case GL_SCISSOR_TEST:
-// case GL_SEPARABLE_2D:
- case GL_STENCIL_TEST:
- // TODO BACK and FRONT ?
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_STENCIL_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_TEXTURE_GEN_Q:
-// case GL_TEXTURE_GEN_R:
-// case GL_TEXTURE_GEN_S:
-// case GL_TEXTURE_GEN_T:
-// case GL_TEXTURE_1D:
-// case GL_TEXTURE_2D:
-// case GL_TEXTURE_3D:
- }
-}
-
-static void nv10Fogfv(GLcontext *ctx, GLenum pname, const GLfloat *params)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte cf[4];
- switch(pname)
- {
- case GL_FOG_MODE:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FOG_MODE, 1);
- OUT_RING_CACHE (ctx->Fog.Mode); /* can we extract it from params ??? */
- break;
- case GL_FOG_COLOR:
- CLAMPED_FLOAT_TO_UBYTE(cf[0], params[0]);
- CLAMPED_FLOAT_TO_UBYTE(cf[1], params[1]);
- CLAMPED_FLOAT_TO_UBYTE(cf[2], params[2]);
- CLAMPED_FLOAT_TO_UBYTE(cf[3], params[3]);
-
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FOG_COLOR, 1);
- OUT_RING_CACHE(PACK_COLOR_8888(cf[3], cf[1], cf[2], cf[0]));
- break;
- /* TODO: unsure about the rest.*/
- default:
- break;
- }
-
-}
-
-static void nv10Hint(GLcontext *ctx, GLenum target, GLenum mode)
-{
- /* TODO I need love (fog and line_smooth hints) */
-}
-
-// void (*IndexMask)(GLcontext *ctx, GLuint mask);
-
-enum {
- SPOTLIGHT_NO_UPDATE,
- SPOTLIGHT_UPDATE_EXPONENT,
- SPOTLIGHT_UPDATE_DIRECTION,
- SPOTLIGHT_UPDATE_ALL
-};
-
-static void nv10Lightfv(GLcontext *ctx, GLenum light, GLenum pname, const GLfloat *params )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLint p = light - GL_LIGHT0;
- struct gl_light *l = &ctx->Light.Light[p];
- int spotlight_update = SPOTLIGHT_NO_UPDATE;
-
- switch(pname)
- {
- case GL_AMBIENT:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_DIFFUSE:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_SPECULAR:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_POSITION:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_SPOT_DIRECTION:
- spotlight_update = SPOTLIGHT_UPDATE_DIRECTION;
- break;
- case GL_SPOT_EXPONENT:
- spotlight_update = SPOTLIGHT_UPDATE_EXPONENT;
- break;
- case GL_SPOT_CUTOFF:
- spotlight_update = SPOTLIGHT_UPDATE_ALL;
- break;
- case GL_CONSTANT_ATTENUATION:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(p), 1);
- OUT_RING_CACHEf(*params);
- break;
- case GL_LINEAR_ATTENUATION:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(p), 1);
- OUT_RING_CACHEf(*params);
- break;
- case GL_QUADRATIC_ATTENUATION:
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(p), 1);
- OUT_RING_CACHEf(*params);
- break;
- default:
- break;
- }
-
- switch(spotlight_update) {
- case SPOTLIGHT_UPDATE_DIRECTION:
- {
- GLfloat x,y,z;
- GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0);
- x = spot_light_coef_a * l->_NormDirection[0];
- y = spot_light_coef_a * l->_NormDirection[1];
- z = spot_light_coef_a * l->_NormDirection[2];
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(p), 3);
- OUT_RING_CACHEf(x);
- OUT_RING_CACHEf(y);
- OUT_RING_CACHEf(z);
- }
- break;
- case SPOTLIGHT_UPDATE_EXPONENT:
- {
- GLfloat cc,lc,qc;
- cc = 1.0; /* FIXME: These need to be correctly computed */
- lc = 0.0;
- qc = 2.0;
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 3);
- OUT_RING_CACHEf(cc);
- OUT_RING_CACHEf(lc);
- OUT_RING_CACHEf(qc);
- }
- break;
- case SPOTLIGHT_UPDATE_ALL:
- {
- GLfloat cc,lc,qc, x,y,z, c;
- GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0);
- cc = 1.0; /* FIXME: These need to be correctly computed */
- lc = 0.0;
- qc = 2.0;
- x = spot_light_coef_a * l->_NormDirection[0];
- y = spot_light_coef_a * l->_NormDirection[1];
- z = spot_light_coef_a * l->_NormDirection[2];
- c = spot_light_coef_a + 1.0;
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 7);
- OUT_RING_CACHEf(cc);
- OUT_RING_CACHEf(lc);
- OUT_RING_CACHEf(qc);
- OUT_RING_CACHEf(x);
- OUT_RING_CACHEf(y);
- OUT_RING_CACHEf(z);
- OUT_RING_CACHEf(c);
- }
- break;
- default:
- break;
- }
-}
-
-/** Set the lighting model parameters */
-static void (*LightModelfv)(GLcontext *ctx, GLenum pname, const GLfloat *params);
-
-
-static void nv10LineStipple(GLcontext *ctx, GLint factor, GLushort pattern )
-{
- /* Not for NV10 */
-}
-
-static void nv10LineWidth(GLcontext *ctx, GLfloat width)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LINE_WIDTH, 1);
- OUT_RING_CACHE(((int) (width * 8.0)) & -4);
-}
-
-static void nv10LogicOpcode(GLcontext *ctx, GLenum opcode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (nmesa->screen->card->type < NV_11) {
- return;
- }
-
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP, 1);
- OUT_RING_CACHE(opcode);
-}
-
-static void nv10PointParameterfv(GLcontext *ctx, GLenum pname, const GLfloat *params)
-{
- /*TODO: not sure what goes here. */
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
-}
-
-static void nv10PointSize(GLcontext *ctx, GLfloat size)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POINT_SIZE, 1);
- OUT_RING_CACHE(((int) (size * 8.0)) & -4);
-}
-
-static void nv10PolygonMode(GLcontext *ctx, GLenum face, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (face == GL_FRONT || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT, 1);
- OUT_RING_CACHE(mode);
- }
- if (face == GL_BACK || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK, 1);
- OUT_RING_CACHE(mode);
- }
-}
-
-/** Set the scale and units used to calculate depth values */
-static void nv10PolygonOffset(GLcontext *ctx, GLfloat factor, GLfloat units)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR, 2);
- OUT_RING_CACHEf(factor);
- OUT_RING_CACHEf(units);
-}
-
-/** Set the polygon stippling pattern */
-static void nv10PolygonStipple(GLcontext *ctx, const GLubyte *mask )
-{
- /* Not for NV10 */
-}
-
-/* Specifies the current buffer for reading */
-void (*ReadBuffer)( GLcontext *ctx, GLenum buffer );
-/** Set rasterization mode */
-void (*RenderMode)(GLcontext *ctx, GLenum mode );
-
-/* Translate GL coords to window coords, clamping w/h to the
- * dimensions of the window.
- */
-static void nv10WindowCoords(nouveauContextPtr nmesa,
- GLuint x, GLuint y, GLuint w, GLuint h,
- GLuint *wX, GLuint *wY, GLuint *wW, GLuint *wH)
-{
- if ((x+w) > nmesa->drawW)
- w = nmesa->drawW - x;
- (*wX) = x + nmesa->drawX;
- (*wW) = w;
-
- if ((y+h) > nmesa->drawH)
- h = nmesa->drawH - y;
- (*wY) = (nmesa->drawH - y) - h + nmesa->drawY;
- (*wH) = h;
-}
-
-/** Define the scissor box */
-static void nv10Scissor(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLuint wX, wY, wW, wH;
-
- /* There's no scissor enable bit, so adjust the scissor to cover the
- * maximum draw buffer bounds
- */
- if (!ctx->Scissor.Enabled) {
- wX = nmesa->drawX;
- wY = nmesa->drawY;
- wW = nmesa->drawW;
- wH = nmesa->drawH;
- } else {
- nv10WindowCoords(nmesa, x, y, w, h, &wX, &wY, &wW, &wH);
- }
-
- if (!wW || !wH) {
- return;
- }
-
- BEGIN_RING_SIZE(NvSub3D,
- NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(0), 1);
- OUT_RING(((wW+wX-1) << 16) | wX | 0x08000800);
- BEGIN_RING_SIZE(NvSub3D,
- NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(0), 1);
- OUT_RING(((wH+wY-1) << 16) | wY | 0x08000800);
-}
-
-/** Select flat or smooth shading */
-static void nv10ShadeModel(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_SHADE_MODEL, 1);
- OUT_RING_CACHE(mode);
-}
-
-/** OpenGL 2.0 two-sided StencilFunc */
-static void nv10StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func,
- GLint ref, GLuint mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- /* NV10 do not have separate FRONT and BACK stencils */
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC, 3);
- OUT_RING_CACHE(func);
- OUT_RING_CACHE(ref);
- OUT_RING_CACHE(mask);
-}
-
-/** OpenGL 2.0 two-sided StencilMask */
-static void nv10StencilMaskSeparate(GLcontext *ctx, GLenum face, GLuint mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- /* NV10 do not have separate FRONT and BACK stencils */
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_STENCIL_MASK, 1);
- OUT_RING_CACHE(mask);
-}
-
-/** OpenGL 2.0 two-sided StencilOp */
-static void nv10StencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail,
- GLenum zfail, GLenum zpass)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- /* NV10 do not have separate FRONT and BACK stencils */
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL, 3);
- OUT_RING_CACHE(fail);
- OUT_RING_CACHE(zfail);
- OUT_RING_CACHE(zpass);
-}
-
-/** Control the generation of texture coordinates */
-void (*TexGen)(GLcontext *ctx, GLenum coord, GLenum pname,
- const GLfloat *params);
-/** Set texture environment parameters */
-void (*TexEnv)(GLcontext *ctx, GLenum target, GLenum pname,
- const GLfloat *param);
-/** Set texture parameters */
-void (*TexParameter)(GLcontext *ctx, GLenum target,
- struct gl_texture_object *texObj,
- GLenum pname, const GLfloat *params);
-
-static void nv10TextureMatrix(GLcontext *ctx, GLuint unit, const GLmatrix *mat)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_TX_MATRIX(unit, 0), 16);
- /*XXX: This SHOULD work.*/
- OUT_RING_CACHEp(mat->m, 16);
-}
-
-static void nv10UpdateProjectionMatrix(GLcontext *ctx)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLfloat w = ((GLfloat) ctx->Viewport.Width) * 0.5;
- GLfloat h = ((GLfloat) ctx->Viewport.Height) * 0.5;
- GLfloat max_depth = (ctx->Viewport.Near + ctx->Viewport.Far) * 0.5;
- GLfloat projection[16];
- int i;
-
- if (ctx->DrawBuffer) {
- if (ctx->DrawBuffer->_DepthBuffer) {
- switch (ctx->DrawBuffer->_DepthBuffer->DepthBits) {
- case 16:
- max_depth *= 32767.0;
- break;
- case 24:
- max_depth *= 16777215.0;
- break;
- }
- }
- }
-
- /* Transpose and rescale for viewport */
- for (i=0; i<4; i++) {
- projection[i] = w * ctx->_ModelProjectMatrix.m[i*4];
- }
- for (i=0; i<4; i++) {
- projection[i+4] = -h * ctx->_ModelProjectMatrix.m[i*4+1];
- }
- for (i=0; i<4; i++) {
- projection[i+8] = max_depth * ctx->_ModelProjectMatrix.m[i*4+2];
- }
- for (i=0; i<4; i++) {
- projection[i+12] = ctx->_ModelProjectMatrix.m[i*4+3];
- }
-
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_PROJECTION_MATRIX(0), 16);
- OUT_RING_CACHE_FORCEp(projection, 16);
-}
-
-static void nv10UpdateModelviewMatrix(GLcontext *ctx)
-{
- /* TODO update modelview if lighting or vertex weight enabled
- update inverse modelview if lighting enabled
- or update projection if lighting and vertex weight disabled
- */
-
- nv10UpdateProjectionMatrix(ctx);
-}
-
-/* Update anything that depends on the window position/size */
-static void nv10WindowMoved(nouveauContextPtr nmesa)
-{
- GLcontext *ctx = nmesa->glCtx;
- GLfloat *v = nmesa->viewport.m;
- GLuint wX, wY, wW, wH;
-
- nv10WindowCoords(nmesa, ctx->Viewport.X, ctx->Viewport.Y,
- ctx->Viewport.Width, ctx->Viewport.Height,
- &wX, &wY, &wW, &wH);
-
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ, 2);
- OUT_RING((wW << 16) | wX);
- OUT_RING((wH << 16) | wY);
-
- nv10ViewportScale(nmesa);
-
- ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
- ctx->Scissor.Width, ctx->Scissor.Height);
-}
-
-/* Initialise any card-specific non-GL related state */
-static GLboolean nv10InitCard(nouveauContextPtr nmesa)
-{
- int i;
- GLfloat projection[16];
-
- nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D);
-
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY0, 2);
- OUT_RING(NvDmaFB); /* 184 dma_in_memory0 */
- OUT_RING(NvDmaTT); /* 188 dma_in_memory1 */
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_SET_DMA_IN_MEMORY2, 2);
- OUT_RING(NvDmaFB); /* 194 dma_in_memory2 */
- OUT_RING(NvDmaFB); /* 198 dma_in_memory3 */
-
- /* 0x0 viewport size */
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ, 2);
- OUT_RING(0);
- OUT_RING(0);
-
- /* Clipping regions */
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_MODE, 1);
- OUT_RING (0);
- BEGIN_RING_SIZE(NvSub3D,
- NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(0), 1);
- OUT_RING(0x07ff0800);
- BEGIN_RING_SIZE(NvSub3D,
- NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(0), 1);
- OUT_RING(0x07ff0800);
- for (i=1; i<8; i++) {
- BEGIN_RING_SIZE(NvSub3D,
- NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(i), 1);
- OUT_RING(0);
- BEGIN_RING_SIZE(NvSub3D,
- NV10_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(i), 1);
- OUT_RING(0);
- }
-
- BEGIN_RING_SIZE(NvSub3D, 0x0290, 1);
- OUT_RING(0x00100001);
- BEGIN_RING_SIZE(NvSub3D, 0x03f4, 1);
- OUT_RING(0);
-
- if (nmesa->screen->card->type >= NV_11) {
- BEGIN_RING_SIZE(NvSub3D, 0x120, 3);
- OUT_RING(0);
- OUT_RING(1);
- OUT_RING(2);
-
- BEGIN_RING_SIZE(NvSubImageBlit, 0x120, 3);
- OUT_RING(0);
- OUT_RING(1);
- OUT_RING(2);
- }
-
- /* Set state for stuff not initialized in nouveau_state.c */
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_TX_ENABLE(0), 2);
- OUT_RING (0);
- OUT_RING (0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_RC_IN_ALPHA(0), 12);
- OUT_RING (0x30141010);
- OUT_RING (0);
- OUT_RING (0x20040000);
- OUT_RING (0);
- OUT_RING (0);
- OUT_RING (0);
- OUT_RING (0x00000c00);
- OUT_RING (0);
- OUT_RING (0x00000c00);
- OUT_RING (0x18000000);
- OUT_RING (0x300e0300);
- OUT_RING (0x0c091c80);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_WEIGHT_ENABLE, 1);
- OUT_RING (0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE, 1);
- OUT_RING (0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LIGHT_MODEL, 1);
- OUT_RING (0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_COLOR_CONTROL, 1);
- OUT_RING (0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POINT_SIZE, 1);
- OUT_RING (8);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_POINT_PARAMETERS_ENABLE, 1);
- OUT_RING (0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_LINE_WIDTH, 1);
- OUT_RING (8);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(0), 8);
- for (i=0;i<8;i++) {
- OUT_RING (0);
- }
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT, 3);
- OUT_RINGf (-1.50);
- OUT_RINGf (-0.09);
- OUT_RINGf ( 0.00);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_FOG_MODE, 2);
- OUT_RING (0x802);
- OUT_RING (2);
-
- /* Projection and modelview matrix */
- memset(projection, 0, sizeof(projection));
- projection[0*4+0] = 1.0;
- projection[1*4+1] = 1.0;
- projection[2*4+2] = 1.0;
- projection[3*4+3] = 1.0;
-
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEW_MATRIX_ENABLE, 1);
- OUT_RING (6); /* enable projection and modelview0 matrix */
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_PROJECTION_MATRIX(0), 16);
- for (i=0; i<16; i++) {
- OUT_RINGf (projection[i]);
- }
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_MODELVIEW0_MATRIX(0), 16);
- for (i=0; i<16; i++) {
- OUT_RINGf (projection[i]);
- }
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR, 2);
- OUT_RINGf (0.0);
- OUT_RINGf (1.0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_SCALE_X, 4);
- OUT_RINGf (1.0);
- OUT_RINGf (1.0);
- OUT_RINGf (1.0);
- OUT_RINGf (1.0);
-
- /* Set per-vertex component */
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_COL_4F_R, 4);
- OUT_RINGf (1.0);
- OUT_RINGf (1.0);
- OUT_RINGf (1.0);
- OUT_RINGf (1.0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_COL2_3F_R, 3);
- OUT_RING (0);
- OUT_RING (0);
- OUT_RING (0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_NOR_3F_X, 3);
- OUT_RINGf (0.0);
- OUT_RINGf (0.0);
- OUT_RINGf (1.0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_TX0_4F_S, 4);
- OUT_RINGf (0.0);
- OUT_RINGf (0.0);
- OUT_RINGf (0.0);
- OUT_RINGf (1.0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_TX1_4F_S, 4);
- OUT_RINGf (0.0);
- OUT_RINGf (0.0);
- OUT_RINGf (0.0);
- OUT_RINGf (1.0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_FOG_1F, 1);
- OUT_RINGf (0.0);
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_EDGEFLAG_ENABLE, 1);
- OUT_RING (1);
-
- return GL_TRUE;
-}
-
-/* Update buffer offset/pitch/format */
-static GLboolean nv10BindBuffers(nouveauContextPtr nmesa, int num_color,
- nouveau_renderbuffer_t **color,
- nouveau_renderbuffer_t *depth)
-{
- GLuint x, y, w, h;
- GLuint pitch, format, depth_pitch;
-
- /* Store buffer pointers in context */
- nmesa->color_buffer = color[0];
- nmesa->depth_buffer = depth;
-
- w = color[0]->mesa.Width;
- h = color[0]->mesa.Height;
- x = nmesa->drawX;
- y = nmesa->drawY;
-
- if (num_color != 1)
- return GL_FALSE;
-
- BEGIN_RING_SIZE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ, 6);
- OUT_RING((w << 16) | x);
- OUT_RING((h << 16) | y);
- depth_pitch = (depth ? depth->pitch : color[0]->pitch);
- pitch = (depth_pitch<<16) | color[0]->pitch;
- format = 0x108;
- if (color[0]->mesa._ActualFormat != GL_RGBA8) {
- format = 0x103; /* R5G6B5 color buffer */
- }
- OUT_RING(format);
- OUT_RING(pitch);
- OUT_RING(color[0]->offset);
- OUT_RING(depth ? depth->offset : color[0]->offset);
-
- return GL_TRUE;
-}
-
-void nv10InitStateFuncs(GLcontext *ctx, struct dd_function_table *func)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- func->AlphaFunc = nv10AlphaFunc;
- func->BlendColor = nv10BlendColor;
- func->BlendEquationSeparate = nv10BlendEquationSeparate;
- func->BlendFuncSeparate = nv10BlendFuncSeparate;
-/* func->Clear = nv10Clear;*/ /* Not for NV10 */
- func->ClearColor = nv10ClearColor; /* Not for NV10 */
- func->ClearDepth = nv10ClearDepth; /* Not for NV10 */
- func->ClearStencil = nv10ClearStencil; /* Not for NV10 */
- func->ClipPlane = nv10ClipPlane;
- func->ColorMask = nv10ColorMask;
- func->ColorMaterial = nv10ColorMaterial;
- func->CullFace = nv10CullFace;
- func->FrontFace = nv10FrontFace;
- func->DepthFunc = nv10DepthFunc;
- func->DepthMask = nv10DepthMask;
- func->DepthRange = nv10DepthRange;
- func->Enable = nv10Enable;
- func->Fogfv = nv10Fogfv;
- func->Hint = nv10Hint;
- func->Lightfv = nv10Lightfv;
-/* func->LightModelfv = nv10LightModelfv; */
- func->LineStipple = nv10LineStipple; /* Not for NV10 */
- func->LineWidth = nv10LineWidth;
- func->LogicOpcode = nv10LogicOpcode;
- func->PointParameterfv = nv10PointParameterfv;
- func->PointSize = nv10PointSize;
- func->PolygonMode = nv10PolygonMode;
- func->PolygonOffset = nv10PolygonOffset;
- func->PolygonStipple = nv10PolygonStipple; /* Not for NV10 */
-/* func->ReadBuffer = nv10ReadBuffer;*/
-/* func->RenderMode = nv10RenderMode;*/
- func->Scissor = nv10Scissor;
- func->ShadeModel = nv10ShadeModel;
- func->StencilFuncSeparate = nv10StencilFuncSeparate;
- func->StencilMaskSeparate = nv10StencilMaskSeparate;
- func->StencilOpSeparate = nv10StencilOpSeparate;
-/* func->TexGen = nv10TexGen;*/
-/* func->TexParameter = nv10TexParameter;*/
- func->TextureMatrix = nv10TextureMatrix;
-
- nmesa->hw_func.InitCard = nv10InitCard;
- nmesa->hw_func.BindBuffers = nv10BindBuffers;
- nmesa->hw_func.WindowMoved = nv10WindowMoved;
- nmesa->hw_func.UpdateProjectionMatrix = nv10UpdateProjectionMatrix;
- nmesa->hw_func.UpdateModelviewMatrix = nv10UpdateModelviewMatrix;
-}
diff --git a/src/mesa/drivers/dri/nouveau/nv10_swtcl.c b/src/mesa/drivers/dri/nouveau/nv10_swtcl.c
deleted file mode 100644
index a55d597ab4..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv10_swtcl.c
+++ /dev/null
@@ -1,714 +0,0 @@
-/*
- * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
- * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
- * Copyright 2006 Stephane Marchesin. All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/* Software TCL for NV10, NV20, NV30, NV40, NV50 */
-
-#include
-#include
-
-#include "glheader.h"
-#include "context.h"
-#include "mtypes.h"
-#include "macros.h"
-#include "colormac.h"
-#include "enums.h"
-
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "tnl/t_context.h"
-#include "tnl/t_pipeline.h"
-
-#include "nouveau_swtcl.h"
-#include "nv10_swtcl.h"
-#include "nouveau_context.h"
-#include "nouveau_span.h"
-#include "nouveau_reg.h"
-#include "nouveau_tex.h"
-#include "nouveau_fifo.h"
-#include "nouveau_msg.h"
-#include "nouveau_object.h"
-
-static void nv10RasterPrimitive( GLcontext *ctx, GLenum rprim, GLuint hwprim );
-static void nv10RenderPrimitive( GLcontext *ctx, GLenum prim );
-static void nv10ResetLineStipple( GLcontext *ctx );
-
-static const int default_attr_size[8]={3,3,3,4,3,1,4,4};
-
-/* Mesa requires us to put pos attribute as the first attribute of the
- * vertex, but on NV10 it is the last attribute.
- * To fix that we put the pos attribute first, and we swap the pos
- * attribute before sending it to the card.
- * Speed cost of the swap seems negligeable
- */
-#if 0
-/* old stuff where pos attribute isn't put first for mesa.
- * Usefull for speed comparaison
- */
-#define INV_VERT(i) i
-#define OUT_RING_VERTp(nmesa, ptr,sz, vertex_size) OUT_RINGp(ptr,sz)
-#define OUT_RING_VERT(nmesa, ptr, vertex_size) OUT_RINGp(ptr,vertex_size)
-#else
-
-#define INV_VERT(i) (i==0?7:i-1)
-
-#define OUT_RING_VERT_RAW(ptr,vertex_size) do{ \
- /* if the vertex size is not null, we have at least pos attribute */ \
- OUT_RINGp((GLfloat *)(ptr) + default_attr_size[_TNL_ATTRIB_POS], (vertex_size) - default_attr_size[_TNL_ATTRIB_POS]); \
- OUT_RINGp((GLfloat *)(ptr), default_attr_size[_TNL_ATTRIB_POS]); \
-}while(0)
-
-#define OUT_RING_VERT(nmesa,ptr,vertex_size) do{ \
- if (nmesa->screen->card->type>=NV_20) \
- OUT_RINGp(ptr, vertex_size); \
- else \
- OUT_RING_VERT_RAW(ptr, vertex_size); \
-}while(0)
-
-
-#define OUT_RING_VERTp(nmesa, ptr,sz, vertex_size) do{ \
- int nb_vert; \
- if (nmesa->screen->card->type>=NV_20) \
- OUT_RINGp(ptr, sz); \
- else \
- for (nb_vert = 0; nb_vert < (sz)/(vertex_size); nb_vert++) { \
- OUT_RING_VERT_RAW((GLfloat*)(ptr)+nb_vert*(vertex_size), vertex_size); \
- } \
-}while(0)
-
-#endif
-
-
-static INLINE void nv10StartPrimitive(struct nouveau_context* nmesa,GLuint primitive,GLuint size)
-{
- if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<=NV_17))
- BEGIN_RING_SIZE(NvSub3D,NV10_TCL_PRIMITIVE_3D_BEGIN_END,1);
- else if (nmesa->screen->card->type==NV_20)
- BEGIN_RING_SIZE(NvSub3D,NV20_TCL_PRIMITIVE_3D_BEGIN_END,1);
- else
- BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_BEGIN_END,1);
- OUT_RING(primitive);
-
- if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<=NV_17))
- BEGIN_RING_SIZE(NvSub3D,NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_DATA|NONINC_METHOD,size);
- else if (nmesa->screen->card->type==NV_20)
- BEGIN_RING_SIZE(NvSub3D,NV20_TCL_PRIMITIVE_3D_VERTEX_DATA|NONINC_METHOD,size);
- else
- BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_VERTEX_DATA|NONINC_METHOD,size);
-}
-
-void nv10FinishPrimitive(struct nouveau_context *nmesa)
-{
- if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<=NV_17))
- BEGIN_RING_SIZE(NvSub3D,NV10_TCL_PRIMITIVE_3D_BEGIN_END,1);
- else if (nmesa->screen->card->type==NV_20)
- BEGIN_RING_SIZE(NvSub3D,NV20_TCL_PRIMITIVE_3D_BEGIN_END,1);
- else
- BEGIN_RING_SIZE(NvSub3D,NV30_TCL_PRIMITIVE_3D_BEGIN_END,1);
- OUT_RING(0x0);
- FIRE_RING();
-}
-
-
-static INLINE void nv10ExtendPrimitive(struct nouveau_context* nmesa, int size)
-{
- /* make sure there's enough room. if not, wait */
- if (RING_AVAILABLE()verts;
- GLuint vertsize = nmesa->vertex_size;
- GLuint size_dword = vertsize*(count-start);
-
- nv10ExtendPrimitive(nmesa, size_dword);
- nv10StartPrimitive(nmesa,prim+1,size_dword);
- OUT_RING_VERTp(nmesa, (nouveauVertex*)(vertptr+(start*vertsize)),size_dword, vertsize);
- nv10FinishPrimitive(nmesa);
-}
-
-static void nv10_render_points_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_POINTS);
-}
-
-static void nv10_render_lines_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_LINES);
-}
-
-static void nv10_render_line_strip_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_LINE_STRIP);
-}
-
-static void nv10_render_line_loop_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_LINE_LOOP);
-}
-
-static void nv10_render_triangles_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_TRIANGLES);
-}
-
-static void nv10_render_tri_strip_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_TRIANGLE_STRIP);
-}
-
-static void nv10_render_tri_fan_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_TRIANGLE_FAN);
-}
-
-static void nv10_render_quads_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_QUADS);
-}
-
-static void nv10_render_quad_strip_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_QUAD_STRIP);
-}
-
-static void nv10_render_poly_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
- nv10_render_generic_primitive_verts(ctx,start,count,flags,GL_POLYGON);
-}
-
-static void nv10_render_noop_verts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags)
-{
-}
-
-static void (*nv10_render_tab_verts[GL_POLYGON+2])(GLcontext *,
- GLuint,
- GLuint,
- GLuint) =
-{
- nv10_render_points_verts,
- nv10_render_lines_verts,
- nv10_render_line_loop_verts,
- nv10_render_line_strip_verts,
- nv10_render_triangles_verts,
- nv10_render_tri_strip_verts,
- nv10_render_tri_fan_verts,
- nv10_render_quads_verts,
- nv10_render_quad_strip_verts,
- nv10_render_poly_verts,
- nv10_render_noop_verts,
-};
-
-
-static INLINE void nv10_render_generic_primitive_elts(GLcontext *ctx,GLuint start,GLuint count,GLuint flags,GLuint prim)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- GLfloat *vertptr = (GLfloat *)nmesa->verts;
- GLuint vertsize = nmesa->vertex_size;
- GLuint size_dword = vertsize*(count-start);
- const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;
- GLuint j;
-
- nv10ExtendPrimitive(nmesa, size_dword);
- nv10StartPrimitive(nmesa,prim+1,size_dword);
- for (j=start; jvertex_attrs[nmesa->vertex_attr_count].attrib = (ATTR); \
- nmesa->vertex_attrs[nmesa->vertex_attr_count].format = (STYLE); \
- nmesa->vertex_attr_count++; \
-} while (0)
-
-static INLINE void nv10_render_point(GLcontext *ctx, GLfloat *vertptr)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- GLuint vertsize = nmesa->vertex_size;
- GLuint size_dword = vertsize;
-
- nv10ExtendPrimitive(nmesa, size_dword);
- nv10StartPrimitive(nmesa,GL_POINTS+1,size_dword);
- OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr),vertsize);
- nv10FinishPrimitive(nmesa);
-}
-
-static INLINE void nv10_render_points(GLcontext *ctx,GLuint first,GLuint last)
-{
- struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb;
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- GLfloat *vertptr = (GLfloat *)nmesa->verts;
- GLuint vertsize = nmesa->vertex_size;
- GLuint i;
-
- if (VB->Elts) {
- for (i = first; i < last; i++)
- if (VB->ClipMask[VB->Elts[i]] == 0)
- nv10_render_point(ctx, vertptr + (VB->Elts[i]*vertsize));
- }
- else {
- for (i = first; i < last; i++)
- if (VB->ClipMask[i] == 0)
- nv10_render_point(ctx, vertptr + (i*vertsize));
- }
-}
-
-static INLINE void nv10_render_line(GLcontext *ctx,GLuint v1,GLuint v2)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- GLfloat *vertptr = (GLfloat *)nmesa->verts;
- GLuint vertsize = nmesa->vertex_size;
- GLuint size_dword = vertsize*2;
-
- nv10ExtendPrimitive(nmesa, size_dword);
- nv10StartPrimitive(nmesa,GL_LINES+1,size_dword);
- OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v1*vertsize)),vertsize);
- OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v2*vertsize)),vertsize);
- nv10FinishPrimitive(nmesa);
-}
-
-static INLINE void nv10_render_triangle(GLcontext *ctx,GLuint v1,GLuint v2,GLuint v3)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- GLfloat *vertptr = (GLfloat *)nmesa->verts;
- GLuint vertsize = nmesa->vertex_size;
- GLuint size_dword = vertsize*3;
-
- nv10ExtendPrimitive(nmesa, size_dword);
- nv10StartPrimitive(nmesa,GL_TRIANGLES+1,size_dword);
- OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v1*vertsize)),vertsize);
- OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v2*vertsize)),vertsize);
- OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v3*vertsize)),vertsize);
- nv10FinishPrimitive(nmesa);
-}
-
-static INLINE void nv10_render_quad(GLcontext *ctx,GLuint v1,GLuint v2,GLuint v3,GLuint v4)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- GLfloat *vertptr = (GLfloat *)nmesa->verts;
- GLuint vertsize = nmesa->vertex_size;
- GLuint size_dword = vertsize*4;
-
- nv10ExtendPrimitive(nmesa, size_dword);
- nv10StartPrimitive(nmesa,GL_QUADS+1,size_dword);
- OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v1*vertsize)),vertsize);
- OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v2*vertsize)),vertsize);
- OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v3*vertsize)),vertsize);
- OUT_RING_VERT(nmesa, (nouveauVertex*)(vertptr+(v4*vertsize)),vertsize);
- nv10FinishPrimitive(nmesa);
-}
-
-
-
-static void nv10ChooseRenderState(GLcontext *ctx)
-{
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
-
- tnl->Driver.Render.PrimTabVerts = nv10_render_tab_verts;
- tnl->Driver.Render.PrimTabElts = nv10_render_tab_elts;
- tnl->Driver.Render.ClippedLine = _tnl_RenderClippedLine;
- tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
- tnl->Driver.Render.Points = nv10_render_points;
- tnl->Driver.Render.Line = nv10_render_line;
- tnl->Driver.Render.Triangle = nv10_render_triangle;
- tnl->Driver.Render.Quad = nv10_render_quad;
-}
-
-
-
-static INLINE void nv10OutputVertexFormat(struct nouveau_context* nmesa)
-{
- GLcontext* ctx=nmesa->glCtx;
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- DECLARE_RENDERINPUTS(index);
- struct vertex_buffer *VB = &tnl->vb;
- int attr_size[16];
- const int nv10_vtx_attribs[8]={
- _TNL_ATTRIB_FOG, _TNL_ATTRIB_WEIGHT,
- _TNL_ATTRIB_NORMAL, _TNL_ATTRIB_TEX1,
- _TNL_ATTRIB_TEX0, _TNL_ATTRIB_COLOR1,
- _TNL_ATTRIB_COLOR0, _TNL_ATTRIB_POS
- };
- int i;
- int slots=0;
- int total_size=0;
-
- nmesa->vertex_attr_count = 0;
- RENDERINPUTS_COPY(index, nmesa->render_inputs_bitset);
-
- /*
- * Determine attribute sizes
- */
- for(i=0;i<8;i++)
- {
- if (RENDERINPUTS_TEST(index, i))
- attr_size[i]=default_attr_size[i];
- else
- attr_size[i]=0;
- }
- for(i=8;i<16;i++)
- {
- if (RENDERINPUTS_TEST(index, i))
- attr_size[i]=VB->TexCoordPtr[i-8]->size;
- else
- attr_size[i]=0;
- }
-
- /*
- * Tell t_vertex about the vertex format
- */
- if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<=NV_17)) {
- for(i=0;i<8;i++) {
- int j = nv10_vtx_attribs[INV_VERT(i)];
- if (RENDERINPUTS_TEST(index, j)) {
- switch(attr_size[j])
- {
- case 1:
- EMIT_ATTR(j,EMIT_1F);
- break;
- case 2:
- EMIT_ATTR(j,EMIT_2F);
- break;
- case 3:
- EMIT_ATTR(j,EMIT_3F);
- break;
- case 4:
- EMIT_ATTR(j,EMIT_4F);
- break;
- }
- total_size+=attr_size[j];
- }
- }
- } else {
- for(i=0;i<16;i++)
- {
- if (RENDERINPUTS_TEST(index, i))
- {
- slots=i+1;
- switch(attr_size[i])
- {
- case 1:
- EMIT_ATTR(i,EMIT_1F);
- break;
- case 2:
- EMIT_ATTR(i,EMIT_2F);
- break;
- case 3:
- EMIT_ATTR(i,EMIT_3F);
- break;
- case 4:
- EMIT_ATTR(i,EMIT_4F);
- break;
- }
- if (i==_TNL_ATTRIB_COLOR0)
- nmesa->color_offset=total_size;
- if (i==_TNL_ATTRIB_COLOR1)
- nmesa->specular_offset=total_size;
- total_size+=attr_size[i];
- }
- }
- }
-
- nmesa->vertex_size=_tnl_install_attrs( ctx,
- nmesa->vertex_attrs,
- nmesa->vertex_attr_count,
- NULL, 0 );
- /* OUT_RINGp wants size in DWORDS */
- nmesa->vertex_size = nmesa->vertex_size / 4;
- assert(nmesa->vertex_size==total_size);
-
- /*
- * Tell the hardware about the vertex format
- */
- if ((nmesa->screen->card->type>=NV_10) && (nmesa->screen->card->type<=NV_17)) {
- int total_stride = 0;
-
-#define NV_VERTEX_ATTRIBUTE_TYPE_FLOAT 2
-
- for(i=0;i<8;i++) {
- int j = nv10_vtx_attribs[i];
- int size;
- int stride = attr_size[j] << 2;
- if (j==_TNL_ATTRIB_POS) {
- stride += total_stride;
- }
- size = attr_size[j] << 4;
- size |= stride << 8;
- size |= NV_VERTEX_ATTRIBUTE_TYPE_FLOAT;
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_ATTR((7-i)),1);
- OUT_RING_CACHE(size);
- total_stride += stride;
- }
-
- BEGIN_RING_CACHE(NvSub3D, NV10_TCL_PRIMITIVE_3D_VERTEX_ARRAY_VALIDATE,1);
- OUT_RING_CACHE(0);
- } else if (nmesa->screen->card->type==NV_20) {
- for(i=0;i<16;i++)
- {
- int size=attr_size[i];
- BEGIN_RING_CACHE(NvSub3D,NV20_TCL_PRIMITIVE_3D_VERTEX_ATTR(i),1);
- OUT_RING_CACHE(NV_VERTEX_ATTRIBUTE_TYPE_FLOAT|(size*0x10));
- }
- } else {
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DO_VERTICES, 1);
- OUT_RING(0);
- BEGIN_RING_CACHE(NvSub3D,NV20_TCL_PRIMITIVE_3D_VB_POINTER_ATTR8_TX0,slots);
- for(i=0;irender_inputs_bitset);
- if (!RENDERINPUTS_EQUAL(index, nmesa->render_inputs_bitset))
- {
- RENDERINPUTS_COPY(nmesa->render_inputs_bitset, index);
- nv10OutputVertexFormat(nmesa);
- }
-
- if (nmesa->screen->card->type == NV_30) {
- nouveauShader *fp;
-
- if (ctx->FragmentProgram.Enabled) {
- fp = (nouveauShader *) ctx->FragmentProgram.Current;
- nvsUpdateShader(ctx, fp);
- } else
- nvsUpdateShader(ctx, nmesa->passthrough_fp);
- }
-
- if (nmesa->screen->card->type >= NV_40) {
- /* Ensure passthrough shader is being used, and mvp matrix
- * is up to date
- */
- nvsUpdateShader(ctx, nmesa->passthrough_vp);
-
- /* Update texenv shader / user fragprog */
- nvsUpdateShader(ctx, (nouveauShader*)ctx->FragmentProgram._Current);
- }
-}
-
-
-/**********************************************************************/
-/* High level hooks for t_vb_render.c */
-/**********************************************************************/
-
-
-static void nv10RenderStart(GLcontext *ctx)
-{
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (nmesa->new_state) {
- nmesa->new_render_state |= nmesa->new_state;
- }
-
- if (nmesa->new_render_state) {
- nv10ChooseVertexState(ctx);
- nv10ChooseRenderState(ctx);
- nmesa->new_render_state = 0;
- }
-}
-
-static void nv10RenderFinish(GLcontext *ctx)
-{
-}
-
-
-/* System to flush dma and emit state changes based on the rasterized
- * primitive.
- */
-void nv10RasterPrimitive(GLcontext *ctx,
- GLenum glprim,
- GLuint hwprim)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
-
- assert (!nmesa->new_state);
-
- if (hwprim != nmesa->current_primitive)
- {
- nmesa->current_primitive=hwprim;
-
- }
-}
-
-static const GLuint hw_prim[GL_POLYGON+1] = {
- GL_POINTS+1,
- GL_LINES+1,
- GL_LINE_STRIP+1,
- GL_LINE_LOOP+1,
- GL_TRIANGLES+1,
- GL_TRIANGLE_STRIP+1,
- GL_TRIANGLE_FAN+1,
- GL_QUADS+1,
- GL_QUAD_STRIP+1,
- GL_POLYGON+1
-};
-
-/* Callback for mesa:
- */
-static void nv10RenderPrimitive( GLcontext *ctx, GLuint prim )
-{
- nv10RasterPrimitive( ctx, prim, hw_prim[prim] );
-}
-
-static void nv10ResetLineStipple( GLcontext *ctx )
-{
- /* FIXME do something here */
- WARN_ONCE("Unimplemented nv10ResetLineStipple\n");
-}
-
-
-/**********************************************************************/
-/* Initialization. */
-/**********************************************************************/
-
-void nv10TriInitFunctions(GLcontext *ctx)
-{
- struct nouveau_context *nmesa = NOUVEAU_CONTEXT(ctx);
- TNLcontext *tnl = TNL_CONTEXT(ctx);
-
- tnl->Driver.RunPipeline = nouveauRunPipeline;
- tnl->Driver.Render.Start = nv10RenderStart;
- tnl->Driver.Render.Finish = nv10RenderFinish;
- tnl->Driver.Render.PrimitiveNotify = nv10RenderPrimitive;
- tnl->Driver.Render.ResetLineStipple = nv10ResetLineStipple;
- tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
- tnl->Driver.Render.CopyPV = _tnl_copy_pv;
- tnl->Driver.Render.Interp = _tnl_interp;
-
- _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
- 64 * sizeof(GLfloat) );
-
- nmesa->verts = (GLubyte *)tnl->clipspace.vertex_buf;
-}
-
-
diff --git a/src/mesa/drivers/dri/nouveau/nv10_swtcl.h b/src/mesa/drivers/dri/nouveau/nv10_swtcl.h
deleted file mode 100644
index 7c854addd2..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv10_swtcl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Stephane Marchesin
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-
-
-#ifndef __NV10_SWTCL_H__
-#define __NV10_SWTCL_H__
-
-#include "mtypes.h"
-
-extern void nv10Fallback( GLcontext *ctx, GLuint bit, GLboolean mode );
-extern void nv10FinishPrimitive(struct nouveau_context *nmesa);
-extern void nv10TriInitFunctions(GLcontext *ctx);
-#define FALLBACK( nmesa, bit, mode ) nouveauFallback( nmesa->glCtx, bit, mode )
-
-#endif /* __NV10_SWTCL_H__ */
-
diff --git a/src/mesa/drivers/dri/nouveau/nv20_shader.h b/src/mesa/drivers/dri/nouveau/nv20_shader.h
deleted file mode 100644
index 7d2e29db66..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv20_shader.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* NV20_TCL_PRIMITIVE_3D_0x0B00 */
-#define NV20_VP_INST_0B00 0x00000000 /* always 0? */
-#define NV20_VP_INST0_KNOWN 0
-
-/* NV20_TCL_PRIMITIVE_3D_0x0B04 */
-#define NV20_VP_INST_SCA_OPCODE_SHIFT 25
-#define NV20_VP_INST_SCA_OPCODE_MASK (0x0F << 25)
-#define NV20_VP_INST_OPCODE_RCP 0x2
-#define NV20_VP_INST_OPCODE_RCC 0x3
-#define NV20_VP_INST_OPCODE_RSQ 0x4
-#define NV20_VP_INST_OPCODE_EXP 0x5
-#define NV20_VP_INST_OPCODE_LOG 0x6
-#define NV20_VP_INST_OPCODE_LIT 0x7
-#define NV20_VP_INST_VEC_OPCODE_SHIFT 21
-#define NV20_VP_INST_VEC_OPCODE_MASK (0x0F << 21)
-#define NV20_VP_INST_OPCODE_NOP 0x0 /* guess */
-#define NV20_VP_INST_OPCODE_MOV 0x1
-#define NV20_VP_INST_OPCODE_MUL 0x2
-#define NV20_VP_INST_OPCODE_ADD 0x3
-#define NV20_VP_INST_OPCODE_MAD 0x4
-#define NV20_VP_INST_OPCODE_DP3 0x5
-#define NV20_VP_INST_OPCODE_DPH 0x6
-#define NV20_VP_INST_OPCODE_DP4 0x7
-#define NV20_VP_INST_OPCODE_DST 0x8
-#define NV20_VP_INST_OPCODE_MIN 0x9
-#define NV20_VP_INST_OPCODE_MAX 0xA
-#define NV20_VP_INST_OPCODE_SLT 0xB
-#define NV20_VP_INST_OPCODE_SGE 0xC
-#define NV20_VP_INST_OPCODE_ARL 0xD
-#define NV20_VP_INST_CONST_SRC_SHIFT 13
-#define NV20_VP_INST_CONST_SRC_MASK (0xFF << 13)
-#define NV20_VP_INST_INPUT_SRC_SHIFT 9
-#define NV20_VP_INST_INPUT_SRC_MASK (0xF << 9) /* guess */
-#define NV20_VP_INST_INPUT_SRC_POS 0
-#define NV20_VP_INST_INPUT_SRC_COL0 3
-#define NV20_VP_INST_INPUT_SRC_COL1 4
-#define NV20_VP_INST_INPUT_SRC_TC(n) (9+n)
-#define NV20_VP_INST_SRC0H_SHIFT 0
-#define NV20_VP_INST_SRC0H_MASK (0x1FF << 0)
-#define NV20_VP_INST1_KNOWN ( \
- NV20_VP_INST_OPCODE_MASK | \
- NV20_VP_INST_CONST_SRC_MASK | \
- NV20_VP_INST_INPUT_SRC_MASK | \
- NV20_VP_INST_SRC0H_MASK \
- )
-
-/* NV20_TCL_PRIMITIVE_3D_0x0B08 */
-#define NV20_VP_INST_SRC0L_SHIFT 26
-#define NV20_VP_INST_SRC0L_MASK (0x3F <<26)
-#define NV20_VP_INST_SRC1_SHIFT 11
-#define NV20_VP_INST_SRC1_MASK (0x7FFF<<11)
-#define NV20_VP_INST_SRC2H_SHIFT 0
-#define NV20_VP_INST_SRC2H_MASK (0x7FF << 0)
-
-/* NV20_TCL_PRIMITIVE_3D_0x0B0C */
-#define NV20_VP_INST_SRC2L_SHIFT 28
-#define NV20_VP_INST_SRC2L_MASK (0x0F <<28)
-#define NV20_VP_INST_VTEMP_WRITEMASK_SHIFT 24
-#define NV20_VP_INST_VTEMP_WRITEMASK_MASK (0x0F <<24)
-# define NV20_VP_INST_TEMP_WRITEMASK_X (1<<27)
-# define NV20_VP_INST_TEMP_WRITEMASK_Y (1<<26)
-# define NV20_VP_INST_TEMP_WRITEMASK_Z (1<<25)
-# define NV20_VP_INST_TEMP_WRITEMASK_W (1<<24)
-#define NV20_VP_INST_DEST_TEMP_ID_SHIFT 20
-#define NV20_VP_INST_DEST_TEMP_ID_MASK (0x0F <<20)
-#define NV20_VP_INST_STEMP_WRITEMASK_SHIFT 16
-#define NV20_VP_INST_STEMP_WRITEMASK_MASK (0x0F <<16)
-# define NV20_VP_INST_STEMP_WRITEMASK_X (1<<19)
-# define NV20_VP_INST_STEMP_WRITEMASK_Y (1<<18)
-# define NV20_VP_INST_STEMP_WRITEMASK_Z (1<<17)
-# define NV20_VP_INST_STEMP_WRITEMASK_W (1<<16)
-#define NV20_VP_INST_DEST_WRITEMASK_SHIFT 12
-#define NV20_VP_INST_DEST_WRITEMASK_MASK (0x0F <<12)
-# define NV20_VP_INST_DEST_WRITEMASK_X (1<<15)
-# define NV20_VP_INST_DEST_WRITEMASK_Y (1<<14)
-# define NV20_VP_INST_DEST_WRITEMASK_Z (1<<13)
-# define NV20_VP_INST_DEST_WRITEMASK_W (1<<12)
-#define NV20_VP_INST_DEST_SHIFT 3
-#define NV20_VP_INST_DEST_MASK (0xF << 3) /* guess */
-#define NV20_VP_INST_DEST_POS 0
-#define NV20_VP_INST_DEST_COL0 3
-#define NV20_VP_INST_DEST_COL1 4
-#define NV20_VP_INST_DEST_TC(n) (9+n)
-#define NV20_VP_INST_INDEX_CONST (1<<1)
-#define NV20_VP_INST3_KNOWN ( \
- NV20_VP_INST_SRC2L_MASK | \
- NV20_VP_INST_TEMP_WRITEMASK_MASK | \
- NV20_VP_INST_DEST_TEMP_ID_MASK | \
- NV20_VP_INST_STEMP_WRITEMASK_MASK | \
- NV20_VP_INST_DEST_WRITEMASK_MASK | \
- NV20_VP_INST_DEST_MASK | \
- NV20_VP_INST_INDEX_CONST \
- )
-
-/* Useful to split the source selection regs into their pieces */
-#define NV20_VP_SRC0_HIGH_SHIFT 6
-#define NV20_VP_SRC0_HIGH_MASK 0x00007FC0
-#define NV20_VP_SRC0_LOW_MASK 0x0000003F
-#define NV20_VP_SRC2_HIGH_SHIFT 4
-#define NV20_VP_SRC2_HIGH_MASK 0x00007FF0
-#define NV20_VP_SRC2_LOW_MASK 0x0000000F
-
-#define NV20_VP_SRC_REG_NEGATE (1<<14)
-#define NV20_VP_SRC_REG_SWZ_X_SHIFT 12
-#define NV20_VP_SRC_REG_SWZ_X_MASK (0x03 <<12)
-#define NV20_VP_SRC_REG_SWZ_Y_SHIFT 10
-#define NV20_VP_SRC_REG_SWZ_Y_MASK (0x03 <<10)
-#define NV20_VP_SRC_REG_SWZ_Z_SHIFT 8
-#define NV20_VP_SRC_REG_SWZ_Z_MASK (0x03 << 8)
-#define NV20_VP_SRC_REG_SWZ_W_SHIFT 6
-#define NV20_VP_SRC_REG_SWZ_W_MASK (0x03 << 6)
-#define NV20_VP_SRC_REG_SWZ_ALL_SHIFT 6
-#define NV20_VP_SRC_REG_SWZ_ALL_MASK (0xFF << 6)
-#define NV20_VP_SRC_REG_TEMP_ID_SHIFT 2
-#define NV20_VP_SRC_REG_TEMP_ID_MASK (0x0F << 0)
-#define NV20_VP_SRC_REG_TYPE_SHIFT 0
-#define NV20_VP_SRC_REG_TYPE_MASK (0x03 << 0)
-#define NV20_VP_SRC_REG_TYPE_TEMP 1
-#define NV20_VP_SRC_REG_TYPE_INPUT 2
-#define NV20_VP_SRC_REG_TYPE_CONST 3 /* guess */
-
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state.c b/src/mesa/drivers/dri/nouveau/nv20_state.c
deleted file mode 100644
index 6b583980a4..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv20_state.c
+++ /dev/null
@@ -1,824 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Nouveau
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-#include "nouveau_context.h"
-#include "nouveau_object.h"
-#include "nouveau_fifo.h"
-#include "nouveau_reg.h"
-
-#include "tnl/t_pipeline.h"
-
-#include "mtypes.h"
-#include "colormac.h"
-
-static void nv20AlphaFunc(GLcontext *ctx, GLenum func, GLfloat ref)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte ubRef;
- CLAMPED_FLOAT_TO_UBYTE(ubRef, ref);
-
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC, 2);
- OUT_RING_CACHE(func);
- OUT_RING_CACHE(ubRef);
-}
-
-static void nv20BlendColor(GLcontext *ctx, const GLfloat color[4])
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte cf[4];
-
- CLAMPED_FLOAT_TO_UBYTE(cf[0], color[0]);
- CLAMPED_FLOAT_TO_UBYTE(cf[1], color[1]);
- CLAMPED_FLOAT_TO_UBYTE(cf[2], color[2]);
- CLAMPED_FLOAT_TO_UBYTE(cf[3], color[3]);
-
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_BLEND_COLOR, 1);
- OUT_RING_CACHE(PACK_COLOR_8888(cf[3], cf[1], cf[2], cf[0]));
-}
-
-static void nv20BlendEquationSeparate(GLcontext *ctx, GLenum modeRGB, GLenum modeA)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_BLEND_EQUATION, 1);
- OUT_RING_CACHE((modeA<<16) | modeRGB);
-}
-
-
-static void nv20BlendFuncSeparate(GLcontext *ctx, GLenum sfactorRGB, GLenum dfactorRGB,
- GLenum sfactorA, GLenum dfactorA)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC, 2);
- OUT_RING_CACHE((sfactorA<<16) | sfactorRGB);
- OUT_RING_CACHE((dfactorA<<16) | dfactorRGB);
-}
-
-static void nv20Clear(GLcontext *ctx, GLbitfield mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLuint hw_bufs = 0;
-
- if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT))
- hw_bufs |= 0xf0;
- if (mask & (BUFFER_BIT_DEPTH))
- hw_bufs |= 0x03;
-
- if (hw_bufs) {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS, 1);
- OUT_RING_CACHE(hw_bufs);
- }
-}
-
-static void nv20ClearColor(GLcontext *ctx, const GLfloat color[4])
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte c[4];
- UNCLAMPED_FLOAT_TO_RGBA_CHAN(c,color);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB, 1);
- OUT_RING_CACHE(PACK_COLOR_8888(c[3],c[0],c[1],c[2]));
-}
-
-static void nv20ClearDepth(GLcontext *ctx, GLclampd d)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nmesa->clear_value=((nmesa->clear_value&0x000000FF)|(((uint32_t)(d*0xFFFFFF))<<8));
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH, 1);
- OUT_RING_CACHE(nmesa->clear_value);
-}
-
-/* we're don't support indexed buffers
- void (*ClearIndex)(GLcontext *ctx, GLuint index)
- */
-
-static void nv20ClearStencil(GLcontext *ctx, GLint s)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nmesa->clear_value=((nmesa->clear_value&0xFFFFFF00)|(s&0x000000FF));
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH, 1);
- OUT_RING_CACHE(nmesa->clear_value);
-}
-
-static void nv20ClipPlane(GLcontext *ctx, GLenum plane, const GLfloat *equation)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_A(plane), 4);
- OUT_RING_CACHEf(equation[0]);
- OUT_RING_CACHEf(equation[1]);
- OUT_RING_CACHEf(equation[2]);
- OUT_RING_CACHEf(equation[3]);
-}
-
-static void nv20ColorMask(GLcontext *ctx, GLboolean rmask, GLboolean gmask,
- GLboolean bmask, GLboolean amask )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_COLOR_MASK, 1);
- OUT_RING_CACHE(((amask && 0x01) << 24) | ((rmask && 0x01) << 16) | ((gmask && 0x01)<< 8) | ((bmask && 0x01) << 0));
-}
-
-static void nv20ColorMaterial(GLcontext *ctx, GLenum face, GLenum mode)
-{
- // TODO I need love
-}
-
-static void nv20CullFace(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CULL_FACE, 1);
- OUT_RING_CACHE(mode);
-}
-
-static void nv20FrontFace(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_FRONT_FACE, 1);
- OUT_RING_CACHE(mode);
-}
-
-static void nv20DepthFunc(GLcontext *ctx, GLenum func)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_DEPTH_FUNC, 1);
- OUT_RING_CACHE(func);
-}
-
-static void nv20DepthMask(GLcontext *ctx, GLboolean flag)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE, 1);
- OUT_RING_CACHE(flag);
-}
-
-static void nv20DepthRange(GLcontext *ctx, GLclampd nearval, GLclampd farval)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR, 2);
- OUT_RING_CACHEf(nearval);
- OUT_RING_CACHEf(farval);
-}
-
-/** Specify the current buffer for writing */
-//void (*DrawBuffer)( GLcontext *ctx, GLenum buffer );
-/** Specify the buffers for writing for fragment programs*/
-//void (*DrawBuffers)( GLcontext *ctx, GLsizei n, const GLenum *buffers );
-
-static void nv20Enable(GLcontext *ctx, GLenum cap, GLboolean state)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- switch(cap)
- {
- case GL_ALPHA_TEST:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_AUTO_NORMAL:
- case GL_BLEND:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_CLIP_PLANE0:
- case GL_CLIP_PLANE1:
- case GL_CLIP_PLANE2:
- case GL_CLIP_PLANE3:
- case GL_CLIP_PLANE4:
- case GL_CLIP_PLANE5:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(cap-GL_CLIP_PLANE0), 1);
- OUT_RING_CACHE(state);
- break;
- case GL_COLOR_LOGIC_OP:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_COLOR_MATERIAL:
-// case GL_COLOR_SUM_EXT:
-// case GL_COLOR_TABLE:
-// case GL_CONVOLUTION_1D:
-// case GL_CONVOLUTION_2D:
- case GL_CULL_FACE:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_DEPTH_TEST:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_DITHER:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_DITHER_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_FOG:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_FOG_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_HISTOGRAM:
-// case GL_INDEX_LOGIC_OP:
- case GL_LIGHT0:
- case GL_LIGHT1:
- case GL_LIGHT2:
- case GL_LIGHT3:
- case GL_LIGHT4:
- case GL_LIGHT5:
- case GL_LIGHT6:
- case GL_LIGHT7:
- {
- uint32_t mask=0x11<<(2*(cap-GL_LIGHT0));
- nmesa->enabled_lights=((nmesa->enabled_lights&mask)|(mask*state));
- if (nmesa->lighting_enabled)
- {
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1);
- OUT_RING_CACHE(nmesa->enabled_lights);
- }
- break;
- }
- case GL_LIGHTING:
- nmesa->lighting_enabled=state;
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1);
- if (nmesa->lighting_enabled)
- OUT_RING_CACHE(nmesa->enabled_lights);
- else
- OUT_RING_CACHE(0x0);
- break;
- case GL_LINE_SMOOTH:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_LINE_STIPPLE:
-// case GL_MAP1_COLOR_4:
-// case GL_MAP1_INDEX:
-// case GL_MAP1_NORMAL:
-// case GL_MAP1_TEXTURE_COORD_1:
-// case GL_MAP1_TEXTURE_COORD_2:
-// case GL_MAP1_TEXTURE_COORD_3:
-// case GL_MAP1_TEXTURE_COORD_4:
-// case GL_MAP1_VERTEX_3:
-// case GL_MAP1_VERTEX_4:
-// case GL_MAP2_COLOR_4:
-// case GL_MAP2_INDEX:
-// case GL_MAP2_NORMAL:
-// case GL_MAP2_TEXTURE_COORD_1:
-// case GL_MAP2_TEXTURE_COORD_2:
-// case GL_MAP2_TEXTURE_COORD_3:
-// case GL_MAP2_TEXTURE_COORD_4:
-// case GL_MAP2_VERTEX_3:
-// case GL_MAP2_VERTEX_4:
-// case GL_MINMAX:
- case GL_NORMALIZE:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_POINT_SMOOTH:
- case GL_POLYGON_OFFSET_POINT:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_OFFSET_LINE:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_OFFSET_FILL:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_SMOOTH:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_STIPPLE:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_POST_COLOR_MATRIX_COLOR_TABLE:
-// case GL_POST_CONVOLUTION_COLOR_TABLE:
-// case GL_RESCALE_NORMAL:
- case GL_SCISSOR_TEST:
- /* No enable bit, nv20Scissor will adjust to max range */
- ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
- ctx->Scissor.Width, ctx->Scissor.Height);
- break;
-// case GL_SEPARABLE_2D:
- case GL_STENCIL_TEST:
- // TODO BACK and FRONT ?
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_STENCIL_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_TEXTURE_GEN_Q:
-// case GL_TEXTURE_GEN_R:
-// case GL_TEXTURE_GEN_S:
-// case GL_TEXTURE_GEN_T:
-// case GL_TEXTURE_1D:
-// case GL_TEXTURE_2D:
-// case GL_TEXTURE_3D:
- }
-}
-
-static void nv20Fogfv(GLcontext *ctx, GLenum pname, const GLfloat *params)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- switch(pname)
- {
- case GL_FOG_MODE:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_FOG_MODE, 1);
- //OUT_RING_CACHE (params);
- break;
- /* TODO: unsure about the rest.*/
- default:
- break;
- }
-
-}
-
-static void nv20Hint(GLcontext *ctx, GLenum target, GLenum mode)
-{
- // TODO I need love (fog and line_smooth hints)
-}
-
-// void (*IndexMask)(GLcontext *ctx, GLuint mask);
-
-enum {
- SPOTLIGHT_NO_UPDATE,
- SPOTLIGHT_UPDATE_EXPONENT,
- SPOTLIGHT_UPDATE_DIRECTION,
- SPOTLIGHT_UPDATE_ALL
-};
-
-static void nv20Lightfv(GLcontext *ctx, GLenum light, GLenum pname, const GLfloat *params )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLint p = light - GL_LIGHT0;
- struct gl_light *l = &ctx->Light.Light[p];
- int spotlight_update = SPOTLIGHT_NO_UPDATE;
-
- /* not sure where the fourth param value goes...*/
- switch(pname)
- {
- case GL_AMBIENT:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_DIFFUSE:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_SPECULAR:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_POSITION:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_SPOT_DIRECTION:
- spotlight_update = SPOTLIGHT_UPDATE_DIRECTION;
- break;
- case GL_SPOT_EXPONENT:
- spotlight_update = SPOTLIGHT_UPDATE_EXPONENT;
- break;
- case GL_SPOT_CUTOFF:
- spotlight_update = SPOTLIGHT_UPDATE_ALL;
- break;
- case GL_CONSTANT_ATTENUATION:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(p), 1);
- OUT_RING_CACHEf(*params);
- break;
- case GL_LINEAR_ATTENUATION:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(p), 1);
- OUT_RING_CACHEf(*params);
- break;
- case GL_QUADRATIC_ATTENUATION:
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(p), 1);
- OUT_RING_CACHEf(*params);
- break;
- default:
- break;
- }
-
- switch(spotlight_update) {
- case SPOTLIGHT_UPDATE_DIRECTION:
- {
- GLfloat x,y,z;
- GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0);
- x = spot_light_coef_a * l->_NormDirection[0];
- y = spot_light_coef_a * l->_NormDirection[1];
- z = spot_light_coef_a * l->_NormDirection[2];
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(p), 3);
- OUT_RING_CACHEf(x);
- OUT_RING_CACHEf(y);
- OUT_RING_CACHEf(z);
- }
- break;
- case SPOTLIGHT_UPDATE_EXPONENT:
- {
- GLfloat cc,lc,qc;
- cc = 1.0; /* FIXME: These need to be correctly computed */
- lc = 0.0;
- qc = 2.0;
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 3);
- OUT_RING_CACHEf(cc);
- OUT_RING_CACHEf(lc);
- OUT_RING_CACHEf(qc);
- }
- break;
- case SPOTLIGHT_UPDATE_ALL:
- {
- GLfloat cc,lc,qc, x,y,z, c;
- GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0);
- cc = 1.0; /* FIXME: These need to be correctly computed */
- lc = 0.0;
- qc = 2.0;
- x = spot_light_coef_a * l->_NormDirection[0];
- y = spot_light_coef_a * l->_NormDirection[1];
- z = spot_light_coef_a * l->_NormDirection[2];
- c = spot_light_coef_a + 1.0;
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 7);
- OUT_RING_CACHEf(cc);
- OUT_RING_CACHEf(lc);
- OUT_RING_CACHEf(qc);
- OUT_RING_CACHEf(x);
- OUT_RING_CACHEf(y);
- OUT_RING_CACHEf(z);
- OUT_RING_CACHEf(c);
- }
- break;
- default:
- break;
- }
-}
-
-/** Set the lighting model parameters */
-static void (*LightModelfv)(GLcontext *ctx, GLenum pname, const GLfloat *params);
-
-
-static void nv20LineStipple(GLcontext *ctx, GLint factor, GLushort pattern )
-{
-/* nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN, 1);
- OUT_RING_CACHE((pattern << 16) | factor);*/
-}
-
-static void nv20LineWidth(GLcontext *ctx, GLfloat width)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LINE_WIDTH, 1);
- OUT_RING_CACHEf(width);
-}
-
-static void nv20LogicOpcode(GLcontext *ctx, GLenum opcode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP, 1);
- OUT_RING_CACHE(opcode);
-}
-
-static void nv20PointParameterfv(GLcontext *ctx, GLenum pname, const GLfloat *params)
-{
- /*TODO: not sure what goes here. */
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
-}
-
-/** Specify the diameter of rasterized points */
-static void nv20PointSize(GLcontext *ctx, GLfloat size)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POINT_SIZE, 1);
- OUT_RING_CACHEf(size);
-}
-
-/** Select a polygon rasterization mode */
-static void nv20PolygonMode(GLcontext *ctx, GLenum face, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (face == GL_FRONT || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT, 1);
- OUT_RING_CACHE(mode);
- }
- if (face == GL_BACK || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK, 1);
- OUT_RING_CACHE(mode);
- }
-}
-
-/** Set the scale and units used to calculate depth values */
-static void nv20PolygonOffset(GLcontext *ctx, GLfloat factor, GLfloat units)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR, 2);
- OUT_RING_CACHEf(factor);
- OUT_RING_CACHEf(units);
-}
-
-/** Set the polygon stippling pattern */
-static void nv20PolygonStipple(GLcontext *ctx, const GLubyte *mask )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN(0), 32);
- OUT_RING_CACHEp(mask, 32);
-}
-
-/* Specifies the current buffer for reading */
-void (*ReadBuffer)( GLcontext *ctx, GLenum buffer );
-/** Set rasterization mode */
-void (*RenderMode)(GLcontext *ctx, GLenum mode );
-
-/** Define the scissor box */
-static void nv20Scissor(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- /* There's no scissor enable bit, so adjust the scissor to cover the
- * maximum draw buffer bounds
- */
- if (!ctx->Scissor.Enabled) {
- x = y = 0;
- w = h = 4095;
- } else {
- x += nmesa->drawX;
- y += nmesa->drawY;
- }
-
- /*BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SCISSOR_X2_X1, 1);
- OUT_RING_CACHE((w << 16) | x );
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SCISSOR_Y2_Y1, 1);
- OUT_RING_CACHE((h << 16) | y );*/
-
-}
-
-/** Select flat or smooth shading */
-static void nv20ShadeModel(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SHADE_MODEL, 1);
- OUT_RING_CACHE(mode);
-}
-
-/** OpenGL 2.0 two-sided StencilFunc */
-static void nv20StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func,
- GLint ref, GLuint mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_STENCIL_FUNC_FUNC, 3);
- OUT_RING_CACHE(func);
- OUT_RING_CACHE(ref);
- OUT_RING_CACHE(mask);
-}
-
-/** OpenGL 2.0 two-sided StencilMask */
-static void nv20StencilMaskSeparate(GLcontext *ctx, GLenum face, GLuint mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_STENCIL_MASK, 1);
- OUT_RING_CACHE(mask);
-}
-
-/** OpenGL 2.0 two-sided StencilOp */
-static void nv20StencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail,
- GLenum zfail, GLenum zpass)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_STENCIL_OP_FAIL, 1);
- OUT_RING_CACHE(fail);
- OUT_RING_CACHE(zfail);
- OUT_RING_CACHE(zpass);
-}
-
-/** Control the generation of texture coordinates */
-void (*TexGen)(GLcontext *ctx, GLenum coord, GLenum pname,
- const GLfloat *params);
-/** Set texture environment parameters */
-void (*TexEnv)(GLcontext *ctx, GLenum target, GLenum pname,
- const GLfloat *param);
-/** Set texture parameters */
-void (*TexParameter)(GLcontext *ctx, GLenum target,
- struct gl_texture_object *texObj,
- GLenum pname, const GLfloat *params);
-
-static void nv20TextureMatrix(GLcontext *ctx, GLuint unit, const GLmatrix *mat)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_TX_MATRIX(unit, 0), 16);
- /*XXX: This SHOULD work.*/
- OUT_RING_CACHEp(mat->m, 16);
-}
-
-/* Update anything that depends on the window position/size */
-static void nv20WindowMoved(nouveauContextPtr nmesa)
-{
- GLcontext *ctx = nmesa->glCtx;
- GLfloat *v = nmesa->viewport.m;
- GLuint w = ctx->Viewport.Width;
- GLuint h = ctx->Viewport.Height;
- GLuint x = ctx->Viewport.X + nmesa->drawX;
- GLuint y = ctx->Viewport.Y + nmesa->drawY;
- int i;
-
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ, 2);
- OUT_RING_CACHE((w << 16) | x);
- OUT_RING_CACHE((h << 16) | y);
-
- BEGIN_RING_SIZE(NvSub3D, 0x02b4, 1);
- OUT_RING(0);
-
- BEGIN_RING_CACHE(NvSub3D,
- NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(0), 1);
- OUT_RING_CACHE((4095 << 16) | 0);
- BEGIN_RING_CACHE(NvSub3D,
- NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(0), 1);
- OUT_RING_CACHE((4095 << 16) | 0);
- for (i=1; i<8; i++) {
- BEGIN_RING_CACHE(NvSub3D,
- NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(i), 1);
- OUT_RING_CACHE(0);
- BEGIN_RING_CACHE(NvSub3D,
- NV20_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_VERT(i), 1);
- OUT_RING_CACHE(0);
- }
-
- ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
- ctx->Scissor.Width, ctx->Scissor.Height);
-
- /* TODO: recalc viewport scale coefs */
-}
-
-/* Initialise any card-specific non-GL related state */
-static GLboolean nv20InitCard(nouveauContextPtr nmesa)
-{
- nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D);
-
- BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SET_OBJECT1, 2);
- OUT_RING(NvDmaFB); /* 184 dma_object1 */
- OUT_RING(NvDmaFB); /* 188 dma_object2 */
- BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SET_OBJECT3, 2);
- OUT_RING(NvDmaFB); /* 194 dma_object3 */
- OUT_RING(NvDmaFB); /* 198 dma_object4 */
- BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_SET_OBJECT8, 1);
- OUT_RING(NvDmaFB); /* 1a8 dma_object8 */
-
- BEGIN_RING_SIZE(NvSub3D, 0x17e0, 3);
- OUT_RINGf(0.0);
- OUT_RINGf(0.0);
- OUT_RINGf(1.0);
-
- BEGIN_RING_SIZE(NvSub3D, 0x1e6c, 1);
- OUT_RING(0x0db6);
- BEGIN_RING_SIZE(NvSub3D, 0x0290, 1);
- OUT_RING(0x00100001);
- BEGIN_RING_SIZE(NvSub3D, 0x09fc, 1);
- OUT_RING(0);
- BEGIN_RING_SIZE(NvSub3D, 0x1d80, 1);
- OUT_RING(1);
- BEGIN_RING_SIZE(NvSub3D, 0x09f8, 1);
- OUT_RING(4);
-
- BEGIN_RING_SIZE(NvSub3D, 0x17ec, 3);
- OUT_RINGf(0.0);
- OUT_RINGf(1.0);
- OUT_RINGf(0.0);
-
- BEGIN_RING_SIZE(NvSub3D, 0x1d88, 1);
- OUT_RING(3);
-
- /* FIXME: More dma objects to setup ? */
-
- BEGIN_RING_SIZE(NvSub3D, 0x1e98, 1);
- OUT_RING(0);
-
- BEGIN_RING_SIZE(NvSub3D, 0x120, 3);
- OUT_RING(0);
- OUT_RING(1);
- OUT_RING(2);
-
- return GL_TRUE;
-}
-
-/* Update buffer offset/pitch/format */
-static GLboolean nv20BindBuffers(nouveauContextPtr nmesa, int num_color,
- nouveau_renderbuffer_t **color,
- nouveau_renderbuffer_t *depth)
-{
- GLuint x, y, w, h;
- GLuint pitch, format, depth_pitch;
-
- w = color[0]->mesa.Width;
- h = color[0]->mesa.Height;
- x = nmesa->drawX;
- y = nmesa->drawY;
-
- if (num_color != 1)
- return GL_FALSE;
-
- BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_VIEWPORT_HORIZ, 6);
- OUT_RING_CACHE((w << 16) | x);
- OUT_RING_CACHE((h << 16) | y);
- depth_pitch = (depth ? depth->pitch : color[0]->pitch);
- pitch = (depth_pitch<<16) | color[0]->pitch;
- format = 0x128;
- if (color[0]->mesa._ActualFormat != GL_RGBA8) {
- format = 0x123; /* R5G6B5 color buffer */
- }
- OUT_RING_CACHE(format);
- OUT_RING_CACHE(pitch);
- OUT_RING_CACHE(color[0]->offset);
- OUT_RING_CACHE(depth ? depth->offset : color[0]->offset);
-
- if (depth) {
- BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH, 2);
- /* TODO: use a different buffer */
- OUT_RING(depth->pitch);
- OUT_RING(depth->offset);
- }
-
- /* Always set to bottom left of buffer */
- /*BEGIN_RING_CACHE(NvSub3D, NV20_TCL_PRIMITIVE_3D_VIEWPORT_ORIGIN_X, 4);
- OUT_RING_CACHEf (0.0);
- OUT_RING_CACHEf ((GLfloat) h);
- OUT_RING_CACHEf (0.0);
- OUT_RING_CACHEf (0.0);*/
-
- return GL_TRUE;
-}
-
-void nv20InitStateFuncs(GLcontext *ctx, struct dd_function_table *func)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- func->AlphaFunc = nv20AlphaFunc;
- func->BlendColor = nv20BlendColor;
- func->BlendEquationSeparate = nv20BlendEquationSeparate;
- func->BlendFuncSeparate = nv20BlendFuncSeparate;
- func->Clear = nv20Clear;
- func->ClearColor = nv20ClearColor;
- func->ClearDepth = nv20ClearDepth;
- func->ClearStencil = nv20ClearStencil;
- func->ClipPlane = nv20ClipPlane;
- func->ColorMask = nv20ColorMask;
- func->ColorMaterial = nv20ColorMaterial;
- func->CullFace = nv20CullFace;
- func->FrontFace = nv20FrontFace;
- func->DepthFunc = nv20DepthFunc;
- func->DepthMask = nv20DepthMask;
- func->DepthRange = nv20DepthRange;
- func->Enable = nv20Enable;
- func->Fogfv = nv20Fogfv;
- func->Hint = nv20Hint;
- func->Lightfv = nv20Lightfv;
-/* func->LightModelfv = nv20LightModelfv; */
- func->LineStipple = nv20LineStipple;
- func->LineWidth = nv20LineWidth;
- func->LogicOpcode = nv20LogicOpcode;
- func->PointParameterfv = nv20PointParameterfv;
- func->PointSize = nv20PointSize;
- func->PolygonMode = nv20PolygonMode;
- func->PolygonOffset = nv20PolygonOffset;
- func->PolygonStipple = nv20PolygonStipple;
-/* func->ReadBuffer = nv20ReadBuffer;*/
-/* func->RenderMode = nv20RenderMode;*/
- func->Scissor = nv20Scissor;
- func->ShadeModel = nv20ShadeModel;
- func->StencilFuncSeparate = nv20StencilFuncSeparate;
- func->StencilMaskSeparate = nv20StencilMaskSeparate;
- func->StencilOpSeparate = nv20StencilOpSeparate;
-/* func->TexGen = nv20TexGen;*/
-/* func->TexParameter = nv20TexParameter;*/
- func->TextureMatrix = nv20TextureMatrix;
-
- nmesa->hw_func.InitCard = nv20InitCard;
- nmesa->hw_func.BindBuffers = nv20BindBuffers;
- nmesa->hw_func.WindowMoved = nv20WindowMoved;
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nv20_vertprog.c b/src/mesa/drivers/dri/nouveau/nv20_vertprog.c
deleted file mode 100644
index 60cfcd7056..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv20_vertprog.c
+++ /dev/null
@@ -1,447 +0,0 @@
-#include "nouveau_context.h"
-#include "nouveau_object.h"
-#include "nouveau_fifo.h"
-#include "nouveau_reg.h"
-
-#include "nouveau_shader.h"
-#include "nv20_shader.h"
-
-unsigned int NVVP_TX_VOP_COUNT = 16;
-unsigned int NVVP_TX_NVS_OP_COUNT = 16;
-struct _op_xlat NVVP_TX_VOP[32];
-struct _op_xlat NVVP_TX_SOP[32];
-
-nvsSwzComp NV20VP_TX_SWIZZLE[4] = { NVS_SWZ_X, NVS_SWZ_Y, NVS_SWZ_Z, NVS_SWZ_W };
-
-/*****************************************************************************
- * Support routines
- */
-static void
-NV20VPUploadToHW(GLcontext *ctx, nouveauShader *nvs)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- int i;
-
- /* XXX: missing a way to say what insn we're uploading from, and possible
- * the program start position (if NV20 has one) */
- for (i=0; iprogram_size; i+=4) {
- BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_INST0, 4);
- OUT_RING(nvs->program[i + 0]);
- OUT_RING(nvs->program[i + 1]);
- OUT_RING(nvs->program[i + 2]);
- OUT_RING(nvs->program[i + 3]);
- }
-}
-
-static void
-NV20VPUpdateConst(GLcontext *ctx, nouveauShader *nvs, int id)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- /* Worth checking if the value *actually* changed? Mesa doesn't tell us this
- * as far as I know..
- */
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID, 1);
- OUT_RING (id);
- BEGIN_RING_SIZE(NvSub3D, NV20_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_X, 4);
- OUT_RINGf(nvs->params[id].source_val[0]);
- OUT_RINGf(nvs->params[id].source_val[1]);
- OUT_RINGf(nvs->params[id].source_val[2]);
- OUT_RINGf(nvs->params[id].source_val[3]);
-}
-
-/*****************************************************************************
- * Assembly routines
- */
-
-/*****************************************************************************
- * Disassembly routines
- */
-void
-NV20VPTXSwizzle(int hwswz, nvsSwzComp *swz)
-{
- swz[NVS_SWZ_X] = NV20VP_TX_SWIZZLE[(hwswz & 0xC0) >> 6];
- swz[NVS_SWZ_Y] = NV20VP_TX_SWIZZLE[(hwswz & 0x30) >> 4];
- swz[NVS_SWZ_Z] = NV20VP_TX_SWIZZLE[(hwswz & 0x0C) >> 2];
- swz[NVS_SWZ_W] = NV20VP_TX_SWIZZLE[(hwswz & 0x03) >> 0];
-}
-
-static int
-NV20VPHasMergedInst(nvsFunc * shader)
-{
- if (shader->GetOpcodeHW(shader, 0) != NV20_VP_INST_OPCODE_NOP &&
- shader->GetOpcodeHW(shader, 1) != NV20_VP_INST_OPCODE_NOP)
- printf
- ("\n\n*****both opcode fields have values - PLEASE REPORT*****\n");
- return 0;
-}
-
-static int
-NV20VPIsLastInst(nvsFunc * shader)
-{
- return ((shader->inst[3] & (1 << 0)) ? 1 : 0);
-}
-
-static int
-NV20VPGetOffsetNext(nvsFunc * shader)
-{
- return 4;
-}
-
-static struct _op_xlat *
-NV20VPGetOPTXRec(nvsFunc * shader, int merged)
-{
- struct _op_xlat *opr;
- int op;
-
- if (shader->GetOpcodeSlot(shader, merged)) {
- opr = NVVP_TX_SOP;
- op = shader->GetOpcodeHW(shader, 1);
- if (op >= NVVP_TX_NVS_OP_COUNT)
- return NULL;
- }
- else {
- opr = NVVP_TX_VOP;
- op = shader->GetOpcodeHW(shader, 0);
- if (op >= NVVP_TX_VOP_COUNT)
- return NULL;
- }
-
- if (opr[op].SOP == NVS_OP_UNKNOWN)
- return NULL;
- return &opr[op];
-}
-
-static struct _op_xlat *
-NV20VPGetOPTXFromSOP(nvsOpcode sop, int *id)
-{
- int i;
-
- for (i=0;iHasMergedInst(shader))
- return merged;
- if (shader->GetOpcodeHW(shader, 0) == NV20_VP_INST_OPCODE_NOP)
- return 1;
- return 0;
-}
-
-static nvsOpcode
-NV20VPGetOpcode(nvsFunc * shader, int merged)
-{
- struct _op_xlat *opr;
-
- opr = shader->GetOPTXRec(shader, merged);
- if (!opr)
- return NVS_OP_UNKNOWN;
-
- return opr->SOP;
-}
-
-static nvsOpcode
-NV20VPGetOpcodeHW(nvsFunc * shader, int slot)
-{
- if (slot)
- return (shader->inst[1] & NV20_VP_INST_SCA_OPCODE_MASK)
- >> NV20_VP_INST_SCA_OPCODE_SHIFT;
- return (shader->inst[1] & NV20_VP_INST_VEC_OPCODE_MASK)
- >> NV20_VP_INST_VEC_OPCODE_SHIFT;
-}
-
-static nvsRegFile
-NV20VPGetDestFile(nvsFunc * shader, int merged)
-{
- switch (shader->GetOpcode(shader, merged)) {
- case NVS_OP_ARL:
- return NVS_FILE_ADDRESS;
- default:
- /*FIXME: This probably isn't correct.. */
- if ((shader->inst[3] & NV20_VP_INST_DEST_WRITEMASK_MASK) == 0)
- return NVS_FILE_TEMP;
- return NVS_FILE_RESULT;
- }
-}
-
-static unsigned int
-NV20VPGetDestID(nvsFunc * shader, int merged)
-{
- int id;
-
- switch (shader->GetDestFile(shader, merged)) {
- case NVS_FILE_RESULT:
- id = ((shader->inst[3] & NV20_VP_INST_DEST_MASK)
- >> NV20_VP_INST_DEST_SHIFT);
- switch (id) {
- case NV20_VP_INST_DEST_POS : return NVS_FR_POSITION;
- case NV20_VP_INST_DEST_COL0 : return NVS_FR_COL0;
- case NV20_VP_INST_DEST_COL1 : return NVS_FR_COL1;
- case NV20_VP_INST_DEST_TC(0): return NVS_FR_TEXCOORD0;
- case NV20_VP_INST_DEST_TC(1): return NVS_FR_TEXCOORD1;
- case NV20_VP_INST_DEST_TC(2): return NVS_FR_TEXCOORD2;
- case NV20_VP_INST_DEST_TC(3): return NVS_FR_TEXCOORD3;
- default:
- return -1;
- }
- case NVS_FILE_ADDRESS:
- return 0;
- case NVS_FILE_TEMP:
- id = ((shader->inst[3] & NV20_VP_INST_DEST_TEMP_ID_MASK)
- >> NV20_VP_INST_DEST_TEMP_ID_SHIFT);
- return id;
- default:
- return -1;
- }
-}
-
-static unsigned int
-NV20VPGetDestMask(nvsFunc * shader, int merged)
-{
- int hwmask, mask = 0;
-
- /* Special handling for ARL - hardware only supports a
- * 1-component address reg
- */
- if (shader->GetOpcode(shader, merged) == NVS_OP_ARL)
- return SMASK_X;
-
- if (shader->GetDestFile(shader, merged) == NVS_FILE_RESULT)
- hwmask = (shader->inst[3] & NV20_VP_INST_DEST_WRITEMASK_MASK)
- >> NV20_VP_INST_DEST_WRITEMASK_SHIFT;
- else if (shader->GetOpcodeSlot(shader, merged))
- hwmask = (shader->inst[3] & NV20_VP_INST_STEMP_WRITEMASK_MASK)
- >> NV20_VP_INST_STEMP_WRITEMASK_SHIFT;
- else
- hwmask = (shader->inst[3] & NV20_VP_INST_VTEMP_WRITEMASK_MASK)
- >> NV20_VP_INST_VTEMP_WRITEMASK_SHIFT;
-
- if (hwmask & (1 << 3)) mask |= SMASK_X;
- if (hwmask & (1 << 2)) mask |= SMASK_Y;
- if (hwmask & (1 << 1)) mask |= SMASK_Z;
- if (hwmask & (1 << 0)) mask |= SMASK_W;
-
- return mask;
-}
-
-static unsigned int
-NV20VPGetSourceHW(nvsFunc * shader, int merged, int pos)
-{
- struct _op_xlat *opr;
- unsigned int src;
-
- opr = shader->GetOPTXRec(shader, merged);
- if (!opr)
- return -1;
-
- switch (opr->srcpos[pos]) {
- case 0:
- src = ((shader->inst[1] & NV20_VP_INST_SRC0H_MASK)
- >> NV20_VP_INST_SRC0H_SHIFT)
- << NV20_VP_SRC0_HIGH_SHIFT;
- src |= ((shader->inst[2] & NV20_VP_INST_SRC0L_MASK)
- >> NV20_VP_INST_SRC0L_SHIFT);
- break;
- case 1:
- src = ((shader->inst[2] & NV20_VP_INST_SRC1_MASK)
- >> NV20_VP_INST_SRC1_SHIFT);
- break;
- case 2:
- src = ((shader->inst[2] & NV20_VP_INST_SRC2H_MASK)
- >> NV20_VP_INST_SRC2H_SHIFT)
- << NV20_VP_SRC2_HIGH_SHIFT;
- src |= ((shader->inst[3] & NV20_VP_INST_SRC2L_MASK)
- >> NV20_VP_INST_SRC2L_SHIFT);
- break;
- default:
- src = -1;
- }
-
- return src;
-}
-
-static nvsRegFile
-NV20VPGetSourceFile(nvsFunc * shader, int merged, int pos)
-{
- unsigned int src;
- struct _op_xlat *opr;
- int file;
-
- opr = shader->GetOPTXRec(shader, merged);
- if (!opr || opr->srcpos[pos] == -1)
- return -1;
-
- switch (opr->srcpos[pos]) {
- case SPOS_ADDRESS:
- return NVS_FILE_ADDRESS;
- default:
- src = NV20VPGetSourceHW(shader, merged, pos);
- file = (src & NV20_VP_SRC_REG_TYPE_MASK) >> NV20_VP_SRC_REG_TYPE_SHIFT;
-
- switch (file) {
- case NV20_VP_SRC_REG_TYPE_TEMP : return NVS_FILE_TEMP;
- case NV20_VP_SRC_REG_TYPE_INPUT: return NVS_FILE_ATTRIB;
- case NV20_VP_SRC_REG_TYPE_CONST: return NVS_FILE_CONST;
- default:
- return NVS_FILE_UNKNOWN;
- }
- }
-}
-
-static int
-NV20VPGetSourceID(nvsFunc * shader, int merged, int pos)
-{
- unsigned int src;
-
- switch (shader->GetSourceFile(shader, merged, pos)) {
- case NVS_FILE_TEMP:
- src = shader->GetSourceHW(shader, merged, pos);
- return ((src & NV20_VP_SRC_REG_TEMP_ID_MASK) >>
- NV20_VP_SRC_REG_TEMP_ID_SHIFT);
- case NVS_FILE_CONST:
- return ((shader->inst[1] & NV20_VP_INST_CONST_SRC_MASK)
- >> NV20_VP_INST_CONST_SRC_SHIFT);
- case NVS_FILE_ATTRIB:
- src = ((shader->inst[1] & NV20_VP_INST_INPUT_SRC_MASK)
- >> NV20_VP_INST_INPUT_SRC_SHIFT);
- switch (src) {
- case NV20_VP_INST_INPUT_SRC_POS : return NVS_FR_POSITION;
- case NV20_VP_INST_INPUT_SRC_COL0 : return NVS_FR_COL0;
- case NV20_VP_INST_INPUT_SRC_COL1 : return NVS_FR_COL1;
- case NV20_VP_INST_INPUT_SRC_TC(0): return NVS_FR_TEXCOORD0;
- case NV20_VP_INST_INPUT_SRC_TC(1): return NVS_FR_TEXCOORD1;
- case NV20_VP_INST_INPUT_SRC_TC(2): return NVS_FR_TEXCOORD2;
- case NV20_VP_INST_INPUT_SRC_TC(3): return NVS_FR_TEXCOORD3;
- default:
- return NVS_FR_UNKNOWN;
- }
- default:
- return -1;
- }
-}
-
-static int
-NV20VPGetSourceNegate(nvsFunc * shader, int merged, int pos)
-{
- unsigned int src;
-
- src = shader->GetSourceHW(shader, merged, pos);
-
- return ((src & NV20_VP_SRC_REG_NEGATE) ? 1 : 0);
-}
-
-static int
-NV20VPGetSourceAbs(nvsFunc * shader, int merged, int pos)
-{
- /* NV20 can't do ABS on sources? Appears to be emulated with
- * MAX reg, reg, -reg
- */
- return 0;
-}
-
-static void
-NV20VPGetSourceSwizzle(nvsFunc * shader, int merged, int pos, nvsSwzComp *swz)
-{
- unsigned int src;
- int swzbits;
-
- src = shader->GetSourceHW(shader, merged, pos);
- swzbits =
- (src & NV20_VP_SRC_REG_SWZ_ALL_MASK) >> NV20_VP_SRC_REG_SWZ_ALL_SHIFT;
- return NV20VPTXSwizzle(swzbits, swz);
-}
-
-static int
-NV20VPGetSourceIndexed(nvsFunc * shader, int merged, int pos)
-{
- /* I don't think NV20 can index into attribs, at least no GL
- * extension is exposed that will allow it.
- */
- if (shader->GetSourceFile(shader, merged, pos) != NVS_FILE_CONST)
- return 0;
- if (shader->inst[3] & NV20_VP_INST_INDEX_CONST)
- return 1;
- return 0;
-}
-
-static int
-NV20VPGetAddressRegID(nvsFunc * shader)
-{
- /* Only 1 address reg */
- return 0;
-}
-
-static nvsSwzComp
-NV20VPGetAddressRegSwizzle(nvsFunc * shader)
-{
- /* Only A0.x available */
- return NVS_SWZ_X;
-}
-
-void
-NV20VPInitShaderFuncs(nvsFunc * shader)
-{
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_NOP, NVS_OP_NOP, -1, -1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_MOV, NVS_OP_MOV, 0, -1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_MUL, NVS_OP_MUL, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_ADD, NVS_OP_ADD, 0, 2, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_MAD, NVS_OP_MAD, 0, 1, 2);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_DP3, NVS_OP_DP3, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_DPH, NVS_OP_DPH, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_DP4, NVS_OP_DP4, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_DST, NVS_OP_DST, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_MIN, NVS_OP_MIN, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_MAX, NVS_OP_MAX, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_SLT, NVS_OP_SLT, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_SGE, NVS_OP_SGE, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV20_VP_INST_OPCODE_ARL, NVS_OP_ARL, 0, -1, -1);
-
- MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_NOP, NVS_OP_NOP, -1, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_RCP, NVS_OP_RCP, 2, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_RCC, NVS_OP_RCC, 2, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_RSQ, NVS_OP_RSQ, 2, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_EXP, NVS_OP_EXP, 2, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_LOG, NVS_OP_LOG, 2, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV20_VP_INST_OPCODE_LIT, NVS_OP_LIT, 2, -1, -1);
-
- shader->UploadToHW = NV20VPUploadToHW;
- shader->UpdateConst = NV20VPUpdateConst;
-
- shader->GetOPTXRec = NV20VPGetOPTXRec;
- shader->GetOPTXFromSOP = NV20VPGetOPTXFromSOP;
-
- shader->HasMergedInst = NV20VPHasMergedInst;
- shader->IsLastInst = NV20VPIsLastInst;
- shader->GetOffsetNext = NV20VPGetOffsetNext;
- shader->GetOpcodeSlot = NV20VPGetOpcodeSlot;
- shader->GetOpcode = NV20VPGetOpcode;
- shader->GetOpcodeHW = NV20VPGetOpcodeHW;
- shader->GetDestFile = NV20VPGetDestFile;
- shader->GetDestID = NV20VPGetDestID;
- shader->GetDestMask = NV20VPGetDestMask;
- shader->GetSourceHW = NV20VPGetSourceHW;
- shader->GetSourceFile = NV20VPGetSourceFile;
- shader->GetSourceID = NV20VPGetSourceID;
- shader->GetSourceNegate = NV20VPGetSourceNegate;
- shader->GetSourceAbs = NV20VPGetSourceAbs;
- shader->GetSourceSwizzle = NV20VPGetSourceSwizzle;
- shader->GetSourceIndexed = NV20VPGetSourceIndexed;
- shader->GetRelAddressRegID = NV20VPGetAddressRegID;
- shader->GetRelAddressSwizzle = NV20VPGetAddressRegSwizzle;
-}
diff --git a/src/mesa/drivers/dri/nouveau/nv30_fragprog.c b/src/mesa/drivers/dri/nouveau/nv30_fragprog.c
deleted file mode 100644
index 5f61f76a0a..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv30_fragprog.c
+++ /dev/null
@@ -1,742 +0,0 @@
-#include
-
-#include "glheader.h"
-#include "macros.h"
-
-#include "nouveau_context.h"
-#include "nouveau_fifo.h"
-#include "nouveau_reg.h"
-#include "nouveau_drm.h"
-#include "nouveau_shader.h"
-#include "nouveau_object.h"
-#include "nouveau_msg.h"
-#include "nouveau_bufferobj.h"
-#include "nv30_shader.h"
-
-unsigned int NVFP_TX_AOP_COUNT = 64;
-struct _op_xlat NVFP_TX_AOP[64];
-
-/*******************************************************************************
- * Support routines
- */
-
-static void
-NV30FPUploadToHW(GLcontext *ctx, nouveauShader *nvs)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nvsCardPriv *priv = &nvs->card_priv;
- uint32_t offset;
-
- if (!nvs->program_buffer)
- nvs->program_buffer = ctx->Driver.NewBufferObject(ctx, 0,
- GL_ARRAY_BUFFER_ARB);
-
- /* Should use STATIC_DRAW_ARB if shader doesn't use changable params */
- nouveau_bo_init_storage(ctx, NOUVEAU_BO_VRAM_OK,
- nvs->program_size * sizeof(uint32_t),
- (const GLvoid *)nvs->program,
- GL_DYNAMIC_DRAW_ARB,
- nvs->program_buffer, 1);
-
- offset = nouveau_bo_gpu_ref(ctx, nvs->program_buffer);
-
- /* Not using state cache here, updated programs at the same address don't
- * seem to take effect unless the ACTIVE_PROGRAM method is called again.
- * HW caches the program somewhere?
- */
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FP_ACTIVE_PROGRAM, 1);
- OUT_RING (offset | 1);
- if (nmesa->screen->card->type == NV_30) {
- BEGIN_RING_SIZE(NvSub3D,
- 0x1d60 /*NV30_TCL_PRIMITIVE_3D_FP_CONTROL*/, 1);
- OUT_RING ((priv->NV30FP.uses_kil << 7));
- BEGIN_RING_SIZE(NvSub3D, 0x1450, 1);
- OUT_RING (priv->NV30FP.num_regs << 16);
- } else {
- BEGIN_RING_SIZE(NvSub3D,
- 0x1d60 /*NV30_TCL_PRIMITIVE_3D_FP_CONTROL*/, 1);
- OUT_RING ((priv->NV30FP.uses_kil << 7) |
- (priv->NV30FP.num_regs << 24));
- }
-}
-
-static void
-NV30FPUpdateConst(GLcontext *ctx, nouveauShader *nvs, int id)
-{
- uint32_t *new = nvs->params[id].source_val ?
- (uint32_t*)nvs->params[id].source_val : (uint32_t*)nvs->params[id].val;
- uint32_t *current;
- int i;
-
- for (i=0; iparams[id].hw_index_cnt; i++) {
- current = nvs->program + nvs->params[id].hw_index[i];
- COPY_4V(current, new);
- }
- nvs->on_hardware = 0;
-}
-
-/*******************************************************************************
- * Assembly helpers
- */
-static struct _op_xlat *
-NV30FPGetOPTXFromSOP(nvsOpcode op, int *id)
-{
- int i;
-
- for (i=0; iGetOPTXFromSOP(op, NULL))
- return 1;
- return 0;
-}
-
-static void
-NV30FPSetOpcode(nvsFunc *shader, unsigned int opcode, int slot)
-{
- if (opcode == NV30_FP_OP_OPCODE_KIL)
- shader->card_priv->NV30FP.uses_kil = GL_TRUE;
- shader->inst[0] &= ~NV30_FP_OP_OPCODE_MASK;
- shader->inst[0] |= (opcode << NV30_FP_OP_OPCODE_SHIFT);
-}
-
-static void
-NV30FPSetCCUpdate(nvsFunc *shader)
-{
- shader->inst[0] |= NV30_FP_OP_COND_WRITE_ENABLE;
-}
-
-static void
-NV30FPSetCondition(nvsFunc *shader, int on, nvsCond cond, int reg,
- nvsSwzComp *swz)
-{
- nvsSwzComp default_swz[4] = { NVS_SWZ_X, NVS_SWZ_Y, NVS_SWZ_Z, NVS_SWZ_W };
- unsigned int hwcond;
-
- /* cond masking is always enabled */
- if (!on) {
- cond = NVS_COND_TR;
- reg = 0;
- swz = default_swz;
- }
-
- switch (cond) {
- case NVS_COND_TR: hwcond = NV30_FP_OP_COND_TR; break;
- case NVS_COND_FL: hwcond = NV30_FP_OP_COND_FL; break;
- case NVS_COND_LT: hwcond = NV30_FP_OP_COND_LT; break;
- case NVS_COND_GT: hwcond = NV30_FP_OP_COND_GT; break;
- case NVS_COND_LE: hwcond = NV30_FP_OP_COND_LE; break;
- case NVS_COND_GE: hwcond = NV30_FP_OP_COND_GE; break;
- case NVS_COND_EQ: hwcond = NV30_FP_OP_COND_EQ; break;
- case NVS_COND_NE: hwcond = NV30_FP_OP_COND_NE; break;
- default:
- WARN_ONCE("unknown fp condmask=%d\n", cond);
- hwcond = NV30_FP_OP_COND_TR;
- break;
- }
-
- shader->inst[1] &= ~NV30_FP_OP_COND_MASK;
- shader->inst[1] |= (hwcond << NV30_FP_OP_COND_SHIFT);
-
- shader->inst[1] &= ~NV30_FP_OP_COND_SWZ_ALL_MASK;
- shader->inst[1] |= (swz[NVS_SWZ_X] << NV30_FP_OP_COND_SWZ_X_SHIFT);
- shader->inst[1] |= (swz[NVS_SWZ_Y] << NV30_FP_OP_COND_SWZ_Y_SHIFT);
- shader->inst[1] |= (swz[NVS_SWZ_Z] << NV30_FP_OP_COND_SWZ_Z_SHIFT);
- shader->inst[1] |= (swz[NVS_SWZ_W] << NV30_FP_OP_COND_SWZ_W_SHIFT);
-}
-
-static void
-NV30FPSetHighReg(nvsFunc *shader, int id)
-{
- if (shader->card_priv->NV30FP.num_regs < (id+1)) {
- if (id == 0)
- id = 1; /* necessary? */
- shader->card_priv->NV30FP.num_regs = (id+1);
- }
-}
-
-static void
-NV30FPSetResult(nvsFunc *shader, nvsRegister *reg, unsigned int mask, int slot)
-{
- unsigned int hwreg;
-
- if (mask & SMASK_X) shader->inst[0] |= NV30_FP_OP_OUT_X;
- if (mask & SMASK_Y) shader->inst[0] |= NV30_FP_OP_OUT_Y;
- if (mask & SMASK_Z) shader->inst[0] |= NV30_FP_OP_OUT_Z;
- if (mask & SMASK_W) shader->inst[0] |= NV30_FP_OP_OUT_W;
-
- if (reg->file == NVS_FILE_RESULT) {
- hwreg = 0; /* FIXME: this is only fragment.color */
- /* This is *not* correct, I have no idea what it is either */
- shader->inst[0] |= NV30_FP_OP_UNK0_7;
- } else {
- shader->inst[0] &= ~NV30_FP_OP_UNK0_7;
- hwreg = reg->index;
- }
- NV30FPSetHighReg(shader, hwreg);
- shader->inst[0] &= ~NV30_FP_OP_OUT_REG_SHIFT;
- shader->inst[0] |= (hwreg << NV30_FP_OP_OUT_REG_SHIFT);
-}
-
-static void
-NV30FPSetSource(nvsFunc *shader, nvsRegister *reg, int pos)
-{
- unsigned int hwsrc = 0;
-
- switch (reg->file) {
- case NVS_FILE_TEMP:
- hwsrc |= (NV30_FP_REG_TYPE_TEMP << NV30_FP_REG_TYPE_SHIFT);
- hwsrc |= (reg->index << NV30_FP_REG_SRC_SHIFT);
- NV30FPSetHighReg(shader, reg->index);
- break;
- case NVS_FILE_ATTRIB:
- {
- unsigned int hwin;
-
- switch (reg->index) {
- case NVS_FR_POSITION : hwin = NV30_FP_OP_INPUT_SRC_POSITION; break;
- case NVS_FR_COL0 : hwin = NV30_FP_OP_INPUT_SRC_COL0; break;
- case NVS_FR_COL1 : hwin = NV30_FP_OP_INPUT_SRC_COL1; break;
- case NVS_FR_FOGCOORD : hwin = NV30_FP_OP_INPUT_SRC_FOGC; break;
- case NVS_FR_TEXCOORD0: hwin = NV30_FP_OP_INPUT_SRC_TC(0); break;
- case NVS_FR_TEXCOORD1: hwin = NV30_FP_OP_INPUT_SRC_TC(1); break;
- case NVS_FR_TEXCOORD2: hwin = NV30_FP_OP_INPUT_SRC_TC(2); break;
- case NVS_FR_TEXCOORD3: hwin = NV30_FP_OP_INPUT_SRC_TC(3); break;
- case NVS_FR_TEXCOORD4: hwin = NV30_FP_OP_INPUT_SRC_TC(4); break;
- case NVS_FR_TEXCOORD5: hwin = NV30_FP_OP_INPUT_SRC_TC(5); break;
- case NVS_FR_TEXCOORD6: hwin = NV30_FP_OP_INPUT_SRC_TC(6); break;
- case NVS_FR_TEXCOORD7: hwin = NV30_FP_OP_INPUT_SRC_TC(7); break;
- default:
- WARN_ONCE("unknown fp input %d\n", reg->index);
- hwin = NV30_FP_OP_INPUT_SRC_COL0;
- break;
- }
- shader->inst[0] &= ~NV30_FP_OP_INPUT_SRC_MASK;
- shader->inst[0] |= (hwin << NV30_FP_OP_INPUT_SRC_SHIFT);
- hwsrc |= (hwin << NV30_FP_REG_SRC_SHIFT);
- }
- hwsrc |= (NV30_FP_REG_TYPE_INPUT << NV30_FP_REG_TYPE_SHIFT);
- break;
- case NVS_FILE_CONST:
- /* consts are inlined after the inst */
- hwsrc |= (NV30_FP_REG_TYPE_CONST << NV30_FP_REG_TYPE_SHIFT);
- break;
- default:
- assert(0);
- break;
- }
-
- if (reg->negate)
- hwsrc |= NV30_FP_REG_NEGATE;
- if (reg->abs)
- shader->inst[1] |= (1 << (29+pos));
- hwsrc |= (reg->swizzle[NVS_SWZ_X] << NV30_FP_REG_SWZ_X_SHIFT);
- hwsrc |= (reg->swizzle[NVS_SWZ_Y] << NV30_FP_REG_SWZ_Y_SHIFT);
- hwsrc |= (reg->swizzle[NVS_SWZ_Z] << NV30_FP_REG_SWZ_Z_SHIFT);
- hwsrc |= (reg->swizzle[NVS_SWZ_W] << NV30_FP_REG_SWZ_W_SHIFT);
-
- shader->inst[pos+1] &= ~NV30_FP_REG_ALL_MASK;
- shader->inst[pos+1] |= hwsrc;
-}
-
-static void
-NV30FPSetTexImageUnit(nvsFunc *shader, int unit)
-{
- shader->inst[0] &= ~NV30_FP_OP_TEX_UNIT_SHIFT;
- shader->inst[0] |= (unit << NV30_FP_OP_TEX_UNIT_SHIFT);
-}
-
-static void
-NV30FPSetSaturate(nvsFunc *shader)
-{
- shader->inst[0] |= NV30_FP_OP_OUT_SAT;
-}
-
-static void
-NV30FPInitInstruction(nvsFunc *shader)
-{
- unsigned int hwsrc;
-
- shader->inst[0] = 0;
-
- hwsrc = (NV30_FP_REG_TYPE_INPUT << NV30_FP_REG_TYPE_SHIFT) |
- (NVS_SWZ_X << NV30_FP_REG_SWZ_X_SHIFT) |
- (NVS_SWZ_Y << NV30_FP_REG_SWZ_Y_SHIFT) |
- (NVS_SWZ_Z << NV30_FP_REG_SWZ_Z_SHIFT) |
- (NVS_SWZ_W << NV30_FP_REG_SWZ_W_SHIFT);
- shader->inst[1] = hwsrc;
- shader->inst[2] = hwsrc;
- shader->inst[3] = hwsrc;
-}
-
-static void
-NV30FPSetLastInst(nvsFunc *shader)
-{
- shader->inst[0] |= 1;
-}
-
-/*******************************************************************************
- * Disassembly helpers
- */
-static struct _op_xlat *
-NV30FPGetOPTXRec(nvsFunc * shader, int merged)
-{
- int op;
-
- op = shader->GetOpcodeHW(shader, 0);
- if (op > NVFP_TX_AOP_COUNT)
- return NULL;
- if (NVFP_TX_AOP[op].SOP == NVS_OP_UNKNOWN)
- return NULL;
- return &NVFP_TX_AOP[op];
-}
-
-static int
-NV30FPHasMergedInst(nvsFunc * shader)
-{
- return 0;
-}
-
-static int
-NV30FPIsLastInst(nvsFunc * shader)
-{
- return ((shader->inst[0] & NV30_FP_OP_PROGRAM_END) ? 1 : 0);
-}
-
-static int
-NV30FPGetOffsetNext(nvsFunc * shader)
-{
- int i;
-
- for (i = 0; i < 3; i++)
- if (shader->GetSourceFile(shader, 0, i) == NVS_FILE_CONST)
- return 8;
- return 4;
-}
-
-static nvsOpcode
-NV30FPGetOpcode(nvsFunc * shader, int merged)
-{
- struct _op_xlat *opr;
-
- opr = shader->GetOPTXRec(shader, merged);
- if (!opr)
- return NVS_OP_UNKNOWN;
-
- return opr->SOP;
-}
-
-static unsigned int
-NV30FPGetOpcodeHW(nvsFunc * shader, int slot)
-{
- int op;
-
- op = (shader->inst[0] & NV30_FP_OP_OPCODE_MASK) >> NV30_FP_OP_OPCODE_SHIFT;
-
- return op;
-}
-
-static nvsRegFile
-NV30FPGetDestFile(nvsFunc * shader, int merged)
-{
- /* Result regs overlap temporary regs */
- return NVS_FILE_TEMP;
-}
-
-static unsigned int
-NV30FPGetDestID(nvsFunc * shader, int merged)
-{
- int id;
-
- switch (shader->GetDestFile(shader, merged)) {
- case NVS_FILE_TEMP:
- id = ((shader->inst[0] & NV30_FP_OP_OUT_REG_MASK)
- >> NV30_FP_OP_OUT_REG_SHIFT);
- return id;
- default:
- return -1;
- }
-}
-
-static unsigned int
-NV30FPGetDestMask(nvsFunc * shader, int merged)
-{
- unsigned int mask = 0;
-
- if (shader->inst[0] & NV30_FP_OP_OUT_X) mask |= SMASK_X;
- if (shader->inst[0] & NV30_FP_OP_OUT_Y) mask |= SMASK_Y;
- if (shader->inst[0] & NV30_FP_OP_OUT_Z) mask |= SMASK_Z;
- if (shader->inst[0] & NV30_FP_OP_OUT_W) mask |= SMASK_W;
-
- return mask;
-}
-
-static unsigned int
-NV30FPGetSourceHW(nvsFunc * shader, int merged, int pos)
-{
- struct _op_xlat *opr;
-
- opr = shader->GetOPTXRec(shader, merged);
- if (!opr || opr->srcpos[pos] == -1)
- return -1;
-
- return shader->inst[opr->srcpos[pos] + 1];
-}
-
-static nvsRegFile
-NV30FPGetSourceFile(nvsFunc * shader, int merged, int pos)
-{
- unsigned int src;
- struct _op_xlat *opr;
- int file;
-
- opr = shader->GetOPTXRec(shader, merged);
- if (!opr || opr->srcpos[pos] == -1)
- return NVS_FILE_UNKNOWN;
-
- switch (opr->srcpos[pos]) {
- case SPOS_ADDRESS: return NVS_FILE_ADDRESS;
- default:
- src = shader->GetSourceHW(shader, merged, pos);
- file = (src & NV30_FP_REG_TYPE_MASK) >> NV30_FP_REG_TYPE_SHIFT;
-
- switch (file) {
- case NV30_FP_REG_TYPE_TEMP : return NVS_FILE_TEMP;
- case NV30_FP_REG_TYPE_INPUT: return NVS_FILE_ATTRIB;
- case NV30_FP_REG_TYPE_CONST: return NVS_FILE_CONST;
- default:
- return NVS_FILE_UNKNOWN;
- }
- }
-}
-
-static int
-NV30FPGetSourceID(nvsFunc * shader, int merged, int pos)
-{
- switch (shader->GetSourceFile(shader, merged, pos)) {
- case NVS_FILE_ATTRIB:
- switch ((shader->inst[0] & NV30_FP_OP_INPUT_SRC_MASK)
- >> NV30_FP_OP_INPUT_SRC_SHIFT) {
- case NV30_FP_OP_INPUT_SRC_POSITION: return NVS_FR_POSITION;
- case NV30_FP_OP_INPUT_SRC_COL0 : return NVS_FR_COL0;
- case NV30_FP_OP_INPUT_SRC_COL1 : return NVS_FR_COL1;
- case NV30_FP_OP_INPUT_SRC_FOGC : return NVS_FR_FOGCOORD;
- case NV30_FP_OP_INPUT_SRC_TC(0) : return NVS_FR_TEXCOORD0;
- case NV30_FP_OP_INPUT_SRC_TC(1) : return NVS_FR_TEXCOORD1;
- case NV30_FP_OP_INPUT_SRC_TC(2) : return NVS_FR_TEXCOORD2;
- case NV30_FP_OP_INPUT_SRC_TC(3) : return NVS_FR_TEXCOORD3;
- case NV30_FP_OP_INPUT_SRC_TC(4) : return NVS_FR_TEXCOORD4;
- case NV30_FP_OP_INPUT_SRC_TC(5) : return NVS_FR_TEXCOORD5;
- case NV30_FP_OP_INPUT_SRC_TC(6) : return NVS_FR_TEXCOORD6;
- case NV30_FP_OP_INPUT_SRC_TC(7) : return NVS_FR_TEXCOORD7;
- default:
- return -1;
- }
- break;
- case NVS_FILE_TEMP:
- {
- unsigned int src;
-
- src = shader->GetSourceHW(shader, merged, pos);
- return ((src & NV30_FP_REG_SRC_MASK) >> NV30_FP_REG_SRC_SHIFT);
- }
- case NVS_FILE_CONST: /* inlined into fragprog */
- default:
- return -1;
- }
-}
-
-static int
-NV30FPGetTexImageUnit(nvsFunc *shader)
-{
- return ((shader->inst[0] & NV30_FP_OP_TEX_UNIT_MASK)
- >> NV30_FP_OP_TEX_UNIT_SHIFT);
-}
-
-static int
-NV30FPGetSourceNegate(nvsFunc * shader, int merged, int pos)
-{
- unsigned int src;
-
- src = shader->GetSourceHW(shader, merged, pos);
-
- if (src == -1)
- return -1;
- return ((src & NV30_FP_REG_NEGATE) ? 1 : 0);
-}
-
-static int
-NV30FPGetSourceAbs(nvsFunc * shader, int merged, int pos)
-{
- struct _op_xlat *opr;
- static unsigned int abspos[3] = {
- NV30_FP_OP_OUT_ABS,
- (1 << 30), /* guess */
- (1 << 31) /* guess */
- };
-
- opr = shader->GetOPTXRec(shader, merged);
- if (!opr || opr->srcpos[pos] == -1)
- return -1;
-
- return ((shader->inst[1] & abspos[opr->srcpos[pos]]) ? 1 : 0);
-}
-
-nvsSwzComp NV30FP_TX_SWIZZLE[4] = {NVS_SWZ_X, NVS_SWZ_Y, NVS_SWZ_Z, NVS_SWZ_W };
-
-static void
-NV30FPTXSwizzle(int hwswz, nvsSwzComp *swz)
-{
- swz[NVS_SWZ_W] = NV30FP_TX_SWIZZLE[(hwswz & 0xC0) >> 6];
- swz[NVS_SWZ_Z] = NV30FP_TX_SWIZZLE[(hwswz & 0x30) >> 4];
- swz[NVS_SWZ_Y] = NV30FP_TX_SWIZZLE[(hwswz & 0x0C) >> 2];
- swz[NVS_SWZ_X] = NV30FP_TX_SWIZZLE[(hwswz & 0x03) >> 0];
-}
-
-static void
-NV30FPGetSourceSwizzle(nvsFunc * shader, int merged, int pos, nvsSwzComp *swz)
-{
- unsigned int src;
- int swzbits;
-
- src = shader->GetSourceHW(shader, merged, pos);
- swzbits = (src & NV30_FP_REG_SWZ_ALL_MASK) >> NV30_FP_REG_SWZ_ALL_SHIFT;
- NV30FPTXSwizzle(swzbits, swz);
-}
-
-static int
-NV30FPGetSourceIndexed(nvsFunc * shader, int merged, int pos)
-{
- switch (shader->GetSourceFile(shader, merged, pos)) {
- case NVS_FILE_ATTRIB:
- return ((shader->inst[3] & NV30_FP_OP_INDEX_INPUT) ? 1 : 0);
- default:
- return 0;
- }
-}
-
-static void
-NV30FPGetSourceConstVal(nvsFunc * shader, int merged, int pos, float *val)
-{
- val[0] = *(float *) &(shader->inst[4]);
- val[1] = *(float *) &(shader->inst[5]);
- val[2] = *(float *) &(shader->inst[6]);
- val[3] = *(float *) &(shader->inst[7]);
-}
-
-static int
-NV30FPGetSourceScale(nvsFunc * shader, int merged, int pos)
-{
-/*FIXME: is this per-source, only for a specific source, or all sources??*/
- return (1 << ((shader->inst[2] & NV30_FP_OP_SRC_SCALE_MASK)
- >> NV30_FP_OP_SRC_SCALE_SHIFT));
-}
-
-static int
-NV30FPGetAddressRegID(nvsFunc * shader)
-{
- return 0;
-}
-
-static nvsSwzComp
-NV30FPGetAddressRegSwizzle(nvsFunc * shader)
-{
- return NVS_SWZ_X;
-}
-
-static int
-NV30FPSupportsConditional(nvsFunc * shader)
-{
- /*FIXME: Is this true of all ops? */
- return 1;
-}
-
-static int
-NV30FPGetConditionUpdate(nvsFunc * shader)
-{
- return ((shader->inst[0] & NV30_FP_OP_COND_WRITE_ENABLE) ? 1 : 0);
-}
-
-static int
-NV30FPGetConditionTest(nvsFunc * shader)
-{
- /*FIXME: always? */
- return 1;
-}
-
-static nvsCond
-NV30FPGetCondition(nvsFunc * shader)
-{
- int cond;
-
- cond = ((shader->inst[1] & NV30_FP_OP_COND_MASK)
- >> NV30_FP_OP_COND_SHIFT);
-
- switch (cond) {
- case NV30_FP_OP_COND_FL: return NVS_COND_FL;
- case NV30_FP_OP_COND_LT: return NVS_COND_LT;
- case NV30_FP_OP_COND_EQ: return NVS_COND_EQ;
- case NV30_FP_OP_COND_LE: return NVS_COND_LE;
- case NV30_FP_OP_COND_GT: return NVS_COND_GT;
- case NV30_FP_OP_COND_NE: return NVS_COND_NE;
- case NV30_FP_OP_COND_GE: return NVS_COND_GE;
- case NV30_FP_OP_COND_TR: return NVS_COND_TR;
- default:
- return NVS_COND_UNKNOWN;
- }
-}
-
-static void
-NV30FPGetCondRegSwizzle(nvsFunc * shader, nvsSwzComp *swz)
-{
- int swzbits;
-
- swzbits = (shader->inst[1] & NV30_FP_OP_COND_SWZ_ALL_MASK)
- >> NV30_FP_OP_COND_SWZ_ALL_SHIFT;
- NV30FPTXSwizzle(swzbits, swz);
-}
-
-static int
-NV30FPGetCondRegID(nvsFunc * shader)
-{
- return 0;
-}
-
-static nvsPrecision
-NV30FPGetPrecision(nvsFunc * shader)
-{
- int p;
-
- p = (shader->inst[0] & NV30_FP_OP_PRECISION_MASK)
- >> NV30_FP_OP_PRECISION_SHIFT;
-
- switch (p) {
- case NV30_FP_PRECISION_FP32: return NVS_PREC_FLOAT32;
- case NV30_FP_PRECISION_FP16: return NVS_PREC_FLOAT16;
- case NV30_FP_PRECISION_FX12: return NVS_PREC_FIXED12;
- default:
- return NVS_PREC_UNKNOWN;
- }
-}
-
-static int
-NV30FPGetSaturate(nvsFunc * shader)
-{
- return ((shader->inst[0] & NV30_FP_OP_OUT_SAT) ? 1 : 0);
-}
-
-/*******************************************************************************
- * Init
- */
-void
-NV30FPInitShaderFuncs(nvsFunc * shader)
-{
- /* These are probably bogus, I made them up... */
- shader->MaxInst = 1024;
- shader->MaxAttrib = 16;
- shader->MaxTemp = 32;
- shader->MaxAddress = 1;
- shader->MaxConst = 256;
- shader->caps = SCAP_SRC_ABS;
-
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_MOV, NVS_OP_MOV, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_MUL, NVS_OP_MUL, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_ADD, NVS_OP_ADD, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_MAD, NVS_OP_MAD, 0, 1, 2);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_DP3, NVS_OP_DP3, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_DP4, NVS_OP_DP4, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_DST, NVS_OP_DST, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_MIN, NVS_OP_MIN, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_MAX, NVS_OP_MAX, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SLT, NVS_OP_SLT, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SGE, NVS_OP_SGE, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_FRC, NVS_OP_FRC, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_FLR, NVS_OP_FLR, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_TEX, NVS_OP_TEX, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_TXD, NVS_OP_TXD, 0, 1, 2);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_TXP, NVS_OP_TXP, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_TXB, NVS_OP_TXB, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SEQ, NVS_OP_SEQ, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SGT, NVS_OP_SGT, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SLE, NVS_OP_SLE, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SNE, NVS_OP_SNE, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_RCP, NVS_OP_RCP, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_LG2, NVS_OP_LG2, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_EX2, NVS_OP_EX2, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_COS, NVS_OP_COS, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_SIN, NVS_OP_SIN, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_NOP, NVS_OP_NOP, -1, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_DDX, NVS_OP_DDX, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_DDY, NVS_OP_DDY, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_KIL, NVS_OP_KIL, -1, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_PK4B, NVS_OP_PK4B, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_UP4B, NVS_OP_UP4B, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_PK2H, NVS_OP_PK2H, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_UP2H, NVS_OP_UP2H, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_PK4UB, NVS_OP_PK4UB, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_UP4UB, NVS_OP_UP4UB, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_PK2US, NVS_OP_PK2US, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_UP2US, NVS_OP_UP2US, 0, -1, -1);
- /*FIXME: Haven't confirmed the source positions for the below opcodes */
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_LIT, NVS_OP_LIT, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_LRP, NVS_OP_LRP, 0, 1, 2);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_POW, NVS_OP_POW, 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_RSQ, NVS_OP_RSQ, 0, -1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV30_FP_OP_OPCODE_RFL, NVS_OP_RFL, 0, 1, -1);
-
- shader->GetOPTXRec = NV30FPGetOPTXRec;
- shader->GetOPTXFromSOP = NV30FPGetOPTXFromSOP;
-
- shader->UploadToHW = NV30FPUploadToHW;
- shader->UpdateConst = NV30FPUpdateConst;
-
- shader->InitInstruction = NV30FPInitInstruction;
- shader->SupportsOpcode = NV30FPSupportsOpcode;
- shader->SetOpcode = NV30FPSetOpcode;
- shader->SetCCUpdate = NV30FPSetCCUpdate;
- shader->SetCondition = NV30FPSetCondition;
- shader->SetResult = NV30FPSetResult;
- shader->SetSource = NV30FPSetSource;
- shader->SetTexImageUnit = NV30FPSetTexImageUnit;
- shader->SetSaturate = NV30FPSetSaturate;
- shader->SetLastInst = NV30FPSetLastInst;
-
- shader->HasMergedInst = NV30FPHasMergedInst;
- shader->IsLastInst = NV30FPIsLastInst;
- shader->GetOffsetNext = NV30FPGetOffsetNext;
- shader->GetOpcode = NV30FPGetOpcode;
- shader->GetOpcodeHW = NV30FPGetOpcodeHW;
- shader->GetDestFile = NV30FPGetDestFile;
- shader->GetDestID = NV30FPGetDestID;
- shader->GetDestMask = NV30FPGetDestMask;
- shader->GetSourceHW = NV30FPGetSourceHW;
- shader->GetSourceFile = NV30FPGetSourceFile;
- shader->GetSourceID = NV30FPGetSourceID;
- shader->GetTexImageUnit = NV30FPGetTexImageUnit;
- shader->GetSourceNegate = NV30FPGetSourceNegate;
- shader->GetSourceAbs = NV30FPGetSourceAbs;
- shader->GetSourceSwizzle = NV30FPGetSourceSwizzle;
- shader->GetSourceIndexed = NV30FPGetSourceIndexed;
- shader->GetSourceConstVal = NV30FPGetSourceConstVal;
- shader->GetSourceScale = NV30FPGetSourceScale;
- shader->GetRelAddressRegID = NV30FPGetAddressRegID;
- shader->GetRelAddressSwizzle = NV30FPGetAddressRegSwizzle;
- shader->GetPrecision = NV30FPGetPrecision;
- shader->GetSaturate = NV30FPGetSaturate;
- shader->SupportsConditional = NV30FPSupportsConditional;
- shader->GetConditionUpdate = NV30FPGetConditionUpdate;
- shader->GetConditionTest = NV30FPGetConditionTest;
- shader->GetCondition = NV30FPGetCondition;
- shader->GetCondRegSwizzle = NV30FPGetCondRegSwizzle;
- shader->GetCondRegID = NV30FPGetCondRegID;
-}
diff --git a/src/mesa/drivers/dri/nouveau/nv30_shader.h b/src/mesa/drivers/dri/nouveau/nv30_shader.h
deleted file mode 100644
index 7a027dd427..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv30_shader.h
+++ /dev/null
@@ -1,379 +0,0 @@
-#ifndef __NV30_SHADER_H__
-#define __NV30_SHADER_H__
-
-/* Vertex programs instruction set
- *
- * 128bit opcodes, split into 4 32-bit ones for ease of use.
- *
- * Non-native instructions
- * ABS - MOV + NV40_VP_INST0_DEST_ABS
- * POW - EX2 + MUL + LG2
- * SUB - ADD, second source negated
- * SWZ - MOV
- * XPD -
- *
- * Register access
- * - Only one INPUT can be accessed per-instruction (move extras into TEMPs)
- * - Only one CONST can be accessed per-instruction (move extras into TEMPs)
- *
- * Relative Addressing
- * According to the value returned for MAX_PROGRAM_NATIVE_ADDRESS_REGISTERS_ARB
- * there are only two address registers available. The destination in the ARL
- * instruction is set to TEMP (The temp isn't actually written).
- *
- * When using vanilla ARB_v_p, the proprietary driver will squish both the available
- * ADDRESS regs into the first hardware reg in the X and Y components.
- *
- * To use an address reg as an index into consts, the CONST_SRC is set to
- * (const_base + offset) and INDEX_CONST is set.
- *
- * To access the second address reg use ADDR_REG_SELECT_1. A particular component
- * of the address regs is selected with ADDR_SWZ.
- *
- * Only one address register can be accessed per instruction.
- *
- * Conditional execution (see NV_vertex_program{2,3} for details)
- * Conditional execution of an instruction is enabled by setting COND_TEST_ENABLE, and
- * selecting the condition which will allow the test to pass with COND_{FL,LT,...}.
- * It is possible to swizzle the values in the condition register, which allows for
- * testing against an individual component.
- *
- * Branching
- * The BRA/CAL instructions seem to follow a slightly different opcode layout. The
- * destination instruction ID (IADDR) overlaps a source field. Instruction ID's seem to
- * be numbered based on the UPLOAD_FROM_ID FIFO command, and is incremented automatically
- * on each UPLOAD_INST FIFO command.
- *
- * Conditional branching is achieved by using the condition tests described above.
- * There doesn't appear to be dedicated looping instructions, but this can be done
- * using a temp reg + conditional branching.
- *
- * Subroutines may be uploaded before the main program itself, but the first executed
- * instruction is determined by the PROGRAM_START_ID FIFO command.
- *
- */
-
-/* DWORD 0 */
-#define NV30_VP_INST_ADDR_REG_SELECT_1 (1 << 24)
-#define NV30_VP_INST_SRC2_ABS (1 << 23) /* guess */
-#define NV30_VP_INST_SRC1_ABS (1 << 22) /* guess */
-#define NV30_VP_INST_SRC0_ABS (1 << 21) /* guess */
-#define NV30_VP_INST_OUT_RESULT (1 << 20)
-#define NV30_VP_INST_DEST_TEMP_ID_SHIFT 16
-#define NV30_VP_INST_DEST_TEMP_ID_MASK (0x0F << 16)
-#define NV30_VP_INST_COND_UPDATE_ENABLE (1<<15)
-#define NV30_VP_INST_COND_TEST_ENABLE (1<<14)
-#define NV30_VP_INST_COND_SHIFT 11
-#define NV30_VP_INST_COND_MASK (0x07 << 11)
-# define NV30_VP_INST_COND_FL 0 /* guess */
-# define NV30_VP_INST_COND_LT 1
-# define NV30_VP_INST_COND_EQ 2
-# define NV30_VP_INST_COND_LE 3
-# define NV30_VP_INST_COND_GT 4
-# define NV30_VP_INST_COND_NE 5
-# define NV30_VP_INST_COND_GE 6
-# define NV30_VP_INST_COND_TR 7 /* guess */
-#define NV30_VP_INST_COND_SWZ_X_SHIFT 9
-#define NV30_VP_INST_COND_SWZ_X_MASK (0x03 << 9)
-#define NV30_VP_INST_COND_SWZ_Y_SHIFT 7
-#define NV30_VP_INST_COND_SWZ_Y_MASK (0x03 << 7)
-#define NV30_VP_INST_COND_SWZ_Z_SHIFT 5
-#define NV30_VP_INST_COND_SWZ_Z_MASK (0x03 << 5)
-#define NV30_VP_INST_COND_SWZ_W_SHIFT 3
-#define NV30_VP_INST_COND_SWZ_W_MASK (0x03 << 3)
-#define NV30_VP_INST_COND_SWZ_ALL_SHIFT 3
-#define NV30_VP_INST_COND_SWZ_ALL_MASK (0xFF << 3)
-#define NV30_VP_INST_ADDR_SWZ_SHIFT 1
-#define NV30_VP_INST_ADDR_SWZ_MASK (0x03 << 1)
-#define NV30_VP_INST_SCA_OPCODEH_SHIFT 0
-#define NV30_VP_INST_SCA_OPCODEH_MASK (0x01 << 0)
-
-/* DWORD 1 */
-#define NV30_VP_INST_SCA_OPCODEL_SHIFT 28
-#define NV30_VP_INST_SCA_OPCODEL_MASK (0x0F << 28)
-# define NV30_VP_INST_OP_NOP 0x00
-# define NV30_VP_INST_OP_RCP 0x02
-# define NV30_VP_INST_OP_RCC 0x03
-# define NV30_VP_INST_OP_RSQ 0x04
-# define NV30_VP_INST_OP_EXP 0x05
-# define NV30_VP_INST_OP_LOG 0x06
-# define NV30_VP_INST_OP_LIT 0x07
-# define NV30_VP_INST_OP_BRA 0x09
-# define NV30_VP_INST_OP_CAL 0x0B
-# define NV30_VP_INST_OP_RET 0x0C
-# define NV30_VP_INST_OP_LG2 0x0D
-# define NV30_VP_INST_OP_EX2 0x0E
-# define NV30_VP_INST_OP_SIN 0x0F
-# define NV30_VP_INST_OP_COS 0x10
-#define NV30_VP_INST_VEC_OPCODE_SHIFT 23
-#define NV30_VP_INST_VEC_OPCODE_MASK (0x1F << 23)
-# define NV30_VP_INST_OP_NOPV 0x00
-# define NV30_VP_INST_OP_MOV 0x01
-# define NV30_VP_INST_OP_MUL 0x02
-# define NV30_VP_INST_OP_ADD 0x03
-# define NV30_VP_INST_OP_MAD 0x04
-# define NV30_VP_INST_OP_DP3 0x05
-# define NV30_VP_INST_OP_DP4 0x07
-# define NV30_VP_INST_OP_DPH 0x06
-# define NV30_VP_INST_OP_DST 0x08
-# define NV30_VP_INST_OP_MIN 0x09
-# define NV30_VP_INST_OP_MAX 0x0A
-# define NV30_VP_INST_OP_SLT 0x0B
-# define NV30_VP_INST_OP_SGE 0x0C
-# define NV30_VP_INST_OP_ARL 0x0D
-# define NV30_VP_INST_OP_FRC 0x0E
-# define NV30_VP_INST_OP_FLR 0x0F
-# define NV30_VP_INST_OP_SEQ 0x10
-# define NV30_VP_INST_OP_SFL 0x11
-# define NV30_VP_INST_OP_SGT 0x12
-# define NV30_VP_INST_OP_SLE 0x13
-# define NV30_VP_INST_OP_SNE 0x14
-# define NV30_VP_INST_OP_STR 0x15
-# define NV30_VP_INST_OP_SSG 0x16
-# define NV30_VP_INST_OP_ARR 0x17
-# define NV30_VP_INST_OP_ARA 0x18
-#define NV30_VP_INST_CONST_SRC_SHIFT 14
-#define NV30_VP_INST_CONST_SRC_MASK (0xFF << 14)
-#define NV30_VP_INST_INPUT_SRC_SHIFT 9 /*NV20*/
-#define NV30_VP_INST_INPUT_SRC_MASK (0x0F << 9) /*NV20*/
-# define NV30_VP_INST_IN_POS 0 /* These seem to match the bindings specified in */
-# define NV30_VP_INST_IN_WEIGHT 1 /* the ARB_v_p spec (2.14.3.1) */
-# define NV30_VP_INST_IN_NORMAL 2
-# define NV30_VP_INST_IN_COL0 3 /* Should probably confirm them all though */
-# define NV30_VP_INST_IN_COL1 4
-# define NV30_VP_INST_IN_FOGC 5
-# define NV30_VP_INST_IN_TC0 8
-# define NV30_VP_INST_IN_TC(n) (8+n)
-#define NV30_VP_INST_SRC0H_SHIFT 0 /*NV20*/
-#define NV30_VP_INST_SRC0H_MASK (0x1FF << 0) /*NV20*/
-
-/* DWORD 2 */
-#define NV30_VP_INST_SRC0L_SHIFT 26 /*NV20*/
-#define NV30_VP_INST_SRC0L_MASK (0x3F <<26) /*NV20*/
-#define NV30_VP_INST_SRC1_SHIFT 11 /*NV20*/
-#define NV30_VP_INST_SRC1_MASK (0x7FFF<<11) /*NV20*/
-#define NV30_VP_INST_SRC2H_SHIFT 0 /*NV20*/
-#define NV30_VP_INST_SRC2H_MASK (0x7FF << 0) /*NV20*/
-#define NV30_VP_INST_IADDR_SHIFT 2
-#define NV30_VP_INST_IADDR_MASK (0xFF << 2) /* guess */
-
-/* DWORD 3 */
-#define NV30_VP_INST_SRC2L_SHIFT 28 /*NV20*/
-#define NV30_VP_INST_SRC2L_MASK (0x0F <<28) /*NV20*/
-#define NV30_VP_INST_STEMP_WRITEMASK_SHIFT 24
-#define NV30_VP_INST_STEMP_WRITEMASK_MASK (0x0F << 24)
-#define NV30_VP_INST_VTEMP_WRITEMASK_SHIFT 20
-#define NV30_VP_INST_VTEMP_WRITEMASK_MASK (0x0F << 20)
-#define NV30_VP_INST_SDEST_WRITEMASK_SHIFT 16
-#define NV30_VP_INST_SDEST_WRITEMASK_MASK (0x0F << 16)
-#define NV30_VP_INST_VDEST_WRITEMASK_SHIFT 12 /*NV20*/
-#define NV30_VP_INST_VDEST_WRITEMASK_MASK (0x0F << 12) /*NV20*/
-#define NV30_VP_INST_DEST_ID_SHIFT 2
-#define NV30_VP_INST_DEST_ID_MASK (0x0F << 2)
-# define NV30_VP_INST_DEST_POS 0
-# define NV30_VP_INST_DEST_COL0 3
-# define NV30_VP_INST_DEST_COL1 4
-# define NV30_VP_INST_DEST_TC(n) (8+n)
-
-/* Source-register definition - matches NV20 exactly */
-#define NV30_VP_SRC_REG_NEGATE (1<<14)
-#define NV30_VP_SRC_REG_SWZ_X_SHIFT 12
-#define NV30_VP_SRC_REG_SWZ_X_MASK (0x03 <<12)
-#define NV30_VP_SRC_REG_SWZ_Y_SHIFT 10
-#define NV30_VP_SRC_REG_SWZ_Y_MASK (0x03 <<10)
-#define NV30_VP_SRC_REG_SWZ_Z_SHIFT 8
-#define NV30_VP_SRC_REG_SWZ_Z_MASK (0x03 << 8)
-#define NV30_VP_SRC_REG_SWZ_W_SHIFT 6
-#define NV30_VP_SRC_REG_SWZ_W_MASK (0x03 << 6)
-#define NV30_VP_SRC_REG_SWZ_ALL_SHIFT 6
-#define NV30_VP_SRC_REG_SWZ_ALL_MASK (0xFF << 6)
-#define NV30_VP_SRC_REG_TEMP_ID_SHIFT 2
-#define NV30_VP_SRC_REG_TEMP_ID_MASK (0x0F << 0)
-#define NV30_VP_SRC_REG_TYPE_SHIFT 0
-#define NV30_VP_SRC_REG_TYPE_MASK (0x03 << 0)
-#define NV30_VP_SRC_REG_TYPE_TEMP 1
-#define NV30_VP_SRC_REG_TYPE_INPUT 2
-#define NV30_VP_SRC_REG_TYPE_CONST 3 /* guess */
-
-/*
- * Each fragment program opcode appears to be comprised of 4 32-bit values.
- *
- * 0 - Opcode, output reg/mask, ATTRIB source
- * 1 - Source 0
- * 2 - Source 1
- * 3 - Source 2
- *
- * There appears to be no special difference between result regs and temp regs.
- * result.color == R0.xyzw
- * result.depth == R1.z
- * When the fragprog contains instructions to write depth, NV30_TCL_PRIMITIVE_3D_UNK1D78=0
- * otherwise it is set to 1.
- *
- * Constants are inserted directly after the instruction that uses them.
- *
- * It appears that it's not possible to use two input registers in one
- * instruction as the input sourcing is done in the instruction dword
- * and not the source selection dwords. As such instructions such as:
- *
- * ADD result.color, fragment.color, fragment.texcoord[0];
- *
- * must be split into two MOV's and then an ADD (nvidia does this) but
- * I'm not sure why it's not just one MOV and then source the second input
- * in the ADD instruction..
- *
- * Negation of the full source is done with NV30_FP_REG_NEGATE, arbitrary
- * negation requires multiplication with a const.
- *
- * Arbitrary swizzling is supported with the exception of SWIZZLE_ZERO/SWIZZLE_ONE
- * The temp/result regs appear to be initialised to (0.0, 0.0, 0.0, 0.0) as SWIZZLE_ZERO
- * is implemented simply by not writing to the relevant components of the destination.
- *
- * Conditional execution
- * TODO
- *
- * Non-native instructions:
- * LIT
- * LRP - MAD+MAD
- * SUB - ADD, negate second source
- * RSQ - LG2 + EX2
- * POW - LG2 + MUL + EX2
- * SCS - COS + SIN
- * XPD
- */
-
-//== Opcode / Destination selection ==
-#define NV30_FP_OP_PROGRAM_END (1 << 0)
-#define NV30_FP_OP_OUT_REG_SHIFT 1
-#define NV30_FP_OP_OUT_REG_MASK (31 << 1) /* uncertain */
-/* Needs to be set when writing outputs to get expected result.. */
-#define NV30_FP_OP_UNK0_7 (1 << 7)
-#define NV30_FP_OP_COND_WRITE_ENABLE (1 << 8)
-#define NV30_FP_OP_OUTMASK_SHIFT 9
-#define NV30_FP_OP_OUTMASK_MASK (0xF << 9)
-# define NV30_FP_OP_OUT_X (1<<9)
-# define NV30_FP_OP_OUT_Y (1<<10)
-# define NV30_FP_OP_OUT_Z (1<<11)
-# define NV30_FP_OP_OUT_W (1<<12)
-/* Uncertain about these, especially the input_src values.. it's possible that
- * they can be dynamically changed.
- */
-#define NV30_FP_OP_INPUT_SRC_SHIFT 13
-#define NV30_FP_OP_INPUT_SRC_MASK (15 << 13)
-# define NV30_FP_OP_INPUT_SRC_POSITION 0x0
-# define NV30_FP_OP_INPUT_SRC_COL0 0x1
-# define NV30_FP_OP_INPUT_SRC_COL1 0x2
-# define NV30_FP_OP_INPUT_SRC_FOGC 0x3
-# define NV30_FP_OP_INPUT_SRC_TC0 0x4
-# define NV30_FP_OP_INPUT_SRC_TC(n) (0x4 + n)
-#define NV30_FP_OP_TEX_UNIT_SHIFT 17
-#define NV30_FP_OP_TEX_UNIT_MASK (0xF << 17) /* guess */
-#define NV30_FP_OP_PRECISION_SHIFT 22
-#define NV30_FP_OP_PRECISION_MASK (3 << 22)
-# define NV30_FP_PRECISION_FP32 0
-# define NV30_FP_PRECISION_FP16 1
-# define NV30_FP_PRECISION_FX12 2
-#define NV30_FP_OP_OPCODE_SHIFT 24
-#define NV30_FP_OP_OPCODE_MASK (0x3F << 24)
-# define NV30_FP_OP_OPCODE_NOP 0x00
-# define NV30_FP_OP_OPCODE_MOV 0x01
-# define NV30_FP_OP_OPCODE_MUL 0x02
-# define NV30_FP_OP_OPCODE_ADD 0x03
-# define NV30_FP_OP_OPCODE_MAD 0x04
-# define NV30_FP_OP_OPCODE_DP3 0x05
-# define NV30_FP_OP_OPCODE_DP4 0x06
-# define NV30_FP_OP_OPCODE_DST 0x07
-# define NV30_FP_OP_OPCODE_MIN 0x08
-# define NV30_FP_OP_OPCODE_MAX 0x09
-# define NV30_FP_OP_OPCODE_SLT 0x0A
-# define NV30_FP_OP_OPCODE_SGE 0x0B
-# define NV30_FP_OP_OPCODE_SLE 0x0C
-# define NV30_FP_OP_OPCODE_SGT 0x0D
-# define NV30_FP_OP_OPCODE_SNE 0x0E
-# define NV30_FP_OP_OPCODE_SEQ 0x0F
-# define NV30_FP_OP_OPCODE_FRC 0x10
-# define NV30_FP_OP_OPCODE_FLR 0x11
-# define NV30_FP_OP_OPCODE_KIL 0x12
-# define NV30_FP_OP_OPCODE_PK4B 0x13
-# define NV30_FP_OP_OPCODE_UP4B 0x14
-# define NV30_FP_OP_OPCODE_DDX 0x15 /* can only write XY */
-# define NV30_FP_OP_OPCODE_DDY 0x16 /* can only write XY */
-# define NV30_FP_OP_OPCODE_TEX 0x17
-# define NV30_FP_OP_OPCODE_TXP 0x18
-# define NV30_FP_OP_OPCODE_TXD 0x19
-# define NV30_FP_OP_OPCODE_RCP 0x1A
-# define NV30_FP_OP_OPCODE_RSQ 0x1B
-# define NV30_FP_OP_OPCODE_EX2 0x1C
-# define NV30_FP_OP_OPCODE_LG2 0x1D
-# define NV30_FP_OP_OPCODE_LIT 0x1E
-# define NV30_FP_OP_OPCODE_LRP 0x1F
-# define NV30_FP_OP_OPCODE_COS 0x22
-# define NV30_FP_OP_OPCODE_SIN 0x23
-# define NV30_FP_OP_OPCODE_PK2H 0x24
-# define NV30_FP_OP_OPCODE_UP2H 0x25
-# define NV30_FP_OP_OPCODE_POW 0x26
-# define NV30_FP_OP_OPCODE_PK4UB 0x27
-# define NV30_FP_OP_OPCODE_UP4UB 0x28
-# define NV30_FP_OP_OPCODE_PK2US 0x29
-# define NV30_FP_OP_OPCODE_UP2US 0x2A
-# define NV30_FP_OP_OPCODE_DP2A 0x2E
-# define NV30_FP_OP_OPCODE_TXB 0x31
-# define NV30_FP_OP_OPCODE_RFL 0x36
-#define NV30_FP_OP_OUT_SAT (1 << 31)
-
-/* high order bits of SRC0 */
-#define NV30_FP_OP_OUT_ABS (1 << 29)
-#define NV30_FP_OP_COND_SWZ_W_SHIFT 27
-#define NV30_FP_OP_COND_SWZ_W_MASK (3 << 27)
-#define NV30_FP_OP_COND_SWZ_Z_SHIFT 25
-#define NV30_FP_OP_COND_SWZ_Z_MASK (3 << 25)
-#define NV30_FP_OP_COND_SWZ_Y_SHIFT 23
-#define NV30_FP_OP_COND_SWZ_Y_MASK (3 << 23)
-#define NV30_FP_OP_COND_SWZ_X_SHIFT 21
-#define NV30_FP_OP_COND_SWZ_X_MASK (3 << 21)
-#define NV30_FP_OP_COND_SWZ_ALL_SHIFT 21
-#define NV30_FP_OP_COND_SWZ_ALL_MASK (0xFF << 21)
-#define NV30_FP_OP_COND_SHIFT 18
-#define NV30_FP_OP_COND_MASK (0x07 << 18)
-# define NV30_FP_OP_COND_FL 0
-# define NV30_FP_OP_COND_LT 1
-# define NV30_FP_OP_COND_EQ 2
-# define NV30_FP_OP_COND_LE 3
-# define NV30_FP_OP_COND_GT 4
-# define NV30_FP_OP_COND_NE 5
-# define NV30_FP_OP_COND_GE 6
-# define NV30_FP_OP_COND_TR 7
-
-/* high order bits of SRC1 */
-#define NV30_FP_OP_SRC_SCALE_SHIFT 28
-#define NV30_FP_OP_SRC_SCALE_MASK (3 << 28)
-
-/* high order bits of SRC2 */
-#define NV30_FP_OP_INDEX_INPUT (1 << 30)
-
-//== Register selection ==
-#define NV30_FP_REG_ALL_MASK (0x1FFFF<<0)
-#define NV30_FP_REG_TYPE_SHIFT 0
-#define NV30_FP_REG_TYPE_MASK (3 << 0)
-# define NV30_FP_REG_TYPE_TEMP 0
-# define NV30_FP_REG_TYPE_INPUT 1
-# define NV30_FP_REG_TYPE_CONST 2
-#define NV30_FP_REG_SRC_SHIFT 2 /* uncertain */
-#define NV30_FP_REG_SRC_MASK (31 << 2)
-#define NV30_FP_REG_UNK_0 (1 << 8)
-#define NV30_FP_REG_SWZ_ALL_SHIFT 9
-#define NV30_FP_REG_SWZ_ALL_MASK (255 << 9)
-#define NV30_FP_REG_SWZ_X_SHIFT 9
-#define NV30_FP_REG_SWZ_X_MASK (3 << 9)
-#define NV30_FP_REG_SWZ_Y_SHIFT 11
-#define NV30_FP_REG_SWZ_Y_MASK (3 << 11)
-#define NV30_FP_REG_SWZ_Z_SHIFT 13
-#define NV30_FP_REG_SWZ_Z_MASK (3 << 13)
-#define NV30_FP_REG_SWZ_W_SHIFT 15
-#define NV30_FP_REG_SWZ_W_MASK (3 << 15)
-# define NV30_FP_SWIZZLE_X 0
-# define NV30_FP_SWIZZLE_Y 1
-# define NV30_FP_SWIZZLE_Z 2
-# define NV30_FP_SWIZZLE_W 3
-#define NV30_FP_REG_NEGATE (1 << 17)
-
-#endif
diff --git a/src/mesa/drivers/dri/nouveau/nv30_state.c b/src/mesa/drivers/dri/nouveau/nv30_state.c
deleted file mode 100644
index cd3ee98688..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv30_state.c
+++ /dev/null
@@ -1,1002 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Nouveau
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-#include "nouveau_context.h"
-#include "nouveau_object.h"
-#include "nouveau_fifo.h"
-#include "nouveau_reg.h"
-#include "nouveau_state.h"
-
-#include "tnl/t_pipeline.h"
-
-#include "mtypes.h"
-#include "colormac.h"
-
-#define NOUVEAU_CARD_USING_SHADERS (nmesa->screen->card->type >= NV_40)
-
-static void nv30AlphaFunc(GLcontext *ctx, GLenum func, GLfloat ref)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte ubRef;
- CLAMPED_FLOAT_TO_UBYTE(ubRef, ref);
-
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC, 2);
- OUT_RING_CACHE(func); /* NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_FUNC */
- OUT_RING_CACHE(ubRef); /* NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF */
-}
-
-static void nv30BlendColor(GLcontext *ctx, const GLfloat color[4])
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte cf[4];
-
- CLAMPED_FLOAT_TO_UBYTE(cf[0], color[0]);
- CLAMPED_FLOAT_TO_UBYTE(cf[1], color[1]);
- CLAMPED_FLOAT_TO_UBYTE(cf[2], color[2]);
- CLAMPED_FLOAT_TO_UBYTE(cf[3], color[3]);
-
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_BLEND_COLOR, 1);
- OUT_RING_CACHE(PACK_COLOR_8888(cf[3], cf[1], cf[2], cf[0]));
-}
-
-static void nv30BlendEquationSeparate(GLcontext *ctx, GLenum modeRGB, GLenum modeA)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_BLEND_EQUATION, 1);
- OUT_RING_CACHE((modeA<<16) | modeRGB);
-}
-
-
-static void nv30BlendFuncSeparate(GLcontext *ctx, GLenum sfactorRGB, GLenum dfactorRGB,
- GLenum sfactorA, GLenum dfactorA)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC, 2);
- OUT_RING_CACHE((sfactorA<<16) | sfactorRGB);
- OUT_RING_CACHE((dfactorA<<16) | dfactorRGB);
-}
-
-static void nv30Clear(GLcontext *ctx, GLbitfield mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLuint hw_bufs = 0;
-
- if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT))
- hw_bufs |= 0xf0;
- if (mask & (BUFFER_BIT_DEPTH))
- hw_bufs |= 0x03;
-
- if (hw_bufs) {
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLEAR_WHICH_BUFFERS, 1);
- OUT_RING(hw_bufs);
- }
-}
-
-static void nv30ClearColor(GLcontext *ctx, const GLfloat color[4])
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte c[4];
- UNCLAMPED_FLOAT_TO_RGBA_CHAN(c,color);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_ARGB, 1);
- OUT_RING_CACHE(PACK_COLOR_8888(c[3],c[0],c[1],c[2]));
-}
-
-static void nv30ClearDepth(GLcontext *ctx, GLclampd d)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nmesa->clear_value=((nmesa->clear_value&0x000000FF)|(((uint32_t)(d*0xFFFFFF))<<8));
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH, 1);
- OUT_RING_CACHE(nmesa->clear_value);
-}
-
-/* we're don't support indexed buffers
- void (*ClearIndex)(GLcontext *ctx, GLuint index)
- */
-
-static void nv30ClearStencil(GLcontext *ctx, GLint s)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- nmesa->clear_value=((nmesa->clear_value&0xFFFFFF00)|(s&0x000000FF));
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLEAR_VALUE_DEPTH, 1);
- OUT_RING_CACHE(nmesa->clear_value);
-}
-
-static void nv30ClipPlane(GLcontext *ctx, GLenum plane, const GLfloat *equation)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (NOUVEAU_CARD_USING_SHADERS)
- return;
-
- plane -= GL_CLIP_PLANE0;
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_A(plane), 4);
- OUT_RING_CACHEf(equation[0]);
- OUT_RING_CACHEf(equation[1]);
- OUT_RING_CACHEf(equation[2]);
- OUT_RING_CACHEf(equation[3]);
-}
-
-static void nv30ColorMask(GLcontext *ctx, GLboolean rmask, GLboolean gmask,
- GLboolean bmask, GLboolean amask )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_COLOR_MASK, 1);
- OUT_RING_CACHE(((amask && 0x01) << 24) | ((rmask && 0x01) << 16) | ((gmask && 0x01)<< 8) | ((bmask && 0x01) << 0));
-}
-
-static void nv30ColorMaterial(GLcontext *ctx, GLenum face, GLenum mode)
-{
- // TODO I need love
-}
-
-static void nv30CullFace(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CULL_FACE, 1);
- OUT_RING_CACHE(mode);
-}
-
-static void nv30FrontFace(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FRONT_FACE, 1);
- OUT_RING_CACHE(mode);
-}
-
-static void nv30DepthFunc(GLcontext *ctx, GLenum func)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DEPTH_FUNC, 1);
- OUT_RING_CACHE(func);
-}
-
-static void nv30DepthMask(GLcontext *ctx, GLboolean flag)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE, 1);
- OUT_RING_CACHE(flag);
-}
-
-static void nv30DepthRange(GLcontext *ctx, GLclampd nearval, GLclampd farval)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR, 2);
- OUT_RING_CACHEf(nearval);
- OUT_RING_CACHEf(farval);
-}
-
-/** Specify the current buffer for writing */
-//void (*DrawBuffer)( GLcontext *ctx, GLenum buffer );
-/** Specify the buffers for writing for fragment programs*/
-//void (*DrawBuffers)( GLcontext *ctx, GLsizei n, const GLenum *buffers );
-
-static void nv30Enable(GLcontext *ctx, GLenum cap, GLboolean state)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- switch(cap)
- {
- case GL_ALPHA_TEST:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_AUTO_NORMAL:
- case GL_BLEND:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_BLEND_FUNC_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_CLIP_PLANE0:
- case GL_CLIP_PLANE1:
- case GL_CLIP_PLANE2:
- case GL_CLIP_PLANE3:
- case GL_CLIP_PLANE4:
- case GL_CLIP_PLANE5:
- if (NOUVEAU_CARD_USING_SHADERS) {
- nouveauShader *nvs = (nouveauShader *)ctx->VertexProgram._Current;
- if (nvs)
- nvs->translated = GL_FALSE;
- } else {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CLIP_PLANE_ENABLE(cap-GL_CLIP_PLANE0), 1);
- OUT_RING_CACHE(state);
- }
- break;
- case GL_COLOR_LOGIC_OP:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_COLOR_MATERIAL:
-// case GL_COLOR_SUM_EXT:
-// case GL_COLOR_TABLE:
-// case GL_CONVOLUTION_1D:
-// case GL_CONVOLUTION_2D:
- case GL_CULL_FACE:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_DEPTH_TEST:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_DITHER:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DITHER_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_FOG:
- if (NOUVEAU_CARD_USING_SHADERS)
- break;
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_HISTOGRAM:
-// case GL_INDEX_LOGIC_OP:
- case GL_LIGHT0:
- case GL_LIGHT1:
- case GL_LIGHT2:
- case GL_LIGHT3:
- case GL_LIGHT4:
- case GL_LIGHT5:
- case GL_LIGHT6:
- case GL_LIGHT7:
- {
- uint32_t mask=0x11<<(2*(cap-GL_LIGHT0));
-
- if (NOUVEAU_CARD_USING_SHADERS)
- break;
-
- nmesa->enabled_lights=((nmesa->enabled_lights&mask)|(mask*state));
- if (nmesa->lighting_enabled)
- {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1);
- OUT_RING_CACHE(nmesa->enabled_lights);
- }
- break;
- }
- case GL_LIGHTING:
- if (NOUVEAU_CARD_USING_SHADERS)
- break;
-
- nmesa->lighting_enabled=state;
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_ENABLED_LIGHTS, 1);
- if (nmesa->lighting_enabled)
- OUT_RING_CACHE(nmesa->enabled_lights);
- else
- OUT_RING_CACHE(0x0);
- break;
-// case GL_LINE_SMOOTH:
-// case GL_LINE_STIPPLE:
-// case GL_MAP1_COLOR_4:
-// case GL_MAP1_INDEX:
-// case GL_MAP1_NORMAL:
-// case GL_MAP1_TEXTURE_COORD_1:
-// case GL_MAP1_TEXTURE_COORD_2:
-// case GL_MAP1_TEXTURE_COORD_3:
-// case GL_MAP1_TEXTURE_COORD_4:
-// case GL_MAP1_VERTEX_3:
-// case GL_MAP1_VERTEX_4:
-// case GL_MAP2_COLOR_4:
-// case GL_MAP2_INDEX:
-// case GL_MAP2_NORMAL:
-// case GL_MAP2_TEXTURE_COORD_1:
-// case GL_MAP2_TEXTURE_COORD_2:
-// case GL_MAP2_TEXTURE_COORD_3:
-// case GL_MAP2_TEXTURE_COORD_4:
-// case GL_MAP2_VERTEX_3:
-// case GL_MAP2_VERTEX_4:
-// case GL_MINMAX:
- case GL_NORMALIZE:
- if (nmesa->screen->card->type != NV_44) {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_NORMALIZE_ENABLE, 1);
- OUT_RING_CACHE(state);
- }
- break;
-// case GL_POINT_SMOOTH:
- case GL_POLYGON_OFFSET_POINT:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_OFFSET_LINE:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_OFFSET_FILL:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_SMOOTH:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_STIPPLE:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_POST_COLOR_MATRIX_COLOR_TABLE:
-// case GL_POST_CONVOLUTION_COLOR_TABLE:
-// case GL_RESCALE_NORMAL:
- case GL_SCISSOR_TEST:
- /* No enable bit, nv30Scissor will adjust to max range */
- ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
- ctx->Scissor.Width, ctx->Scissor.Height);
- break;
-// case GL_SEPARABLE_2D:
- case GL_STENCIL_TEST:
- // TODO BACK and FRONT ?
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_ENABLE, 1);
- OUT_RING_CACHE(state);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_TEXTURE_GEN_Q:
-// case GL_TEXTURE_GEN_R:
-// case GL_TEXTURE_GEN_S:
-// case GL_TEXTURE_GEN_T:
-// case GL_TEXTURE_1D:
-// case GL_TEXTURE_2D:
-// case GL_TEXTURE_3D:
- }
-}
-
-static void nv30Fogfv(GLcontext *ctx, GLenum pname, const GLfloat *params)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (NOUVEAU_CARD_USING_SHADERS)
- return;
-
- switch(pname)
- {
- case GL_FOG_MODE:
- {
- int mode = 0;
- /* The modes are different in GL and the card. */
- switch(ctx->Fog.Mode)
- {
- case GL_LINEAR:
- mode = 0x804;
- break;
- case GL_EXP:
- mode = 0x802;
- break;
- case GL_EXP2:
- mode = 0x803;
- break;
- }
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_MODE, 1);
- OUT_RING_CACHE (mode);
- break;
- }
- case GL_FOG_COLOR:
- {
- GLubyte c[4];
- UNCLAMPED_FLOAT_TO_RGBA_CHAN(c,params);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_COLOR, 1);
- /* nvidia ignores the alpha channel */
- OUT_RING_CACHE(PACK_COLOR_8888_REV(c[0],c[1],c[2],c[3]));
- break;
- }
- case GL_FOG_DENSITY:
- case GL_FOG_START:
- case GL_FOG_END:
- {
- GLfloat f=0., c=0.;
- switch(ctx->Fog.Mode)
- {
- case GL_LINEAR:
- f = -1.0/(ctx->Fog.End - ctx->Fog.Start);
- c = ctx->Fog.Start/(ctx->Fog.End - ctx->Fog.Start) + 2.001953;
- break;
- case GL_EXP:
- f = -0.090168*ctx->Fog.Density;
- c = 1.5;
- case GL_EXP2:
- f = -0.212330*ctx->Fog.Density;
- c = 1.5;
- }
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_LINEAR, 1);
- OUT_RING_CACHE(f);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_CONSTANT, 1);
- OUT_RING_CACHE(c);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_FOG_EQUATION_QUADRATIC, 1);
- OUT_RING_CACHE(0); /* Is this always the same? */
- break;
- }
-// case GL_FOG_COORD_SRC:
- default:
- break;
- }
-}
-
-static void nv30Hint(GLcontext *ctx, GLenum target, GLenum mode)
-{
- // TODO I need love (fog and line_smooth hints)
-}
-
-// void (*IndexMask)(GLcontext *ctx, GLuint mask);
-
-enum {
- SPOTLIGHT_NO_UPDATE,
- SPOTLIGHT_UPDATE_EXPONENT,
- SPOTLIGHT_UPDATE_DIRECTION,
- SPOTLIGHT_UPDATE_ALL
-};
-
-static void nv30Lightfv(GLcontext *ctx, GLenum light, GLenum pname, const GLfloat *params )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLint p = light - GL_LIGHT0;
- struct gl_light *l = &ctx->Light.Light[p];
- int spotlight_update = SPOTLIGHT_NO_UPDATE;
-
- if (NOUVEAU_CARD_USING_SHADERS)
- return;
-
- /* not sure where the fourth param value goes...*/
- switch(pname)
- {
- case GL_AMBIENT:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_DIFFUSE:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_SPECULAR:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_POSITION:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_POSITION_X(p), 3);
- OUT_RING_CACHEf(params[0]);
- OUT_RING_CACHEf(params[1]);
- OUT_RING_CACHEf(params[2]);
- break;
- case GL_SPOT_DIRECTION:
- spotlight_update = SPOTLIGHT_UPDATE_DIRECTION;
- break;
- case GL_SPOT_EXPONENT:
- spotlight_update = SPOTLIGHT_UPDATE_EXPONENT;
- break;
- case GL_SPOT_CUTOFF:
- spotlight_update = SPOTLIGHT_UPDATE_ALL;
- break;
- case GL_CONSTANT_ATTENUATION:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_CONSTANT_ATTENUATION(p), 1);
- OUT_RING_CACHEf(*params);
- break;
- case GL_LINEAR_ATTENUATION:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_LINEAR_ATTENUATION(p), 1);
- OUT_RING_CACHEf(*params);
- break;
- case GL_QUADRATIC_ATTENUATION:
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_QUADRATIC_ATTENUATION(p), 1);
- OUT_RING_CACHEf(*params);
- break;
- default:
- break;
- }
-
- switch(spotlight_update) {
- case SPOTLIGHT_UPDATE_DIRECTION:
- {
- GLfloat x,y,z;
- GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0);
- x = spot_light_coef_a * l->_NormDirection[0];
- y = spot_light_coef_a * l->_NormDirection[1];
- z = spot_light_coef_a * l->_NormDirection[2];
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_DIR_X(p), 3);
- OUT_RING_CACHEf(x);
- OUT_RING_CACHEf(y);
- OUT_RING_CACHEf(z);
- }
- break;
- case SPOTLIGHT_UPDATE_EXPONENT:
- {
- GLfloat cc,lc,qc;
- cc = 1.0; /* FIXME: These need to be correctly computed */
- lc = 0.0;
- qc = 2.0;
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 3);
- OUT_RING_CACHEf(cc);
- OUT_RING_CACHEf(lc);
- OUT_RING_CACHEf(qc);
- }
- break;
- case SPOTLIGHT_UPDATE_ALL:
- {
- GLfloat cc,lc,qc, x,y,z, c;
- GLfloat spot_light_coef_a = 1.0 / (l->_CosCutoff - 1.0);
- cc = 1.0; /* FIXME: These need to be correctly computed */
- lc = 0.0;
- qc = 2.0;
- x = spot_light_coef_a * l->_NormDirection[0];
- y = spot_light_coef_a * l->_NormDirection[1];
- z = spot_light_coef_a * l->_NormDirection[2];
- c = spot_light_coef_a + 1.0;
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LIGHT_SPOT_CUTOFF_A(p), 7);
- OUT_RING_CACHEf(cc);
- OUT_RING_CACHEf(lc);
- OUT_RING_CACHEf(qc);
- OUT_RING_CACHEf(x);
- OUT_RING_CACHEf(y);
- OUT_RING_CACHEf(z);
- OUT_RING_CACHEf(c);
- }
- break;
- default:
- break;
- }
-}
-
-/** Set the lighting model parameters */
-void (*LightModelfv)(GLcontext *ctx, GLenum pname, const GLfloat *params);
-
-
-static void nv30LineStipple(GLcontext *ctx, GLint factor, GLushort pattern )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN, 1);
- OUT_RING_CACHE((pattern << 16) | factor);
-}
-
-static void nv30LineWidth(GLcontext *ctx, GLfloat width)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte ubWidth;
-
- ubWidth = (GLubyte)(width * 8.0) & 0xFF;
-
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LINE_WIDTH_SMOOTH, 1);
- OUT_RING_CACHE(ubWidth);
-}
-
-static void nv30LogicOpcode(GLcontext *ctx, GLenum opcode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_COLOR_LOGIC_OP_OP, 1);
- OUT_RING_CACHE(opcode);
-}
-
-static void nv30PointParameterfv(GLcontext *ctx, GLenum pname, const GLfloat *params)
-{
- /*TODO: not sure what goes here. */
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
-}
-
-/** Specify the diameter of rasterized points */
-static void nv30PointSize(GLcontext *ctx, GLfloat size)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POINT_SIZE, 1);
- OUT_RING_CACHEf(size);
-}
-
-/** Select a polygon rasterization mode */
-static void nv30PolygonMode(GLcontext *ctx, GLenum face, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (face == GL_FRONT || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT, 1);
- OUT_RING_CACHE(mode);
- }
- if (face == GL_BACK || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK, 1);
- OUT_RING_CACHE(mode);
- }
-}
-
-/** Set the scale and units used to calculate depth values */
-static void nv30PolygonOffset(GLcontext *ctx, GLfloat factor, GLfloat units)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR, 2);
- OUT_RING_CACHEf(factor);
-
- /* Looks like we always multiply units by 2.0... according to the dumps.*/
- OUT_RING_CACHEf(units * 2.0);
-}
-
-/** Set the polygon stippling pattern */
-static void nv30PolygonStipple(GLcontext *ctx, const GLubyte *mask )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN(0), 32);
- OUT_RING_CACHEp(mask, 32);
-}
-
-/* Specifies the current buffer for reading */
-void (*ReadBuffer)( GLcontext *ctx, GLenum buffer );
-/** Set rasterization mode */
-void (*RenderMode)(GLcontext *ctx, GLenum mode );
-
-/* Translate GL coords to window coords, clamping w/h to the
- * dimensions of the window.
- */
-static void nv30WindowCoords(nouveauContextPtr nmesa,
- GLuint x, GLuint y, GLuint w, GLuint h,
- GLuint *wX, GLuint *wY, GLuint *wW, GLuint *wH)
-{
- if ((x+w) > nmesa->drawW)
- w = nmesa->drawW - x;
- (*wX) = x + nmesa->drawX;
- (*wW) = w;
-
- if ((y+h) > nmesa->drawH)
- h = nmesa->drawH - y;
- (*wY) = (nmesa->drawH - y) - h + nmesa->drawY;
- (*wH) = h;
-}
-
-/** Define the scissor box */
-static void nv30Scissor(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLuint wX, wY, wW, wH;
-
- /* There's no scissor enable bit, so adjust the scissor to cover the
- * maximum draw buffer bounds
- */
- if (!ctx->Scissor.Enabled) {
- wX = nmesa->drawX;
- wY = nmesa->drawY;
- wW = nmesa->drawW;
- wH = nmesa->drawH;
- } else {
- nv30WindowCoords(nmesa, x, y, w, h, &wX, &wY, &wW, &wH);
- }
-
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS, 2);
- OUT_RING_CACHE ((wW << 16) | wX);
- OUT_RING_CACHE ((wH << 16) | wY);
-}
-
-/** Select flat or smooth shading */
-static void nv30ShadeModel(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SHADE_MODEL, 1);
- OUT_RING_CACHE(mode);
-}
-
-/** OpenGL 2.0 two-sided StencilFunc */
-static void nv30StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func,
- GLint ref, GLuint mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (face == GL_FRONT || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC, 3);
- OUT_RING_CACHE(func);
- OUT_RING_CACHE(ref);
- OUT_RING_CACHE(mask);
- }
- if (face == GL_BACK || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC, 3);
- OUT_RING_CACHE(func);
- OUT_RING_CACHE(ref);
- OUT_RING_CACHE(mask);
- }
-}
-
-/** OpenGL 2.0 two-sided StencilMask */
-static void nv30StencilMaskSeparate(GLcontext *ctx, GLenum face, GLuint mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (face == GL_FRONT || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_MASK, 1);
- OUT_RING_CACHE(mask);
- }
- if (face == GL_BACK || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_MASK, 1);
- OUT_RING_CACHE(mask);
- }
-}
-
-/** OpenGL 2.0 two-sided StencilOp */
-static void nv30StencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail,
- GLenum zfail, GLenum zpass)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (face == GL_FRONT || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL, 3);
- OUT_RING_CACHE(fail);
- OUT_RING_CACHE(zfail);
- OUT_RING_CACHE(zpass);
- }
- if (face == GL_BACK || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL, 3);
- OUT_RING_CACHE(fail);
- OUT_RING_CACHE(zfail);
- OUT_RING_CACHE(zpass);
- }
-}
-
-/** Control the generation of texture coordinates */
-void (*TexGen)(GLcontext *ctx, GLenum coord, GLenum pname,
- const GLfloat *params);
-/** Set texture environment parameters */
-void (*TexEnv)(GLcontext *ctx, GLenum target, GLenum pname,
- const GLfloat *param);
-/** Set texture parameters */
-void (*TexParameter)(GLcontext *ctx, GLenum target,
- struct gl_texture_object *texObj,
- GLenum pname, const GLfloat *params);
-
-static void nv30TextureMatrix(GLcontext *ctx, GLuint unit, const GLmatrix *mat)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (!NOUVEAU_CARD_USING_SHADERS) {
- BEGIN_RING_CACHE(NvSub3D,
- NV30_TCL_PRIMITIVE_3D_TX_MATRIX(unit, 0), 16);
- /*XXX: This SHOULD work.*/
- OUT_RING_CACHEp(mat->m, 16);
- }
-}
-
-static void nv30WindowMoved(nouveauContextPtr nmesa)
-{
- GLcontext *ctx = nmesa->glCtx;
- GLfloat *v = nmesa->viewport.m;
- GLuint wX, wY, wW, wH;
-
- nv30WindowCoords(nmesa, ctx->Viewport.X, ctx->Viewport.Y,
- ctx->Viewport.Width, ctx->Viewport.Height,
- &wX, &wY, &wW, &wH);
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VIEWPORT_DIMS_0, 2);
- OUT_RING_CACHE ((wW << 16) | wX);
- OUT_RING_CACHE ((wH << 16) | wY);
-
- /* something to do with clears, possibly doesn't belong here */
- BEGIN_RING_CACHE(NvSub3D,
- NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_OFS0, 2);
- OUT_RING_CACHE(((nmesa->drawX + nmesa->drawW) << 16) | nmesa->drawX);
- OUT_RING_CACHE(((nmesa->drawY + nmesa->drawH) << 16) | nmesa->drawY);
-
- /* viewport transform */
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VIEWPORT_XFRM_OX, 8);
- OUT_RING_CACHEf (v[MAT_TX]);
- OUT_RING_CACHEf (v[MAT_TY]);
- OUT_RING_CACHEf (v[MAT_TZ]);
- OUT_RING_CACHEf (0.0);
- OUT_RING_CACHEf (v[MAT_SX]);
- OUT_RING_CACHEf (v[MAT_SY]);
- OUT_RING_CACHEf (v[MAT_SZ]);
- OUT_RING_CACHEf (0.0);
-
- ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
- ctx->Scissor.Width, ctx->Scissor.Height);
-}
-
-static GLboolean nv30InitCard(nouveauContextPtr nmesa)
-{
- int i;
- nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D);
-
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT1, 3);
- OUT_RING(NvDmaFB);
- OUT_RING(NvDmaTT);
- OUT_RING(NvDmaFB);
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT8, 1);
- OUT_RING(NvDmaFB);
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT4, 2);
- OUT_RING(NvDmaFB);
- OUT_RING(NvDmaFB);
- BEGIN_RING_SIZE(NvSub3D, 0x1b0, 1); /* SET_OBJECT8B*/
- OUT_RING(NvDmaFB);
-
- for(i = 0x2c8; i <= 0x2fc; i += 4)
- {
- BEGIN_RING_SIZE(NvSub3D, i, 1);
- OUT_RING(0x0);
- }
-
- BEGIN_RING_SIZE(NvSub3D, 0x0220, 1);
- OUT_RING(1);
-
- BEGIN_RING_SIZE(NvSub3D, 0x03b0, 1);
- OUT_RING(0x00100000);
- BEGIN_RING_SIZE(NvSub3D, 0x1454, 1);
- OUT_RING(0);
- BEGIN_RING_SIZE(NvSub3D, 0x1d80, 1);
- OUT_RING(3);
-
- /* NEW */
- BEGIN_RING_SIZE(NvSub3D, 0x1e98, 1);
- OUT_RING(0);
- BEGIN_RING_SIZE(NvSub3D, 0x17e0, 3);
- OUT_RING(0);
- OUT_RING(0);
- OUT_RING(0x3f800000);
- BEGIN_RING_SIZE(NvSub3D, 0x1f80, 16);
- OUT_RING(0); OUT_RING(0); OUT_RING(0); OUT_RING(0);
- OUT_RING(0); OUT_RING(0); OUT_RING(0); OUT_RING(0);
- OUT_RING(0x0000ffff);
- OUT_RING(0); OUT_RING(0); OUT_RING(0); OUT_RING(0);
- OUT_RING(0); OUT_RING(0); OUT_RING(0);
-/*
- BEGIN_RING_SIZE(NvSub3D, 0x100, 2);
- OUT_RING(0);
- OUT_RING(0);
-*/
- BEGIN_RING_SIZE(NvSub3D, 0x120, 3);
- OUT_RING(0);
- OUT_RING(1);
- OUT_RING(2);
-
- BEGIN_RING_SIZE(NvSub3D, 0x1d88, 1);
- OUT_RING(0x00001200);
-
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_RC_ENABLE, 1);
- OUT_RING (0);
-
- return GL_TRUE;
-}
-
-static GLboolean nv40InitCard(nouveauContextPtr nmesa)
-{
- nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D);
-
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT1, 2);
- OUT_RING(NvDmaFB);
- OUT_RING(NvDmaFB);
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT8, 1);
- OUT_RING(NvDmaFB);
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_OBJECT4, 2);
- OUT_RING(NvDmaFB);
- OUT_RING(NvDmaFB);
- BEGIN_RING_SIZE(NvSub3D, 0x0220, 1);
- OUT_RING(1);
-
- BEGIN_RING_SIZE(NvSub3D, 0x1ea4, 3);
- OUT_RING(0x00000010);
- OUT_RING(0x01000100);
- OUT_RING(0xff800006);
- BEGIN_RING_SIZE(NvSub3D, 0x1fc4, 1);
- OUT_RING(0x06144321);
- BEGIN_RING_SIZE(NvSub3D, 0x1fc8, 2);
- OUT_RING(0xedcba987);
- OUT_RING(0x00000021);
- BEGIN_RING_SIZE(NvSub3D, 0x1fd0, 1);
- OUT_RING(0x00171615);
- BEGIN_RING_SIZE(NvSub3D, 0x1fd4, 1);
- OUT_RING(0x001b1a19);
-
- BEGIN_RING_SIZE(NvSub3D, 0x1ef8, 1);
- OUT_RING(0x0020ffff);
- BEGIN_RING_SIZE(NvSub3D, 0x1d64, 1);
- OUT_RING(0x00d30000);
- BEGIN_RING_SIZE(NvSub3D, 0x1e94, 1);
- OUT_RING(0x00000001);
-
- return GL_TRUE;
-}
-
-static GLboolean
-nv30BindBuffers(nouveauContextPtr nmesa, int num_color,
- nouveau_renderbuffer_t **color, nouveau_renderbuffer_t *depth)
-{
- GLuint x, y, w, h;
-
- w = color[0]->mesa.Width;
- h = color[0]->mesa.Height;
- x = nmesa->drawX;
- y = nmesa->drawY;
-
- if (num_color != 1)
- return GL_FALSE;
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VIEWPORT_COLOR_BUFFER_DIM0, 5);
- OUT_RING (((w+x)<<16)|x);
- OUT_RING (((h+y)<<16)|y);
- if (color[0]->mesa._ActualFormat == GL_RGBA8)
- OUT_RING (0x148);
- else
- OUT_RING (0x143);
- if (nmesa->screen->card->type >= NV_40)
- OUT_RING (color[0]->pitch);
- else
- OUT_RING (color[0]->pitch | (depth ? (depth->pitch << 16): 0));
- OUT_RING (color[0]->offset);
-
- if (depth) {
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_DEPTH_OFFSET, 1);
- OUT_RING (depth->offset);
- if (nmesa->screen->card->type >= NV_40) {
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_LMA_DEPTH_BUFFER_PITCH, 1);
- OUT_RING (depth->pitch);
- }
- }
-
- return GL_TRUE;
-}
-
-void nv30InitStateFuncs(GLcontext *ctx, struct dd_function_table *func)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- func->AlphaFunc = nv30AlphaFunc;
- func->BlendColor = nv30BlendColor;
- func->BlendEquationSeparate = nv30BlendEquationSeparate;
- func->BlendFuncSeparate = nv30BlendFuncSeparate;
- func->Clear = nv30Clear;
- func->ClearColor = nv30ClearColor;
- func->ClearDepth = nv30ClearDepth;
- func->ClearStencil = nv30ClearStencil;
- func->ClipPlane = nv30ClipPlane;
- func->ColorMask = nv30ColorMask;
- func->ColorMaterial = nv30ColorMaterial;
- func->CullFace = nv30CullFace;
- func->FrontFace = nv30FrontFace;
- func->DepthFunc = nv30DepthFunc;
- func->DepthMask = nv30DepthMask;
- func->DepthRange = nv30DepthRange;
- func->Enable = nv30Enable;
- func->Fogfv = nv30Fogfv;
- func->Hint = nv30Hint;
- func->Lightfv = nv30Lightfv;
-/* func->LightModelfv = nv30LightModelfv; */
- func->LineStipple = nv30LineStipple;
- func->LineWidth = nv30LineWidth;
- func->LogicOpcode = nv30LogicOpcode;
- func->PointParameterfv = nv30PointParameterfv;
- func->PointSize = nv30PointSize;
- func->PolygonMode = nv30PolygonMode;
- func->PolygonOffset = nv30PolygonOffset;
- func->PolygonStipple = nv30PolygonStipple;
-#if 0
- func->ReadBuffer = nv30ReadBuffer;
- func->RenderMode = nv30RenderMode;
-#endif
- func->Scissor = nv30Scissor;
- func->ShadeModel = nv30ShadeModel;
- func->StencilFuncSeparate = nv30StencilFuncSeparate;
- func->StencilMaskSeparate = nv30StencilMaskSeparate;
- func->StencilOpSeparate = nv30StencilOpSeparate;
-#if 0
- func->TexGen = nv30TexGen;
- func->TexParameter = nv30TexParameter;
-#endif
- func->TextureMatrix = nv30TextureMatrix;
-
-
- if (nmesa->screen->card->type >= NV_40)
- nmesa->hw_func.InitCard = nv40InitCard;
- else
- nmesa->hw_func.InitCard = nv30InitCard;
- nmesa->hw_func.BindBuffers = nv30BindBuffers;
- nmesa->hw_func.WindowMoved = nv30WindowMoved;
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nv30_vertprog.c b/src/mesa/drivers/dri/nouveau/nv30_vertprog.c
deleted file mode 100644
index d023e8439e..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv30_vertprog.c
+++ /dev/null
@@ -1,367 +0,0 @@
-#include "nouveau_context.h"
-#include "nouveau_object.h"
-#include "nouveau_fifo.h"
-#include "nouveau_reg.h"
-
-#include "nouveau_shader.h"
-#include "nv30_shader.h"
-
-/*****************************************************************************
- * Support routines
- */
-static void
-NV30VPUploadToHW(GLcontext *ctx, nouveauShader *nvs)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- int i;
-
- /* We can do better here and keep more than one VP on the hardware, and
- * switch between them with PROGRAM_START_ID..
- */
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_FROM_ID, 1);
- OUT_RING(0);
- for (i=0; iprogram_size; i+=4) {
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_INST0, 4);
- OUT_RING(nvs->program[i + 0]);
- OUT_RING(nvs->program[i + 1]);
- OUT_RING(nvs->program[i + 2]);
- OUT_RING(nvs->program[i + 3]);
- }
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_PROGRAM_START_ID, 1);
- OUT_RING(0);
-
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_IN_REG, 2);
- OUT_RING(nvs->card_priv.NV30VP.vp_in_reg);
- OUT_RING(nvs->card_priv.NV30VP.vp_out_reg);
-
- BEGIN_RING_CACHE(NvSub3D, NV30_TCL_PRIMITIVE_3D_SET_CLIPPING_PLANES, 1);
- OUT_RING_CACHE (nvs->card_priv.NV30VP.clip_enables);
-}
-
-static void
-NV30VPUpdateConst(GLcontext *ctx, nouveauShader *nvs, int id)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLfloat *val;
-
- val = nvs->params[id].source_val ?
- nvs->params[id].source_val : nvs->params[id].val;
-
- BEGIN_RING_SIZE(NvSub3D, NV30_TCL_PRIMITIVE_3D_VP_UPLOAD_CONST_ID, 5);
- OUT_RING (id);
- OUT_RINGp(val, 4);
-}
-
-/*****************************************************************************
- * Assembly routines
- */
-static void
-NV30VPSetBranchTarget(nvsFunc *shader, int addr)
-{
- shader->inst[2] &= ~NV30_VP_INST_IADDR_MASK;
- shader->inst[2] |= (addr << NV30_VP_INST_IADDR_SHIFT);
-}
-
-/*****************************************************************************
- * Disassembly routines
- */
-static unsigned int
-NV30VPGetOpcodeHW(nvsFunc * shader, int slot)
-{
- int op;
-
- if (slot) {
- op = (shader->inst[1] & NV30_VP_INST_SCA_OPCODEL_MASK)
- >> NV30_VP_INST_SCA_OPCODEL_SHIFT;
- op |= ((shader->inst[0] & NV30_VP_INST_SCA_OPCODEH_MASK)
- >> NV30_VP_INST_SCA_OPCODEH_SHIFT) << 4;
- }
- else {
- op = (shader->inst[1] & NV30_VP_INST_VEC_OPCODE_MASK)
- >> NV30_VP_INST_VEC_OPCODE_SHIFT;
- }
-
- return op;
-}
-
-static nvsRegFile
-NV30VPGetDestFile(nvsFunc * shader, int merged)
-{
- switch (shader->GetOpcode(shader, merged)) {
- case NVS_OP_ARL:
- case NVS_OP_ARR:
- case NVS_OP_ARA:
- return NVS_FILE_ADDRESS;
- default:
- /*FIXME: This probably isn't correct.. */
- if ((shader->inst[3] & NV30_VP_INST_VDEST_WRITEMASK_MASK) != 0)
- return NVS_FILE_RESULT;
- if ((shader->inst[3] & NV30_VP_INST_SDEST_WRITEMASK_MASK) != 0)
- return NVS_FILE_RESULT;
- return NVS_FILE_TEMP;
- }
-}
-
-static unsigned int
-NV30VPGetDestID(nvsFunc * shader, int merged)
-{
- int id;
-
- switch (shader->GetDestFile(shader, merged)) {
- case NVS_FILE_RESULT:
- id = ((shader->inst[3] & NV30_VP_INST_DEST_ID_MASK)
- >> NV30_VP_INST_DEST_ID_SHIFT);
- switch (id) {
- case NV30_VP_INST_DEST_POS : return NVS_FR_POSITION;
- case NV30_VP_INST_DEST_COL0 : return NVS_FR_COL0;
- case NV30_VP_INST_DEST_COL1 : return NVS_FR_COL1;
- case NV30_VP_INST_DEST_TC(0): return NVS_FR_TEXCOORD0;
- case NV30_VP_INST_DEST_TC(1): return NVS_FR_TEXCOORD1;
- case NV30_VP_INST_DEST_TC(2): return NVS_FR_TEXCOORD2;
- case NV30_VP_INST_DEST_TC(3): return NVS_FR_TEXCOORD3;
- case NV30_VP_INST_DEST_TC(4): return NVS_FR_TEXCOORD4;
- case NV30_VP_INST_DEST_TC(5): return NVS_FR_TEXCOORD5;
- case NV30_VP_INST_DEST_TC(6): return NVS_FR_TEXCOORD6;
- case NV30_VP_INST_DEST_TC(7): return NVS_FR_TEXCOORD7;
- default:
- return -1;
- }
- case NVS_FILE_ADDRESS:
- case NVS_FILE_TEMP:
- return (shader->inst[0] & NV30_VP_INST_DEST_TEMP_ID_MASK)
- >> NV30_VP_INST_DEST_TEMP_ID_SHIFT;
- default:
- return -1;
- }
-}
-
-static unsigned int
-NV30VPGetDestMask(nvsFunc * shader, int merged)
-{
- int hwmask, mask = 0;
-
- if (shader->GetDestFile(shader, merged) == NVS_FILE_RESULT)
- if (shader->GetOpcodeSlot(shader, merged))
- hwmask = (shader->inst[3] & NV30_VP_INST_SDEST_WRITEMASK_MASK)
- >> NV30_VP_INST_SDEST_WRITEMASK_SHIFT;
- else
- hwmask = (shader->inst[3] & NV30_VP_INST_VDEST_WRITEMASK_MASK)
- >> NV30_VP_INST_VDEST_WRITEMASK_SHIFT;
- else if (shader->GetOpcodeSlot(shader, merged))
- hwmask = (shader->inst[3] & NV30_VP_INST_STEMP_WRITEMASK_MASK)
- >> NV30_VP_INST_STEMP_WRITEMASK_SHIFT;
- else
- hwmask = (shader->inst[3] & NV30_VP_INST_VTEMP_WRITEMASK_MASK)
- >> NV30_VP_INST_VTEMP_WRITEMASK_SHIFT;
-
- if (hwmask & (1 << 3)) mask |= SMASK_X;
- if (hwmask & (1 << 2)) mask |= SMASK_Y;
- if (hwmask & (1 << 1)) mask |= SMASK_Z;
- if (hwmask & (1 << 0)) mask |= SMASK_W;
-
- return mask;
-}
-
-static int
-NV30VPGetSourceID(nvsFunc * shader, int merged, int pos)
-{
- unsigned int src;
-
- switch (shader->GetSourceFile(shader, merged, pos)) {
- case NVS_FILE_TEMP:
- src = shader->GetSourceHW(shader, merged, pos);
- return ((src & NV30_VP_SRC_REG_TEMP_ID_MASK) >>
- NV30_VP_SRC_REG_TEMP_ID_SHIFT);
- case NVS_FILE_CONST:
- return ((shader->inst[1] & NV30_VP_INST_CONST_SRC_MASK)
- >> NV30_VP_INST_CONST_SRC_SHIFT);
- case NVS_FILE_ATTRIB:
- src = ((shader->inst[1] & NV30_VP_INST_INPUT_SRC_MASK)
- >> NV30_VP_INST_INPUT_SRC_SHIFT);
- switch (src) {
- case NV30_VP_INST_IN_POS : return NVS_FR_POSITION;
- case NV30_VP_INST_IN_COL0 : return NVS_FR_COL0;
- case NV30_VP_INST_IN_COL1 : return NVS_FR_COL1;
- case NV30_VP_INST_IN_TC(0): return NVS_FR_TEXCOORD0;
- case NV30_VP_INST_IN_TC(1): return NVS_FR_TEXCOORD1;
- case NV30_VP_INST_IN_TC(2): return NVS_FR_TEXCOORD2;
- case NV30_VP_INST_IN_TC(3): return NVS_FR_TEXCOORD3;
- case NV30_VP_INST_IN_TC(4): return NVS_FR_TEXCOORD4;
- case NV30_VP_INST_IN_TC(5): return NVS_FR_TEXCOORD5;
- case NV30_VP_INST_IN_TC(6): return NVS_FR_TEXCOORD6;
- case NV30_VP_INST_IN_TC(7): return NVS_FR_TEXCOORD7;
- default:
- return NVS_FR_UNKNOWN;
- }
- default:
- return -1;
- }
-}
-
-static int
-NV30VPGetSourceAbs(nvsFunc * shader, int merged, int pos)
-{
- struct _op_xlat *opr;
- static unsigned int abspos[3] = {
- NV30_VP_INST_SRC0_ABS,
- NV30_VP_INST_SRC1_ABS,
- NV30_VP_INST_SRC2_ABS,
- };
-
- opr = shader->GetOPTXRec(shader, merged);
- if (!opr || opr->srcpos[pos] == -1 || opr->srcpos[pos] > 2)
- return 0;
-
- return ((shader->inst[0] & abspos[opr->srcpos[pos]]) ? 1 : 0);
-}
-
-static int
-NV30VPGetRelAddressRegID(nvsFunc * shader)
-{
- return ((shader->inst[0] & NV30_VP_INST_ADDR_REG_SELECT_1) ? 1 : 0);
-}
-
-static nvsSwzComp
-NV30VPGetRelAddressSwizzle(nvsFunc * shader)
-{
- nvsSwzComp swz;
-
- swz = NV20VP_TX_SWIZZLE[(shader->inst[0] & NV30_VP_INST_ADDR_SWZ_MASK)
- >> NV30_VP_INST_ADDR_SWZ_SHIFT];
- return swz;
-}
-
-static int
-NV30VPSupportsConditional(nvsFunc * shader)
-{
- /*FIXME: Is this true of all ops? */
- return 1;
-}
-
-static int
-NV30VPGetConditionUpdate(nvsFunc * shader)
-{
- return ((shader->inst[0] & NV30_VP_INST_COND_UPDATE_ENABLE) ? 1 : 0);
-}
-
-static int
-NV30VPGetConditionTest(nvsFunc * shader)
-{
- int op;
-
- /* The condition test is unconditionally enabled on some
- * instructions. ie: the condition test bit does *NOT* have
- * to be set.
- *
- * FIXME: check other relevant ops for this situation.
- */
- op = shader->GetOpcodeHW(shader, 1);
- switch (op) {
- case NV30_VP_INST_OP_BRA:
- return 1;
- default:
- return ((shader->inst[0] & NV30_VP_INST_COND_TEST_ENABLE) ? 1 : 0);
- }
-}
-
-static nvsCond
-NV30VPGetCondition(nvsFunc * shader)
-{
- int cond;
-
- cond = ((shader->inst[0] & NV30_VP_INST_COND_MASK)
- >> NV30_VP_INST_COND_SHIFT);
-
- switch (cond) {
- case NV30_VP_INST_COND_FL: return NVS_COND_FL;
- case NV30_VP_INST_COND_LT: return NVS_COND_LT;
- case NV30_VP_INST_COND_EQ: return NVS_COND_EQ;
- case NV30_VP_INST_COND_LE: return NVS_COND_LE;
- case NV30_VP_INST_COND_GT: return NVS_COND_GT;
- case NV30_VP_INST_COND_NE: return NVS_COND_NE;
- case NV30_VP_INST_COND_GE: return NVS_COND_GE;
- case NV30_VP_INST_COND_TR: return NVS_COND_TR;
- default:
- return NVS_COND_UNKNOWN;
- }
-}
-
-static void
-NV30VPGetCondRegSwizzle(nvsFunc * shader, nvsSwzComp *swz)
-{
- int swzbits;
-
- swzbits = (shader->inst[0] & NV30_VP_INST_COND_SWZ_ALL_MASK)
- >> NV30_VP_INST_COND_SWZ_ALL_SHIFT;
- NV20VPTXSwizzle(swzbits, swz);
-}
-
-static int
-NV30VPGetCondRegID(nvsFunc * shader)
-{
- return 0;
-}
-
-
-static int
-NV30VPGetBranch(nvsFunc * shader)
-{
- return ((shader->inst[2] & NV30_VP_INST_IADDR_MASK)
- >> NV30_VP_INST_IADDR_SHIFT);
-}
-
-void
-NV30VPInitShaderFuncs(nvsFunc * shader)
-{
- /* Inherit NV20 code, a lot of it is the same */
- NV20VPInitShaderFuncs(shader);
-
- /* Increase max valid opcode ID, and add new instructions */
- NVVP_TX_VOP_COUNT = NVVP_TX_NVS_OP_COUNT = 32;
-
- MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_FRC, NVS_OP_FRC, 0, -1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_FLR, NVS_OP_FLR, 0, -1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SEQ, NVS_OP_SEQ, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SFL, NVS_OP_SFL, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SGT, NVS_OP_SGT, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SLE, NVS_OP_SLE, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SNE, NVS_OP_SNE, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_STR, NVS_OP_STR, 0, 1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_SSG, NVS_OP_SSG, 0, -1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_ARR, NVS_OP_ARR, 0, -1, -1);
- MOD_OPCODE(NVVP_TX_VOP, NV30_VP_INST_OP_ARA, NVS_OP_ARA, 3, -1, -1);
-
- MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_BRA, NVS_OP_BRA, -1, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_CAL, NVS_OP_CAL, -1, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_RET, NVS_OP_RET, -1, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_LG2, NVS_OP_LG2, 2, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_EX2, NVS_OP_EX2, 2, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_SIN, NVS_OP_SIN, 2, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV30_VP_INST_OP_COS, NVS_OP_COS, 2, -1, -1);
-
- shader->UploadToHW = NV30VPUploadToHW;
- shader->UpdateConst = NV30VPUpdateConst;
-
- shader->GetOpcodeHW = NV30VPGetOpcodeHW;
-
- shader->GetDestFile = NV30VPGetDestFile;
- shader->GetDestID = NV30VPGetDestID;
- shader->GetDestMask = NV30VPGetDestMask;
-
- shader->GetSourceID = NV30VPGetSourceID;
- shader->GetSourceAbs = NV30VPGetSourceAbs;
-
- shader->GetRelAddressRegID = NV30VPGetRelAddressRegID;
- shader->GetRelAddressSwizzle = NV30VPGetRelAddressSwizzle;
-
- shader->SupportsConditional = NV30VPSupportsConditional;
- shader->GetConditionUpdate = NV30VPGetConditionUpdate;
- shader->GetConditionTest = NV30VPGetConditionTest;
- shader->GetCondition = NV30VPGetCondition;
- shader->GetCondRegSwizzle = NV30VPGetCondRegSwizzle;
- shader->GetCondRegID = NV30VPGetCondRegID;
-
- shader->GetBranch = NV30VPGetBranch;
- shader->SetBranchTarget = NV30VPSetBranchTarget;
-}
-
diff --git a/src/mesa/drivers/dri/nouveau/nv40_fragprog.c b/src/mesa/drivers/dri/nouveau/nv40_fragprog.c
deleted file mode 100644
index 3e4ae0496e..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv40_fragprog.c
+++ /dev/null
@@ -1,224 +0,0 @@
-#include "nouveau_shader.h"
-#include "nv40_shader.h"
-
-/* branching ops */
-unsigned int NVFP_TX_BOP_COUNT = 5;
-struct _op_xlat NVFP_TX_BOP[64];
-
-
-/*****************************************************************************
- * Assembly routines
- * - These extend the NV30 routines, which are almost identical. NV40
- * just has branching hacked into the instruction set.
- */
-static int
-NV40FPSupportsResultScale(nvsFunc *shader, nvsScale scale)
-{
- switch (scale) {
- case NVS_SCALE_1X:
- case NVS_SCALE_2X:
- case NVS_SCALE_4X:
- case NVS_SCALE_8X:
- case NVS_SCALE_INV_2X:
- case NVS_SCALE_INV_4X:
- case NVS_SCALE_INV_8X:
- return 1;
- default:
- return 0;
- }
-}
-
-static void
-NV40FPSetResultScale(nvsFunc *shader, nvsScale scale)
-{
- shader->inst[2] &= ~NV40_FP_OP_DST_SCALE_MASK;
- shader->inst[2] |= ((unsigned int)scale << NV40_FP_OP_DST_SCALE_SHIFT);
-}
-
-static void
-NV40FPSetBranchTarget(nvsFunc *shader, int addr)
-{
- shader->inst[2] &= ~NV40_FP_OP_IADDR_MASK;
- shader->inst[2] |= (addr << NV40_FP_OP_IADDR_SHIFT);
-}
-
-static void
-NV40FPSetBranchElse(nvsFunc *shader, int addr)
-{
- shader->inst[2] &= ~NV40_FP_OP_ELSE_ID_MASK;
- shader->inst[2] |= (addr << NV40_FP_OP_ELSE_ID_SHIFT);
-}
-
-static void
-NV40FPSetBranchEnd(nvsFunc *shader, int addr)
-{
- shader->inst[3] &= ~NV40_FP_OP_END_ID_MASK;
- shader->inst[3] |= (addr << NV40_FP_OP_END_ID_SHIFT);
-}
-
-static void
-NV40FPSetLoopParams(nvsFunc *shader, int count, int initial, int increment)
-{
- shader->inst[2] &= ~(NV40_FP_OP_LOOP_COUNT_MASK |
- NV40_FP_OP_LOOP_INDEX_MASK |
- NV40_FP_OP_LOOP_INCR_MASK);
- shader->inst[2] |= ((count << NV40_FP_OP_LOOP_COUNT_SHIFT) |
- (initial << NV40_FP_OP_LOOP_INDEX_SHIFT) |
- (increment << NV40_FP_OP_LOOP_INCR_SHIFT));
-}
-
-/*****************************************************************************
- * Disassembly routines
- */
-static struct _op_xlat *
-NV40FPGetOPTXRec(nvsFunc * shader, int merged)
-{
- struct _op_xlat *opr;
- int op;
-
- op = shader->GetOpcodeHW(shader, 0);
- if (shader->inst[2] & NV40_FP_OP_OPCODE_IS_BRANCH) {
- opr = NVFP_TX_BOP;
- op &= ~NV40_FP_OP_OPCODE_IS_BRANCH;
- if (op > NVFP_TX_BOP_COUNT)
- return NULL;
- }
- else {
- opr = NVFP_TX_AOP;
- if (op > NVFP_TX_AOP_COUNT)
- return NULL;
- }
-
- if (opr[op].SOP == NVS_OP_UNKNOWN)
- return NULL;
- return &opr[op];
-}
-
-static int
-NV40FPGetSourceID(nvsFunc * shader, int merged, int pos)
-{
- switch (shader->GetSourceFile(shader, merged, pos)) {
- case NVS_FILE_ATTRIB:
- switch ((shader->inst[0] & NV40_FP_OP_INPUT_SRC_MASK)
- >> NV40_FP_OP_INPUT_SRC_SHIFT) {
- case NV40_FP_OP_INPUT_SRC_POSITION: return NVS_FR_POSITION;
- case NV40_FP_OP_INPUT_SRC_COL0 : return NVS_FR_COL0;
- case NV40_FP_OP_INPUT_SRC_COL1 : return NVS_FR_COL1;
- case NV40_FP_OP_INPUT_SRC_FOGC : return NVS_FR_FOGCOORD;
- case NV40_FP_OP_INPUT_SRC_TC(0) : return NVS_FR_TEXCOORD0;
- case NV40_FP_OP_INPUT_SRC_TC(1) : return NVS_FR_TEXCOORD1;
- case NV40_FP_OP_INPUT_SRC_TC(2) : return NVS_FR_TEXCOORD2;
- case NV40_FP_OP_INPUT_SRC_TC(3) : return NVS_FR_TEXCOORD3;
- case NV40_FP_OP_INPUT_SRC_TC(4) : return NVS_FR_TEXCOORD4;
- case NV40_FP_OP_INPUT_SRC_TC(5) : return NVS_FR_TEXCOORD5;
- case NV40_FP_OP_INPUT_SRC_TC(6) : return NVS_FR_TEXCOORD6;
- case NV40_FP_OP_INPUT_SRC_TC(7) : return NVS_FR_TEXCOORD7;
- case NV40_FP_OP_INPUT_SRC_FACING : return NVS_FR_FACING;
- default:
- return -1;
- }
- break;
- case NVS_FILE_TEMP:
- {
- unsigned int src;
-
- src = shader->GetSourceHW(shader, merged, pos);
- return ((src & NV40_FP_REG_SRC_MASK) >> NV40_FP_REG_SRC_SHIFT);
- }
- case NVS_FILE_CONST: /* inlined into fragprog */
- default:
- return -1;
- }
-}
-
-static int
-NV40FPGetBranch(nvsFunc * shader)
-{
- return ((shader->inst[2] & NV40_FP_OP_IADDR_MASK)
- >> NV40_FP_OP_IADDR_SHIFT);;
-}
-
-static int
-NV40FPGetBranchElse(nvsFunc * shader)
-{
- return ((shader->inst[2] & NV40_FP_OP_ELSE_ID_MASK)
- >> NV40_FP_OP_ELSE_ID_SHIFT);
-}
-
-static int
-NV40FPGetBranchEnd(nvsFunc * shader)
-{
- return ((shader->inst[3] & NV40_FP_OP_END_ID_MASK)
- >> NV40_FP_OP_END_ID_SHIFT);
-}
-
-static int
-NV40FPGetLoopCount(nvsFunc * shader)
-{
- return ((shader->inst[2] & NV40_FP_OP_LOOP_COUNT_MASK)
- >> NV40_FP_OP_LOOP_COUNT_SHIFT);
-}
-
-static int
-NV40FPGetLoopInitial(nvsFunc * shader)
-{
- return ((shader->inst[2] & NV40_FP_OP_LOOP_INDEX_MASK)
- >> NV40_FP_OP_LOOP_INDEX_SHIFT);
-}
-
-static int
-NV40FPGetLoopIncrement(nvsFunc * shader)
-{
- return ((shader->inst[2] & NV40_FP_OP_LOOP_INCR_MASK)
- >> NV40_FP_OP_LOOP_INCR_SHIFT);
-}
-
-void
-NV40FPInitShaderFuncs(nvsFunc * shader)
-{
- /* Inherit NV30 FP code, it's mostly the same */
- NV30FPInitShaderFuncs(shader);
-
- /* Kill off opcodes seen on NV30, but not seen on NV40 - need to find
- * out if these actually work or not.
- *
- * update: either LIT/RSQ don't work on nv40, or I generate bad code for
- * them. haven't tested the others yet
- */
- MOD_OPCODE(NVFP_TX_AOP, 0x1B, NVS_OP_UNKNOWN, -1, -1, -1); /* NV30 RSQ */
- MOD_OPCODE(NVFP_TX_AOP, 0x1E, NVS_OP_UNKNOWN, -1, -1, -1); /* NV30 LIT */
- MOD_OPCODE(NVFP_TX_AOP, 0x1F, NVS_OP_UNKNOWN, -1, -1, -1); /* NV30 LRP */
- MOD_OPCODE(NVFP_TX_AOP, 0x26, NVS_OP_UNKNOWN, -1, -1, -1); /* NV30 POW */
- MOD_OPCODE(NVFP_TX_AOP, 0x36, NVS_OP_UNKNOWN, -1, -1, -1); /* NV30 RFL */
-
- /* Extra opcodes supported on NV40 */
- MOD_OPCODE(NVFP_TX_AOP, NV40_FP_OP_OPCODE_DIV , NVS_OP_DIV , 0, 1, -1);
- MOD_OPCODE(NVFP_TX_AOP, NV40_FP_OP_OPCODE_DP2A , NVS_OP_DP2A, 0, 1, 2);
- MOD_OPCODE(NVFP_TX_AOP, NV40_FP_OP_OPCODE_TXL , NVS_OP_TXL , 0, -1, -1);
-
- MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_BRK , NVS_OP_BRK , -1, -1, -1);
- MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_CAL , NVS_OP_CAL , -1, -1, -1);
- MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_IF , NVS_OP_IF , -1, -1, -1);
- MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_LOOP, NVS_OP_LOOP, -1, -1, -1);
- MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_REP , NVS_OP_REP , -1, -1, -1);
- MOD_OPCODE(NVFP_TX_BOP, NV40_FP_OP_BRA_OPCODE_RET , NVS_OP_RET , -1, -1, -1);
-
- shader->SupportsResultScale = NV40FPSupportsResultScale;
- shader->SetResultScale = NV40FPSetResultScale;
-
- /* fragment.facing */
- shader->GetSourceID = NV40FPGetSourceID;
-
- /* branching */
- shader->GetOPTXRec = NV40FPGetOPTXRec;
- shader->GetBranch = NV40FPGetBranch;
- shader->GetBranchElse = NV40FPGetBranchElse;
- shader->GetBranchEnd = NV40FPGetBranchEnd;
- shader->GetLoopCount = NV40FPGetLoopCount;
- shader->GetLoopInitial = NV40FPGetLoopInitial;
- shader->GetLoopIncrement = NV40FPGetLoopIncrement;
- shader->SetBranchTarget = NV40FPSetBranchTarget;
- shader->SetBranchElse = NV40FPSetBranchElse;
- shader->SetBranchEnd = NV40FPSetBranchEnd;
- shader->SetLoopParams = NV40FPSetLoopParams;
-}
diff --git a/src/mesa/drivers/dri/nouveau/nv40_shader.h b/src/mesa/drivers/dri/nouveau/nv40_shader.h
deleted file mode 100644
index 584f4c23e0..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv40_shader.h
+++ /dev/null
@@ -1,467 +0,0 @@
-#ifndef __NV40_SHADER_H__
-#define __NV40_SHADER_H__
-
-/* Vertex programs instruction set
- *
- * The NV40 instruction set is very similar to NV30. Most fields are in
- * a slightly different position in the instruction however.
- *
- * Merged instructions
- * In some cases it is possible to put two instructions into one opcode
- * slot. The rules for when this is OK is not entirely clear to me yet.
- *
- * There are separate writemasks and dest temp register fields for each
- * grouping of instructions. There is however only one field with the
- * ID of a result register. Writing to temp/result regs is selected by
- * setting VEC_RESULT/SCA_RESULT.
- *
- * Temporary registers
- * The source/dest temp register fields have been extended by 1 bit, to
- * give a total of 32 temporary registers.
- *
- * Relative Addressing
- * NV40 can use an address register to index into vertex attribute regs.
- * This is done by putting the offset value into INPUT_SRC and setting
- * the INDEX_INPUT flag.
- *
- * Conditional execution (see NV_vertex_program{2,3} for details)
- * There is a second condition code register on NV40, it's use is enabled
- * by setting the COND_REG_SELECT_1 flag.
- *
- * Texture lookup
- * TODO
- */
-
-/* ---- OPCODE BITS 127:96 / data DWORD 0 --- */
-#define NV40_VP_INST_VEC_RESULT (1 << 30)
-/* uncertain.. */
-#define NV40_VP_INST_COND_UPDATE_ENABLE ((1 << 14)|1<<29)
-/* use address reg as index into attribs */
-#define NV40_VP_INST_INDEX_INPUT (1 << 27)
-#define NV40_VP_INST_COND_REG_SELECT_1 (1 << 25)
-#define NV40_VP_INST_ADDR_REG_SELECT_1 (1 << 24)
-#define NV40_VP_INST_SRC2_ABS (1 << 23)
-#define NV40_VP_INST_SRC1_ABS (1 << 22)
-#define NV40_VP_INST_SRC0_ABS (1 << 21)
-#define NV40_VP_INST_VEC_DEST_TEMP_SHIFT 15
-#define NV40_VP_INST_VEC_DEST_TEMP_MASK (0x1F << 15)
-#define NV40_VP_INST_COND_TEST_ENABLE (1 << 13)
-#define NV40_VP_INST_COND_SHIFT 10
-#define NV40_VP_INST_COND_MASK (0x7 << 10)
-# define NV40_VP_INST_COND_FL 0
-# define NV40_VP_INST_COND_LT 1
-# define NV40_VP_INST_COND_EQ 2
-# define NV40_VP_INST_COND_LE 3
-# define NV40_VP_INST_COND_GT 4
-# define NV40_VP_INST_COND_NE 5
-# define NV40_VP_INST_COND_GE 6
-# define NV40_VP_INST_COND_TR 7
-#define NV40_VP_INST_COND_SWZ_X_SHIFT 8
-#define NV40_VP_INST_COND_SWZ_X_MASK (3 << 8)
-#define NV40_VP_INST_COND_SWZ_Y_SHIFT 6
-#define NV40_VP_INST_COND_SWZ_Y_MASK (3 << 6)
-#define NV40_VP_INST_COND_SWZ_Z_SHIFT 4
-#define NV40_VP_INST_COND_SWZ_Z_MASK (3 << 4)
-#define NV40_VP_INST_COND_SWZ_W_SHIFT 2
-#define NV40_VP_INST_COND_SWZ_W_MASK (3 << 2)
-#define NV40_VP_INST_COND_SWZ_ALL_SHIFT 2
-#define NV40_VP_INST_COND_SWZ_ALL_MASK (0xFF << 2)
-#define NV40_VP_INST_ADDR_SWZ_SHIFT 0
-#define NV40_VP_INST_ADDR_SWZ_MASK (0x03 << 0)
-#define NV40_VP_INST0_KNOWN ( \
- NV40_VP_INST_INDEX_INPUT | \
- NV40_VP_INST_COND_REG_SELECT_1 | \
- NV40_VP_INST_ADDR_REG_SELECT_1 | \
- NV40_VP_INST_SRC2_ABS | \
- NV40_VP_INST_SRC1_ABS | \
- NV40_VP_INST_SRC0_ABS | \
- NV40_VP_INST_VEC_DEST_TEMP_MASK | \
- NV40_VP_INST_COND_TEST_ENABLE | \
- NV40_VP_INST_COND_MASK | \
- NV40_VP_INST_COND_SWZ_ALL_MASK | \
- NV40_VP_INST_ADDR_SWZ_MASK)
-
-/* ---- OPCODE BITS 95:64 / data DWORD 1 --- */
-#define NV40_VP_INST_VEC_OPCODE_SHIFT 22
-#define NV40_VP_INST_VEC_OPCODE_MASK (0x1F << 22)
-# define NV40_VP_INST_OP_NOP 0x00
-# define NV40_VP_INST_OP_MOV 0x01
-# define NV40_VP_INST_OP_MUL 0x02
-# define NV40_VP_INST_OP_ADD 0x03
-# define NV40_VP_INST_OP_MAD 0x04
-# define NV40_VP_INST_OP_DP3 0x05
-# define NV40_VP_INST_OP_DP4 0x07
-# define NV40_VP_INST_OP_DPH 0x06
-# define NV40_VP_INST_OP_DST 0x08
-# define NV40_VP_INST_OP_MIN 0x09
-# define NV40_VP_INST_OP_MAX 0x0A
-# define NV40_VP_INST_OP_SLT 0x0B
-# define NV40_VP_INST_OP_SGE 0x0C
-# define NV40_VP_INST_OP_ARL 0x0D
-# define NV40_VP_INST_OP_FRC 0x0E
-# define NV40_VP_INST_OP_FLR 0x0F
-# define NV40_VP_INST_OP_SEQ 0x10
-# define NV40_VP_INST_OP_SFL 0x11
-# define NV40_VP_INST_OP_SGT 0x12
-# define NV40_VP_INST_OP_SLE 0x13
-# define NV40_VP_INST_OP_SNE 0x14
-# define NV40_VP_INST_OP_STR 0x15
-# define NV40_VP_INST_OP_SSG 0x16
-# define NV40_VP_INST_OP_ARR 0x17
-# define NV40_VP_INST_OP_ARA 0x18
-# define NV40_VP_INST_OP_TXWHAT 0x19
-#define NV40_VP_INST_SCA_OPCODE_SHIFT 27
-#define NV40_VP_INST_SCA_OPCODE_MASK (0x1F << 27)
-# define NV40_VP_INST_OP_RCP 0x02
-# define NV40_VP_INST_OP_RCC 0x03
-# define NV40_VP_INST_OP_RSQ 0x04
-# define NV40_VP_INST_OP_EXP 0x05
-# define NV40_VP_INST_OP_LOG 0x06
-# define NV40_VP_INST_OP_LIT 0x07
-# define NV40_VP_INST_OP_BRA 0x09
-# define NV40_VP_INST_OP_CAL 0x0B
-# define NV40_VP_INST_OP_RET 0x0C
-# define NV40_VP_INST_OP_LG2 0x0D
-# define NV40_VP_INST_OP_EX2 0x0E
-# define NV40_VP_INST_OP_SIN 0x0F
-# define NV40_VP_INST_OP_COS 0x10
-# define NV40_VP_INST_OP_PUSHA 0x13
-# define NV40_VP_INST_OP_POPA 0x14
-#define NV40_VP_INST_CONST_SRC_SHIFT 12
-#define NV40_VP_INST_CONST_SRC_MASK (0xFF << 12)
-#define NV40_VP_INST_INPUT_SRC_SHIFT 8
-#define NV40_VP_INST_INPUT_SRC_MASK (0x0F << 8)
-# define NV40_VP_INST_IN_POS 0
-# define NV40_VP_INST_IN_WEIGHT 1
-# define NV40_VP_INST_IN_NORMAL 2
-# define NV40_VP_INST_IN_COL0 3
-# define NV40_VP_INST_IN_COL1 4
-# define NV40_VP_INST_IN_FOGC 5
-# define NV40_VP_INST_IN_TC0 8
-# define NV40_VP_INST_IN_TC(n) (8+n)
-#define NV40_VP_INST_SRC0H_SHIFT 0
-#define NV40_VP_INST_SRC0H_MASK (0xFF << 0)
-#define NV40_VP_INST1_KNOWN ( \
- NV40_VP_INST_VEC_OPCODE_MASK | \
- NV40_VP_INST_SCA_OPCODE_MASK | \
- NV40_VP_INST_CONST_SRC_MASK | \
- NV40_VP_INST_INPUT_SRC_MASK | \
- NV40_VP_INST_SRC0H_MASK \
- )
-
-/* ---- OPCODE BITS 63:32 / data DWORD 2 --- */
-#define NV40_VP_INST_SRC0L_SHIFT 23
-#define NV40_VP_INST_SRC0L_MASK (0x1FF << 23)
-#define NV40_VP_INST_SRC1_SHIFT 6
-#define NV40_VP_INST_SRC1_MASK (0x1FFFF << 6)
-#define NV40_VP_INST_SRC2H_SHIFT 0
-#define NV40_VP_INST_SRC2H_MASK (0x3F << 0)
-#define NV40_VP_INST_IADDRH_SHIFT 0
-#define NV40_VP_INST_IADDRH_MASK (0x1F << 0)
-
-/* ---- OPCODE BITS 31:0 / data DWORD 3 --- */
-#define NV40_VP_INST_IADDRL_SHIFT 29
-#define NV40_VP_INST_IADDRL_MASK (7 << 29)
-#define NV40_VP_INST_SRC2L_SHIFT 21
-#define NV40_VP_INST_SRC2L_MASK (0x7FF << 21)
-#define NV40_VP_INST_SCA_WRITEMASK_SHIFT 17
-#define NV40_VP_INST_SCA_WRITEMASK_MASK (0xF << 17)
-# define NV40_VP_INST_SCA_WRITEMASK_X (1 << 20)
-# define NV40_VP_INST_SCA_WRITEMASK_Y (1 << 19)
-# define NV40_VP_INST_SCA_WRITEMASK_Z (1 << 18)
-# define NV40_VP_INST_SCA_WRITEMASK_W (1 << 17)
-#define NV40_VP_INST_VEC_WRITEMASK_SHIFT 13
-#define NV40_VP_INST_VEC_WRITEMASK_MASK (0xF << 13)
-# define NV40_VP_INST_VEC_WRITEMASK_X (1 << 16)
-# define NV40_VP_INST_VEC_WRITEMASK_Y (1 << 15)
-# define NV40_VP_INST_VEC_WRITEMASK_Z (1 << 14)
-# define NV40_VP_INST_VEC_WRITEMASK_W (1 << 13)
-#define NV40_VP_INST_SCA_RESULT (1 << 12)
-#define NV40_VP_INST_SCA_DEST_TEMP_SHIFT 7
-#define NV40_VP_INST_SCA_DEST_TEMP_MASK (0x1F << 7)
-#define NV40_VP_INST_DEST_SHIFT 2
-#define NV40_VP_INST_DEST_MASK (31 << 2)
-# define NV40_VP_INST_DEST_POS 0
-# define NV40_VP_INST_DEST_COL0 1
-# define NV40_VP_INST_DEST_COL1 2
-# define NV40_VP_INST_DEST_BFC0 3
-# define NV40_VP_INST_DEST_BFC1 4
-# define NV40_VP_INST_DEST_FOGC 5
-# define NV40_VP_INST_DEST_PSZ 6
-# define NV40_VP_INST_DEST_TC0 7
-# define NV40_VP_INST_DEST_TC(n) (7+n)
-# define NV40_VP_INST_DEST_TEMP 0x1F
-#define NV40_VP_INST_INDEX_CONST (1 << 1)
-#define NV40_VP_INST_LAST (1 << 0)
-#define NV40_VP_INST3_KNOWN ( \
- NV40_VP_INST_SRC2L_MASK |\
- NV40_VP_INST_SCA_WRITEMASK_MASK |\
- NV40_VP_INST_VEC_WRITEMASK_MASK |\
- NV40_VP_INST_SCA_DEST_TEMP_MASK |\
- NV40_VP_INST_DEST_MASK |\
- NV40_VP_INST_INDEX_CONST)
-
-/* Useful to split the source selection regs into their pieces */
-#define NV40_VP_SRC0_HIGH_SHIFT 9
-#define NV40_VP_SRC0_HIGH_MASK 0x0001FE00
-#define NV40_VP_SRC0_LOW_MASK 0x000001FF
-#define NV40_VP_SRC2_HIGH_SHIFT 11
-#define NV40_VP_SRC2_HIGH_MASK 0x0001F800
-#define NV40_VP_SRC2_LOW_MASK 0x000007FF
-
-/* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */
-#define NV40_VP_SRC_NEGATE (1 << 16)
-#define NV40_VP_SRC_SWZ_X_SHIFT 14
-#define NV40_VP_SRC_SWZ_X_MASK (3 << 14)
-#define NV40_VP_SRC_SWZ_Y_SHIFT 12
-#define NV40_VP_SRC_SWZ_Y_MASK (3 << 12)
-#define NV40_VP_SRC_SWZ_Z_SHIFT 10
-#define NV40_VP_SRC_SWZ_Z_MASK (3 << 10)
-#define NV40_VP_SRC_SWZ_W_SHIFT 8
-#define NV40_VP_SRC_SWZ_W_MASK (3 << 8)
-#define NV40_VP_SRC_SWZ_ALL_SHIFT 8
-#define NV40_VP_SRC_SWZ_ALL_MASK (0xFF << 8)
-#define NV40_VP_SRC_TEMP_SRC_SHIFT 2
-#define NV40_VP_SRC_TEMP_SRC_MASK (0x1F << 2)
-#define NV40_VP_SRC_REG_TYPE_SHIFT 0
-#define NV40_VP_SRC_REG_TYPE_MASK (3 << 0)
-# define NV40_VP_SRC_REG_TYPE_UNK0 0
-# define NV40_VP_SRC_REG_TYPE_TEMP 1
-# define NV40_VP_SRC_REG_TYPE_INPUT 2
-# define NV40_VP_SRC_REG_TYPE_CONST 3
-
-
-/*
- * Each fragment program opcode appears to be comprised of 4 32-bit values.
- *
- * 0 - Opcode, output reg/mask, ATTRIB source
- * 1 - Source 0
- * 2 - Source 1
- * 3 - Source 2
- *
- * There appears to be no special difference between result regs and temp regs.
- * result.color == R0.xyzw
- * result.depth == R1.z
- * When the fragprog contains instructions to write depth,
- * NV30_TCL_PRIMITIVE_3D_UNK1D78=0 otherwise it is set to 1.
- *
- * Constants are inserted directly after the instruction that uses them.
- *
- * It appears that it's not possible to use two input registers in one
- * instruction as the input sourcing is done in the instruction dword
- * and not the source selection dwords. As such instructions such as:
- *
- * ADD result.color, fragment.color, fragment.texcoord[0];
- *
- * must be split into two MOV's and then an ADD (nvidia does this) but
- * I'm not sure why it's not just one MOV and then source the second input
- * in the ADD instruction..
- *
- * Negation of the full source is done with NV30_FP_REG_NEGATE, arbitrary
- * negation requires multiplication with a const.
- *
- * Arbitrary swizzling is supported with the exception of SWIZZLE_ZERO and
- * SWIZZLE_ONE.
- *
- * The temp/result regs appear to be initialised to (0.0, 0.0, 0.0, 0.0) as
- * SWIZZLE_ZERO is implemented simply by not writing to the relevant components
- * of the destination.
- *
- * Looping
- * Loops appear to be fairly expensive on NV40 at least, the proprietary
- * driver goes to a lot of effort to avoid using the native looping
- * instructions. If the total number of *executed* instructions between
- * REP/ENDREP or LOOP/ENDLOOP is <=500, the driver will unroll the loop.
- * The maximum loop count is 255.
- *
- * Conditional execution
- * TODO
- *
- * Non-native instructions:
- * LIT
- * LRP - MAD+MAD
- * SUB - ADD, negate second source
- * RSQ - LG2 + EX2
- * POW - LG2 + MUL + EX2
- * SCS - COS + SIN
- * XPD
- * DP2 - MUL + ADD
- * NRM
- */
-
-//== Opcode / Destination selection ==
-#define NV40_FP_OP_PROGRAM_END (1 << 0)
-#define NV40_FP_OP_OUT_REG_SHIFT 1
-#define NV40_FP_OP_OUT_REG_MASK (31 << 1)
-/* Needs to be set when writing outputs to get expected result.. */
-#define NV40_FP_OP_UNK0_7 (1 << 7)
-#define NV40_FP_OP_COND_WRITE_ENABLE (1 << 8)
-#define NV40_FP_OP_OUTMASK_SHIFT 9
-#define NV40_FP_OP_OUTMASK_MASK (0xF << 9)
-# define NV40_FP_OP_OUT_X (1 << 9)
-# define NV40_FP_OP_OUT_Y (1 <<10)
-# define NV40_FP_OP_OUT_Z (1 <<11)
-# define NV40_FP_OP_OUT_W (1 <<12)
-/* Uncertain about these, especially the input_src values.. it's possible that
- * they can be dynamically changed.
- */
-#define NV40_FP_OP_INPUT_SRC_SHIFT 13
-#define NV40_FP_OP_INPUT_SRC_MASK (15 << 13)
-# define NV40_FP_OP_INPUT_SRC_POSITION 0x0
-# define NV40_FP_OP_INPUT_SRC_COL0 0x1
-# define NV40_FP_OP_INPUT_SRC_COL1 0x2
-# define NV40_FP_OP_INPUT_SRC_FOGC 0x3
-# define NV40_FP_OP_INPUT_SRC_TC0 0x4
-# define NV40_FP_OP_INPUT_SRC_TC(n) (0x4 + n)
-# define NV40_FP_OP_INPUT_SRC_FACING 0xE
-#define NV40_FP_OP_TEX_UNIT_SHIFT 17
-#define NV40_FP_OP_TEX_UNIT_MASK (0xF << 17)
-#define NV40_FP_OP_PRECISION_SHIFT 22
-#define NV40_FP_OP_PRECISION_MASK (3 << 22)
-# define NV40_FP_PRECISION_FP32 0
-# define NV40_FP_PRECISION_FP16 1
-# define NV40_FP_PRECISION_FX12 2
-#define NV40_FP_OP_OPCODE_SHIFT 24
-#define NV40_FP_OP_OPCODE_MASK (0x3F << 24)
-# define NV40_FP_OP_OPCODE_NOP 0x00
-# define NV40_FP_OP_OPCODE_MOV 0x01
-# define NV40_FP_OP_OPCODE_MUL 0x02
-# define NV40_FP_OP_OPCODE_ADD 0x03
-# define NV40_FP_OP_OPCODE_MAD 0x04
-# define NV40_FP_OP_OPCODE_DP3 0x05
-# define NV40_FP_OP_OPCODE_DP4 0x06
-# define NV40_FP_OP_OPCODE_DST 0x07
-# define NV40_FP_OP_OPCODE_MIN 0x08
-# define NV40_FP_OP_OPCODE_MAX 0x09
-# define NV40_FP_OP_OPCODE_SLT 0x0A
-# define NV40_FP_OP_OPCODE_SGE 0x0B
-# define NV40_FP_OP_OPCODE_SLE 0x0C
-# define NV40_FP_OP_OPCODE_SGT 0x0D
-# define NV40_FP_OP_OPCODE_SNE 0x0E
-# define NV40_FP_OP_OPCODE_SEQ 0x0F
-# define NV40_FP_OP_OPCODE_FRC 0x10
-# define NV40_FP_OP_OPCODE_FLR 0x11
-# define NV40_FP_OP_OPCODE_KIL 0x12
-# define NV40_FP_OP_OPCODE_PK4B 0x13
-# define NV40_FP_OP_OPCODE_UP4B 0x14
-/* DDX/DDY can only write to XY */
-# define NV40_FP_OP_OPCODE_DDX 0x15
-# define NV40_FP_OP_OPCODE_DDY 0x16
-# define NV40_FP_OP_OPCODE_TEX 0x17
-# define NV40_FP_OP_OPCODE_TXP 0x18
-# define NV40_FP_OP_OPCODE_TXD 0x19
-# define NV40_FP_OP_OPCODE_RCP 0x1A
-# define NV40_FP_OP_OPCODE_EX2 0x1C
-# define NV40_FP_OP_OPCODE_LG2 0x1D
-# define NV40_FP_OP_OPCODE_COS 0x22
-# define NV40_FP_OP_OPCODE_SIN 0x23
-# define NV40_FP_OP_OPCODE_PK2H 0x24
-# define NV40_FP_OP_OPCODE_UP2H 0x25
-# define NV40_FP_OP_OPCODE_PK4UB 0x27
-# define NV40_FP_OP_OPCODE_UP4UB 0x28
-# define NV40_FP_OP_OPCODE_PK2US 0x29
-# define NV40_FP_OP_OPCODE_UP2US 0x2A
-# define NV40_FP_OP_OPCODE_DP2A 0x2E
-# define NV40_FP_OP_OPCODE_TXL 0x2F
-# define NV40_FP_OP_OPCODE_TXB 0x31
-# define NV40_FP_OP_OPCODE_DIV 0x3A
-/* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/
-# define NV40_FP_OP_BRA_OPCODE_BRK 0x0
-# define NV40_FP_OP_BRA_OPCODE_CAL 0x1
-# define NV40_FP_OP_BRA_OPCODE_IF 0x2
-# define NV40_FP_OP_BRA_OPCODE_LOOP 0x3
-# define NV40_FP_OP_BRA_OPCODE_REP 0x4
-# define NV40_FP_OP_BRA_OPCODE_RET 0x5
-#define NV40_FP_OP_OUT_SAT (1 << 31)
-
-/* high order bits of SRC0 */
-#define NV40_FP_OP_OUT_ABS (1 << 29)
-#define NV40_FP_OP_COND_SWZ_W_SHIFT 27
-#define NV40_FP_OP_COND_SWZ_W_MASK (3 << 27)
-#define NV40_FP_OP_COND_SWZ_Z_SHIFT 25
-#define NV40_FP_OP_COND_SWZ_Z_MASK (3 << 25)
-#define NV40_FP_OP_COND_SWZ_Y_SHIFT 23
-#define NV40_FP_OP_COND_SWZ_Y_MASK (3 << 23)
-#define NV40_FP_OP_COND_SWZ_X_SHIFT 21
-#define NV40_FP_OP_COND_SWZ_X_MASK (3 << 21)
-#define NV40_FP_OP_COND_SWZ_ALL_SHIFT 21
-#define NV40_FP_OP_COND_SWZ_ALL_MASK (0xFF << 21)
-#define NV40_FP_OP_COND_SHIFT 18
-#define NV40_FP_OP_COND_MASK (0x07 << 18)
-# define NV40_FP_OP_COND_FL 0
-# define NV40_FP_OP_COND_LT 1
-# define NV40_FP_OP_COND_EQ 2
-# define NV40_FP_OP_COND_LE 3
-# define NV40_FP_OP_COND_GT 4
-# define NV40_FP_OP_COND_NE 5
-# define NV40_FP_OP_COND_GE 6
-# define NV40_FP_OP_COND_TR 7
-
-/* high order bits of SRC1 */
-#define NV40_FP_OP_OPCODE_IS_BRANCH (1<<31)
-#define NV40_FP_OP_DST_SCALE_SHIFT 28
-#define NV40_FP_OP_DST_SCALE_MASK (3 << 28)
-
-/* SRC1 LOOP */
-#define NV40_FP_OP_LOOP_INCR_SHIFT 19
-#define NV40_FP_OP_LOOP_INCR_MASK (0xFF << 19)
-#define NV40_FP_OP_LOOP_INDEX_SHIFT 10
-#define NV40_FP_OP_LOOP_INDEX_MASK (0xFF << 10)
-#define NV40_FP_OP_LOOP_COUNT_SHIFT 2
-#define NV40_FP_OP_LOOP_COUNT_MASK (0xFF << 2)
-
-/* SRC1 IF */
-#define NV40_FP_OP_ELSE_ID_SHIFT 2
-#define NV40_FP_OP_ELSE_ID_MASK (0xFF << 2)
-
-/* SRC1 CAL */
-#define NV40_FP_OP_IADDR_SHIFT 2
-#define NV40_FP_OP_IADDR_MASK (0xFF << 2)
-
-/* SRC1 REP
- * I have no idea why there are 3 count values here.. but they
- * have always been filled with the same value in my tests so
- * far..
- */
-#define NV40_FP_OP_REP_COUNT1_SHIFT 2
-#define NV40_FP_OP_REP_COUNT1_MASK (0xFF << 2)
-#define NV40_FP_OP_REP_COUNT2_SHIFT 10
-#define NV40_FP_OP_REP_COUNT2_MASK (0xFF << 10)
-#define NV40_FP_OP_REP_COUNT3_SHIFT 19
-#define NV40_FP_OP_REP_COUNT3_MASK (0xFF << 19)
-
-/* SRC2 REP/IF */
-#define NV40_FP_OP_END_ID_SHIFT 2
-#define NV40_FP_OP_END_ID_MASK (0xFF << 2)
-
-// SRC2 high-order
-#define NV40_FP_OP_INDEX_INPUT (1 << 30)
-#define NV40_FP_OP_ADDR_INDEX_SHIFT 19
-#define NV40_FP_OP_ADDR_INDEX_MASK (0xF << 19)
-
-//== Register selection ==
-#define NV40_FP_REG_TYPE_SHIFT 0
-#define NV40_FP_REG_TYPE_MASK (3 << 0)
-# define NV40_FP_REG_TYPE_TEMP 0
-# define NV40_FP_REG_TYPE_INPUT 1
-# define NV40_FP_REG_TYPE_CONST 2
-#define NV40_FP_REG_SRC_SHIFT 2
-#define NV40_FP_REG_SRC_MASK (31 << 2)
-#define NV40_FP_REG_UNK_0 (1 << 8)
-#define NV40_FP_REG_SWZ_ALL_SHIFT 9
-#define NV40_FP_REG_SWZ_ALL_MASK (255 << 9)
-#define NV40_FP_REG_SWZ_X_SHIFT 9
-#define NV40_FP_REG_SWZ_X_MASK (3 << 9)
-#define NV40_FP_REG_SWZ_Y_SHIFT 11
-#define NV40_FP_REG_SWZ_Y_MASK (3 << 11)
-#define NV40_FP_REG_SWZ_Z_SHIFT 13
-#define NV40_FP_REG_SWZ_Z_MASK (3 << 13)
-#define NV40_FP_REG_SWZ_W_SHIFT 15
-#define NV40_FP_REG_SWZ_W_MASK (3 << 15)
-# define NV40_FP_SWIZZLE_X 0
-# define NV40_FP_SWIZZLE_Y 1
-# define NV40_FP_SWIZZLE_Z 2
-# define NV40_FP_SWIZZLE_W 3
-#define NV40_FP_REG_NEGATE (1 << 17)
-
-#endif
diff --git a/src/mesa/drivers/dri/nouveau/nv40_vertprog.c b/src/mesa/drivers/dri/nouveau/nv40_vertprog.c
deleted file mode 100644
index d054140bcd..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv40_vertprog.c
+++ /dev/null
@@ -1,778 +0,0 @@
-#include "nouveau_shader.h"
-#include "nouveau_msg.h"
-#include "nv40_shader.h"
-
-/*****************************************************************************
- * Assembly routines
- */
-static int
-NV40VPSupportsOpcode(nvsFunc * shader, nvsOpcode op)
-{
- if (shader->GetOPTXFromSOP(op, NULL))
- return 1;
- return 0;
-}
-
-static void
-NV40VPSetOpcode(nvsFunc *shader, unsigned int opcode, int slot)
-{
- if (slot) {
- shader->inst[1] &= ~NV40_VP_INST_SCA_OPCODE_MASK;
- shader->inst[1] |= (opcode << NV40_VP_INST_SCA_OPCODE_SHIFT);
- } else {
- shader->inst[1] &= ~NV40_VP_INST_VEC_OPCODE_MASK;
- shader->inst[1] |= (opcode << NV40_VP_INST_VEC_OPCODE_SHIFT);
- }
-}
-
-static void
-NV40VPSetCCUpdate(nvsFunc *shader)
-{
- shader->inst[0] |= NV40_VP_INST_COND_UPDATE_ENABLE;
-}
-
-static void
-NV40VPSetCondition(nvsFunc *shader, int on, nvsCond cond, int reg,
- nvsSwzComp *swizzle)
-{
- unsigned int hwcond;
-
- if (on ) shader->inst[0] |= NV40_VP_INST_COND_TEST_ENABLE;
- else shader->inst[0] &= ~NV40_VP_INST_COND_TEST_ENABLE;
- if (reg) shader->inst[0] |= NV40_VP_INST_COND_REG_SELECT_1;
- else shader->inst[0] &= ~NV40_VP_INST_COND_REG_SELECT_1;
-
- switch (cond) {
- case NVS_COND_TR: hwcond = NV40_VP_INST_COND_TR; break;
- case NVS_COND_FL: hwcond = NV40_VP_INST_COND_FL; break;
- case NVS_COND_LT: hwcond = NV40_VP_INST_COND_LT; break;
- case NVS_COND_GT: hwcond = NV40_VP_INST_COND_GT; break;
- case NVS_COND_NE: hwcond = NV40_VP_INST_COND_NE; break;
- case NVS_COND_EQ: hwcond = NV40_VP_INST_COND_EQ; break;
- case NVS_COND_GE: hwcond = NV40_VP_INST_COND_GE; break;
- case NVS_COND_LE: hwcond = NV40_VP_INST_COND_LE; break;
- default:
- WARN_ONCE("unknown vp cond %d\n", cond);
- hwcond = NV40_VP_INST_COND_TR;
- break;
- }
- shader->inst[0] &= ~NV40_VP_INST_COND_MASK;
- shader->inst[0] |= (hwcond << NV40_VP_INST_COND_SHIFT);
-
- shader->inst[0] &= ~NV40_VP_INST_COND_SWZ_ALL_MASK;
- shader->inst[0] |= (swizzle[NVS_SWZ_X] << NV40_VP_INST_COND_SWZ_X_SHIFT);
- shader->inst[0] |= (swizzle[NVS_SWZ_Y] << NV40_VP_INST_COND_SWZ_Y_SHIFT);
- shader->inst[0] |= (swizzle[NVS_SWZ_Z] << NV40_VP_INST_COND_SWZ_Z_SHIFT);
- shader->inst[0] |= (swizzle[NVS_SWZ_W] << NV40_VP_INST_COND_SWZ_W_SHIFT);
-}
-
-/* these just exist here until nouveau_reg.h has them. */
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL0 (1<<0)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1 (1<<1)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0 (1<<2)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1 (1<<3)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC (1<<4)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ (1<<5)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0 (1<<6)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1 (1<<7)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2 (1<<8)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3 (1<<9)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4 (1<<10)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5 (1<<11)
-#define NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0 (1<<14)
-
-static unsigned int
-NV40VPTranslateResultReg(nvsFunc *shader, nvsFixedReg result,
- unsigned int *mask_ret)
-{
- unsigned int *out_reg = &shader->card_priv->NV30VP.vp_out_reg;
- unsigned int *clip_en = &shader->card_priv->NV30VP.clip_enables;
-
- *mask_ret = 0xf;
-
- switch (result) {
- case NVS_FR_POSITION:
- /* out_reg POS implied */
- return NV40_VP_INST_DEST_POS;
- case NVS_FR_COL0:
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL0;
- return NV40_VP_INST_DEST_COL0;
- case NVS_FR_COL1:
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_COL1;
- return NV40_VP_INST_DEST_COL1;
- case NVS_FR_BFC0:
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC0;
- return NV40_VP_INST_DEST_BFC0;
- case NVS_FR_BFC1:
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_BFC1;
- return NV40_VP_INST_DEST_BFC1;
- case NVS_FR_FOGCOORD:
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_FOGC;
- *mask_ret = 0x8;
- return NV40_VP_INST_DEST_FOGC;
- case NVS_FR_CLIP0:
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP0;
- (*clip_en) |= 0x00000002;
- *mask_ret = 0x4;
- return NV40_VP_INST_DEST_FOGC;
- case NVS_FR_CLIP1:
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP1;
- (*clip_en) |= 0x00000020;
- *mask_ret = 0x2;
- return NV40_VP_INST_DEST_FOGC;
- case NVS_FR_CLIP2:
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP2;
- (*clip_en) |= 0x00000200;
- *mask_ret = 0x1;
- return NV40_VP_INST_DEST_FOGC;
- case NVS_FR_POINTSZ:
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_PSZ;
- *mask_ret = 0x8;
- return NV40_VP_INST_DEST_PSZ;
- case NVS_FR_CLIP3:
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP3;
- (*clip_en) |= 0x00002000;
- *mask_ret = 0x4;
- return NV40_VP_INST_DEST_PSZ;
- case NVS_FR_CLIP4:
- (*clip_en) |= 0x00020000;
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP4;
- *mask_ret = 0x2;
- return NV40_VP_INST_DEST_PSZ;
- case NVS_FR_CLIP5:
- (*clip_en) |= 0x00200000;
- (*out_reg) |= NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_CLP5;
- *mask_ret = 0x1;
- return NV40_VP_INST_DEST_PSZ;
- case NVS_FR_TEXCOORD0:
- case NVS_FR_TEXCOORD1:
- case NVS_FR_TEXCOORD2:
- case NVS_FR_TEXCOORD3:
- case NVS_FR_TEXCOORD4:
- case NVS_FR_TEXCOORD5:
- case NVS_FR_TEXCOORD6:
- case NVS_FR_TEXCOORD7:
- {
- int unit = result - NVS_FR_TEXCOORD0;
- (*out_reg) |= (NV30_TCL_PRIMITIVE_3D_VP_OUT_REG_TEX0 << unit);
- return NV40_VP_INST_DEST_TC(unit);
- }
- default:
- WARN_ONCE("unknown vp output %d\n", result);
- return NV40_VP_INST_DEST_POS;
- }
-}
-
-static void
-NV40VPSetResult(nvsFunc *shader, nvsRegister * dest, unsigned int mask,
- int slot)
-{
- unsigned int hwmask = 0;
-
- if (mask & SMASK_X) hwmask |= (1 << 3);
- if (mask & SMASK_Y) hwmask |= (1 << 2);
- if (mask & SMASK_Z) hwmask |= (1 << 1);
- if (mask & SMASK_W) hwmask |= (1 << 0);
-
- if (dest->file == NVS_FILE_RESULT) {
- unsigned int valid_mask;
- int hwidx;
-
- hwidx = NV40VPTranslateResultReg(shader, dest->index, &valid_mask);
- if (hwmask & ~valid_mask)
- WARN_ONCE("writing invalid components of result reg\n");
- hwmask &= valid_mask;
-
- shader->inst[3] &= ~NV40_VP_INST_DEST_MASK;
- shader->inst[3] |= (hwidx << NV40_VP_INST_DEST_SHIFT);
-
- if (slot) shader->inst[3] |= NV40_VP_INST_SCA_RESULT;
- else shader->inst[0] |= NV40_VP_INST_VEC_RESULT;
- } else {
- /* NVS_FILE_TEMP || NVS_FILE_ADDRESS */
- if (slot) {
- shader->inst[3] &= ~NV40_VP_INST_SCA_RESULT;
- shader->inst[3] &= ~NV40_VP_INST_SCA_DEST_TEMP_MASK;
- shader->inst[3] |= (dest->index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
- } else {
- shader->inst[0] &= ~NV40_VP_INST_VEC_RESULT;
- shader->inst[0] &= ~(NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20));
- shader->inst[0] |= (dest->index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
- }
- }
-
- if (slot) {
- shader->inst[3] &= ~NV40_VP_INST_SCA_WRITEMASK_MASK;
- shader->inst[3] |= (hwmask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
- } else {
- shader->inst[3] &= ~NV40_VP_INST_VEC_WRITEMASK_MASK;
- shader->inst[3] |= (hwmask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
- }
-}
-
-static void
-NV40VPInsertSource(nvsFunc *shader, unsigned int hw, int pos)
-{
- switch (pos) {
- case 0:
- shader->inst[1] &= ~NV40_VP_INST_SRC0H_MASK;
- shader->inst[2] &= ~NV40_VP_INST_SRC0L_MASK;
- shader->inst[1] |= ((hw & NV40_VP_SRC0_HIGH_MASK) >>
- NV40_VP_SRC0_HIGH_SHIFT)
- << NV40_VP_INST_SRC0H_SHIFT;
- shader->inst[2] |= (hw & NV40_VP_SRC0_LOW_MASK)
- << NV40_VP_INST_SRC0L_SHIFT;
- break;
- case 1:
- shader->inst[2] &= ~NV40_VP_INST_SRC1_MASK;
- shader->inst[2] |= hw
- << NV40_VP_INST_SRC1_SHIFT;
- break;
- case 2:
- shader->inst[2] &= ~NV40_VP_INST_SRC2H_MASK;
- shader->inst[3] &= ~NV40_VP_INST_SRC2L_MASK;
- shader->inst[2] |= ((hw & NV40_VP_SRC2_HIGH_MASK) >>
- NV40_VP_SRC2_HIGH_SHIFT)
- << NV40_VP_INST_SRC2H_SHIFT;
- shader->inst[3] |= (hw & NV40_VP_SRC2_LOW_MASK)
- << NV40_VP_INST_SRC2L_SHIFT;
- break;
- default:
- assert(0);
- break;
- }
-}
-
-static void
-NV40VPSetSource(nvsFunc *shader, nvsRegister * src, int pos)
-{
- unsigned int hw = 0;
-
- switch (src->file) {
- case NVS_FILE_ADDRESS:
- break;
- case NVS_FILE_ATTRIB:
- hw |= (NV40_VP_SRC_REG_TYPE_INPUT << NV40_VP_SRC_REG_TYPE_SHIFT);
-
- shader->inst[1] &= ~NV40_VP_INST_INPUT_SRC_MASK;
- shader->inst[1] |= (src->index << NV40_VP_INST_INPUT_SRC_SHIFT);
- shader->card_priv->NV30VP.vp_in_reg |= (1 << src->index);
- if (src->indexed) {
- shader->inst[0] |= NV40_VP_INST_INDEX_INPUT;
- if (src->addr_reg)
- shader->inst[0] |= NV40_VP_INST_ADDR_REG_SELECT_1;
- else
- shader->inst[0] &= ~NV40_VP_INST_ADDR_REG_SELECT_1;
- shader->inst[0] &= ~NV40_VP_INST_ADDR_SWZ_SHIFT;
- shader->inst[0] |= (src->addr_comp << NV40_VP_INST_ADDR_SWZ_SHIFT);
- } else
- shader->inst[0] &= ~NV40_VP_INST_INDEX_INPUT;
- break;
- case NVS_FILE_CONST:
- hw |= (NV40_VP_SRC_REG_TYPE_CONST << NV40_VP_SRC_REG_TYPE_SHIFT);
-
- shader->inst[1] &= ~NV40_VP_INST_CONST_SRC_MASK;
- shader->inst[1] |= (src->index << NV40_VP_INST_CONST_SRC_SHIFT);
- if (src->indexed) {
- shader->inst[3] |= NV40_VP_INST_INDEX_CONST;
- if (src->addr_reg)
- shader->inst[0] |= NV40_VP_INST_ADDR_REG_SELECT_1;
- else
- shader->inst[0] &= ~NV40_VP_INST_ADDR_REG_SELECT_1;
- shader->inst[0] &= ~NV40_VP_INST_ADDR_SWZ_MASK;
- shader->inst[0] |= (src->addr_comp << NV40_VP_INST_ADDR_SWZ_SHIFT);
- } else
- shader->inst[3] &= ~NV40_VP_INST_INDEX_CONST;
- break;
- case NVS_FILE_TEMP:
- hw |= (NV40_VP_SRC_REG_TYPE_TEMP << NV40_VP_SRC_REG_TYPE_SHIFT);
- hw |= (src->index << NV40_VP_SRC_TEMP_SRC_SHIFT);
- break;
- default:
- fprintf(stderr, "unknown source file %d\n", src->file);
- assert(0);
- break;
- }
-
- if (src->file != NVS_FILE_ADDRESS) {
- if (src->negate)
- hw |= NV40_VP_SRC_NEGATE;
- if (src->abs)
- shader->inst[0] |= (1 << (21 + pos));
- else
- shader->inst[0] &= ~(1 << (21 + pos));
- hw |= (src->swizzle[0] << NV40_VP_SRC_SWZ_X_SHIFT);
- hw |= (src->swizzle[1] << NV40_VP_SRC_SWZ_Y_SHIFT);
- hw |= (src->swizzle[2] << NV40_VP_SRC_SWZ_Z_SHIFT);
- hw |= (src->swizzle[3] << NV40_VP_SRC_SWZ_W_SHIFT);
-
- NV40VPInsertSource(shader, hw, pos);
- }
-}
-
-static void
-NV40VPSetBranchTarget(nvsFunc *shader, int addr)
-{
- shader->inst[2] &= ~NV40_VP_INST_IADDRH_MASK;
- shader->inst[2] |= ((addr & 0xf8) >> 3) << NV40_VP_INST_IADDRH_SHIFT;
- shader->inst[3] &= ~NV40_VP_INST_IADDRL_MASK;
- shader->inst[3] |= ((addr & 0x07) << NV40_VP_INST_IADDRL_SHIFT);
-}
-
-static void
-NV40VPInitInstruction(nvsFunc *shader)
-{
- unsigned int hwsrc = 0;
-
- shader->inst[0] = /*NV40_VP_INST_VEC_RESULT | */
- NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
- shader->inst[1] = 0;
- shader->inst[2] = 0;
- shader->inst[3] = NV40_VP_INST_SCA_RESULT |
- NV40_VP_INST_SCA_DEST_TEMP_MASK |
- NV40_VP_INST_DEST_MASK;
-
- hwsrc = (NV40_VP_SRC_REG_TYPE_INPUT << NV40_VP_SRC_REG_TYPE_SHIFT) |
- (NVS_SWZ_X << NV40_VP_SRC_SWZ_X_SHIFT) |
- (NVS_SWZ_Y << NV40_VP_SRC_SWZ_Y_SHIFT) |
- (NVS_SWZ_Z << NV40_VP_SRC_SWZ_Z_SHIFT) |
- (NVS_SWZ_W << NV40_VP_SRC_SWZ_W_SHIFT);
- NV40VPInsertSource(shader, hwsrc, 0);
- NV40VPInsertSource(shader, hwsrc, 1);
- NV40VPInsertSource(shader, hwsrc, 2);
-}
-
-static void
-NV40VPSetLastInst(nvsFunc *shader)
-{
- shader->inst[3] |= 1;
-}
-
-/*****************************************************************************
- * Disassembly routines
- */
-static int
-NV40VPHasMergedInst(nvsFunc * shader)
-{
- if (shader->GetOpcodeHW(shader, 0) != NV40_VP_INST_OP_NOP &&
- shader->GetOpcodeHW(shader, 1) != NV40_VP_INST_OP_NOP)
- return 1;
- return 0;
-}
-
-static unsigned int
-NV40VPGetOpcodeHW(nvsFunc * shader, int slot)
-{
- int op;
-
- if (slot)
- op = (shader->inst[1] & NV40_VP_INST_SCA_OPCODE_MASK)
- >> NV40_VP_INST_SCA_OPCODE_SHIFT;
- else
- op = (shader->inst[1] & NV40_VP_INST_VEC_OPCODE_MASK)
- >> NV40_VP_INST_VEC_OPCODE_SHIFT;
-
- return op;
-}
-
-static nvsRegFile
-NV40VPGetDestFile(nvsFunc * shader, int merged)
-{
- nvsOpcode op;
-
- op = shader->GetOpcode(shader, merged);
- switch (op) {
- case NVS_OP_ARL:
- case NVS_OP_ARR:
- case NVS_OP_ARA:
- case NVS_OP_POPA:
- return NVS_FILE_ADDRESS;
- default:
- if (shader->GetOpcodeSlot(shader, merged)) {
- if (shader->inst[3] & NV40_VP_INST_SCA_RESULT)
- return NVS_FILE_RESULT;
- }
- else {
- if (shader->inst[0] & NV40_VP_INST_VEC_RESULT)
- return NVS_FILE_RESULT;
- }
- return NVS_FILE_TEMP;
- }
-
-}
-
-static unsigned int
-NV40VPGetDestID(nvsFunc * shader, int merged)
-{
- int id;
-
- switch (shader->GetDestFile(shader, merged)) {
- case NVS_FILE_RESULT:
- id = ((shader->inst[3] & NV40_VP_INST_DEST_MASK)
- >> NV40_VP_INST_DEST_SHIFT);
- switch (id) {
- case NV40_VP_INST_DEST_POS : return NVS_FR_POSITION;
- case NV40_VP_INST_DEST_COL0: return NVS_FR_COL0;
- case NV40_VP_INST_DEST_COL1: return NVS_FR_COL1;
- case NV40_VP_INST_DEST_BFC0: return NVS_FR_BFC0;
- case NV40_VP_INST_DEST_BFC1: return NVS_FR_BFC1;
- case NV40_VP_INST_DEST_FOGC: {
- int mask = shader->GetDestMask(shader, merged);
- switch (mask) {
- case SMASK_X: return NVS_FR_FOGCOORD;
- case SMASK_Y: return NVS_FR_CLIP0;
- case SMASK_Z: return NVS_FR_CLIP1;
- case SMASK_W: return NVS_FR_CLIP2;
- default:
- printf("more than 1 mask component set in FOGC writemask!\n");
- return NVS_FR_UNKNOWN;
- }
- }
- case NV40_VP_INST_DEST_PSZ:
- {
- int mask = shader->GetDestMask(shader, merged);
- switch (mask) {
- case SMASK_X: return NVS_FR_POINTSZ;
- case SMASK_Y: return NVS_FR_CLIP3;
- case SMASK_Z: return NVS_FR_CLIP4;
- case SMASK_W: return NVS_FR_CLIP5;
- default:
- printf("more than 1 mask component set in PSZ writemask!\n");
- return NVS_FR_UNKNOWN;
- }
- }
- case NV40_VP_INST_DEST_TC(0): return NVS_FR_TEXCOORD0;
- case NV40_VP_INST_DEST_TC(1): return NVS_FR_TEXCOORD1;
- case NV40_VP_INST_DEST_TC(2): return NVS_FR_TEXCOORD2;
- case NV40_VP_INST_DEST_TC(3): return NVS_FR_TEXCOORD3;
- case NV40_VP_INST_DEST_TC(4): return NVS_FR_TEXCOORD4;
- case NV40_VP_INST_DEST_TC(5): return NVS_FR_TEXCOORD5;
- case NV40_VP_INST_DEST_TC(6): return NVS_FR_TEXCOORD6;
- case NV40_VP_INST_DEST_TC(7): return NVS_FR_TEXCOORD7;
- default:
- return -1;
- }
- case NVS_FILE_ADDRESS:
- /* Instructions that write address regs are encoded as if
- * they would write temps.
- */
- case NVS_FILE_TEMP:
- if (shader->GetOpcodeSlot(shader, merged))
- id = ((shader->inst[3] & NV40_VP_INST_SCA_DEST_TEMP_MASK)
- >> NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
- else
- id = ((shader->inst[0] & NV40_VP_INST_VEC_DEST_TEMP_MASK)
- >> NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
- return id;
- default:
- return -1;
- }
-}
-
-static unsigned int
-NV40VPGetDestMask(nvsFunc * shader, int merged)
-{
- unsigned int mask = 0;
-
- if (shader->GetOpcodeSlot(shader, merged)) {
- if (shader->inst[3] & NV40_VP_INST_SCA_WRITEMASK_X) mask |= SMASK_X;
- if (shader->inst[3] & NV40_VP_INST_SCA_WRITEMASK_Y) mask |= SMASK_Y;
- if (shader->inst[3] & NV40_VP_INST_SCA_WRITEMASK_Z) mask |= SMASK_Z;
- if (shader->inst[3] & NV40_VP_INST_SCA_WRITEMASK_W) mask |= SMASK_W;
- } else {
- if (shader->inst[3] & NV40_VP_INST_VEC_WRITEMASK_X) mask |= SMASK_X;
- if (shader->inst[3] & NV40_VP_INST_VEC_WRITEMASK_Y) mask |= SMASK_Y;
- if (shader->inst[3] & NV40_VP_INST_VEC_WRITEMASK_Z) mask |= SMASK_Z;
- if (shader->inst[3] & NV40_VP_INST_VEC_WRITEMASK_W) mask |= SMASK_W;
- }
-
- return mask;
-}
-
-static unsigned int
-NV40VPGetSourceHW(nvsFunc * shader, int merged, int pos)
-{
- struct _op_xlat *opr;
- unsigned int src;
-
- opr = shader->GetOPTXRec(shader, merged);
- if (!opr)
- return -1;
-
- switch (opr->srcpos[pos]) {
- case 0:
- src = ((shader->inst[1] & NV40_VP_INST_SRC0H_MASK)
- >> NV40_VP_INST_SRC0H_SHIFT)
- << NV40_VP_SRC0_HIGH_SHIFT;
- src |= ((shader->inst[2] & NV40_VP_INST_SRC0L_MASK)
- >> NV40_VP_INST_SRC0L_SHIFT);
- break;
- case 1:
- src = ((shader->inst[2] & NV40_VP_INST_SRC1_MASK)
- >> NV40_VP_INST_SRC1_SHIFT);
- break;
- case 2:
- src = ((shader->inst[2] & NV40_VP_INST_SRC2H_MASK)
- >> NV40_VP_INST_SRC2H_SHIFT)
- << NV40_VP_SRC2_HIGH_SHIFT;
- src |= ((shader->inst[3] & NV40_VP_INST_SRC2L_MASK)
- >> NV40_VP_INST_SRC2L_SHIFT);
- break;
- default:
- src = -1;
- }
-
- return src;
-}
-
-static nvsRegFile
-NV40VPGetSourceFile(nvsFunc * shader, int merged, int pos)
-{
- unsigned int src;
- struct _op_xlat *opr;
- int file;
-
- opr = shader->GetOPTXRec(shader, merged);
- if (!opr || opr->srcpos[pos] == -1)
- return -1;
-
- switch (opr->srcpos[pos]) {
- case SPOS_ADDRESS: return NVS_FILE_ADDRESS;
- default:
- src = shader->GetSourceHW(shader, merged, pos);
- file = (src & NV40_VP_SRC_REG_TYPE_MASK) >> NV40_VP_SRC_REG_TYPE_SHIFT;
-
- switch (file) {
- case NV40_VP_SRC_REG_TYPE_TEMP : return NVS_FILE_TEMP;
- case NV40_VP_SRC_REG_TYPE_INPUT: return NVS_FILE_ATTRIB;
- case NV40_VP_SRC_REG_TYPE_CONST: return NVS_FILE_CONST;
- default:
- return NVS_FILE_UNKNOWN;
- }
- }
-}
-
-static int
-NV40VPGetSourceID(nvsFunc * shader, int merged, int pos)
-{
- switch (shader->GetSourceFile(shader, merged, pos)) {
- case NVS_FILE_ATTRIB:
- switch ((shader->inst[1] & NV40_VP_INST_INPUT_SRC_MASK)
- >> NV40_VP_INST_INPUT_SRC_SHIFT) {
- case NV40_VP_INST_IN_POS: return NVS_FR_POSITION;
- case NV40_VP_INST_IN_WEIGHT: return NVS_FR_WEIGHT;
- case NV40_VP_INST_IN_NORMAL: return NVS_FR_NORMAL;
- case NV40_VP_INST_IN_COL0: return NVS_FR_COL0;
- case NV40_VP_INST_IN_COL1: return NVS_FR_COL1;
- case NV40_VP_INST_IN_FOGC: return NVS_FR_FOGCOORD;
- case NV40_VP_INST_IN_TC(0): return NVS_FR_TEXCOORD0;
- case NV40_VP_INST_IN_TC(1): return NVS_FR_TEXCOORD1;
- case NV40_VP_INST_IN_TC(2): return NVS_FR_TEXCOORD2;
- case NV40_VP_INST_IN_TC(3): return NVS_FR_TEXCOORD3;
- case NV40_VP_INST_IN_TC(4): return NVS_FR_TEXCOORD4;
- case NV40_VP_INST_IN_TC(5): return NVS_FR_TEXCOORD5;
- case NV40_VP_INST_IN_TC(6): return NVS_FR_TEXCOORD6;
- case NV40_VP_INST_IN_TC(7): return NVS_FR_TEXCOORD7;
- default:
- return -1;
- }
- break;
- case NVS_FILE_CONST:
- return ((shader->inst[1] & NV40_VP_INST_CONST_SRC_MASK)
- >> NV40_VP_INST_CONST_SRC_SHIFT);
- case NVS_FILE_TEMP:
- {
- unsigned int src;
-
- src = shader->GetSourceHW(shader, merged, pos);
- return ((src & NV40_VP_SRC_TEMP_SRC_MASK) >>
- NV40_VP_SRC_TEMP_SRC_SHIFT);
- }
- default:
- return -1;
- }
-}
-
-static int
-NV40VPGetSourceNegate(nvsFunc * shader, int merged, int pos)
-{
- unsigned int src;
-
- src = shader->GetSourceHW(shader, merged, pos);
-
- if (src == -1)
- return -1;
- return ((src & NV40_VP_SRC_NEGATE) ? 1 : 0);
-}
-
-static void
-NV40VPGetSourceSwizzle(nvsFunc * shader, int merged, int pos, nvsSwzComp *swz)
-{
- unsigned int src;
- int swzbits;
-
- src = shader->GetSourceHW(shader, merged, pos);
- swzbits = (src & NV40_VP_SRC_SWZ_ALL_MASK) >> NV40_VP_SRC_SWZ_ALL_SHIFT;
- NV20VPTXSwizzle(swzbits, swz);
-}
-
-static int
-NV40VPGetSourceIndexed(nvsFunc * shader, int merged, int pos)
-{
- switch (shader->GetSourceFile(shader, merged, pos)) {
- case NVS_FILE_ATTRIB:
- return ((shader->inst[0] & NV40_VP_INST_INDEX_INPUT) ? 1 : 0);
- case NVS_FILE_CONST:
- return ((shader->inst[3] & NV40_VP_INST_INDEX_CONST) ? 1 : 0);
- default:
- return 0;
- }
-}
-
-static nvsSwzComp
-NV40VPGetAddressRegSwizzle(nvsFunc * shader)
-{
- nvsSwzComp swz;
-
- swz = NV20VP_TX_SWIZZLE[(shader->inst[0] & NV40_VP_INST_ADDR_SWZ_MASK)
- >> NV40_VP_INST_ADDR_SWZ_SHIFT];
- return swz;
-}
-
-static int
-NV40VPSupportsConditional(nvsFunc * shader)
-{
- /*FIXME: Is this true of all ops? */
- return 1;
-}
-
-static int
-NV40VPGetConditionUpdate(nvsFunc * shader)
-{
- return ((shader->inst[0] & NV40_VP_INST_COND_UPDATE_ENABLE) ? 1 : 0);
-}
-
-static int
-NV40VPGetConditionTest(nvsFunc * shader)
-{
- int op;
-
- /* The condition test is unconditionally enabled on some
- * instructions. ie: the condition test bit does *NOT* have
- * to be set.
- *
- * FIXME: check other relevant ops for this situation.
- */
- op = shader->GetOpcodeHW(shader, 1);
- switch (op) {
- case NV40_VP_INST_OP_BRA:
- return 1;
- default:
- return ((shader->inst[0] & NV40_VP_INST_COND_TEST_ENABLE) ? 1 : 0);
- }
-}
-
-static nvsCond
-NV40VPGetCondition(nvsFunc * shader)
-{
- int cond;
-
- cond = ((shader->inst[0] & NV40_VP_INST_COND_MASK)
- >> NV40_VP_INST_COND_SHIFT);
-
- switch (cond) {
- case NV40_VP_INST_COND_FL: return NVS_COND_FL;
- case NV40_VP_INST_COND_LT: return NVS_COND_LT;
- case NV40_VP_INST_COND_EQ: return NVS_COND_EQ;
- case NV40_VP_INST_COND_LE: return NVS_COND_LE;
- case NV40_VP_INST_COND_GT: return NVS_COND_GT;
- case NV40_VP_INST_COND_NE: return NVS_COND_NE;
- case NV40_VP_INST_COND_GE: return NVS_COND_GE;
- case NV40_VP_INST_COND_TR: return NVS_COND_TR;
- default:
- return NVS_COND_UNKNOWN;
- }
-}
-
-static void
-NV40VPGetCondRegSwizzle(nvsFunc * shader, nvsSwzComp *swz)
-{
- int swzbits;
-
- swzbits = (shader->inst[0] & NV40_VP_INST_COND_SWZ_ALL_MASK)
- >> NV40_VP_INST_COND_SWZ_ALL_SHIFT;
- NV20VPTXSwizzle(swzbits, swz);
-}
-
-static int
-NV40VPGetCondRegID(nvsFunc * shader)
-{
- return ((shader->inst[0] & NV40_VP_INST_COND_REG_SELECT_1) ? 1 : 0);
-}
-
-static int
-NV40VPGetBranch(nvsFunc * shader)
-{
- int addr;
-
- addr = ((shader->inst[2] & NV40_VP_INST_IADDRH_MASK)
- >> NV40_VP_INST_IADDRH_SHIFT) << 3;
- addr |= ((shader->inst[3] & NV40_VP_INST_IADDRL_MASK)
- >> NV40_VP_INST_IADDRL_SHIFT);
- return addr;
-}
-
-void
-NV40VPInitShaderFuncs(nvsFunc * shader)
-{
- /* Inherit NV30 VP code, we share some of it */
- NV30VPInitShaderFuncs(shader);
-
- /* Limits */
- shader->MaxInst = 4096;
- shader->MaxAttrib = 16;
- shader->MaxTemp = 32;
- shader->MaxAddress = 2;
- shader->MaxConst = 256;
- shader->caps = SCAP_SRC_ABS;
-
- /* Add extra opcodes for NV40+ */
-// MOD_OPCODE(NVVP_TX_VOP, NV40_VP_INST_OP_TXWHAT, NVS_OP_TEX , 0, 4, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV40_VP_INST_OP_PUSHA, NVS_OP_PUSHA, 3, -1, -1);
- MOD_OPCODE(NVVP_TX_SOP, NV40_VP_INST_OP_POPA , NVS_OP_POPA , -1, -1, -1);
-
- shader->InitInstruction = NV40VPInitInstruction;
- shader->SupportsOpcode = NV40VPSupportsOpcode;
- shader->SetOpcode = NV40VPSetOpcode;
- shader->SetCCUpdate = NV40VPSetCCUpdate;
- shader->SetCondition = NV40VPSetCondition;
- shader->SetResult = NV40VPSetResult;
- shader->SetSource = NV40VPSetSource;
- shader->SetLastInst = NV40VPSetLastInst;
- shader->SetBranchTarget = NV40VPSetBranchTarget;
-
- shader->HasMergedInst = NV40VPHasMergedInst;
- shader->GetOpcodeHW = NV40VPGetOpcodeHW;
-
- shader->GetDestFile = NV40VPGetDestFile;
- shader->GetDestID = NV40VPGetDestID;
- shader->GetDestMask = NV40VPGetDestMask;
-
- shader->GetSourceHW = NV40VPGetSourceHW;
- shader->GetSourceFile = NV40VPGetSourceFile;
- shader->GetSourceID = NV40VPGetSourceID;
- shader->GetSourceNegate = NV40VPGetSourceNegate;
- shader->GetSourceSwizzle = NV40VPGetSourceSwizzle;
- shader->GetSourceIndexed = NV40VPGetSourceIndexed;
-
- shader->GetRelAddressSwizzle = NV40VPGetAddressRegSwizzle;
-
- shader->SupportsConditional = NV40VPSupportsConditional;
- shader->GetConditionUpdate = NV40VPGetConditionUpdate;
- shader->GetConditionTest = NV40VPGetConditionTest;
- shader->GetCondition = NV40VPGetCondition;
- shader->GetCondRegSwizzle = NV40VPGetCondRegSwizzle;
- shader->GetCondRegID = NV40VPGetCondRegID;
-
- shader->GetBranch = NV40VPGetBranch;
-}
diff --git a/src/mesa/drivers/dri/nouveau/nv50_state.c b/src/mesa/drivers/dri/nouveau/nv50_state.c
deleted file mode 100644
index a9236f093c..0000000000
--- a/src/mesa/drivers/dri/nouveau/nv50_state.c
+++ /dev/null
@@ -1,641 +0,0 @@
-/**************************************************************************
-
-Copyright 2006 Nouveau
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ERIC ANHOLT OR SILICON INTEGRATED SYSTEMS CORP BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-#include "nouveau_context.h"
-#include "nouveau_object.h"
-#include "nouveau_fifo.h"
-#include "nouveau_reg.h"
-#include "nouveau_state.h"
-
-#include "tnl/t_pipeline.h"
-
-#include "mtypes.h"
-#include "colormac.h"
-
-static void nv50AlphaFunc(GLcontext *ctx, GLenum func, GLfloat ref)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLubyte ubRef;
- CLAMPED_FLOAT_TO_UBYTE(ubRef, ref);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_REF, 2);
- OUT_RING_CACHE(ubRef);
- OUT_RING_CACHE(func);
-}
-
-static void nv50BlendColor(GLcontext *ctx, const GLfloat color[4])
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_BLEND_COLOR_R, 4);
- OUT_RING_CACHEf(color[0]);
- OUT_RING_CACHEf(color[1]);
- OUT_RING_CACHEf(color[2]);
- OUT_RING_CACHEf(color[3]);
-}
-
-static void nv50BlendEquationSeparate(GLcontext *ctx, GLenum modeRGB, GLenum modeA)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_RGB, 1);
- OUT_RING_CACHE(modeRGB);
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_BLEND_EQUATION_ALPHA, 1);
- OUT_RING_CACHE(modeA);
-}
-
-
-static void nv50BlendFuncSeparate(GLcontext *ctx, GLenum sfactorRGB, GLenum dfactorRGB,
- GLenum sfactorA, GLenum dfactorA)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_RGB, 2);
- OUT_RING_CACHE(sfactorRGB); /* FIXME, sometimes has |0x4000 */
- OUT_RING_CACHE(dfactorRGB); /* FIXME, sometimes has |0x4000 */
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_BLEND_FUNC_SRC_ALPHA, 2);
- OUT_RING_CACHE(sfactorA); /* FIXME, sometimes has |0x4000 */
- OUT_RING_CACHE(dfactorA); /* FIXME, sometimes has |0x4000 */
-}
-
-static void nv50Clear(GLcontext *ctx, GLbitfield mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- GLuint hw_bufs = 0;
-
- if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT))
- hw_bufs |= 0x3c;
- if (mask & (BUFFER_BIT_STENCIL))
- hw_bufs |= 0x02;
- if (mask & (BUFFER_BIT_DEPTH))
- hw_bufs |= 0x01;
-
- if (hw_bufs) {
- BEGIN_RING_SIZE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CLEAR_BUFFERS, 1);
- OUT_RING(hw_bufs);
- }
-}
-
-static void nv50ClearColor(GLcontext *ctx, const GLfloat color[4])
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CLEAR_COLOR_R, 4);
- OUT_RING_CACHEf(color[0]);
- OUT_RING_CACHEf(color[1]);
- OUT_RING_CACHEf(color[2]);
- OUT_RING_CACHEf(color[3]);
-}
-
-static void nv50ClearDepth(GLcontext *ctx, GLclampd d)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CLEAR_DEPTH, 1);
- OUT_RING_CACHEf(d);
-}
-
-/* we're don't support indexed buffers
- void (*ClearIndex)(GLcontext *ctx, GLuint index)
- */
-
-static void nv50ClearStencil(GLcontext *ctx, GLint s)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CLEAR_STENCIL, 1);
- OUT_RING_CACHE(s);
-}
-
-static void nv50ClipPlane(GLcontext *ctx, GLenum plane, const GLfloat *equation)
-{
- /* Only using shaders */
-}
-
-static void nv50ColorMask(GLcontext *ctx, GLboolean rmask, GLboolean gmask,
- GLboolean bmask, GLboolean amask )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- int i;
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_COLOR_MASK(0), 8);
- for (i=0; i<8; i++) {
- OUT_RING_CACHE(((amask && 0x01) << 12) | ((bmask && 0x01) << 8) | ((gmask && 0x01)<< 4) | ((rmask && 0x01) << 0));
- }
-}
-
-static void nv50ColorMaterial(GLcontext *ctx, GLenum face, GLenum mode)
-{
- // TODO I need love
-}
-
-static void nv50CullFace(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CULL_FACE, 1);
- OUT_RING_CACHE(mode);
-}
-
-static void nv50FrontFace(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_FRONT_FACE, 1);
- OUT_RING_CACHE(mode);
-}
-
-static void nv50DepthFunc(GLcontext *ctx, GLenum func)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_DEPTH_FUNC, 1);
- OUT_RING_CACHE(func);
-}
-
-static void nv50DepthMask(GLcontext *ctx, GLboolean flag)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_DEPTH_WRITE_ENABLE, 1);
- OUT_RING_CACHE(flag);
-}
-
-static void nv50DepthRange(GLcontext *ctx, GLclampd nearval, GLclampd farval)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_DEPTH_RANGE_NEAR, 2);
- OUT_RING_CACHEf(nearval);
- OUT_RING_CACHEf(farval);
-}
-
-/** Specify the current buffer for writing */
-//void (*DrawBuffer)( GLcontext *ctx, GLenum buffer );
-/** Specify the buffers for writing for fragment programs*/
-//void (*DrawBuffers)( GLcontext *ctx, GLsizei n, const GLenum *buffers );
-
-static void nv50Enable(GLcontext *ctx, GLenum cap, GLboolean state)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- switch(cap)
- {
- case GL_ALPHA_TEST:
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_ALPHA_FUNC_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_AUTO_NORMAL:
-// case GL_BLEND:
-// case GL_CLIP_PLANE0:
-// case GL_CLIP_PLANE1:
-// case GL_CLIP_PLANE2:
-// case GL_CLIP_PLANE3:
-// case GL_CLIP_PLANE4:
-// case GL_CLIP_PLANE5:
- case GL_COLOR_LOGIC_OP:
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LOGIC_OP_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_COLOR_MATERIAL:
-// case GL_COLOR_SUM_EXT:
-// case GL_COLOR_TABLE:
-// case GL_CONVOLUTION_1D:
-// case GL_CONVOLUTION_2D:
- case GL_CULL_FACE:
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_CULL_FACE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_DEPTH_TEST:
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_DEPTH_TEST_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_DITHER:
-// case GL_FOG:
-// case GL_HISTOGRAM:
-// case GL_INDEX_LOGIC_OP:
-// case GL_LIGHT0:
-// case GL_LIGHT1:
-// case GL_LIGHT2:
-// case GL_LIGHT3:
-// case GL_LIGHT4:
-// case GL_LIGHT5:
-// case GL_LIGHT6:
-// case GL_LIGHT7:
-// case GL_LIGHTING:
- case GL_LINE_SMOOTH:
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LINE_SMOOTH_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_LINE_STIPPLE:
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_MAP1_COLOR_4:
-// case GL_MAP1_INDEX:
-// case GL_MAP1_NORMAL:
-// case GL_MAP1_TEXTURE_COORD_1:
-// case GL_MAP1_TEXTURE_COORD_2:
-// case GL_MAP1_TEXTURE_COORD_3:
-// case GL_MAP1_TEXTURE_COORD_4:
-// case GL_MAP1_VERTEX_3:
-// case GL_MAP1_VERTEX_4:
-// case GL_MAP2_COLOR_4:
-// case GL_MAP2_INDEX:
-// case GL_MAP2_NORMAL:
-// case GL_MAP2_TEXTURE_COORD_1:
-// case GL_MAP2_TEXTURE_COORD_2:
-// case GL_MAP2_TEXTURE_COORD_3:
-// case GL_MAP2_TEXTURE_COORD_4:
-// case GL_MAP2_VERTEX_3:
-// case GL_MAP2_VERTEX_4:
-// case GL_MINMAX:
-// case GL_NORMALIZE:
-// case GL_POINT_SMOOTH:
- case GL_POLYGON_OFFSET_POINT:
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_POINT_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_OFFSET_LINE:
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_LINE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_OFFSET_FILL:
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FILL_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_SMOOTH:
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_SMOOTH_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
- case GL_POLYGON_STIPPLE:
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_POST_COLOR_MATRIX_COLOR_TABLE:
-// case GL_POST_CONVOLUTION_COLOR_TABLE:
-// case GL_RESCALE_NORMAL:
- case GL_SCISSOR_TEST:
- /* No enable bit, nv50Scissor will adjust to max range */
- ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
- ctx->Scissor.Width, ctx->Scissor.Height);
- break;
-// case GL_SEPARABLE_2D:
- case GL_STENCIL_TEST:
- // TODO BACK and FRONT ?
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_ENABLE, 1);
- OUT_RING_CACHE(state);
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_ENABLE, 1);
- OUT_RING_CACHE(state);
- break;
-// case GL_TEXTURE_GEN_Q:
-// case GL_TEXTURE_GEN_R:
-// case GL_TEXTURE_GEN_S:
-// case GL_TEXTURE_GEN_T:
-// case GL_TEXTURE_1D:
-// case GL_TEXTURE_2D:
-// case GL_TEXTURE_3D:
- }
-}
-
-static void nv50Fogfv(GLcontext *ctx, GLenum pname, const GLfloat *params)
-{
- /* Only using shaders */
-}
-
-static void nv50Hint(GLcontext *ctx, GLenum target, GLenum mode)
-{
- // TODO I need love (fog and line_smooth hints)
-}
-
-// void (*IndexMask)(GLcontext *ctx, GLuint mask);
-
-static void nv50Lightfv(GLcontext *ctx, GLenum light, GLenum pname, const GLfloat *params )
-{
- /* Only with shaders */
-}
-
-/** Set the lighting model parameters */
-void (*LightModelfv)(GLcontext *ctx, GLenum pname, const GLfloat *params);
-
-
-static void nv50LineStipple(GLcontext *ctx, GLint factor, GLushort pattern )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LINE_STIPPLE_PATTERN, 1);
- OUT_RING_CACHE((pattern << 8) | factor);
-}
-
-static void nv50LineWidth(GLcontext *ctx, GLfloat width)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LINE_WIDTH, 1);
- OUT_RING_CACHEf(width);
-}
-
-static void nv50LogicOpcode(GLcontext *ctx, GLenum opcode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_LOGIC_OP_OP, 1);
- OUT_RING_CACHE(opcode);
-}
-
-static void nv50PointParameterfv(GLcontext *ctx, GLenum pname, const GLfloat *params)
-{
- /*TODO: not sure what goes here. */
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
-}
-
-/** Specify the diameter of rasterized points */
-static void nv50PointSize(GLcontext *ctx, GLfloat size)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POINT_SIZE, 1);
- OUT_RING_CACHEf(size);
-}
-
-/** Select a polygon rasterization mode */
-static void nv50PolygonMode(GLcontext *ctx, GLenum face, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (face == GL_FRONT || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_FRONT, 1);
- OUT_RING_CACHE(mode);
- }
- if (face == GL_BACK || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_MODE_BACK, 1);
- OUT_RING_CACHE(mode);
- }
-}
-
-/** Set the scale and units used to calculate depth values */
-static void nv50PolygonOffset(GLcontext *ctx, GLfloat factor, GLfloat units)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_FACTOR, 1);
- OUT_RING_CACHEf(factor);
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_OFFSET_UNITS, 1);
- OUT_RING_CACHEf(units);
-}
-
-/** Set the polygon stippling pattern */
-static void nv50PolygonStipple(GLcontext *ctx, const GLubyte *mask )
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_POLYGON_STIPPLE_PATTERN(0), 32);
- OUT_RING_CACHEp(mask, 32);
-}
-
-/* Specifies the current buffer for reading */
-void (*ReadBuffer)( GLcontext *ctx, GLenum buffer );
-/** Set rasterization mode */
-void (*RenderMode)(GLcontext *ctx, GLenum mode );
-
-/** Define the scissor box */
-static void nv50Scissor(GLcontext *ctx, GLint x, GLint y, GLsizei w, GLsizei h)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- /* There's no scissor enable bit, so adjust the scissor to cover the
- * maximum draw buffer bounds
- */
- if (!ctx->Scissor.Enabled) {
- x = y = 0;
- w = h = 8191;
- } else {
- x += nmesa->drawX;
- y += nmesa->drawY;
- }
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_SCISSOR_WIDTH_XPOS, 2);
- OUT_RING_CACHE(((w) << 16) | x);
- OUT_RING_CACHE(((h) << 16) | y);
-}
-
-/** Select flat or smooth shading */
-static void nv50ShadeModel(GLcontext *ctx, GLenum mode)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_SHADE_MODEL, 1);
- OUT_RING_CACHE(mode);
-}
-
-/** OpenGL 2.0 two-sided StencilFunc */
-static void nv50StencilFuncSeparate(GLcontext *ctx, GLenum face, GLenum func,
- GLint ref, GLuint mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (face == GL_FRONT || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_FUNC, 1);
- OUT_RING_CACHE(func);
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_REF, 1);
- OUT_RING_CACHE(ref);
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_FUNC_MASK, 1);
- OUT_RING_CACHE(mask);
- }
- if (face == GL_BACK || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_FUNC, 2);
- OUT_RING_CACHE(func);
- OUT_RING_CACHE(ref);
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_FUNC_MASK, 1);
- OUT_RING_CACHE(mask);
- }
-}
-
-/** OpenGL 2.0 two-sided StencilMask */
-static void nv50StencilMaskSeparate(GLcontext *ctx, GLenum face, GLuint mask)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (face == GL_FRONT || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_MASK, 1);
- OUT_RING_CACHE(mask);
- }
- if (face == GL_BACK || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_MASK, 1);
- OUT_RING_CACHE(mask);
- }
-}
-
-/** OpenGL 2.0 two-sided StencilOp */
-static void nv50StencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail,
- GLenum zfail, GLenum zpass)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- if (face == GL_FRONT || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_FRONT_OP_FAIL, 3);
- OUT_RING_CACHE(fail);
- OUT_RING_CACHE(zfail);
- OUT_RING_CACHE(zpass);
- }
- if (face == GL_BACK || face == GL_FRONT_AND_BACK) {
- BEGIN_RING_CACHE(NvSub3D, NV50_TCL_PRIMITIVE_3D_STENCIL_BACK_OP_FAIL, 3);
- OUT_RING_CACHE(fail);
- OUT_RING_CACHE(zfail);
- OUT_RING_CACHE(zpass);
- }
-}
-
-/** Control the generation of texture coordinates */
-void (*TexGen)(GLcontext *ctx, GLenum coord, GLenum pname,
- const GLfloat *params);
-/** Set texture environment parameters */
-void (*TexEnv)(GLcontext *ctx, GLenum target, GLenum pname,
- const GLfloat *param);
-/** Set texture parameters */
-void (*TexParameter)(GLcontext *ctx, GLenum target,
- struct gl_texture_object *texObj,
- GLenum pname, const GLfloat *params);
-
-static void nv50TextureMatrix(GLcontext *ctx, GLuint unit, const GLmatrix *mat)
-{
- /* Only with shaders */
-}
-
-static void nv50WindowMoved(nouveauContextPtr nmesa)
-{
- GLcontext *ctx = nmesa->glCtx;
- GLfloat *v = nmesa->viewport.m;
- GLuint w = ctx->Viewport.Width;
- GLuint h = ctx->Viewport.Height;
- GLuint x = ctx->Viewport.X + nmesa->drawX;
- GLuint y = ctx->Viewport.Y + nmesa->drawY;
- int i;
-
- BEGIN_RING_CACHE(NvSub3D,
- NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(0), 2);
- OUT_RING_CACHE((8191 << 16) | 0);
- OUT_RING_CACHE((8191 << 16) | 0);
- for (i=1; i<8; i++) {
- BEGIN_RING_CACHE(NvSub3D,
- NV50_TCL_PRIMITIVE_3D_VIEWPORT_CLIP_HORIZ(i), 2);
- OUT_RING_CACHE(0);
- OUT_RING_CACHE(0);
- }
-
- ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
- ctx->Scissor.Width, ctx->Scissor.Height);
-}
-
-static GLboolean nv50InitCard(nouveauContextPtr nmesa)
-{
- int i,j;
-
- nouveauObjectOnSubchannel(nmesa, NvSub3D, Nv3D);
-
- BEGIN_RING_SIZE(NvSub3D, 0x1558, 1);
- OUT_RING(1);
-
- BEGIN_RING_SIZE(NvSub3D, NV50_TCL_PRIMITIVE_3D_SET_OBJECT_1(0), 8);
- for (i=0; i<8; i++) {
- OUT_RING(NvDmaFB);
- }
-
- BEGIN_RING_SIZE(NvSub3D, NV50_TCL_PRIMITIVE_3D_SET_OBJECT_0(0), 12);
- for (i=0; i<12; i++) {
- OUT_RING(NvDmaFB);
- }
-
- BEGIN_RING_SIZE(NvSub3D, 0x121c, 1);
- OUT_RING(1);
-
- for (i=0; i<8; i++) {
- BEGIN_RING_SIZE(NvSub3D, 0x0200 + (i*0x20), 5);
- for (j=0; j<5; j++) {
- OUT_RING(0);
- }
- }
-
- BEGIN_RING_SIZE(NvSub3D, 0x0fe0, 5);
- OUT_RING(0);
- OUT_RING(0);
- OUT_RING(0x16);
- OUT_RING(0);
- OUT_RING(0);
-
- return GL_FALSE;
-}
-
-static GLboolean
-nv50BindBuffers(nouveauContextPtr nmesa, int num_color,
- nouveau_renderbuffer_t **color, nouveau_renderbuffer_t *depth)
-{
- return GL_FALSE;
-}
-
-void nv50InitStateFuncs(GLcontext *ctx, struct dd_function_table *func)
-{
- nouveauContextPtr nmesa = NOUVEAU_CONTEXT(ctx);
-
- func->AlphaFunc = nv50AlphaFunc;
- func->BlendColor = nv50BlendColor;
- func->BlendEquationSeparate = nv50BlendEquationSeparate;
- func->BlendFuncSeparate = nv50BlendFuncSeparate;
- func->Clear = nv50Clear;
- func->ClearColor = nv50ClearColor;
- func->ClearDepth = nv50ClearDepth;
- func->ClearStencil = nv50ClearStencil;
- func->ClipPlane = nv50ClipPlane;
- func->ColorMask = nv50ColorMask;
- func->ColorMaterial = nv50ColorMaterial;
- func->CullFace = nv50CullFace;
- func->FrontFace = nv50FrontFace;
- func->DepthFunc = nv50DepthFunc;
- func->DepthMask = nv50DepthMask;
- func->DepthRange = nv50DepthRange;
- func->Enable = nv50Enable;
- func->Fogfv = nv50Fogfv;
- func->Hint = nv50Hint;
- func->Lightfv = nv50Lightfv;
-/* func->LightModelfv = nv50LightModelfv; */
- func->LineStipple = nv50LineStipple;
- func->LineWidth = nv50LineWidth;
- func->LogicOpcode = nv50LogicOpcode;
- func->PointParameterfv = nv50PointParameterfv;
- func->PointSize = nv50PointSize;
- func->PolygonMode = nv50PolygonMode;
- func->PolygonOffset = nv50PolygonOffset;
- func->PolygonStipple = nv50PolygonStipple;
-/* func->ReadBuffer = nv50ReadBuffer; */
-/* func->RenderMode = nv50RenderMode; */
- func->Scissor = nv50Scissor;
- func->ShadeModel = nv50ShadeModel;
- func->StencilFuncSeparate = nv50StencilFuncSeparate;
- func->StencilMaskSeparate = nv50StencilMaskSeparate;
- func->StencilOpSeparate = nv50StencilOpSeparate;
-/* func->TexGen = nv50TexGen; */
-/* func->TexParameter = nv50TexParameter; */
- func->TextureMatrix = nv50TextureMatrix;
-
- nmesa->hw_func.InitCard = nv50InitCard;
- nmesa->hw_func.BindBuffers = nv50BindBuffers;
- nmesa->hw_func.WindowMoved = nv50WindowMoved;
-}
--
cgit v1.2.3
From 5e600209f4908ece2ba8b7f880e1d7e950d2cfb4 Mon Sep 17 00:00:00 2001
From: Chris Rankin
Date: Mon, 14 Jul 2008 10:09:58 +0200
Subject: radeon: SetTexOffset support
This patch is a straightforward duplication of the R200 SetTexOffset code,
except that there is no big-endian tx_table[] array.
---
src/mesa/drivers/dri/radeon/radeon_context.h | 2 +
src/mesa/drivers/dri/radeon/radeon_screen.c | 12 ++++
src/mesa/drivers/dri/radeon/radeon_tex.h | 4 ++
src/mesa/drivers/dri/radeon/radeon_texmem.c | 2 +-
src/mesa/drivers/dri/radeon/radeon_texstate.c | 83 ++++++++++++++++++++-------
5 files changed, 82 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h
index 7c45c37b03..bc43fc5960 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -161,6 +161,8 @@ struct radeon_tex_obj {
drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
/* Six, for the cube faces */
+ GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
+
GLuint pp_txfilter; /* hardware register values */
GLuint pp_txformat;
GLuint pp_txoffset; /* Image location in texmem.
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 02152499c4..84b5c46bf1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -49,6 +49,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#if !RADEON_COMMON
#include "radeon_context.h"
#include "radeon_span.h"
+#include "radeon_tex.h"
#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
#include "r200_context.h"
#include "r200_ioctl.h"
@@ -321,6 +322,13 @@ radeonFillInModes( __DRIscreenPrivate *psp,
return (const __DRIconfig **) configs;
}
+#if !RADEON_COMMON
+static const __DRItexOffsetExtension radeonTexOffsetExtension = {
+ { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
+ radeonSetTexOffset,
+};
+#endif
+
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
static const __DRIallocateExtension r200AllocateExtension = {
{ __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
@@ -934,6 +942,10 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->extensions[i++] = &driMediaStreamCounterExtension.base;
}
+#if !RADEON_COMMON
+ screen->extensions[i++] = &radeonTexOffsetExtension.base;
+#endif
+
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
if (IS_R200_CLASS(screen))
screen->extensions[i++] = &r200AllocateExtension.base;
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.h b/src/mesa/drivers/dri/radeon/radeon_tex.h
index a806981ae6..0b955eda14 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex.h
+++ b/src/mesa/drivers/dri/radeon/radeon_tex.h
@@ -38,6 +38,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef __RADEON_TEX_H__
#define __RADEON_TEX_H__
+extern void radeonSetTexOffset(__DRIcontext *pDRICtx, GLint texname,
+ unsigned long long offset, GLint depth,
+ GLuint pitch);
+
extern void radeonUpdateTextureState( GLcontext *ctx );
extern int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t,
diff --git a/src/mesa/drivers/dri/radeon/radeon_texmem.c b/src/mesa/drivers/dri/radeon/radeon_texmem.c
index 20f25dd34b..0a3d745bd0 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texmem.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texmem.c
@@ -334,7 +334,7 @@ int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint fac
{
int numLevels;
- if ( !t || t->base.totalSize == 0 )
+ if ( !t || t->base.totalSize == 0 || t->image_override )
return 0;
if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
index 37bb749223..ecd375473b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -40,6 +40,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "context.h"
#include "macros.h"
#include "texformat.h"
+#include "texobj.h"
#include "enums.h"
#include "radeon_context.h"
@@ -84,7 +85,7 @@ tx_table[] =
_ALPHA_REV(RGBA8888),
_ALPHA(ARGB8888),
_ALPHA_REV(ARGB8888),
- _INVALID(RGB888),
+ [ MESA_FORMAT_RGB888 ] = { RADEON_TXFORMAT_ARGB8888, 0 },
_COLOR(RGB565),
_COLOR_REV(RGB565),
_ALPHA(ARGB4444),
@@ -134,18 +135,19 @@ static void radeonSetTexImages( radeonContextPtr rmesa,
/* Set the hardware texture format
*/
-
- t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK |
- RADEON_TXFORMAT_ALPHA_IN_MAP);
- t->pp_txfilter &= ~RADEON_YUV_TO_RGB;
-
- if ( VALID_FORMAT( baseImage->TexFormat->MesaFormat ) ) {
- t->pp_txformat |= tx_table[ baseImage->TexFormat->MesaFormat ].format;
- t->pp_txfilter |= tx_table[ baseImage->TexFormat->MesaFormat ].filter;
- }
- else {
- _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__);
- return;
+ if ( !t->image_override ) {
+ t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK |
+ RADEON_TXFORMAT_ALPHA_IN_MAP);
+ t->pp_txfilter &= ~RADEON_YUV_TO_RGB;
+
+ if ( VALID_FORMAT( baseImage->TexFormat->MesaFormat ) ) {
+ t->pp_txformat |= tx_table[ baseImage->TexFormat->MesaFormat ].format;
+ t->pp_txfilter |= tx_table[ baseImage->TexFormat->MesaFormat ].filter;
+ }
+ else {
+ _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__);
+ return;
+ }
}
texelBytes = baseImage->TexFormat->TexelBytes;
@@ -341,11 +343,13 @@ static void radeonSetTexImages( radeonContextPtr rmesa,
* requires 64-byte aligned pitches, and we may/may not need the
* blitter. NPOT only!
*/
- if (baseImage->IsCompressed)
- t->pp_txpitch = (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63);
- else
- t->pp_txpitch = ((tObj->Image[0][t->base.firstLevel]->Width * texelBytes) + 63) & ~(63);
- t->pp_txpitch -= 32;
+ if ( !t->image_override ) {
+ if (baseImage->IsCompressed)
+ t->pp_txpitch = (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63);
+ else
+ t->pp_txpitch = ((tObj->Image[0][t->base.firstLevel]->Width * texelBytes) + 63) & ~(63);
+ t->pp_txpitch -= 32;
+ }
t->dirty_state = TEX_ALL;
@@ -840,6 +844,44 @@ static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit )
return GL_TRUE;
}
+void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
+ unsigned long long offset, GLint depth, GLuint pitch)
+{
+ radeonContextPtr rmesa = pDRICtx->driverPrivate;
+ struct gl_texture_object *tObj =
+ _mesa_lookup_texture(rmesa->glCtx, texname);
+ radeonTexObjPtr t;
+
+ if (tObj == NULL)
+ return;
+
+ t = (radeonTexObjPtr) tObj->DriverData;
+
+ t->image_override = GL_TRUE;
+
+ if (!offset)
+ return;
+
+ t->pp_txoffset = offset;
+ t->pp_txpitch = pitch - 32;
+
+ switch (depth) {
+ case 32:
+ t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format;
+ t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter;
+ break;
+ case 24:
+ default:
+ t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format;
+ t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter;
+ break;
+ case 16:
+ t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format;
+ t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter;
+ break;
+ }
+}
+
#define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
RADEON_MIN_FILTER_MASK | \
RADEON_MAG_FILTER_MASK | \
@@ -1136,7 +1178,7 @@ static GLboolean enable_tex_2d( GLcontext *ctx, int unit )
RADEON_FIREVERTICES( rmesa );
radeonSetTexImages( rmesa, tObj );
radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
- if ( !t->base.memBlock )
+ if ( !t->base.memBlock && !t->image_override )
return GL_FALSE;
}
@@ -1203,7 +1245,8 @@ static GLboolean enable_tex_rect( GLcontext *ctx, int unit )
RADEON_FIREVERTICES( rmesa );
radeonSetTexImages( rmesa, tObj );
radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
- if ( !t->base.memBlock /* && !rmesa->prefer_gart_client_texturing FIXME */ ) {
+ if ( !t->base.memBlock &&
+ !t->image_override /* && !rmesa->prefer_gart_client_texturing FIXME */ ) {
fprintf(stderr, "%s: upload failed\n", __FUNCTION__);
return GL_FALSE;
}
--
cgit v1.2.3
From 62db707a3dd4bf821b189e937fa133009007a2b5 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Wed, 9 Jul 2008 15:58:31 -0600
Subject: mesa: check for null shader->Source
---
src/mesa/shader/slang/slang_compile.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/shader/slang/slang_compile.c b/src/mesa/shader/slang/slang_compile.c
index 75d1d7621d..e02331b973 100644
--- a/src/mesa/shader/slang/slang_compile.c
+++ b/src/mesa/shader/slang/slang_compile.c
@@ -2167,6 +2167,9 @@ _slang_compile(GLcontext *ctx, struct gl_shader *shader)
type = SLANG_UNIT_FRAGMENT_SHADER;
}
+ if (!shader->Source)
+ return GL_FALSE;
+
ctx->Shader.MemPool = _slang_new_mempool(1024*1024);
/* XXX temporary hack */
--
cgit v1.2.3
From a63b90712aad81d544eb8931493a6c4a7805f7fb Mon Sep 17 00:00:00 2001
From: Blair Sadewitz
Date: Mon, 14 Jul 2008 08:15:10 -0600
Subject: mesa: also check for __NetBSD__
---
src/mesa/main/execmem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/execmem.c b/src/mesa/main/execmem.c
index 0719d0051c..f95c31862a 100644
--- a/src/mesa/main/execmem.c
+++ b/src/mesa/main/execmem.c
@@ -36,7 +36,7 @@
-#if defined(__linux__) || defined(__OpenBSD__)
+#if defined(__linux__) || defined(__OpenBSD__) || defined(_NetBSD__)
/*
* Allocate a large block of memory which can hold code then dole it out
--
cgit v1.2.3
From f7eb0cec69f35c88baa82b8366b37964269feb92 Mon Sep 17 00:00:00 2001
From: Julien Cristau
Date: Sun, 13 Jul 2008 17:13:32 +0200
Subject: mklib: don't version symbols when using --exports
Use the default version instead of one based on the library SONAME
in the version script created by --exports.
---
bin/mklib | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bin/mklib b/bin/mklib
index 0dc3135d50..69e82420a1 100755
--- a/bin/mklib
+++ b/bin/mklib
@@ -271,7 +271,7 @@ case $ARCH in
if [ $EXPORTS ] ; then
#OPTS="${OPTS} -Xlinker --retain-symbols-file ${EXPORTS}"
# Make the 'exptmp' file for --version-script option
- echo "VERSION_${MAJOR}.${MINOR} {" > exptmp
+ echo "{" > exptmp
echo "global:" >> exptmp
sed 's/$/;/' ${EXPORTS} >> exptmp
echo "local:" >> exptmp
--
cgit v1.2.3
From 0a7df3794c35ed53c0243ec2b5e954debedfdfe6 Mon Sep 17 00:00:00 2001
From: Julien Cristau
Date: Sun, 13 Jul 2008 17:27:58 +0200
Subject: glu: only export public symbols
---
src/glu/sgi/Makefile | 1 +
src/glu/sgi/glu.exports | 59 +++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 60 insertions(+)
create mode 100644 src/glu/sgi/glu.exports
diff --git a/src/glu/sgi/Makefile b/src/glu/sgi/Makefile
index 63eca5cbe7..cd1354cc80 100644
--- a/src/glu/sgi/Makefile
+++ b/src/glu/sgi/Makefile
@@ -139,6 +139,7 @@ $(TOP)/$(LIB_DIR)/$(GLU_LIB_NAME): $(OBJECTS)
$(MKLIB) -o $(GLU_LIB) -linker '$(CXX)' -ldflags '$(LDFLAGS)' \
-major $(GLU_MAJOR) -minor $(GLU_MINOR) -patch $(GLU_TINY) \
-cplusplus $(MKLIB_OPTIONS) -install $(TOP)/$(LIB_DIR) \
+ -exports glu.exports \
$(GLU_LIB_DEPS) $(OBJECTS)
diff --git a/src/glu/sgi/glu.exports b/src/glu/sgi/glu.exports
new file mode 100644
index 0000000000..1d1b6da24f
--- /dev/null
+++ b/src/glu/sgi/glu.exports
@@ -0,0 +1,59 @@
+ gluBeginCurve
+ gluBeginPolygon
+ gluBeginSurface
+ gluBeginTrim
+ gluBuild1DMipmapLevels
+ gluBuild1DMipmaps
+ gluBuild2DMipmapLevels
+ gluBuild2DMipmaps
+ gluBuild3DMipmapLevels
+ gluBuild3DMipmaps
+ gluCheckExtension
+ gluCylinder
+ gluDeleteNurbsRenderer
+ gluDeleteQuadric
+ gluDeleteTess
+ gluDisk
+ gluEndCurve
+ gluEndPolygon
+ gluEndSurface
+ gluEndTrim
+ gluErrorString
+ gluGetNurbsProperty
+ gluGetString
+ gluGetTessProperty
+ gluLoadSamplingMatrices
+ gluLookAt
+ gluNewNurbsRenderer
+ gluNewQuadric
+ gluNewTess
+ gluNextContour
+ gluNurbsCallback
+ gluNurbsCallbackData
+ gluNurbsCallbackDataEXT
+ gluNurbsCurve
+ gluNurbsProperty
+ gluNurbsSurface
+ gluOrtho2D
+ gluPartialDisk
+ gluPerspective
+ gluPickMatrix
+ gluProject
+ gluPwlCurve
+ gluQuadricCallback
+ gluQuadricDrawStyle
+ gluQuadricNormals
+ gluQuadricOrientation
+ gluQuadricTexture
+ gluScaleImage
+ gluSphere
+ gluTessBeginContour
+ gluTessBeginPolygon
+ gluTessCallback
+ gluTessEndContour
+ gluTessEndPolygon
+ gluTessNormal
+ gluTessProperty
+ gluTessVertex
+ gluUnProject
+ gluUnProject4
--
cgit v1.2.3
From 4430597bf6944951136a16c39a7bc458dc926800 Mon Sep 17 00:00:00 2001
From: Guillaume Melquiond
Date: Mon, 14 Jul 2008 08:50:36 -0600
Subject: fix gltrace (bug 16691)
---
progs/tools/trace/gltrace_support.cc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/progs/tools/trace/gltrace_support.cc b/progs/tools/trace/gltrace_support.cc
index b188e73f29..0b76d3247d 100644
--- a/progs/tools/trace/gltrace_support.cc
+++ b/progs/tools/trace/gltrace_support.cc
@@ -20,6 +20,8 @@
*/
#include "gltrace_support.h"
+#include
+#include
#include
#include
#include
@@ -136,7 +138,7 @@ namespace gltrace {
struct timeval now;
struct tm t;
- static char *months[12] =
+ static char const *months[12] =
{
"Jan", "Feb", "Mar", "Apr", "May", "Jun",
"Jul", "Aug", "Sep", "Oct", "Nov", "Dec"
--
cgit v1.2.3
From c62cb6be6c0e67a94320e3f25c182b07b3e78056 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Mon, 14 Jul 2008 09:51:35 -0600
Subject: mesa: fix stencil state problem when GL_ATI_separate_stencil wasn't
enabled
In glStencilFunc/Op/Mask() set both the front and back-face state, unless
GL_EXT_stencil_two_side is enabled. Before, we only set the front+back state
if GL_ATI_separate_stencil was enabled.
Ultimately, we probably should remove GL_EXT_stencil_two_side since it's
incompatible with GL 2.x.
---
src/mesa/main/stencil.c | 96 +++++++++++++++++++++++++------------------------
1 file changed, 49 insertions(+), 47 deletions(-)
diff --git a/src/mesa/main/stencil.c b/src/mesa/main/stencil.c
index c1906197de..2a4c38b1f2 100644
--- a/src/mesa/main/stencil.c
+++ b/src/mesa/main/stencil.c
@@ -207,7 +207,23 @@ _mesa_StencilFunc( GLenum func, GLint ref, GLuint mask )
ref = CLAMP( ref, 0, stencilMax );
- if (ctx->Extensions.ATI_separate_stencil) {
+ if (ctx->Extensions.EXT_stencil_two_side) {
+ /* only set active face state */
+ const GLint face = ctx->Stencil.ActiveFace;
+ if (ctx->Stencil.Function[face] == func &&
+ ctx->Stencil.ValueMask[face] == mask &&
+ ctx->Stencil.Ref[face] == ref)
+ return;
+ FLUSH_VERTICES(ctx, _NEW_STENCIL);
+ ctx->Stencil.Function[face] = func;
+ ctx->Stencil.Ref[face] = ref;
+ ctx->Stencil.ValueMask[face] = mask;
+ if (ctx->Driver.StencilFuncSeparate) {
+ ctx->Driver.StencilFuncSeparate(ctx, face ? GL_BACK : GL_FRONT,
+ func, ref, mask);
+ }
+ }
+ else {
/* set both front and back state */
if (ctx->Stencil.Function[0] == func &&
ctx->Stencil.Function[1] == func &&
@@ -225,22 +241,6 @@ _mesa_StencilFunc( GLenum func, GLint ref, GLuint mask )
func, ref, mask);
}
}
- else {
- /* only set active face state */
- const GLint face = ctx->Stencil.ActiveFace;
- if (ctx->Stencil.Function[face] == func &&
- ctx->Stencil.ValueMask[face] == mask &&
- ctx->Stencil.Ref[face] == ref)
- return;
- FLUSH_VERTICES(ctx, _NEW_STENCIL);
- ctx->Stencil.Function[face] = func;
- ctx->Stencil.Ref[face] = ref;
- ctx->Stencil.ValueMask[face] = mask;
- if (ctx->Driver.StencilFuncSeparate) {
- ctx->Driver.StencilFuncSeparate(ctx, face ? GL_BACK : GL_FRONT,
- func, ref, mask);
- }
- }
}
@@ -261,26 +261,26 @@ _mesa_StencilMask( GLuint mask )
GET_CURRENT_CONTEXT(ctx);
ASSERT_OUTSIDE_BEGIN_END(ctx);
- if (ctx->Extensions.ATI_separate_stencil) {
- /* set both front and back state */
- if (ctx->Stencil.WriteMask[0] == mask &&
- ctx->Stencil.WriteMask[1] == mask)
+ if (ctx->Extensions.EXT_stencil_two_side) {
+ /* only set active face state */
+ const GLint face = ctx->Stencil.ActiveFace;
+ if (ctx->Stencil.WriteMask[face] == mask)
return;
FLUSH_VERTICES(ctx, _NEW_STENCIL);
- ctx->Stencil.WriteMask[0] = ctx->Stencil.WriteMask[1] = mask;
+ ctx->Stencil.WriteMask[face] = mask;
if (ctx->Driver.StencilMaskSeparate) {
- ctx->Driver.StencilMaskSeparate(ctx, GL_FRONT_AND_BACK, mask);
+ ctx->Driver.StencilMaskSeparate(ctx, face ? GL_BACK : GL_FRONT, mask);
}
}
else {
- /* only set active face state */
- const GLint face = ctx->Stencil.ActiveFace;
- if (ctx->Stencil.WriteMask[face] == mask)
+ /* set both front and back state */
+ if (ctx->Stencil.WriteMask[0] == mask &&
+ ctx->Stencil.WriteMask[1] == mask)
return;
FLUSH_VERTICES(ctx, _NEW_STENCIL);
- ctx->Stencil.WriteMask[face] = mask;
+ ctx->Stencil.WriteMask[0] = ctx->Stencil.WriteMask[1] = mask;
if (ctx->Driver.StencilMaskSeparate) {
- ctx->Driver.StencilMaskSeparate(ctx, face ? GL_BACK : GL_FRONT, mask);
+ ctx->Driver.StencilMaskSeparate(ctx, GL_FRONT_AND_BACK, mask);
}
}
}
@@ -319,7 +319,23 @@ _mesa_StencilOp(GLenum fail, GLenum zfail, GLenum zpass)
return;
}
- if (ctx->Extensions.ATI_separate_stencil) {
+ if (ctx->Extensions.EXT_stencil_two_side) {
+ /* only set active face state */
+ const GLint face = ctx->Stencil.ActiveFace;
+ if (ctx->Stencil.ZFailFunc[face] == zfail &&
+ ctx->Stencil.ZPassFunc[face] == zpass &&
+ ctx->Stencil.FailFunc[face] == fail)
+ return;
+ FLUSH_VERTICES(ctx, _NEW_STENCIL);
+ ctx->Stencil.ZFailFunc[face] = zfail;
+ ctx->Stencil.ZPassFunc[face] = zpass;
+ ctx->Stencil.FailFunc[face] = fail;
+ if (ctx->Driver.StencilOpSeparate) {
+ ctx->Driver.StencilOpSeparate(ctx, face ? GL_BACK : GL_FRONT,
+ fail, zfail, zpass);
+ }
+ }
+ else {
/* set both front and back state */
if (ctx->Stencil.ZFailFunc[0] == zfail &&
ctx->Stencil.ZFailFunc[1] == zfail &&
@@ -337,22 +353,6 @@ _mesa_StencilOp(GLenum fail, GLenum zfail, GLenum zpass)
fail, zfail, zpass);
}
}
- else {
- /* only set active face state */
- const GLint face = ctx->Stencil.ActiveFace;
- if (ctx->Stencil.ZFailFunc[face] == zfail &&
- ctx->Stencil.ZPassFunc[face] == zpass &&
- ctx->Stencil.FailFunc[face] == fail)
- return;
- FLUSH_VERTICES(ctx, _NEW_STENCIL);
- ctx->Stencil.ZFailFunc[face] = zfail;
- ctx->Stencil.ZPassFunc[face] = zpass;
- ctx->Stencil.FailFunc[face] = fail;
- if (ctx->Driver.StencilOpSeparate) {
- ctx->Driver.StencilOpSeparate(ctx, face ? GL_BACK : GL_FRONT,
- fail, zfail, zpass);
- }
- }
}
@@ -463,12 +463,14 @@ _mesa_StencilFuncSeparate(GLenum face, GLenum func, GLint ref, GLuint mask)
FLUSH_VERTICES(ctx, _NEW_STENCIL);
- if (face == GL_FRONT || face == GL_FRONT_AND_BACK) {
+ if (face != GL_BACK) {
+ /* set front */
ctx->Stencil.Function[0] = func;
ctx->Stencil.Ref[0] = ref;
ctx->Stencil.ValueMask[0] = mask;
}
- if (face == GL_BACK || face == GL_FRONT_AND_BACK) {
+ if (face != GL_FRONT) {
+ /* set back */
ctx->Stencil.Function[1] = func;
ctx->Stencil.Ref[1] = ref;
ctx->Stencil.ValueMask[1] = mask;
--
cgit v1.2.3
From 946abd9b5a55f999ef21f807769f5fb81b10a426 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Mon, 14 Jul 2008 13:55:37 -0700
Subject: i915: fix build after previous commit.
---
src/mesa/drivers/dri/i915/intel_pixel_read.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i915/intel_pixel_read.c b/src/mesa/drivers/dri/i915/intel_pixel_read.c
index 72e1f9ed28..d009590a4b 100644
--- a/src/mesa/drivers/dri/i915/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i915/intel_pixel_read.c
@@ -263,7 +263,7 @@ do_blit_readpixels(GLcontext * ctx,
intelEmitCopyBlit(intel,
src->cpp,
- src->pitch, src->buffer, 0, src->tiled,
+ src->pitch, src->buffer, 0, src->tiling,
rowLength, dst_buffer, dst_offset, GL_FALSE,
rect.x1,
rect.y1,
--
cgit v1.2.3
From f214a848abb7cefb3d2c0bb7d172d54deeb05308 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Mon, 14 Jul 2008 15:59:44 -0600
Subject: mesa: assemble main() after all other functions
Before, main() had to come after any functions it called.
---
src/mesa/shader/slang/slang_compile.c | 36 +++++++++++++++++++++--------------
1 file changed, 22 insertions(+), 14 deletions(-)
diff --git a/src/mesa/shader/slang/slang_compile.c b/src/mesa/shader/slang/slang_compile.c
index e02331b973..20bca01c46 100644
--- a/src/mesa/shader/slang/slang_compile.c
+++ b/src/mesa/shader/slang/slang_compile.c
@@ -1788,20 +1788,6 @@ parse_function(slang_parse_ctx * C, slang_output_ctx * O, int definition,
*parsed_func_ret = found_func;
}
- /* assemble the parsed function */
- {
- slang_assemble_ctx A;
-
- A.atoms = C->atoms;
- A.space.funcs = O->funs;
- A.space.structs = O->structs;
- A.space.vars = O->vars;
- A.program = O->program;
- A.vartable = O->vartable;
- A.log = C->L;
-
- _slang_codegen_function(&A, *parsed_func_ret);
- }
return GL_TRUE;
}
@@ -1844,6 +1830,7 @@ parse_code_unit(slang_parse_ctx * C, slang_code_unit * unit,
slang_output_ctx o;
GLboolean success;
GLuint maxRegs;
+ slang_function *mainFunc = NULL;
if (unit->type == SLANG_UNIT_FRAGMENT_BUILTIN ||
unit->type == SLANG_UNIT_FRAGMENT_SHADER) {
@@ -1871,6 +1858,11 @@ parse_code_unit(slang_parse_ctx * C, slang_code_unit * unit,
{
slang_function *func;
success = parse_function(C, &o, 1, &func);
+ if (success &&
+ _mesa_strcmp((char *) func->header.a_name, "main") == 0) {
+ /* found main() */
+ mainFunc = func;
+ }
}
break;
case EXTERNAL_DECLARATION:
@@ -1888,6 +1880,22 @@ parse_code_unit(slang_parse_ctx * C, slang_code_unit * unit,
}
C->I++;
+ if (mainFunc) {
+ /* assemble (generate code) for main() */
+ slang_assemble_ctx A;
+
+ A.atoms = C->atoms;
+ A.space.funcs = o.funs;
+ A.space.structs = o.structs;
+ A.space.vars = o.vars;
+ A.program = o.program;
+ A.vartable = o.vartable;
+ A.log = C->L;
+
+ _slang_codegen_function(&A, mainFunc);
+
+ }
+
_slang_pop_var_table(o.vartable);
_slang_delete_var_table(o.vartable);
--
cgit v1.2.3
From 67108adb48f3be927d7fb92ba8f6bd5c9d165222 Mon Sep 17 00:00:00 2001
From: Ian Romanick
Date: Tue, 15 Jul 2008 11:06:04 -0700
Subject: glx: Trivial clean-ups to __glXSetArrayEnable
---
src/glx/x11/indirect_vertex_array.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/glx/x11/indirect_vertex_array.c b/src/glx/x11/indirect_vertex_array.c
index 09d7244ba9..769c88f4d2 100644
--- a/src/glx/x11/indirect_vertex_array.c
+++ b/src/glx/x11/indirect_vertex_array.c
@@ -1601,17 +1601,21 @@ void __indirect_glClientActiveTextureARB(GLenum texture)
/**
+ * Modify the enable state for the selected array
*/
GLboolean
-__glXSetArrayEnable( __GLXattribute * state,
- GLenum key, unsigned index, GLboolean enable )
+__glXSetArrayEnable(__GLXattribute *state, GLenum key, unsigned index,
+ GLboolean enable)
{
struct array_state_vector * arrays = state->array_state;
struct array_state * a;
- if ( key == GL_TEXTURE_COORD_ARRAY ) {
- index = arrays->active_texture_unit;
+ /* Texture coordinate arrays have an implict index set when the
+ * application calls glClientActiveTexture.
+ */
+ if (key == GL_TEXTURE_COORD_ARRAY) {
+ index = arrays->active_texture_unit;
}
a = get_array_entry( arrays, key, index );
--
cgit v1.2.3
From 27e3f7f21d4405edbdbe98b5b62b1eaeec0d4aab Mon Sep 17 00:00:00 2001
From: Ian Romanick
Date: Tue, 15 Jul 2008 11:06:31 -0700
Subject: glx: Update my e-mail address. :)
---
src/glx/x11/indirect_vertex_array.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glx/x11/indirect_vertex_array.c b/src/glx/x11/indirect_vertex_array.c
index 769c88f4d2..15e3ece148 100644
--- a/src/glx/x11/indirect_vertex_array.c
+++ b/src/glx/x11/indirect_vertex_array.c
@@ -62,7 +62,7 @@
* "vbo", to support multiple texture coordinate arrays, generic attributes,
* and vertex buffer objects.
*
- * \author Ian Romanick
+ * \author Ian Romanick
*/
static void emit_DrawArrays_none( GLenum mode, GLint first, GLsizei count );
--
cgit v1.2.3
From a5f02368d2a9ab1f814eba2c997729c6c655fc5e Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Tue, 15 Jul 2008 13:14:18 -0700
Subject: intel-gem: Disable spantmp sse/mmx functions when tile swizzling.
Those functions rely on being able to treat the GET_PTR returned value as an
array indexed by x, but that's not the case for our tiling.
Bug #16387
---
src/mesa/drivers/dri/common/spantmp2.h | 16 +++++++++++++---
src/mesa/drivers/dri/intel/intel_span.c | 4 ++++
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/common/spantmp2.h b/src/mesa/drivers/dri/common/spantmp2.h
index 53f5f846a0..5e51112a20 100644
--- a/src/mesa/drivers/dri/common/spantmp2.h
+++ b/src/mesa/drivers/dri/common/spantmp2.h
@@ -48,6 +48,10 @@
#define HW_WRITE_CLIPLOOP() HW_CLIPLOOP()
#endif
+/* Whether GET_PTR(x, y) + cpp != GET_PTR(x+1, y) */
+#ifndef GET_PTR_NONLINEAR
+#define GET_PTR_NONLINEAR 0
+#endif
#if (SPANTMP_PIXEL_FMT == GL_RGB) && (SPANTMP_PIXEL_TYPE == GL_UNSIGNED_SHORT_5_6_5)
@@ -389,7 +393,8 @@ static void TAG(ReadRGBASpan)( GLcontext *ctx,
}
-#if defined(USE_MMX_ASM) && \
+#if !GET_PTR_NONLINEAR && \
+ defined(USE_MMX_ASM) && \
(((SPANTMP_PIXEL_FMT == GL_BGRA) && \
(SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV)) || \
((SPANTMP_PIXEL_FMT == GL_RGB) && \
@@ -440,7 +445,8 @@ static void TAG2(ReadRGBASpan,_MMX)( GLcontext *ctx,
#endif
-#if defined(USE_SSE_ASM) && \
+#if !GET_PTR_NONLINEAR && \
+ defined(USE_SSE_ASM) && \
(SPANTMP_PIXEL_FMT == GL_BGRA) && \
(SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV)
static void TAG2(ReadRGBASpan,_SSE2)( GLcontext *ctx,
@@ -474,7 +480,8 @@ static void TAG2(ReadRGBASpan,_SSE2)( GLcontext *ctx,
}
#endif
-#if defined(USE_SSE_ASM) && \
+#if !GET_PTR_NONLINEAR && \
+ defined(USE_SSE_ASM) && \
(SPANTMP_PIXEL_FMT == GL_BGRA) && \
(SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV)
static void TAG2(ReadRGBASpan,_SSE)( GLcontext *ctx,
@@ -567,6 +574,7 @@ static void TAG(InitPointers)(struct gl_renderbuffer *rb)
rb->PutMonoValues = TAG(WriteMonoRGBAPixels);
rb->GetValues = TAG(ReadRGBAPixels);
+#if !GET_PTR_NONLINEAR
#if defined(USE_SSE_ASM) && \
(SPANTMP_PIXEL_FMT == GL_BGRA) && \
(SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV)
@@ -596,6 +604,7 @@ static void TAG(InitPointers)(struct gl_renderbuffer *rb)
}
else
#endif
+#endif /* GET_PTR_NONLINEAR */
{
if (DBG) fprintf( stderr, "Using %s version of GetRow\n", "C" );
rb->GetRow = TAG(ReadRGBASpan);
@@ -611,5 +620,6 @@ static void TAG(InitPointers)(struct gl_renderbuffer *rb)
#undef TAG
#undef TAG2
#undef GET_PTR
+#undef GET_PTR_NONLINEAR
#undef SPANTMP_PIXEL_FMT
#undef SPANTMP_PIXEL_TYPE
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 3065d15e32..4f0855df0a 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -273,6 +273,7 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
#define TAG(x) intel_XTile_##x##_RGB565
#define TAG2(x,y) intel_XTile_##x##_RGB565##y
#define GET_PTR(X,Y) x_tile_swizzle(irb, intel, X, Y)
+#define GET_PTR_NONLINEAR 1
#include "spantmp2.h"
#define SPANTMP_PIXEL_FMT GL_RGB
@@ -281,6 +282,7 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
#define TAG(x) intel_YTile_##x##_RGB565
#define TAG2(x,y) intel_YTile_##x##_RGB565##y
#define GET_PTR(X,Y) y_tile_swizzle(irb, intel, X, Y)
+#define GET_PTR_NONLINEAR 1
#include "spantmp2.h"
/* 32 bit ARGB888 color tile spanline and pixel functions
@@ -292,6 +294,7 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
#define TAG(x) intel_XTile_##x##_ARGB8888
#define TAG2(x,y) intel_XTile_##x##_ARGB8888##y
#define GET_PTR(X,Y) x_tile_swizzle(irb, intel, X, Y)
+#define GET_PTR_NONLINEAR 1
#include "spantmp2.h"
#define SPANTMP_PIXEL_FMT GL_BGRA
@@ -300,6 +303,7 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
#define TAG(x) intel_YTile_##x##_ARGB8888
#define TAG2(x,y) intel_YTile_##x##_ARGB8888##y
#define GET_PTR(X,Y) y_tile_swizzle(irb, intel, X, Y)
+#define GET_PTR_NONLINEAR 1
#include "spantmp2.h"
#define LOCAL_DEPTH_VARS \
--
cgit v1.2.3
From 7d7d114e5963abf57ad50159524f830e430ec51d Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Tue, 15 Jul 2008 14:41:47 -0600
Subject: mesa: fix storage size computation in emit_arith()
---
src/mesa/shader/slang/slang_emit.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/shader/slang/slang_emit.c b/src/mesa/shader/slang/slang_emit.c
index 6d79380ab5..b087483b02 100644
--- a/src/mesa/shader/slang/slang_emit.c
+++ b/src/mesa/shader/slang/slang_emit.c
@@ -539,8 +539,9 @@ emit_arith(slang_emit_info *emitInfo, slang_ir_node *n)
/* result storage */
if (!n->Store) {
- /* XXX this size isn't correct, it depends on the operands */
- if (!alloc_temp_storage(emitInfo, n, info->ResultSize))
+ GLint size = n->Children[0]->Store
+ ? n->Children[0]->Store->Size : info->ResultSize;
+ if (!alloc_temp_storage(emitInfo, n, size))
return NULL;
}
storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
--
cgit v1.2.3
From 8c653f6e093624bfdef47ca83728465c86f338b7 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Tue, 15 Jul 2008 15:03:42 -0600
Subject: mesa: fix some broken bool, bvec2, bvec3, bvec4 constructors
---
src/mesa/shader/slang/library/slang_core.gc | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/mesa/shader/slang/library/slang_core.gc b/src/mesa/shader/slang/library/slang_core.gc
index 15a0792f43..82828a826c 100644
--- a/src/mesa/shader/slang/library/slang_core.gc
+++ b/src/mesa/shader/slang/library/slang_core.gc
@@ -113,13 +113,13 @@ int __constructor(const float f)
bool __constructor(const int i)
{
const float zero = 0.0;
- __asm vec4_seq __retVal, i, zero;
+ __asm vec4_sne __retVal, i, zero;
}
bool __constructor(const float f)
{
const float zero = 0.0;
- __asm vec4_seq __retVal, i, zero;
+ __asm vec4_sne __retVal, f, zero;
}
int __constructor(const bool b)
@@ -349,25 +349,25 @@ bvec2 __constructor(const bool b)
bvec2 __constructor(const float f)
{
const vec2 zero = vec2(0.0, 0.0);
- __asm vec4_seq __retVal.xy, f.xx, zero;
+ __asm vec4_sne __retVal.xy, f.xx, zero;
}
bvec2 __constructor(const int i)
{
const ivec2 zero = ivec2(0, 0);
- __asm vec4_seq __retVal.xy, i.xx, zero;
+ __asm vec4_sne __retVal.xy, i.xx, zero;
}
bvec2 __constructor(const vec2 v)
{
const vec2 zero = vec2(0.0, 0.0);
- __asm vec4_seq __retVal.xy, v, zero;
+ __asm vec4_sne __retVal.xy, v, zero;
}
bvec2 __constructor(const ivec2 v)
{
const ivec2 zero = ivec2(0, 0);
- __asm vec4_seq __retVal.xy, v, zero;
+ __asm vec4_sne __retVal.xy, v, zero;
}
@@ -389,25 +389,25 @@ bvec3 __constructor(const bool b)
bvec3 __constructor(const float f)
{
const vec3 zero = vec3(0.0, 0.0, 0.0);
- __asm vec4_seq __retVal.xyz, f.xxx, zero;
+ __asm vec4_sne __retVal.xyz, f.xxx, zero;
}
bvec3 __constructor(const int i)
{
const ivec3 zero = ivec3(0, 0, 0);
- __asm vec4_seq __retVal.xyz, i.xxx, zero;
+ __asm vec4_sne __retVal.xyz, i.xxx, zero;
}
bvec3 __constructor(const vec3 v)
{
const vec3 zero = vec3(0.0, 0.0, 0.0);
- __asm vec4_seq __retVal.xyz, v, zero;
+ __asm vec4_sne __retVal.xyz, v, zero;
}
bvec3 __constructor(const ivec3 v)
{
const ivec3 zero = ivec3(0, 0, 0);
- __asm vec4_seq __retVal.xyz, v, zero;
+ __asm vec4_sne __retVal.xyz, v, zero;
}
@@ -430,25 +430,25 @@ bvec4 __constructor(const bool b)
bvec4 __constructor(const float f)
{
const vec4 zero = vec4(0.0, 0.0, 0.0, 0.0);
- __asm vec4_seq __retVal, f.xxxx, zero;
+ __asm vec4_sne __retVal, f.xxxx, zero;
}
bvec4 __constructor(const int i)
{
const ivec4 zero = ivec4(0, 0, 0, 0);
- __asm vec4_seq __retVal, i.xxxx, zero;
+ __asm vec4_sne __retVal, i.xxxx, zero;
}
bvec4 __constructor(const vec4 v)
{
const vec4 zero = vec4(0.0, 0.0, 0.0, 0.0);
- __asm vec4_seq __retVal, v, zero;
+ __asm vec4_sne __retVal, v, zero;
}
bvec4 __constructor(const ivec4 v)
{
const ivec4 zero = ivec4(0, 0, 0, 0);
- __asm vec4_seq __retVal, v, zero;
+ __asm vec4_sne __retVal, v, zero;
}
--
cgit v1.2.3
From b0d173f4053ee006717fb1c04cf12d1d687052e6 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Tue, 15 Jul 2008 15:32:53 -0600
Subject: mesa: fix some broken /= operators
---
src/mesa/shader/slang/library/slang_core.gc | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/shader/slang/library/slang_core.gc b/src/mesa/shader/slang/library/slang_core.gc
index 82828a826c..0fd2b7e6b3 100644
--- a/src/mesa/shader/slang/library/slang_core.gc
+++ b/src/mesa/shader/slang/library/slang_core.gc
@@ -1226,6 +1226,7 @@ void __operator /= (inout int a, const int b)
float invB;
__asm float_rcp invB, b;
__asm vec4_multiply a, a, invB;
+ __asm float_to_int __retVal, a;
}
@@ -1518,7 +1519,7 @@ void __operator /= (inout vec2 v, const float a)
{
float invA;
__asm float_rcp invA, a;
- __asm vec4_multiply v.xy, v.xy, a.xx;
+ __asm vec4_multiply v.xy, v.xy, invA.xx;
}
@@ -1543,7 +1544,7 @@ void __operator /= (inout vec3 v, const float a)
{
float invA;
__asm float_rcp invA, a;
- __asm vec4_multiply v.xyz, v.xyz, a.xxx;
+ __asm vec4_multiply v.xyz, v.xyz, invA.xxx;
}
@@ -1568,7 +1569,7 @@ void __operator /= (inout vec4 v, const float a)
{
float invA;
__asm float_rcp invA, a;
- __asm vec4_multiply v, v, a.xxxx;
+ __asm vec4_multiply v, v, invA.xxxx;
}
--
cgit v1.2.3
From 716f70d7826c15cfaf09653ae525286f3eb59a07 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Tue, 15 Jul 2008 16:04:26 -0600
Subject: mesa: add missing IR_LOG2 case
---
src/mesa/shader/slang/slang_emit.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/shader/slang/slang_emit.c b/src/mesa/shader/slang/slang_emit.c
index b087483b02..f025b15de9 100644
--- a/src/mesa/shader/slang/slang_emit.c
+++ b/src/mesa/shader/slang/slang_emit.c
@@ -1658,6 +1658,9 @@ emit(slang_emit_info *emitInfo, slang_ir_node *n)
case IR_COS:
case IR_DDX:
case IR_DDY:
+ case IR_EXP:
+ case IR_EXP2:
+ case IR_LOG2:
case IR_NOISE1:
case IR_NOISE2:
case IR_NOISE3:
@@ -1678,8 +1681,6 @@ emit(slang_emit_info *emitInfo, slang_ir_node *n)
case IR_SLE:
case IR_SLT:
case IR_POW:
- case IR_EXP:
- case IR_EXP2:
/* trinary operators */
case IR_LRP:
return emit_arith(emitInfo, n);
--
cgit v1.2.3
From 461e17880650500cdbb35133ba12c3b809b778f1 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Tue, 15 Jul 2008 16:55:23 -0600
Subject: mesa: regenerated file
---
src/mesa/shader/slang/library/slang_core_gc.h | 758 +++++++++++++-------------
1 file changed, 380 insertions(+), 378 deletions(-)
diff --git a/src/mesa/shader/slang/library/slang_core_gc.h b/src/mesa/shader/slang/library/slang_core_gc.h
index 5213b693b3..09ceb69edd 100644
--- a/src/mesa/shader/slang/library/slang_core_gc.h
+++ b/src/mesa/shader/slang/library/slang_core_gc.h
@@ -4,9 +4,9 @@
3,1,0,5,1,1,1,0,9,102,0,0,0,1,4,102,108,111,97,116,95,116,111,95,105,110,116,0,18,95,95,114,101,
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0,0,0,1,0,5,1,1,1,0,1,98,0,0,0,1,9,18,95,95,114,101,116,86,97,108,0,18,98,0,20,0,0,1,0,9,1,1,1,0,1,
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@@ -60,28 +60,28 @@
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@@ -89,15 +89,15 @@
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@@ -364,7 +364,8 @@
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@@ -450,372 +451,373 @@
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+77,69,83,65,0,18,109,0,16,8,48,0,57,0,0,0,9,58,112,114,105,110,116,77,69,83,65,0,18,109,0,16,10,49,
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+105,110,116,77,69,83,65,0,1,1,0,15,109,0,0,0,1,9,58,112,114,105,110,116,77,69,83,65,0,18,109,0,16,
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+105,110,116,77,69,83,65,0,18,109,0,16,10,50,0,57,0,0,0,9,58,112,114,105,110,116,77,69,83,65,0,18,
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+114,105,110,116,77,69,83,65,0,1,1,0,19,101,0,0,0,1,4,105,110,116,95,112,114,105,110,116,0,18,101,0,
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+116,95,112,114,105,110,116,0,18,101,0,0,0,0,0
--
cgit v1.2.3
From 546c7fb221e2d0b7e56fb390f6e911a5f515328c Mon Sep 17 00:00:00 2001
From: Blair Sadewitz
Date: Tue, 15 Jul 2008 17:05:28 -0600
Subject: mesa: extra braces
---
src/mesa/drivers/x11/xm_tri.c | 192 +++++++++++++++++++++---------------------
1 file changed, 96 insertions(+), 96 deletions(-)
diff --git a/src/mesa/drivers/x11/xm_tri.c b/src/mesa/drivers/x11/xm_tri.c
index c87a293756..77fceec194 100644
--- a/src/mesa/drivers/x11/xm_tri.c
+++ b/src/mesa/drivers/x11/xm_tri.c
@@ -66,7 +66,7 @@
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLint x = span.x, y = YFLIP(xrb, span.y); \
GLuint i; \
for (i = 0; i < span.end; i++, x++) { \
@@ -82,7 +82,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -102,7 +102,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
const DEPTH_TYPE z = FixedToDepth(span.z); \
@@ -117,7 +117,7 @@
span.blue += span.blueStep; \
span.alpha += span.alphaStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -137,7 +137,7 @@
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
const DEPTH_TYPE z = FixedToDepth(span.z); \
@@ -152,7 +152,7 @@
span.blue += span.blueStep; \
span.alpha += span.alphaStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -171,7 +171,7 @@
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
const DEPTH_TYPE z = FixedToDepth(span.z); \
@@ -184,7 +184,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -202,7 +202,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
const DEPTH_TYPE z = FixedToDepth(span.z); \
@@ -217,7 +217,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -232,7 +232,7 @@
#define SETUP_CODE \
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -248,7 +248,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -265,7 +265,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
const DEPTH_TYPE z = FixedToDepth(span.z); \
@@ -278,7 +278,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -296,7 +296,7 @@
#define SETUP_CODE \
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -310,7 +310,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -327,7 +327,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
XDITHER_SETUP(y); \
@@ -342,7 +342,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -357,7 +357,7 @@
#define SETUP_CODE \
GET_XRB(xrb); \
XMesaImage *img = xrb->ximage;
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
XDITHER_SETUP(y); \
@@ -373,7 +373,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -390,7 +390,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
LOOKUP_SETUP; \
for (i = 0; i < span.end; i++) { \
@@ -404,7 +404,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -422,7 +422,7 @@
#define SETUP_CODE \
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -436,7 +436,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -453,7 +453,7 @@
XMesaImage *img = xrb->ximage; \
unsigned long pixel; \
PACK_TRUECOLOR(pixel, v2->color[0], v2->color[1], v2->color[2]);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -463,7 +463,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -481,7 +481,7 @@
GET_XRB(xrb); \
GLuint p = PACK_8A8B8G8R( v2->color[0], v2->color[1],\
v2->color[2], v2->color[3]);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
const DEPTH_TYPE z = FixedToDepth(span.z); \
@@ -490,7 +490,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -508,7 +508,7 @@
GET_XRB(xrb); \
GLuint p = PACK_8A8R8G8B(v2->color[0], v2->color[1], \
v2->color[2], v2->color[3]);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
const DEPTH_TYPE z = FixedToDepth(span.z); \
@@ -517,7 +517,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -534,7 +534,7 @@
#define SETUP_CODE \
GET_XRB(xrb); \
GLuint p = PACK_8R8G8B( v2->color[0], v2->color[1], v2->color[2] );
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
DEPTH_TYPE z = FixedToDepth(span.z); \
@@ -543,7 +543,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -561,7 +561,7 @@
#define SETUP_CODE \
GET_XRB(xrb); \
const GLubyte *color = v2->color;
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
const DEPTH_TYPE z = FixedToDepth(span.z); \
@@ -573,7 +573,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -588,7 +588,7 @@
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb); \
XMesaImage *img = xrb->ximage;
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -601,7 +601,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -618,7 +618,7 @@
#define SETUP_CODE \
GET_XRB(xrb); \
GLushort p = PACK_5R6G5B( v2->color[0], v2->color[1], v2->color[2] );
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
const DEPTH_TYPE z = FixedToDepth(span.z); \
@@ -627,7 +627,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -645,7 +645,7 @@
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb); \
const GLubyte *color = v2->color;
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -656,7 +656,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -673,7 +673,7 @@
#define SETUP_CODE \
GET_XRB(xrb); \
FLAT_DITHER_SETUP( v2->color[0], v2->color[1], v2->color[2] );
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
FLAT_DITHER_ROW_SETUP(YFLIP(xrb, y)); \
@@ -684,7 +684,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -699,7 +699,7 @@
GET_XRB(xrb); \
XMesaImage *img = xrb->ximage; \
FLAT_DITHER_SETUP( v2->color[0], v2->color[1], v2->color[2] );
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
FLAT_DITHER_ROW_SETUP(y); \
@@ -711,7 +711,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -731,7 +731,7 @@
GLubyte r = v2->color[0]; \
GLubyte g = v2->color[1]; \
GLubyte b = v2->color[2];
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -741,7 +741,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -762,7 +762,7 @@
GLubyte g = v2->color[1]; \
GLubyte b = v2->color[2]; \
GLubyte p = LOOKUP(r,g,b);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
const DEPTH_TYPE z = FixedToDepth(span.z); \
@@ -771,7 +771,7 @@
zRow[i] = z; \
} \
span.z += span.zStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -785,7 +785,7 @@
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb); \
XMesaImage *img = xrb->ximage;
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -796,7 +796,7 @@
span.red += span.redStep; \
span.green += span.greenStep; \
span.blue += span.blueStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -812,7 +812,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
pRow[i] = PACK_8A8B8G8R(FixedToInt(span.red), \
@@ -822,7 +822,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.alpha += span.alphaStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -838,7 +838,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
pRow[i] = PACK_8A8R8G8B(FixedToInt(span.red), \
@@ -848,7 +848,7 @@
span.green += span.greenStep; \
span.blue += span.blueStep; \
span.alpha += span.alphaStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -863,7 +863,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
pRow[i] = PACK_8R8G8B(FixedToInt(span.red), \
@@ -871,7 +871,7 @@
span.red += span.redStep; \
span.green += span.greenStep; \
span.blue += span.blueStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -886,7 +886,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
PIXEL_TYPE *pixel = pRow; \
for (i = 0; i < span.end; i++, pixel++) { \
@@ -896,7 +896,7 @@
span.red += span.redStep; \
span.green += span.greenStep; \
span.blue += span.blueStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -910,7 +910,7 @@
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb); \
XMesaImage *img = xrb->ximage;
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -921,7 +921,7 @@
span.red += span.redStep; \
span.green += span.greenStep; \
span.blue += span.blueStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -936,7 +936,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
pRow[i] = (PIXEL_TYPE) PACK_5R6G5B(FixedToInt(span.red), \
@@ -944,7 +944,7 @@
span.red += span.redStep; \
span.green += span.greenStep; \
span.blue += span.blueStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -960,7 +960,7 @@
#define SETUP_CODE \
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -969,7 +969,7 @@
span.red += span.redStep; \
span.green += span.greenStep; \
span.blue += span.blueStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -984,7 +984,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
XDITHER_SETUP(y); \
@@ -994,7 +994,7 @@
span.red += span.redStep; \
span.green += span.greenStep; \
span.blue += span.blueStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1007,7 +1007,7 @@
#define SETUP_CODE \
GET_XRB(xrb); \
XMesaImage *img = xrb->ximage;
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
XDITHER_SETUP(y); \
@@ -1018,7 +1018,7 @@
span.red += span.redStep; \
span.green += span.greenStep; \
span.blue += span.blueStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1033,7 +1033,7 @@
#define BYTES_PER_ROW (xrb->ximage->bytes_per_line)
#define SETUP_CODE \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
LOOKUP_SETUP; \
for (i = 0; i < span.end; i++) { \
@@ -1042,7 +1042,7 @@
span.red += span.redStep; \
span.green += span.greenStep; \
span.blue += span.blueStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1058,7 +1058,7 @@
#define SETUP_CODE \
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -1067,7 +1067,7 @@
span.red += span.redStep; \
span.green += span.greenStep; \
span.blue += span.blueStep; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1082,12 +1082,12 @@
XMesaImage *img = xrb->ximage; \
unsigned long pixel; \
PACK_TRUECOLOR(pixel, v2->color[0], v2->color[1], v2->color[2]);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
XMesaPutPixel(img, x, y, pixel); \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1103,11 +1103,11 @@
GET_XRB(xrb); \
unsigned long p = PACK_8B8G8R( v2->color[0], \
v2->color[1], v2->color[2] );
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
pRow[i] = (PIXEL_TYPE) p; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1123,11 +1123,11 @@
GET_XRB(xrb); \
unsigned long p = PACK_8R8G8B( v2->color[0], \
v2->color[1], v2->color[2] );
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
pRow[i] = (PIXEL_TYPE) p; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1143,11 +1143,11 @@
GET_XRB(xrb); \
unsigned long p = PACK_8R8G8B( v2->color[0], \
v2->color[1], v2->color[2] );
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
pRow[i] = (PIXEL_TYPE) p; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1162,14 +1162,14 @@
#define SETUP_CODE \
GET_XRB(xrb); \
const GLubyte *color = v2->color;
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
PIXEL_TYPE *pixel = pRow; \
for (i = 0; i < span.end; i++, pixel++) { \
pixel->r = color[RCOMP]; \
pixel->g = color[GCOMP]; \
pixel->b = color[BCOMP]; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1182,7 +1182,7 @@
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb); \
XMesaImage *img = xrb->ximage;
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
@@ -1190,7 +1190,7 @@
PACK_TRUEDITHER(p, x, y, v2->color[0], \
v2->color[1], v2->color[2] ); \
XMesaPutPixel(img, x, y, p); \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1206,11 +1206,11 @@
GET_XRB(xrb); \
unsigned long p = PACK_5R6G5B( v2->color[0], \
v2->color[1], v2->color[2] );
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
pRow[i] = (PIXEL_TYPE) p; \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1226,13 +1226,13 @@
XMesaContext xmesa = XMESA_CONTEXT(ctx); \
GET_XRB(xrb); \
const GLubyte *color = v2->color;
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
PACK_TRUEDITHER(pRow[i], x, y, color[RCOMP], \
color[GCOMP], color[BCOMP]); \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1247,13 +1247,13 @@
#define SETUP_CODE \
GET_XRB(xrb); \
FLAT_DITHER_SETUP( v2->color[0], v2->color[1], v2->color[2] );
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
FLAT_DITHER_ROW_SETUP(YFLIP(xrb, y)); \
for (i = 0; i < span.end; i++, x++) { \
pRow[i] = (PIXEL_TYPE) FLAT_DITHER(x); \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1266,14 +1266,14 @@
GET_XRB(xrb); \
XMesaImage *img = xrb->ximage; \
FLAT_DITHER_SETUP( v2->color[0], v2->color[1], v2->color[2] );
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
FLAT_DITHER_ROW_SETUP(y); \
for (i = 0; i < span.end; i++, x++) { \
unsigned long p = FLAT_DITHER(x); \
XMesaPutPixel(img, x, y, p ); \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1291,12 +1291,12 @@
GLubyte r = v2->color[0]; \
GLubyte g = v2->color[1]; \
GLubyte b = v2->color[2];
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
GLint x = span.x, y = YFLIP(xrb, span.y); \
for (i = 0; i < span.end; i++, x++) { \
pRow[i] = (PIXEL_TYPE) DITHER_HPCR(x, y, r, g, b); \
- }
+ } }
#include "swrast/s_tritemp.h"
@@ -1315,11 +1315,11 @@
GLubyte g = v2->color[1]; \
GLubyte b = v2->color[2]; \
GLubyte p = LOOKUP(r,g,b);
-#define RENDER_SPAN( span ) \
+#define RENDER_SPAN( span ) { \
GLuint i; \
for (i = 0; i < span.end; i++) { \
pRow[i] = (PIXEL_TYPE) p; \
- }
+ } }
#include "swrast/s_tritemp.h"
--
cgit v1.2.3
From e6218d071db46cbf98486f97b238cccf78c4aefa Mon Sep 17 00:00:00 2001
From: Blair Sadewitz
Date: Tue, 15 Jul 2008 17:06:17 -0600
Subject: mesa: check for __INTERIX to typedef uintptr_t
---
src/mesa/main/glheader.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/main/glheader.h b/src/mesa/main/glheader.h
index 533e4a2bd8..6f3b2089c3 100644
--- a/src/mesa/main/glheader.h
+++ b/src/mesa/main/glheader.h
@@ -72,6 +72,12 @@
# if _MSC_VER == 1200
typedef UINT_PTR uintptr_t;
# endif
+#elif defined(__INTERIX)
+/* Interix 3.x has a gcc that shadows this. */
+# ifndef _UINTPTR_T_DEFINED
+ typedef unsigned long uintptr_t;
+# define _UINTPTR_T_DEFINED
+# endif
#else
# include
#endif
--
cgit v1.2.3
From 4c6dcbf091b5a83c2b75e8b42299497b1b187109 Mon Sep 17 00:00:00 2001
From: Blair Sadewitz
Date: Tue, 15 Jul 2008 17:11:33 -0600
Subject: mesa: added test for __NetBSD__
---
src/mesa/x86/assyntax.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/x86/assyntax.h b/src/mesa/x86/assyntax.h
index 8eb47e41a1..524944f73a 100644
--- a/src/mesa/x86/assyntax.h
+++ b/src/mesa/x86/assyntax.h
@@ -985,7 +985,8 @@ SECTION _DATA public align=16 class=DATA use32 flat
#if defined(Lynx) || (defined(SYSV) || defined(SVR4)) \
|| (defined(__linux__) || defined(__OS2ELF__)) && defined(__ELF__) \
- || defined(__FreeBSD__) && __FreeBSD__ >= 3
+ || (defined(__FreeBSD__) && __FreeBSD__ >= 3) \
+ || (defined(__NetBSD__) && defined(__ELF__))
#define GLNAME(a) a
#else
#define GLNAME(a) CONCAT(_, a)
--
cgit v1.2.3
From ece7183ff1b1bba1ae8e41b143e2ccbc38376dc3 Mon Sep 17 00:00:00 2001
From: Blair Sadewitz
Date: Tue, 15 Jul 2008 17:12:23 -0600
Subject: mesa: added test for __NetBSD__
---
src/mesa/x86/common_x86.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/mesa/x86/common_x86.c b/src/mesa/x86/common_x86.c
index 0b2af0a370..d93241a977 100644
--- a/src/mesa/x86/common_x86.c
+++ b/src/mesa/x86/common_x86.c
@@ -113,6 +113,14 @@ static void check_os_sse_support( void )
if (ret || !enabled)
_mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
}
+#elif defined (__NetBSD__)
+ {
+ int ret, enabled;
+ size_t len = sizeof(enabled);
+ ret = sysctlbyname("machdep.sse", &enabled, &len, (void *)NULL, 0);
+ if (ret || !enabled)
+ _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
+ }
#elif defined(WIN32)
LPTOP_LEVEL_EXCEPTION_FILTER oldFilter;
--
cgit v1.2.3
From b7c54945fe212811d9749b623f582569522bc440 Mon Sep 17 00:00:00 2001
From: Blair Sadewitz
Date: Tue, 15 Jul 2008 17:21:43 -0600
Subject: additional preprocessor checks for stdint.h, inttypes.h, etc
The patches to glext.h and glxext.h have been sent to Khronos/bugzilla.
---
include/GL/glext.h | 8 ++++----
include/GL/glxext.h | 6 +++---
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/GL/glext.h b/include/GL/glext.h
index 2b22714c30..f7377bb310 100644
--- a/include/GL/glext.h
+++ b/include/GL/glext.h
@@ -3419,16 +3419,16 @@ typedef unsigned short GLhalfNV;
#endif
#ifndef GLEXT_64_TYPES_DEFINED
-/* This code block is duplicated in glext.h, so must be protected */
+/* This code block is duplicated in glxext.h, so must be protected */
#define GLEXT_64_TYPES_DEFINED
/* Define int32_t, int64_t, and uint64_t types for UST/MSC */
/* (as used in the GL_EXT_timer_query extension). */
#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
#include
-#elif defined(__sun__)
+#elif defined(__sun__) || defined(__digital__)
#include
#if defined(__STDC__)
-#if defined(__arch64__)
+#if defined(__arch64__) || defined(_LP64)
typedef long int int64_t;
typedef unsigned long int uint64_t;
#else
@@ -3436,7 +3436,7 @@ typedef long long int int64_t;
typedef unsigned long long int uint64_t;
#endif /* __arch64__ */
#endif /* __STDC__ */
-#elif defined( __VMS )
+#elif defined( __VMS ) || defined(__sgi)
#include
#elif defined(__SCO__) || defined(__USLC__)
#include
diff --git a/include/GL/glxext.h b/include/GL/glxext.h
index 0f66df6277..aedc311cbf 100644
--- a/include/GL/glxext.h
+++ b/include/GL/glxext.h
@@ -380,7 +380,7 @@ typedef struct {
#endif
#ifndef GLEXT_64_TYPES_DEFINED
-/* This code block is duplicated in glxext.h, so must be protected */
+/* This code block is duplicated in glext.h, so must be protected */
#define GLEXT_64_TYPES_DEFINED
/* Define int32_t, int64_t, and uint64_t types for UST/MSC */
/* (as used in the GLX_OML_sync_control extension). */
@@ -389,7 +389,7 @@ typedef struct {
#elif defined(__sun__) || defined(__digital__)
#include
#if defined(__STDC__)
-#if defined(__arch64__)
+#if defined(__arch64__) || defined(_LP64)
typedef long int int64_t;
typedef unsigned long int uint64_t;
#else
@@ -397,7 +397,7 @@ typedef long long int int64_t;
typedef unsigned long long int uint64_t;
#endif /* __arch64__ */
#endif /* __STDC__ */
-#elif defined( __VMS )
+#elif defined( __VMS ) || defined(__sgi)
#include
#elif defined(__SCO__) || defined(__USLC__)
#include
--
cgit v1.2.3
From 7d13dded5c581c2a1741252b1ef04f7ae4a9627b Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Wed, 16 Jul 2008 10:23:28 -0600
Subject: mesa: add GL_POLYGON_OFFSET_POINT/LINE/FILL queries, remove
GL_TEXTURE_ENV_COLOR, GL_TEXTURE_ENV_MODE
Issues found by Bob Ellison.
---
src/mesa/main/get.c | 63 +++++++++++++++++++++---------------------------
src/mesa/main/get_gen.py | 9 +++----
2 files changed, 30 insertions(+), 42 deletions(-)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 9d8f2002c9..b36154afff 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -753,6 +753,15 @@ _mesa_GetBooleanv( GLenum pname, GLboolean *params )
case GL_POLYGON_OFFSET_UNITS:
params[0] = FLOAT_TO_BOOLEAN(ctx->Polygon.OffsetUnits );
break;
+ case GL_POLYGON_OFFSET_POINT:
+ params[0] = ctx->Polygon.OffsetPoint;
+ break;
+ case GL_POLYGON_OFFSET_LINE:
+ params[0] = ctx->Polygon.OffsetLine;
+ break;
+ case GL_POLYGON_OFFSET_FILL:
+ params[0] = ctx->Polygon.OffsetFill;
+ break;
case GL_POLYGON_SMOOTH:
params[0] = ctx->Polygon.SmoothFlag;
break;
@@ -895,18 +904,6 @@ _mesa_GetBooleanv( GLenum pname, GLboolean *params )
CHECK_EXT1(MESA_texture_array, "GetBooleanv");
params[0] = INT_TO_BOOLEAN(ctx->Texture.Unit[ctx->Texture.CurrentUnit].Current2DArray->Name);
break;
- case GL_TEXTURE_ENV_COLOR:
- {
- const GLfloat *color = ctx->Texture.Unit[ctx->Texture.CurrentUnit].EnvColor;
- params[0] = FLOAT_TO_BOOLEAN(color[0]);
- params[1] = FLOAT_TO_BOOLEAN(color[1]);
- params[2] = FLOAT_TO_BOOLEAN(color[2]);
- params[3] = FLOAT_TO_BOOLEAN(color[3]);
- }
- break;
- case GL_TEXTURE_ENV_MODE:
- params[0] = ENUM_TO_BOOLEAN(ctx->Texture.Unit[ctx->Texture.CurrentUnit].EnvMode);
- break;
case GL_TEXTURE_GEN_S:
params[0] = ((ctx->Texture.Unit[ctx->Texture.CurrentUnit].TexGenEnabled & S_BIT) ? 1 : 0);
break;
@@ -2604,6 +2601,15 @@ _mesa_GetFloatv( GLenum pname, GLfloat *params )
case GL_POLYGON_OFFSET_UNITS:
params[0] = ctx->Polygon.OffsetUnits ;
break;
+ case GL_POLYGON_OFFSET_POINT:
+ params[0] = BOOLEAN_TO_FLOAT(ctx->Polygon.OffsetPoint);
+ break;
+ case GL_POLYGON_OFFSET_LINE:
+ params[0] = BOOLEAN_TO_FLOAT(ctx->Polygon.OffsetLine);
+ break;
+ case GL_POLYGON_OFFSET_FILL:
+ params[0] = BOOLEAN_TO_FLOAT(ctx->Polygon.OffsetFill);
+ break;
case GL_POLYGON_SMOOTH:
params[0] = BOOLEAN_TO_FLOAT(ctx->Polygon.SmoothFlag);
break;
@@ -2746,18 +2752,6 @@ _mesa_GetFloatv( GLenum pname, GLfloat *params )
CHECK_EXT1(MESA_texture_array, "GetFloatv");
params[0] = (GLfloat)(ctx->Texture.Unit[ctx->Texture.CurrentUnit].Current2DArray->Name);
break;
- case GL_TEXTURE_ENV_COLOR:
- {
- const GLfloat *color = ctx->Texture.Unit[ctx->Texture.CurrentUnit].EnvColor;
- params[0] = color[0];
- params[1] = color[1];
- params[2] = color[2];
- params[3] = color[3];
- }
- break;
- case GL_TEXTURE_ENV_MODE:
- params[0] = ENUM_TO_FLOAT(ctx->Texture.Unit[ctx->Texture.CurrentUnit].EnvMode);
- break;
case GL_TEXTURE_GEN_S:
params[0] = BOOLEAN_TO_FLOAT(((ctx->Texture.Unit[ctx->Texture.CurrentUnit].TexGenEnabled & S_BIT) ? 1 : 0));
break;
@@ -4455,6 +4449,15 @@ _mesa_GetIntegerv( GLenum pname, GLint *params )
case GL_POLYGON_OFFSET_UNITS:
params[0] = IROUND(ctx->Polygon.OffsetUnits );
break;
+ case GL_POLYGON_OFFSET_POINT:
+ params[0] = BOOLEAN_TO_INT(ctx->Polygon.OffsetPoint);
+ break;
+ case GL_POLYGON_OFFSET_LINE:
+ params[0] = BOOLEAN_TO_INT(ctx->Polygon.OffsetLine);
+ break;
+ case GL_POLYGON_OFFSET_FILL:
+ params[0] = BOOLEAN_TO_INT(ctx->Polygon.OffsetFill);
+ break;
case GL_POLYGON_SMOOTH:
params[0] = BOOLEAN_TO_INT(ctx->Polygon.SmoothFlag);
break;
@@ -4597,18 +4600,6 @@ _mesa_GetIntegerv( GLenum pname, GLint *params )
CHECK_EXT1(MESA_texture_array, "GetIntegerv");
params[0] = ctx->Texture.Unit[ctx->Texture.CurrentUnit].Current2DArray->Name;
break;
- case GL_TEXTURE_ENV_COLOR:
- {
- const GLfloat *color = ctx->Texture.Unit[ctx->Texture.CurrentUnit].EnvColor;
- params[0] = FLOAT_TO_INT(color[0]);
- params[1] = FLOAT_TO_INT(color[1]);
- params[2] = FLOAT_TO_INT(color[2]);
- params[3] = FLOAT_TO_INT(color[3]);
- }
- break;
- case GL_TEXTURE_ENV_MODE:
- params[0] = ENUM_TO_INT(ctx->Texture.Unit[ctx->Texture.CurrentUnit].EnvMode);
- break;
case GL_TEXTURE_GEN_S:
params[0] = BOOLEAN_TO_INT(((ctx->Texture.Unit[ctx->Texture.CurrentUnit].TexGenEnabled & S_BIT) ? 1 : 0));
break;
diff --git a/src/mesa/main/get_gen.py b/src/mesa/main/get_gen.py
index 819a7cc5d7..1c0279c026 100644
--- a/src/mesa/main/get_gen.py
+++ b/src/mesa/main/get_gen.py
@@ -372,6 +372,9 @@ StateVars = [
( "GL_POLYGON_OFFSET_BIAS_EXT", GLfloat, ["ctx->Polygon.OffsetUnits"], "", None ),
( "GL_POLYGON_OFFSET_FACTOR", GLfloat, ["ctx->Polygon.OffsetFactor "], "", None ),
( "GL_POLYGON_OFFSET_UNITS", GLfloat, ["ctx->Polygon.OffsetUnits "], "", None ),
+ ( "GL_POLYGON_OFFSET_POINT", GLboolean, ["ctx->Polygon.OffsetPoint"], "", None ),
+ ( "GL_POLYGON_OFFSET_LINE", GLboolean, ["ctx->Polygon.OffsetLine"], "", None ),
+ ( "GL_POLYGON_OFFSET_FILL", GLboolean, ["ctx->Polygon.OffsetFill"], "", None ),
( "GL_POLYGON_SMOOTH", GLboolean, ["ctx->Polygon.SmoothFlag"], "", None ),
( "GL_POLYGON_SMOOTH_HINT", GLenum, ["ctx->Hint.PolygonSmooth"], "", None ),
( "GL_POLYGON_STIPPLE", GLboolean, ["ctx->Polygon.StippleFlag"], "", None ),
@@ -437,12 +440,6 @@ StateVars = [
["ctx->Texture.Unit[ctx->Texture.CurrentUnit].Current1DArray->Name"], "", ["MESA_texture_array"] ),
( "GL_TEXTURE_BINDING_2D_ARRAY_EXT", GLint,
["ctx->Texture.Unit[ctx->Texture.CurrentUnit].Current2DArray->Name"], "", ["MESA_texture_array"] ),
- ( "GL_TEXTURE_ENV_COLOR", GLfloatN,
- ["color[0]", "color[1]", "color[2]", "color[3]"],
- "const GLfloat *color = ctx->Texture.Unit[ctx->Texture.CurrentUnit].EnvColor;",
- None ),
- ( "GL_TEXTURE_ENV_MODE", GLenum,
- ["ctx->Texture.Unit[ctx->Texture.CurrentUnit].EnvMode"], "", None ),
( "GL_TEXTURE_GEN_S", GLboolean,
["((ctx->Texture.Unit[ctx->Texture.CurrentUnit].TexGenEnabled & S_BIT) ? 1 : 0)"], "", None ),
( "GL_TEXTURE_GEN_T", GLboolean,
--
cgit v1.2.3
From 442c195c4afce2509130a718c44a69a5b009979e Mon Sep 17 00:00:00 2001
From: Ian Romanick
Date: Wed, 9 Jul 2008 08:57:02 -0700
Subject: Remove redundant initalization of MaxTextureUnits
---
src/mesa/drivers/dri/i965/brw_context.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 33f1bba085..efe850b4d3 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -134,7 +134,6 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
ctx->Const.Max3DTextureLevels = 9;
ctx->Const.MaxCubeTextureLevels = 12;
ctx->Const.MaxTextureRectSize = (1<<11);
- ctx->Const.MaxTextureUnits = BRW_MAX_TEX_UNIT;
/* ctx->Const.MaxNativeVertexProgramTemps = 32; */
--
cgit v1.2.3
From 29cb89d0c2cb17e2fa38563fc93794a6ebd75cf9 Mon Sep 17 00:00:00 2001
From: Ian Romanick
Date: Wed, 16 Jul 2008 10:37:49 -0700
Subject: intel: Clean-up ARB_texture_env_crossbar
Enable support for ARB_texture_env_crossbar in the master extension
list instead of in every single device-specific list.
---
src/mesa/drivers/dri/i915/i830_context.c | 8 --------
src/mesa/drivers/dri/i915/i915_context.c | 1 -
src/mesa/drivers/dri/intel/intel_context.c | 7 +++----
3 files changed, 3 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c
index acb7178a5c..16c8a8d24f 100644
--- a/src/mesa/drivers/dri/i915/i830_context.c
+++ b/src/mesa/drivers/dri/i915/i830_context.c
@@ -42,12 +42,6 @@
* Mesa's Driver Functions
***************************************/
-static const struct dri_extension i830_extensions[] = {
- {"GL_ARB_texture_env_crossbar", NULL},
- {NULL, NULL}
-};
-
-
static void
i830InitDriverFunctions(struct dd_function_table *functions)
{
@@ -105,8 +99,6 @@ i830CreateContext(const __GLcontextModes * mesaVis,
intel->verts = TNL_CONTEXT(ctx)->clipspace.vertex_buf;
- driInitExtensions(ctx, i830_extensions, GL_FALSE);
-
i830InitState(i830);
i830InitMetaFuncs(i830);
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index 532b402db7..bd9f1d5f5d 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -54,7 +54,6 @@ static const struct dri_extension i915_extensions[] = {
{"GL_ARB_depth_texture", NULL},
{"GL_ARB_fragment_program", NULL},
{"GL_ARB_shadow", NULL},
- {"GL_ARB_texture_env_crossbar", NULL},
{"GL_ARB_texture_non_power_of_two", NULL},
{"GL_EXT_shadow_funcs", NULL},
/* ARB extn won't work if not enabled */
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index f8ea6461c9..f9f0c7444e 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -194,9 +194,8 @@ intelGetString(GLcontext * ctx, GLenum name)
/**
* Extension strings exported by the intel driver.
*
- * \note
- * It appears that ARB_texture_env_crossbar has "disappeared" compared to the
- * old i830-specific driver.
+ * Extensions supported by all chips supported by i830_dri, i915_dri, or
+ * i965_dri.
*/
static const struct dri_extension card_extensions[] = {
{"GL_ARB_multisample", GL_ARB_multisample_functions},
@@ -208,6 +207,7 @@ static const struct dri_extension card_extensions[] = {
{"GL_ARB_texture_cube_map", NULL},
{"GL_ARB_texture_env_add", NULL},
{"GL_ARB_texture_env_combine", NULL},
+ {"GL_ARB_texture_env_crossbar", NULL},
{"GL_ARB_texture_env_dot3", NULL},
{"GL_ARB_texture_mirrored_repeat", NULL},
{"GL_ARB_texture_non_power_of_two", NULL },
@@ -264,7 +264,6 @@ static const struct dri_extension brw_extensions[] = {
{ "GL_EXT_shadow_funcs", NULL },
/* ARB extn won't work if not enabled */
{ "GL_SGIX_depth_texture", NULL },
- { "GL_ARB_texture_env_crossbar", NULL },
{ "GL_EXT_texture_sRGB", NULL},
{ NULL, NULL }
};
--
cgit v1.2.3
From 082cde143b880d4c87f11680b3a40a8e09c44367 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Wed, 16 Jul 2008 14:47:21 -0600
Subject: mesa: fix copy&paste errors in degrees() functions
---
src/mesa/shader/slang/library/slang_common_builtin.gc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/shader/slang/library/slang_common_builtin.gc b/src/mesa/shader/slang/library/slang_common_builtin.gc
index f741c657e4..b095a6434b 100644
--- a/src/mesa/shader/slang/library/slang_common_builtin.gc
+++ b/src/mesa/shader/slang/library/slang_common_builtin.gc
@@ -203,19 +203,19 @@ float degrees(const float rad)
vec2 degrees(const vec2 rad)
{
- const float c = 3.1415926 / 180.0;
+ const float c = 180.0 / 3.1415926;
__asm vec4_multiply __retVal.xy, rad.xy, c.xx;
}
vec3 degrees(const vec3 rad)
{
- const float c = 3.1415926 / 180.0;
+ const float c = 180.0 / 3.1415926;
__asm vec4_multiply __retVal.xyz, rad.xyz, c.xxx;
}
vec4 degrees(const vec4 rad)
{
- const float c = 3.1415926 / 180.0;
+ const float c = 180.0 / 3.1415926;
__asm vec4_multiply __retVal, rad, c.xxxx;
}
--
cgit v1.2.3
From 33a25729e8d7563ac181303c6a8f69f35155f059 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Wed, 16 Jul 2008 16:04:43 -0600
Subject: mesa: fix temp re-use bug in emit_arith()
---
src/mesa/shader/slang/slang_emit.c | 28 ++++++++++++++++++++--------
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/src/mesa/shader/slang/slang_emit.c b/src/mesa/shader/slang/slang_emit.c
index f025b15de9..c997c11a7d 100644
--- a/src/mesa/shader/slang/slang_emit.c
+++ b/src/mesa/shader/slang/slang_emit.c
@@ -469,6 +469,12 @@ emit_arith(slang_emit_info *emitInfo, slang_ir_node *n)
const slang_ir_info *info = _slang_ir_info(n->Opcode);
char *srcAnnot[3], *dstAnnot;
GLuint i;
+ slang_ir_node *temps[3];
+
+ /* we'll save pointers to nodes/storage to free in temps[] until
+ * the very end.
+ */
+ temps[0] = temps[1] = temps[2] = NULL;
assert(info);
assert(info->InstOpcode != OPCODE_NOP);
@@ -489,9 +495,9 @@ emit_arith(slang_emit_info *emitInfo, slang_ir_node *n)
storage_to_src_reg(&inst->SrcReg[0], n->Children[0]->Children[0]->Store);
storage_to_src_reg(&inst->SrcReg[1], n->Children[0]->Children[1]->Store);
storage_to_src_reg(&inst->SrcReg[2], n->Children[1]->Store);
- free_temp_storage(emitInfo->vt, n->Children[0]->Children[0]);
- free_temp_storage(emitInfo->vt, n->Children[0]->Children[1]);
- free_temp_storage(emitInfo->vt, n->Children[1]);
+ temps[0] = n->Children[0]->Children[0];
+ temps[1] = n->Children[0]->Children[1];
+ temps[2] = n->Children[1];
}
else if (info->NumParams == 2 &&
n->Opcode == IR_ADD && n->Children[1]->Opcode == IR_MUL) {
@@ -505,9 +511,9 @@ emit_arith(slang_emit_info *emitInfo, slang_ir_node *n)
storage_to_src_reg(&inst->SrcReg[0], n->Children[1]->Children[0]->Store);
storage_to_src_reg(&inst->SrcReg[1], n->Children[1]->Children[1]->Store);
storage_to_src_reg(&inst->SrcReg[2], n->Children[0]->Store);
- free_temp_storage(emitInfo->vt, n->Children[1]->Children[0]);
- free_temp_storage(emitInfo->vt, n->Children[1]->Children[1]);
- free_temp_storage(emitInfo->vt, n->Children[0]);
+ temps[0] = n->Children[1]->Children[0];
+ temps[1] = n->Children[1]->Children[1];
+ temps[2] = n->Children[0];
}
else
#endif
@@ -532,9 +538,9 @@ emit_arith(slang_emit_info *emitInfo, slang_ir_node *n)
for (i = 0; i < info->NumParams; i++)
srcAnnot[i] = storage_annotation(n->Children[i], emitInfo->prog);
- /* free temps */
+ /* record (potential) temps to free */
for (i = 0; i < info->NumParams; i++)
- free_temp_storage(emitInfo->vt, n->Children[i]);
+ temps[i] = n->Children[i];
}
/* result storage */
@@ -544,6 +550,7 @@ emit_arith(slang_emit_info *emitInfo, slang_ir_node *n)
if (!alloc_temp_storage(emitInfo, n, size))
return NULL;
}
+
storage_to_dst_reg(&inst->DstReg, n->Store, n->Writemask);
dstAnnot = storage_annotation(n, emitInfo->prog);
@@ -551,6 +558,11 @@ emit_arith(slang_emit_info *emitInfo, slang_ir_node *n)
inst->Comment = instruction_annotation(inst->Opcode, dstAnnot, srcAnnot[0],
srcAnnot[1], srcAnnot[2]);
+ /* really free temps now */
+ for (i = 0; i < 3; i++)
+ if (temps[i])
+ free_temp_storage(emitInfo->vt, temps[i]);
+
/*_mesa_print_instruction(inst);*/
return inst;
}
--
cgit v1.2.3
From 0138435643d77478f5e06ef4572e704e0230163b Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Wed, 16 Jul 2008 16:27:14 -0600
Subject: mesa: regenerated file
---
.../shader/slang/library/slang_common_builtin_gc.h | 36 +++++++++++-----------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/src/mesa/shader/slang/library/slang_common_builtin_gc.h b/src/mesa/shader/slang/library/slang_common_builtin_gc.h
index 260a768de6..a8698712c5 100644
--- a/src/mesa/shader/slang/library/slang_common_builtin_gc.h
+++ b/src/mesa/shader/slang/library/slang_common_builtin_gc.h
@@ -116,25 +116,25 @@
101,103,114,101,101,115,0,1,1,0,9,114,97,100,0,0,0,1,3,2,1,9,1,99,0,2,17,49,56,48,0,48,0,0,17,51,0,
49,52,49,53,57,50,54,0,0,49,0,0,4,118,101,99,52,95,109,117,108,116,105,112,108,121,0,18,95,95,114,
101,116,86,97,108,0,59,120,0,0,18,114,97,100,0,0,18,99,0,0,0,0,1,0,10,0,100,101,103,114,101,101,
-115,0,1,1,0,10,114,97,100,0,0,0,1,3,2,1,9,1,99,0,2,17,51,0,49,52,49,53,57,50,54,0,0,17,49,56,48,0,
-48,0,0,49,0,0,4,118,101,99,52,95,109,117,108,116,105,112,108,121,0,18,95,95,114,101,116,86,97,108,
+115,0,1,1,0,10,114,97,100,0,0,0,1,3,2,1,9,1,99,0,2,17,49,56,48,0,48,0,0,17,51,0,49,52,49,53,57,50,
+54,0,0,49,0,0,4,118,101,99,52,95,109,117,108,116,105,112,108,121,0,18,95,95,114,101,116,86,97,108,
0,59,120,121,0,0,18,114,97,100,0,59,120,121,0,0,18,99,0,59,120,120,0,0,0,0,1,0,11,0,100,101,103,
-114,101,101,115,0,1,1,0,11,114,97,100,0,0,0,1,3,2,1,9,1,99,0,2,17,51,0,49,52,49,53,57,50,54,0,0,17,
-49,56,48,0,48,0,0,49,0,0,4,118,101,99,52,95,109,117,108,116,105,112,108,121,0,18,95,95,114,101,116,
-86,97,108,0,59,120,121,122,0,0,18,114,97,100,0,59,120,121,122,0,0,18,99,0,59,120,120,120,0,0,0,0,1,
-0,12,0,100,101,103,114,101,101,115,0,1,1,0,12,114,97,100,0,0,0,1,3,2,1,9,1,99,0,2,17,51,0,49,52,49,
-53,57,50,54,0,0,17,49,56,48,0,48,0,0,49,0,0,4,118,101,99,52,95,109,117,108,116,105,112,108,121,0,
-18,95,95,114,101,116,86,97,108,0,0,18,114,97,100,0,0,18,99,0,59,120,120,120,120,0,0,0,0,1,0,9,0,
-115,105,110,0,1,1,0,9,114,97,100,105,97,110,115,0,0,0,1,4,102,108,111,97,116,95,115,105,110,101,0,
-18,95,95,114,101,116,86,97,108,0,59,120,0,0,18,114,97,100,105,97,110,115,0,0,0,0,1,0,10,0,115,105,
-110,0,1,1,0,10,114,97,100,105,97,110,115,0,0,0,1,4,102,108,111,97,116,95,115,105,110,101,0,18,95,
-95,114,101,116,86,97,108,0,59,120,0,0,18,114,97,100,105,97,110,115,0,59,120,0,0,0,4,102,108,111,97,
-116,95,115,105,110,101,0,18,95,95,114,101,116,86,97,108,0,59,121,0,0,18,114,97,100,105,97,110,115,
-0,59,121,0,0,0,0,1,0,11,0,115,105,110,0,1,1,0,11,114,97,100,105,97,110,115,0,0,0,1,4,102,108,111,
-97,116,95,115,105,110,101,0,18,95,95,114,101,116,86,97,108,0,59,120,0,0,18,114,97,100,105,97,110,
-115,0,59,120,0,0,0,4,102,108,111,97,116,95,115,105,110,101,0,18,95,95,114,101,116,86,97,108,0,59,
-121,0,0,18,114,97,100,105,97,110,115,0,59,121,0,0,0,4,102,108,111,97,116,95,115,105,110,101,0,18,
-95,95,114,101,116,86,97,108,0,59,122,0,0,18,114,97,100,105,97,110,115,0,59,122,0,0,0,0,1,0,12,0,
+114,101,101,115,0,1,1,0,11,114,97,100,0,0,0,1,3,2,1,9,1,99,0,2,17,49,56,48,0,48,0,0,17,51,0,49,52,
+49,53,57,50,54,0,0,49,0,0,4,118,101,99,52,95,109,117,108,116,105,112,108,121,0,18,95,95,114,101,
+116,86,97,108,0,59,120,121,122,0,0,18,114,97,100,0,59,120,121,122,0,0,18,99,0,59,120,120,120,0,0,0,
+0,1,0,12,0,100,101,103,114,101,101,115,0,1,1,0,12,114,97,100,0,0,0,1,3,2,1,9,1,99,0,2,17,49,56,48,
+0,48,0,0,17,51,0,49,52,49,53,57,50,54,0,0,49,0,0,4,118,101,99,52,95,109,117,108,116,105,112,108,
+121,0,18,95,95,114,101,116,86,97,108,0,0,18,114,97,100,0,0,18,99,0,59,120,120,120,120,0,0,0,0,1,0,
+9,0,115,105,110,0,1,1,0,9,114,97,100,105,97,110,115,0,0,0,1,4,102,108,111,97,116,95,115,105,110,
+101,0,18,95,95,114,101,116,86,97,108,0,59,120,0,0,18,114,97,100,105,97,110,115,0,0,0,0,1,0,10,0,
+115,105,110,0,1,1,0,10,114,97,100,105,97,110,115,0,0,0,1,4,102,108,111,97,116,95,115,105,110,101,0,
+18,95,95,114,101,116,86,97,108,0,59,120,0,0,18,114,97,100,105,97,110,115,0,59,120,0,0,0,4,102,108,
+111,97,116,95,115,105,110,101,0,18,95,95,114,101,116,86,97,108,0,59,121,0,0,18,114,97,100,105,97,
+110,115,0,59,121,0,0,0,0,1,0,11,0,115,105,110,0,1,1,0,11,114,97,100,105,97,110,115,0,0,0,1,4,102,
+108,111,97,116,95,115,105,110,101,0,18,95,95,114,101,116,86,97,108,0,59,120,0,0,18,114,97,100,105,
+97,110,115,0,59,120,0,0,0,4,102,108,111,97,116,95,115,105,110,101,0,18,95,95,114,101,116,86,97,108,
+0,59,121,0,0,18,114,97,100,105,97,110,115,0,59,121,0,0,0,4,102,108,111,97,116,95,115,105,110,101,0,
+18,95,95,114,101,116,86,97,108,0,59,122,0,0,18,114,97,100,105,97,110,115,0,59,122,0,0,0,0,1,0,12,0,
115,105,110,0,1,1,0,12,114,97,100,105,97,110,115,0,0,0,1,4,102,108,111,97,116,95,115,105,110,101,0,
18,95,95,114,101,116,86,97,108,0,59,120,0,0,18,114,97,100,105,97,110,115,0,59,120,0,0,0,4,102,108,
111,97,116,95,115,105,110,101,0,18,95,95,114,101,116,86,97,108,0,59,121,0,0,18,114,97,100,105,97,
--
cgit v1.2.3
From f49d345a51bb208fee19fc25762bcdb0e7f67174 Mon Sep 17 00:00:00 2001
From: Brad Smith
Date: Thu, 17 Jul 2008 08:15:57 -0600
Subject: mesa: added checks for OpenBSD
---
src/mesa/x86/common_x86.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/src/mesa/x86/common_x86.c b/src/mesa/x86/common_x86.c
index d93241a977..0caa36a5a0 100644
--- a/src/mesa/x86/common_x86.c
+++ b/src/mesa/x86/common_x86.c
@@ -42,6 +42,11 @@
#include
#include
#endif
+#if defined(USE_SSE_ASM) && defined(__OpenBSD__)
+#include
+#include
+#include
+#endif
#include "common_x86_asm.h"
#include "imports.h"
@@ -121,6 +126,19 @@ static void check_os_sse_support( void )
if (ret || !enabled)
_mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
}
+#elif defined(__OpenBSD__)
+ {
+ int mib[2];
+ int ret, enabled;
+ size_t len = sizeof(enabled);
+
+ mib[0] = CTL_MACHDEP;
+ mib[1] = CPU_SSE;
+
+ ret = sysctl(mib, 2, &enabled, &len, NULL, 0);
+ if (ret || !enabled)
+ _mesa_x86_cpu_features &= ~(X86_FEATURE_XMM);
+ }
#elif defined(WIN32)
LPTOP_LEVEL_EXCEPTION_FILTER oldFilter;
--
cgit v1.2.3
From d9f4d04111133a7dab5e645021e56245febea2ae Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Thu, 17 Jul 2008 10:03:10 -0600
Subject: mesa: fix/improve the atan(y,x) function
---
.../shader/slang/library/slang_common_builtin.gc | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/src/mesa/shader/slang/library/slang_common_builtin.gc b/src/mesa/shader/slang/library/slang_common_builtin.gc
index b095a6434b..3726335471 100644
--- a/src/mesa/shader/slang/library/slang_common_builtin.gc
+++ b/src/mesa/shader/slang/library/slang_common_builtin.gc
@@ -401,16 +401,17 @@ vec4 atan(const vec4 y_over_x)
float atan(const float y, const float x)
{
- if (x == 0.0)
- return 0.0;
- float z = atan(y / x);
- if (x < 0.0)
- {
- if (y < 0.0)
- return z - 3.141593;
- return z + 3.141593;
- }
- return z;
+ float r;
+ if (abs(x) > 1.0e-4) {
+ r = atan(y / x);
+ if (x < 0.0) {
+ r = r + sign(y) * 3.141593;
+ }
+ }
+ else {
+ r = sign(y) * 1.5707965; // pi/2
+ }
+ return r;
}
vec2 atan(const vec2 u, const vec2 v)
--
cgit v1.2.3
From 73b8ee412110598b5c54ac695fcfce2878fdbe07 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Thu, 17 Jul 2008 10:09:04 -0600
Subject: mesa: regenerated file
---
.../shader/slang/library/slang_common_builtin_gc.h | 965 +++++++++++----------
1 file changed, 483 insertions(+), 482 deletions(-)
diff --git a/src/mesa/shader/slang/library/slang_common_builtin_gc.h b/src/mesa/shader/slang/library/slang_common_builtin_gc.h
index a8698712c5..0a43cad2a3 100644
--- a/src/mesa/shader/slang/library/slang_common_builtin_gc.h
+++ b/src/mesa/shader/slang/library/slang_common_builtin_gc.h
@@ -210,500 +210,501 @@
121,0,0,0,20,0,9,18,95,95,114,101,116,86,97,108,0,59,122,0,58,97,116,97,110,0,18,121,95,111,118,
101,114,95,120,0,59,122,0,0,0,20,0,9,18,95,95,114,101,116,86,97,108,0,59,119,0,58,97,116,97,110,0,
18,121,95,111,118,101,114,95,120,0,59,119,0,0,0,20,0,0,1,0,9,0,97,116,97,110,0,1,1,0,9,121,0,0,1,1,
-0,9,120,0,0,0,1,10,18,120,0,17,48,0,48,0,0,38,0,8,17,48,0,48,0,0,0,9,14,0,3,2,0,9,1,122,0,2,58,97,
-116,97,110,0,18,121,0,18,120,0,49,0,0,0,0,10,18,120,0,17,48,0,48,0,0,40,0,2,10,18,121,0,17,48,0,48,
-0,0,40,0,8,18,122,0,17,51,0,49,52,49,53,57,51,0,0,47,0,9,14,0,8,18,122,0,17,51,0,49,52,49,53,57,51,
-0,0,46,0,0,9,14,0,8,18,122,0,0,0,1,0,10,0,97,116,97,110,0,1,1,0,10,117,0,0,1,1,0,10,118,0,0,0,1,9,
-18,95,95,114,101,116,86,97,108,0,59,120,0,58,97,116,97,110,0,18,117,0,59,120,0,0,18,118,0,59,120,0,
-0,0,20,0,9,18,95,95,114,101,116,86,97,108,0,59,121,0,58,97,116,97,110,0,18,117,0,59,121,0,0,18,118,
-0,59,121,0,0,0,20,0,0,1,0,11,0,97,116,97,110,0,1,1,0,11,117,0,0,1,1,0,11,118,0,0,0,1,9,18,95,95,
-114,101,116,86,97,108,0,59,120,0,58,97,116,97,110,0,18,117,0,59,120,0,0,18,118,0,59,120,0,0,0,20,0,
-9,18,95,95,114,101,116,86,97,108,0,59,121,0,58,97,116,97,110,0,18,117,0,59,121,0,0,18,118,0,59,121,
-0,0,0,20,0,9,18,95,95,114,101,116,86,97,108,0,59,122,0,58,97,116,97,110,0,18,117,0,59,122,0,0,18,
-118,0,59,122,0,0,0,20,0,0,1,0,12,0,97,116,97,110,0,1,1,0,12,117,0,0,1,1,0,12,118,0,0,0,1,9,18,95,
-95,114,101,116,86,97,108,0,59,120,0,58,97,116,97,110,0,18,117,0,59,120,0,0,18,118,0,59,120,0,0,0,
-20,0,9,18,95,95,114,101,116,86,97,108,0,59,121,0,58,97,116,97,110,0,18,117,0,59,121,0,0,18,118,0,
-59,121,0,0,0,20,0,9,18,95,95,114,101,116,86,97,108,0,59,122,0,58,97,116,97,110,0,18,117,0,59,122,0,
-0,18,118,0,59,122,0,0,0,20,0,9,18,95,95,114,101,116,86,97,108,0,59,119,0,58,97,116,97,110,0,18,117,
-0,59,119,0,0,18,118,0,59,119,0,0,0,20,0,0,1,0,9,0,112,111,119,0,1,1,0,9,97,0,0,1,1,0,9,98,0,0,0,1,
-4,102,108,111,97,116,95,112,111,119,101,114,0,18,95,95,114,101,116,86,97,108,0,59,120,0,0,18,97,0,
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-120,0,0,0,4,102,108,111,97,116,95,112,111,119,101,114,0,18,95,95,114,101,116,86,97,108,0,59,121,0,
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-0,1,4,102,108,111,97,116,95,112,111,119,101,114,0,18,95,95,114,101,116,86,97,108,0,59,120,0,0,18,
-97,0,59,120,0,0,18,98,0,59,120,0,0,0,4,102,108,111,97,116,95,112,111,119,101,114,0,18,95,95,114,
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-111,119,101,114,0,18,95,95,114,101,116,86,97,108,0,59,122,0,0,18,97,0,59,122,0,0,18,98,0,59,122,0,
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-108,111,97,116,95,112,111,119,101,114,0,18,95,95,114,101,116,86,97,108,0,59,120,0,0,18,101,0,0,18,
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--
cgit v1.2.3
From 3bfedb7ed4a35cfcc7187bc22314833ef1d96ec9 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Thu, 17 Jul 2008 15:40:10 -0600
Subject: mesa: build the stand-alone glslcompiler by default, update the docs
---
configs/default | 2 +-
docs/shading.html | 42 ++++++++++++++++++++++++++----------------
2 files changed, 27 insertions(+), 17 deletions(-)
diff --git a/configs/default b/configs/default
index a14078fa26..36dc483c9a 100644
--- a/configs/default
+++ b/configs/default
@@ -67,7 +67,7 @@ GLW_SOURCES = GLwDrawA.c
LIB_DIR = lib
SRC_DIRS = mesa glu glut/glx glw
GLU_DIRS = sgi
-DRIVER_DIRS = x11 osmesa
+DRIVER_DIRS = x11 osmesa glslcompiler
# Which subdirs under $(TOP)/progs/ to enter:
PROGRAM_DIRS = demos redbook samples glsl xdemos
diff --git a/docs/shading.html b/docs/shading.html
index 0a9f5f36f4..1a60e5b708 100644
--- a/docs/shading.html
+++ b/docs/shading.html
@@ -25,7 +25,7 @@ Contents
Unsupported Features
Implementation Notes
Programming Hints
-Stand-alone Compiler
+Stand-alone GLSL Compiler
Compiler Implementation
Compiler Validation
@@ -133,7 +133,7 @@ These issues will be addressed/resolved in the future.
-Stand-alone Compiler
+Stand-alone GLSL Compiler
A unique stand-alone GLSL compiler driver has been added to Mesa.
@@ -155,12 +155,11 @@ This tool is useful for:
-To build the glslcompiler program (this will be improved someday):
+After building Mesa the glslcompiler should be found in the Mesa/bin/ directory.
+If it's not there, it can be built manually:
- cd src/mesa
- make libmesa.a
- cd drivers/glslcompiler
+ cd src/mesa/drivers/glslcompiler
make
@@ -170,20 +169,31 @@ Here's an example of using the compiler to compile a vertex shader and
emit GL_ARB_vertex_program-style instructions:
- glslcompiler --arb --linenumbers --vs vertshader.txt
+ bin/glslcompiler --debug --numbers --fs progs/glsl/CH06-brick.frag.txt
-The output may look similar to this:
+results in:
-!!ARBvp1.0
- 0: MOV result.texcoord[0], vertex.texcoord[0];
- 1: DP4 temp0.x, state.matrix.mvp.row[0], vertex.position;
- 2: DP4 temp0.y, state.matrix.mvp.row[1], vertex.position;
- 3: DP4 temp0.z, state.matrix.mvp.row[2], vertex.position;
- 4: DP4 temp0.w, state.matrix.mvp.row[3], vertex.position;
- 5: MOV result.position, temp0;
- 6: END
+# Fragment Program/Shader
+ 0: RCP TEMP[4].x, UNIFORM[2].xxxx;
+ 1: RCP TEMP[4].y, UNIFORM[2].yyyy;
+ 2: MUL TEMP[3].xy, VARYING[0], TEMP[4];
+ 3: MOV TEMP[1], TEMP[3];
+ 4: MUL TEMP[0].w, TEMP[1].yyyy, CONST[4].xxxx;
+ 5: FRC TEMP[1].z, TEMP[0].wwww;
+ 6: SGT.C TEMP[0].w, TEMP[1].zzzz, CONST[4].xxxx;
+ 7: IF (NE.wwww); # (if false, goto 9);
+ 8: ADD TEMP[1].x, TEMP[1].xxxx, CONST[4].xxxx;
+ 9: ENDIF;
+ 10: FRC TEMP[1].xy, TEMP[1];
+ 11: SGT TEMP[2].xy, UNIFORM[3], TEMP[1];
+ 12: MUL TEMP[1].z, TEMP[2].xxxx, TEMP[2].yyyy;
+ 13: LRP TEMP[0], TEMP[1].zzzz, UNIFORM[0], UNIFORM[1];
+ 14: MUL TEMP[0].xyz, TEMP[0], VARYING[1].xxxx;
+ 15: MOV OUTPUT[0].xyz, TEMP[0];
+ 16: MOV OUTPUT[0].w, CONST[4].yyyy;
+ 17: END
--
cgit v1.2.3
From b4b7326717d3253656f9702fc04f06f8d210a6aa Mon Sep 17 00:00:00 2001
From: "Xiang, Haihao"
Date: Fri, 18 Jul 2008 17:40:11 +0800
Subject: intel: fix texture border issue. (bug #16697)
---
src/mesa/drivers/dri/i965/brw_fallback.c | 5 ++++-
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 5 ++++-
src/mesa/drivers/dri/intel/intel_tex_image.c | 5 ++++-
src/mesa/drivers/dri/intel/intel_tex_validate.c | 5 ++++-
4 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c
index b5cf821a93..8a8fb50cb9 100644
--- a/src/mesa/drivers/dri/i965/brw_fallback.c
+++ b/src/mesa/drivers/dri/i965/brw_fallback.c
@@ -73,7 +73,10 @@ static GLboolean do_check_fallback(struct brw_context *brw)
if (texUnit->_ReallyEnabled) {
struct intel_texture_object *intelObj = intel_texture_object(texUnit->_Current);
struct gl_texture_image *texImage = intelObj->base.Image[0][intelObj->firstLevel];
- if (texImage->Border) {
+ if (texImage->Border ||
+ ((texImage->_BaseFormat == GL_DEPTH_COMPONENT) &&
+ ((texImage->TexObject->WrapS == GL_CLAMP_TO_BORDER) ||
+ (texImage->TexObject->WrapT == GL_CLAMP_TO_BORDER)))) {
DBG("FALLBACK: texture border\n");
return GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 9205627813..1b645c7262 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -265,7 +265,10 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
{
/* Images with borders are never pulled into mipmap trees.
*/
- if (image->Border)
+ if (image->Border ||
+ ((image->_BaseFormat == GL_DEPTH_COMPONENT) &&
+ ((image->TexObject->WrapS == GL_CLAMP_TO_BORDER) ||
+ (image->TexObject->WrapT == GL_CLAMP_TO_BORDER))))
return GL_FALSE;
if (image->InternalFormat != mt->internal_format ||
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 95ddbd5920..f261034c18 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -75,7 +75,10 @@ guess_and_alloc_mipmap_tree(struct intel_context *intel,
DBG("%s\n", __FUNCTION__);
- if (intelImage->base.Border)
+ if (intelImage->base.Border ||
+ ((intelImage->base._BaseFormat == GL_DEPTH_COMPONENT) &&
+ ((intelObj->base.WrapS == GL_CLAMP_TO_BORDER) ||
+ (intelObj->base.WrapT == GL_CLAMP_TO_BORDER))))
return;
if (intelImage->level > intelObj->base.BaseLevel &&
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index 992c75c519..f56c236e61 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -144,7 +144,10 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit)
/* Fallback case:
*/
- if (firstImage->base.Border) {
+ if (firstImage->base.Border ||
+ ((firstImage->base._BaseFormat == GL_DEPTH_COMPONENT) &&
+ ((tObj->WrapS == GL_CLAMP_TO_BORDER) ||
+ (tObj->WrapT == GL_CLAMP_TO_BORDER)))) {
if (intelObj->mt) {
intel_miptree_release(intel, &intelObj->mt);
}
--
cgit v1.2.3
From 776c60d3c33b05f59181a2052a9f03147bc51111 Mon Sep 17 00:00:00 2001
From: Dan Nicholson
Date: Fri, 18 Jul 2008 07:40:41 -0700
Subject: autoconf: Support Motif widgets in GLw with --enable-motif
Add an --enable-motif option, which will enable the Motif widgets in
libGLw and link it with libXm. The Motif installation information will
be gathered from the motif-config script (this comes with LessTif) or
fallback to the standard autoconf checks.
To allow the location of the Motif headers to be set from configure, the
default setting of -I/usr/include/Motif1.2 has been moved into
configs/default and then passed to the Makefile through the MOTIF_CFLAGS
variable.
---
configs/autoconf.in | 4 ++++
configs/default | 1 +
configure.ac | 30 ++++++++++++++++++++++++++++--
src/glw/Makefile | 2 +-
4 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/configs/autoconf.in b/configs/autoconf.in
index 8ed1c93d11..a3eaed5c9d 100644
--- a/configs/autoconf.in
+++ b/configs/autoconf.in
@@ -66,6 +66,10 @@ USING_EGL = @USING_EGL@
# Dependencies
X11_INCLUDES = @X11_INCLUDES@
+# GLw motif setup
+GLW_SOURCES = @GLW_SOURCES@
+MOTIF_CFLAGS = @MOTIF_CFLAGS@
+
# Library/program dependencies
GL_LIB_DEPS = $(EXTRA_LIB_PATH) @GL_LIB_DEPS@
OSMESA_LIB_DEPS = -L$(TOP)/$(LIB_DIR) @OSMESA_MESA_DEPS@ \
diff --git a/configs/default b/configs/default
index 36dc483c9a..31ba2f62a0 100644
--- a/configs/default
+++ b/configs/default
@@ -61,6 +61,7 @@ ASM_SOURCES =
# GLw widget sources (Append "GLwMDrawA.c" here and add -lXm to GLW_LIB_DEPS in
# order to build the Motif widget too)
GLW_SOURCES = GLwDrawA.c
+MOTIF_CFLAGS = -I/usr/include/Motif1.2
# Directories to build
diff --git a/configure.ac b/configure.ac
index acb29e4468..9014f8e158 100644
--- a/configure.ac
+++ b/configure.ac
@@ -878,6 +878,12 @@ if test "x$enable_glw" = xyes && test "$mesa_driver" = osmesa; then
AC_MSG_WARN([Disabling GLw since the driver is OSMesa])
enable_glw=no
fi
+AC_ARG_ENABLE([motif],
+ [AS_HELP_STRING([--enable-motif],
+ [use Motif widgets in GLw @<:@default=disabled@:>@])],
+ [enable_motif="$enableval"],
+ [enable_motif=no])
+
if test "x$enable_glw" = xyes; then
SRC_DIRS="$SRC_DIRS glw"
if test "$x11_pkgconfig" = yes; then
@@ -885,7 +891,25 @@ if test "x$enable_glw" = xyes; then
GLW_LIB_DEPS="$GLW_LIBS"
else
# should check these...
- GLW_LIB_DEPS="$X_LIBS -lX11 -lXt"
+ GLW_LIB_DEPS="$X_LIBS -lXt -lX11"
+ fi
+
+ GLW_SOURCES="GLwDrawA.c"
+ MOTIF_CFLAGS=
+ if test "x$enable_motif" = xyes; then
+ GLW_SOURCES="$GLW_SOURCES GLwMDrawA.c"
+ AC_PATH_PROG([MOTIF_CONFIG], [motif-config], [no])
+ if test "x$MOTIF_CONFIG" != xno; then
+ MOTIF_CFLAGS=`$MOTIF_CONFIG --cflags`
+ MOTIF_LIBS=`$MOTIF_CONFIG --libs`
+ else
+ AC_CHECK_HEADER([Xm/PrimitiveP.h], [],
+ [AC_MSG_ERROR([Can't locate Motif headers])])
+ AC_CHECK_LIB([Xm], [XmGetPixmap], [MOTIF_LIBS="-lXm"],
+ [AC_MSG_ERROR([Can't locate Motif Xm library])])
+ fi
+ # MOTIF_LIBS is prepended to GLW_LIB_DEPS since Xm needs Xt/X11
+ GLW_LIB_DEPS="$MOTIF_LIBS $GLW_LIB_DEPS"
fi
# If static, empty GLW_LIB_DEPS and add libs for programs to link
@@ -900,6 +924,8 @@ if test "x$enable_glw" = xyes; then
fi
AC_SUBST([GLW_LIB_DEPS])
AC_SUBST([GLW_MESA_DEPS])
+AC_SUBST([GLW_SOURCES])
+AC_SUBST([MOTIF_CFLAGS])
dnl
dnl GLUT configuration
@@ -1025,7 +1051,7 @@ echo ""
echo " Shared libs: $enable_shared"
echo " Static libs: $enable_static"
echo " GLU: $enable_glu"
-echo " GLw: $enable_glw"
+echo " GLw: $enable_glw (Motif: $enable_motif)"
echo " glut: $enable_glut"
dnl Programs
diff --git a/src/glw/Makefile b/src/glw/Makefile
index a9a174508f..6a522eccba 100644
--- a/src/glw/Makefile
+++ b/src/glw/Makefile
@@ -7,7 +7,7 @@ MAJOR = 1
MINOR = 0
TINY = 0
-INCDIRS = -I$(TOP)/include -I/usr/include/Motif1.2 $(X11_INCLUDES)
+INCDIRS = -I$(TOP)/include $(MOTIF_CFLAGS) $(X11_INCLUDES)
OBJECTS = $(GLW_SOURCES:.c=.o)
--
cgit v1.2.3
From 99fe0c222c2853a612b73aa6fcffb0a532ce5747 Mon Sep 17 00:00:00 2001
From: Ian Romanick
Date: Fri, 18 Jul 2008 12:40:04 -0700
Subject: intel-gem: Bump driver date
Bump the driver date and insert the string "GEM". When running tests,
this make it much easier to know that the right driver is being used.
---
src/mesa/drivers/dri/intel/intel_context.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 7e3f370ad0..f573cf4d4f 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -96,11 +96,13 @@ int INTEL_DEBUG = (0);
#include "extension_helper.h"
-#define DRIVER_DATE "20061102"
+#define DRIVER_DATE "20080716"
+#define DRIVER_DATE_GEM "GEM " DRIVER_DATE
static const GLubyte *
intelGetString(GLcontext * ctx, GLenum name)
{
+ const struct intel_context *const intel = intel_context(ctx);
const char *chipset;
static char buffer[128];
@@ -110,7 +112,7 @@ intelGetString(GLcontext * ctx, GLenum name)
break;
case GL_RENDERER:
- switch (intel_context(ctx)->intelScreen->deviceID) {
+ switch (intel->intelScreen->deviceID) {
case PCI_CHIP_845_G:
chipset = "Intel(R) 845G";
break;
@@ -181,7 +183,9 @@ intelGetString(GLcontext * ctx, GLenum name)
break;
}
- (void) driGetRendererString(buffer, chipset, DRIVER_DATE, 0);
+ (void) driGetRendererString(buffer, chipset,
+ (intel->ttm) ? DRIVER_DATE_GEM : DRIVER_DATE,
+ 0);
return (GLubyte *) buffer;
default:
--
cgit v1.2.3
From 77497eb73b9aa349f41f3bcb493d84610e302371 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Mon, 21 Jul 2008 09:01:21 -0600
Subject: mesa: revert building glslcompiler by default
---
configs/default | 2 +-
docs/shading.html | 3 +--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/configs/default b/configs/default
index 31ba2f62a0..154797265f 100644
--- a/configs/default
+++ b/configs/default
@@ -68,7 +68,7 @@ MOTIF_CFLAGS = -I/usr/include/Motif1.2
LIB_DIR = lib
SRC_DIRS = mesa glu glut/glx glw
GLU_DIRS = sgi
-DRIVER_DIRS = x11 osmesa glslcompiler
+DRIVER_DIRS = x11 osmesa
# Which subdirs under $(TOP)/progs/ to enter:
PROGRAM_DIRS = demos redbook samples glsl xdemos
diff --git a/docs/shading.html b/docs/shading.html
index 1a60e5b708..02f393cc9e 100644
--- a/docs/shading.html
+++ b/docs/shading.html
@@ -155,8 +155,7 @@ This tool is useful for:
-After building Mesa the glslcompiler should be found in the Mesa/bin/ directory.
-If it's not there, it can be built manually:
+After building Mesa, the glslcompiler can be built by manually running:
cd src/mesa/drivers/glslcompiler
--
cgit v1.2.3
From b993d539a76e7f1446890a85e4b61deec4d4162d Mon Sep 17 00:00:00 2001
From: Pawel Pieczul
Date: Mon, 21 Jul 2008 10:57:20 -0700
Subject: 965: Fix color clamping issues
---
src/mesa/drivers/dri/i965/brw_vs_emit.c | 26 +++++++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 7767d1369c..8c7bc98c61 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1160,9 +1160,29 @@ void brw_vs_emit(struct brw_vs_compile *c )
}
if (inst->DstReg.File == PROGRAM_OUTPUT
- &&inst->DstReg.Index != VERT_RESULT_HPOS
- &&c->output_regs[inst->DstReg.Index].used_in_src)
- brw_MOV(p, get_dst(c, inst->DstReg), dst);
+ && inst->DstReg.Index != VERT_RESULT_HPOS
+ && c->output_regs[inst->DstReg.Index].used_in_src) {
+ /* Result color clamping.
+ *
+ * When destination register is an output register and it's
+ * primary/secondary front/back color, we have to clamp the result
+ * to [0,1]. This is done by enabling the saturation bit for the
+ * last instruction.
+ *
+ * We don't use brw_set_saturate() as it modifies
+ * p->current->header.saturate, which affects all the subsequent
+ * instructions. Instead, we directly modify the header of the last
+ * (already stored) instruction.
+ */
+ if (inst->DstReg.File == PROGRAM_OUTPUT) {
+ if ((inst->DstReg.Index == VERT_RESULT_COL0) ||
+ (inst->DstReg.Index == VERT_RESULT_COL1) ||
+ (inst->DstReg.Index == VERT_RESULT_BFC0) ||
+ (inst->DstReg.Index == VERT_RESULT_BFC1)) {
+ p->store[p->nr_insn-1].header.saturate = 1;
+ }
+ }
+ }
release_tmps(c);
}
--
cgit v1.2.3
From 97988ccc46c0248177cd71937021ca8cc2a7452b Mon Sep 17 00:00:00 2001
From: Jesse Barnes
Date: Tue, 22 Jul 2008 09:39:23 -0700
Subject: intel: fix buffer swaps and enable page flipping on 965
Some buffer swap intel render buffer fields (pf_num_pages & vbl_pending) are
also used for page flipping, so enable the code that sets & updates them on
965. This allows buffer swaps and page flips to work on 965 and prevents hangs
in LOCK_HARDWARE in the buffer swap case due to an uninitialized vbl_pending
field.
Fixes FDO #16118.
---
src/mesa/drivers/dri/intel/intel_buffers.c | 54 +++++++++---------------------
1 file changed, 15 insertions(+), 39 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c
index 2a25f079e9..348c490af0 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -197,7 +197,6 @@ intelSetBackClipRects(struct intel_context *intel)
}
}
-#ifdef I915
static void
intelUpdatePageFlipping(struct intel_context *intel,
GLint areaA, GLint areaB)
@@ -267,7 +266,6 @@ intelUpdatePageFlipping(struct intel_context *intel,
intel_flip_renderbuffers(intel_fb);
intel_draw_buffer(&intel->ctx, intel->ctx.DrawBuffer);
}
-#endif /* I915 */
/**
* This will be called whenever the currently bound window is moved/resized.
@@ -318,9 +316,7 @@ intelWindowMoved(struct intel_context *intel)
GLint areaB = driIntersectArea( drw_rect, planeB_rect );
GLuint flags = dPriv->vblFlags;
-#ifdef I915
intelUpdatePageFlipping(intel, areaA, areaB);
-#endif
/* Update vblank info
*/
@@ -645,7 +641,6 @@ intel_wait_flips(struct intel_context *intel)
static GLboolean
intelPageFlip(const __DRIdrawablePrivate * dPriv)
{
-#ifdef I915
struct intel_context *intel;
int ret;
struct intel_framebuffer *intel_fb = dPriv->driverPrivate;
@@ -698,40 +693,8 @@ intelPageFlip(const __DRIdrawablePrivate * dPriv)
intel_draw_buffer(&intel->ctx, &intel_fb->Base);
return GL_TRUE;
-#else
- return GL_FALSE;
-#endif
}
-#if 0
-void
-intelSwapBuffers(__DRIdrawablePrivate * dPriv)
-{
- if (dPriv->driverPrivate) {
- const struct gl_framebuffer *fb
- = (struct gl_framebuffer *) dPriv->driverPrivate;
- if (fb->Visual.doubleBufferMode) {
- GET_CURRENT_CONTEXT(ctx);
- if (ctx && ctx->DrawBuffer == fb) {
- _mesa_notifySwapBuffers(ctx); /* flush pending rendering */
- }
- if (intel->doPageFlip) {
- intelPageFlip(dPriv);
- }
- else {
- intelCopyBuffer(dPriv);
- }
- }
- }
- else {
- _mesa_problem(NULL,
- "dPriv has no gl_framebuffer pointer in intelSwapBuffers");
- }
-}
-#else
-/* Trunk version:
- */
-
static GLboolean
intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target)
{
@@ -746,8 +709,10 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target)
if (!dPriv->vblFlags ||
(dPriv->vblFlags & VBLANK_FLAG_NO_IRQ) ||
- intelScreen->drmMinor < (intel_fb->pf_active ? 9 : 6))
+ intelScreen->drmMinor < (intel_fb->pf_active ? 9 : 6)) {
+ printf("swap schedule failed: bad flags or drm minor\n");
return GL_FALSE;
+ }
interval = driGetVBlankInterval(dPriv);
@@ -756,6 +721,7 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target)
if (dPriv->vblFlags & VBLANK_FLAG_SYNC) {
swap.seqtype |= DRM_VBLANK_NEXTONMISS;
} else if (interval == 0) {
+ printf("swap schedule failed: bad interval\n");
return GL_FALSE;
}
@@ -803,6 +769,7 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target)
}
ret = GL_FALSE;
+ printf("swap schedule failed: vblank swap failed\n");
}
UNLOCK_HARDWARE(intel);
@@ -832,8 +799,18 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv)
_mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */
if (!intelScheduleSwap(dPriv, &missed_target)) {
+ printf("schedule swap failed, trying to wait manually\n");
driWaitForVBlank(dPriv, &missed_target);
+ /*
+ * Update each buffer's vbl_pending so we don't get too out of
+ * sync
+ */
+ intel_get_renderbuffer(&intel_fb->Base,
+ BUFFER_BACK_LEFT)->vbl_pending =
+ intel_get_renderbuffer(&intel_fb->Base,
+ BUFFER_FRONT_LEFT)->vbl_pending =
+ dPriv->vblSeq;
if (!intelPageFlip(dPriv)) {
intelCopyBuffer(dPriv, NULL);
}
@@ -854,7 +831,6 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv)
fprintf(stderr, "%s: drawable has no context!\n", __FUNCTION__);
}
}
-#endif
void
intelCopySubBuffer(__DRIdrawablePrivate * dPriv, int x, int y, int w, int h)
--
cgit v1.2.3
From bdaa06ad639821368ac8d1af7b7561fd7e83fb13 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Tue, 15 Jul 2008 14:26:19 -0700
Subject: intel: move renderbuffer mapping to separate functions.
This lets us avoid duplicated code for doing so, including the depthstencil
paths that aren't covered by SpanRenderStart/Finish. Those paths were
missing the span funcs setup, leading to a null dereference in the fbotexture
demo.
---
src/mesa/drivers/dri/intel/intel_depthstencil.c | 80 ++++++------------
src/mesa/drivers/dri/intel/intel_span.c | 103 ++++++++++++------------
src/mesa/drivers/dri/intel/intel_span.h | 4 +
3 files changed, 80 insertions(+), 107 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_depthstencil.c b/src/mesa/drivers/dri/intel/intel_depthstencil.c
index 90baecd8c2..70ba68e9e3 100644
--- a/src/mesa/drivers/dri/intel/intel_depthstencil.c
+++ b/src/mesa/drivers/dri/intel/intel_depthstencil.c
@@ -39,7 +39,7 @@
#include "intel_fbo.h"
#include "intel_depthstencil.h"
#include "intel_regions.h"
-
+#include "intel_span.h"
/**
* The GL_EXT_framebuffer_object allows the user to create their own
@@ -86,68 +86,33 @@
*
*/
-
-
-static void
-map_regions(GLcontext * ctx,
- struct intel_renderbuffer *depthRb,
- struct intel_renderbuffer *stencilRb)
-{
- struct intel_context *intel = intel_context(ctx);
- if (depthRb && depthRb->region) {
- intel_region_map(intel, depthRb->region);
- depthRb->pfMap = depthRb->region->map;
- depthRb->pfPitch = depthRb->region->pitch;
- }
- if (stencilRb && stencilRb->region) {
- intel_region_map(intel, stencilRb->region);
- stencilRb->pfMap = stencilRb->region->map;
- stencilRb->pfPitch = stencilRb->region->pitch;
- }
-}
-
-static void
-unmap_regions(GLcontext * ctx,
- struct intel_renderbuffer *depthRb,
- struct intel_renderbuffer *stencilRb)
-{
- struct intel_context *intel = intel_context(ctx);
- if (depthRb && depthRb->region) {
- intel_region_unmap(intel, depthRb->region);
- depthRb->pfMap = NULL;
- depthRb->pfPitch = 0;
- }
- if (stencilRb && stencilRb->region) {
- intel_region_unmap(intel, stencilRb->region);
- stencilRb->pfMap = NULL;
- stencilRb->pfPitch = 0;
- }
-}
-
-
-
/**
* Undo the pairing/interleaving between depth and stencil buffers.
* irb should be a depth/stencil or stencil renderbuffer.
*/
void
-intel_unpair_depth_stencil(GLcontext * ctx, struct intel_renderbuffer *irb)
+intel_unpair_depth_stencil(GLcontext *ctx, struct intel_renderbuffer *irb)
{
+ struct intel_context *intel = intel_context(ctx);
+ struct gl_renderbuffer *rb = &irb->Base;
+
if (irb->PairedStencil) {
/* irb is a depth/stencil buffer */
struct gl_renderbuffer *stencilRb;
struct intel_renderbuffer *stencilIrb;
- ASSERT(irb->Base._ActualFormat == GL_DEPTH24_STENCIL8_EXT);
+ ASSERT(rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT);
stencilRb = _mesa_lookup_renderbuffer(ctx, irb->PairedStencil);
stencilIrb = intel_renderbuffer(stencilRb);
if (stencilIrb) {
/* need to extract stencil values from the depth buffer */
- ASSERT(stencilIrb->PairedDepth == irb->Base.Name);
- map_regions(ctx, irb, stencilIrb);
- _mesa_extract_stencil(ctx, &irb->Base, &stencilIrb->Base);
- unmap_regions(ctx, irb, stencilIrb);
+ ASSERT(stencilIrb->PairedDepth == rb->Name);
+ intel_renderbuffer_map(intel, rb);
+ intel_renderbuffer_map(intel, stencilRb);
+ _mesa_extract_stencil(ctx, rb, stencilRb);
+ intel_renderbuffer_unmap(intel, stencilRb);
+ intel_renderbuffer_unmap(intel, rb);
stencilIrb->PairedDepth = 0;
}
irb->PairedStencil = 0;
@@ -157,17 +122,19 @@ intel_unpair_depth_stencil(GLcontext * ctx, struct intel_renderbuffer *irb)
struct gl_renderbuffer *depthRb;
struct intel_renderbuffer *depthIrb;
- ASSERT(irb->Base._ActualFormat == GL_STENCIL_INDEX8_EXT ||
- irb->Base._ActualFormat == GL_DEPTH24_STENCIL8_EXT);
+ ASSERT(rb->_ActualFormat == GL_STENCIL_INDEX8_EXT ||
+ rb->_ActualFormat == GL_DEPTH24_STENCIL8_EXT);
depthRb = _mesa_lookup_renderbuffer(ctx, irb->PairedDepth);
depthIrb = intel_renderbuffer(depthRb);
if (depthIrb) {
/* need to extract stencil values from the depth buffer */
- ASSERT(depthIrb->PairedStencil == irb->Base.Name);
- map_regions(ctx, depthIrb, irb);
- _mesa_extract_stencil(ctx, &depthIrb->Base, &irb->Base);
- unmap_regions(ctx, depthIrb, irb);
+ ASSERT(depthIrb->PairedStencil == rb->Name);
+ intel_renderbuffer_map(intel, rb);
+ intel_renderbuffer_map(intel, depthRb);
+ _mesa_extract_stencil(ctx, depthRb, rb);
+ intel_renderbuffer_unmap(intel, depthRb);
+ intel_renderbuffer_unmap(intel, rb);
depthIrb->PairedStencil = 0;
}
irb->PairedDepth = 0;
@@ -194,6 +161,7 @@ void
intel_validate_paired_depth_stencil(GLcontext * ctx,
struct gl_framebuffer *fb)
{
+ struct intel_context *intel = intel_context(ctx);
struct intel_renderbuffer *depthRb, *stencilRb;
depthRb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
@@ -230,9 +198,11 @@ intel_validate_paired_depth_stencil(GLcontext * ctx,
stencilRb->Base._ActualFormat == GL_DEPTH24_STENCIL8_EXT);
/* establish new pairing: interleave stencil into depth buffer */
- map_regions(ctx, depthRb, stencilRb);
+ intel_renderbuffer_map(intel, &depthRb->Base);
+ intel_renderbuffer_map(intel, &stencilRb->Base);
_mesa_insert_stencil(ctx, &depthRb->Base, &stencilRb->Base);
- unmap_regions(ctx, depthRb, stencilRb);
+ intel_renderbuffer_unmap(intel, &stencilRb->Base);
+ intel_renderbuffer_unmap(intel, &depthRb->Base);
depthRb->PairedStencil = stencilRb->Base.Name;
stencilRb->PairedDepth = depthRb->Base.Name;
}
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 4f0855df0a..c9d413ec43 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -474,7 +474,39 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
#define TAG(x) intel_YTile_##x##_z24_s8
#include "stenciltmp.h"
+void
+intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
+{
+ struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+
+ if (irb == NULL || irb->region == NULL)
+ return;
+
+ intel_region_map(intel, irb->region);
+
+ irb->pfMap = irb->region->map;
+ irb->pfPitch = irb->region->pitch;
+
+ intel_set_span_functions(intel, rb);
+}
+
+void
+intel_renderbuffer_unmap(struct intel_context *intel,
+ struct gl_renderbuffer *rb)
+{
+ struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+
+ if (irb == NULL || irb->region == NULL)
+ return;
+ intel_region_unmap(intel, irb->region);
+
+ irb->pfMap = NULL;
+ irb->pfPitch = 0;
+
+ rb->GetRow = NULL;
+ rb->PutRow = NULL;
+}
/**
* Map or unmap all the renderbuffers which we may need during
@@ -493,21 +525,13 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
{
GLcontext *ctx = &intel->ctx;
GLuint i, j;
- struct intel_renderbuffer *irb;
/* color draw buffers */
for (j = 0; j < ctx->DrawBuffer->_NumColorDrawBuffers; j++) {
- struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[j];
- irb = intel_renderbuffer(rb);
- if (irb && irb->region) {
- intel_set_span_functions(intel, rb);
- if (map)
- intel_region_map(intel, irb->region);
- else
- intel_region_unmap(intel, irb->region);
- irb->pfMap = irb->region->map;
- irb->pfPitch = irb->region->pitch;
- }
+ if (map)
+ intel_renderbuffer_map(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
+ else
+ intel_renderbuffer_unmap(intel, ctx->DrawBuffer->_ColorDrawBuffers[j]);
}
/* check for render to textures */
@@ -530,16 +554,10 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
}
/* color read buffers */
- irb = intel_renderbuffer(ctx->ReadBuffer->_ColorReadBuffer);
- if (irb && irb->region) {
- intel_set_span_functions(intel, ctx->ReadBuffer->_ColorReadBuffer);
- if (map)
- intel_region_map(intel, irb->region);
- else
- intel_region_unmap(intel, irb->region);
- irb->pfMap = irb->region->map;
- irb->pfPitch = irb->region->pitch;
- }
+ if (map)
+ intel_renderbuffer_map(intel, ctx->ReadBuffer->_ColorReadBuffer);
+ else
+ intel_renderbuffer_unmap(intel, ctx->ReadBuffer->_ColorReadBuffer);
/* Account for front/back color page flipping.
* The span routines use the pfMap and pfPitch fields which will
@@ -572,40 +590,21 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
/* depth buffer (Note wrapper!) */
if (ctx->DrawBuffer->_DepthBuffer) {
- irb = intel_renderbuffer(ctx->DrawBuffer->_DepthBuffer->Wrapped);
- if (irb && irb->region) {
- if (map) {
- intel_set_span_functions(intel,
- ctx->DrawBuffer->_DepthBuffer->Wrapped);
- intel_region_map(intel, irb->region);
- irb->pfMap = irb->region->map;
- irb->pfPitch = irb->region->pitch;
- }
- else {
- intel_region_unmap(intel, irb->region);
- irb->pfMap = irb->region->map;
- irb->pfPitch = irb->region->pitch;
- }
- }
+ if (map)
+ intel_renderbuffer_map(intel, ctx->DrawBuffer->_DepthBuffer->Wrapped);
+ else
+ intel_renderbuffer_unmap(intel,
+ ctx->DrawBuffer->_DepthBuffer->Wrapped);
}
/* stencil buffer (Note wrapper!) */
if (ctx->DrawBuffer->_StencilBuffer) {
- irb = intel_renderbuffer(ctx->DrawBuffer->_StencilBuffer->Wrapped);
- if (irb && irb->region) {
- if (map) {
- intel_set_span_functions(intel,
- ctx->DrawBuffer->_StencilBuffer->Wrapped);
- intel_region_map(intel, irb->region);
- irb->pfMap = irb->region->map;
- irb->pfPitch = irb->region->pitch;
- }
- else {
- intel_region_unmap(intel, irb->region);
- irb->pfMap = irb->region->map;
- irb->pfPitch = irb->region->pitch;
- }
- }
+ if (map)
+ intel_renderbuffer_map(intel,
+ ctx->DrawBuffer->_StencilBuffer->Wrapped);
+ else
+ intel_renderbuffer_unmap(intel,
+ ctx->DrawBuffer->_StencilBuffer->Wrapped);
}
}
diff --git a/src/mesa/drivers/dri/intel/intel_span.h b/src/mesa/drivers/dri/intel/intel_span.h
index d2d4d6ecd4..acbeb4abe1 100644
--- a/src/mesa/drivers/dri/intel/intel_span.h
+++ b/src/mesa/drivers/dri/intel/intel_span.h
@@ -32,5 +32,9 @@ extern void intelInitSpanFuncs(GLcontext * ctx);
extern void intelSpanRenderFinish(GLcontext * ctx);
extern void intelSpanRenderStart(GLcontext * ctx);
+void intel_renderbuffer_map(struct intel_context *intel,
+ struct gl_renderbuffer *rb);
+void intel_renderbuffer_unmap(struct intel_context *intel,
+ struct gl_renderbuffer *rb);
#endif
--
cgit v1.2.3
From 1c8791c581ba2e3906a98a74e998dd51dd474ddb Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 16 Jul 2008 10:34:39 -0700
Subject: intel: Fix CopyTexSubImage's src tiling arg for the blit.
Didn't hurt 915, but needed for 965.
---
src/mesa/drivers/dri/intel/intel_tex_copy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index cf8eb4ed3c..d0ab464a1c 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -144,7 +144,7 @@ do_copy_texsubimage(struct intel_context *intel,
-src->pitch,
src->buffer,
src->height * src->pitch * src->cpp,
- GL_FALSE,
+ src->tiling,
intelImage->mt->pitch,
intelImage->mt->region->buffer,
image_offset,
--
cgit v1.2.3
From f0ca917924a749b1fa287cc9536607ace03c2f89 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 16 Jul 2008 11:13:35 -0700
Subject: intel: improve 2d batchbuffer debug output.
---
src/mesa/drivers/dri/intel/intel_decode.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_decode.c b/src/mesa/drivers/dri/intel/intel_decode.c
index a1240639f4..9c105013c0 100644
--- a/src/mesa/drivers/dri/intel/intel_decode.c
+++ b/src/mesa/drivers/dri/intel/intel_decode.c
@@ -183,9 +183,10 @@ decode_2d(uint32_t *data, int count, uint32_t hw_offset, int *failures)
switch ((data[0] & 0x1fc00000) >> 22) {
case 0x50:
instr_out(data, hw_offset, 0,
- "XY_COLOR_BLT (rgb %sabled, alpha %sabled)\n",
+ "XY_COLOR_BLT (rgb %sabled, alpha %sabled, dst tile %d)\n",
(data[0] & (1 << 20)) ? "en" : "dis",
- (data[0] & (1 << 21)) ? "en" : "dis");
+ (data[0] & (1 << 21)) ? "en" : "dis",
+ (data[0] >> 11) & 1);
len = (data[0] & 0x000000ff) + 2;
if (len != 6)
@@ -210,7 +211,8 @@ decode_2d(uint32_t *data, int count, uint32_t hw_offset, int *failures)
instr_out(data, hw_offset, 1, "format %s, pitch %d, "
"clipping %sabled\n", format,
- data[1] & 0xffff, data[1] & (1 << 30) ? "en" : "dis");
+ (short)(data[1] & 0xffff),
+ data[1] & (1 << 30) ? "en" : "dis");
instr_out(data, hw_offset, 2, "(%d,%d)\n",
data[2] & 0xffff, data[2] >> 16);
instr_out(data, hw_offset, 3, "(%d,%d)\n",
@@ -220,9 +222,12 @@ decode_2d(uint32_t *data, int count, uint32_t hw_offset, int *failures)
return len;
case 0x53:
instr_out(data, hw_offset, 0,
- "XY_SRC_COPY_BLT (rgb %sabled, alpha %sabled)\n",
+ "XY_SRC_COPY_BLT (rgb %sabled, alpha %sabled, "
+ "src tile %d, dst tile %d)\n",
(data[0] & (1 << 20)) ? "en" : "dis",
- (data[0] & (1 << 21)) ? "en" : "dis");
+ (data[0] & (1 << 21)) ? "en" : "dis",
+ (data[0] >> 15) & 1,
+ (data[0] >> 11) & 1);
len = (data[0] & 0x000000ff) + 2;
if (len != 8)
@@ -247,16 +252,17 @@ decode_2d(uint32_t *data, int count, uint32_t hw_offset, int *failures)
instr_out(data, hw_offset, 1, "format %s, dst pitch %d, "
"clipping %sabled\n", format,
- data[1] & 0xffff, data[1] & (1 << 30) ? "en" : "dis");
+ (short)(data[1] & 0xffff),
+ data[1] & (1 << 30) ? "en" : "dis");
instr_out(data, hw_offset, 2, "dst (%d,%d)\n",
data[2] & 0xffff, data[2] >> 16);
instr_out(data, hw_offset, 3, "dst (%d,%d)\n",
- data[2] & 0xffff, data[2] >> 16);
+ data[3] & 0xffff, data[3] >> 16);
instr_out(data, hw_offset, 4, "dst offset 0x%08x\n", data[4]);
instr_out(data, hw_offset, 5, "src (%d,%d)\n",
data[5] & 0xffff, data[5] >> 16);
instr_out(data, hw_offset, 6, "src pitch %d\n",
- data[6] & 0xffff);
+ (short)(data[6] & 0xffff));
instr_out(data, hw_offset, 7, "src offset 0x%08x\n", data[7]);
return len;
}
--
cgit v1.2.3
From d2d5abfaeb46fc7b4d4267a6c9e92420fc9b5334 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Tue, 22 Jul 2008 15:20:07 -0700
Subject: intel-gem: Use pread/pwrite for span access.
This will avoid clflushing entire buffers for small acesses, such as those
commonly used by regression tests.
---
src/mesa/drivers/dri/common/spantmp2.h | 64 ++++----
src/mesa/drivers/dri/intel/intel_fbo.c | 1 -
src/mesa/drivers/dri/intel/intel_fbo.h | 1 -
src/mesa/drivers/dri/intel/intel_span.c | 272 +++++++++++++-------------------
4 files changed, 141 insertions(+), 197 deletions(-)
diff --git a/src/mesa/drivers/dri/common/spantmp2.h b/src/mesa/drivers/dri/common/spantmp2.h
index 5e51112a20..a1e56eb148 100644
--- a/src/mesa/drivers/dri/common/spantmp2.h
+++ b/src/mesa/drivers/dri/common/spantmp2.h
@@ -48,40 +48,34 @@
#define HW_WRITE_CLIPLOOP() HW_CLIPLOOP()
#endif
-/* Whether GET_PTR(x, y) + cpp != GET_PTR(x+1, y) */
-#ifndef GET_PTR_NONLINEAR
-#define GET_PTR_NONLINEAR 0
-#endif
-
#if (SPANTMP_PIXEL_FMT == GL_RGB) && (SPANTMP_PIXEL_TYPE == GL_UNSIGNED_SHORT_5_6_5)
/**
** GL_RGB, GL_UNSIGNED_SHORT_5_6_5
**/
+#ifndef GET_VALUE
#ifndef GET_PTR
#define GET_PTR(_x, _y) (buf + (_x) * 2 + (_y) * pitch)
#endif
+#define GET_VALUE(_x, _y) *(volatile GLushort *)(GET_PTR(_x, _y))
+#define PUT_VALUE(_x, _y, _v) *(volatile GLushort *)(GET_PTR(_x, _y)) = (_v)
+#endif /* GET_VALUE */
+
#define INIT_MONO_PIXEL(p, color) \
p = PACK_COLOR_565( color[0], color[1], color[2] )
#define WRITE_RGBA( _x, _y, r, g, b, a ) \
- do { \
- GLshort * _p = (GLshort *) GET_PTR(_x, _y); \
- _p[0] = ((((int)r & 0xf8) << 8) | (((int)g & 0xfc) << 3) | \
- (((int)b & 0xf8) >> 3)); \
- } while(0)
+ PUT_VALUE(_x, _y, ((((int)r & 0xf8) << 8) | \
+ (((int)g & 0xfc) << 3) | \
+ (((int)b & 0xf8) >> 3))) \
-#define WRITE_PIXEL( _x, _y, p ) \
- do { \
- GLushort * _p = (GLushort *) GET_PTR(_x, _y); \
- _p[0] = p; \
- } while(0)
+#define WRITE_PIXEL( _x, _y, p ) PUT_VALUE(_x, _y, p)
#define READ_RGBA( rgba, _x, _y ) \
do { \
- GLushort p = *(volatile GLshort *) GET_PTR(_x, _y); \
+ GLushort p = GET_VALUE(_x, _y); \
rgba[0] = ((p >> 8) & 0xf8) * 255 / 0xf8; \
rgba[1] = ((p >> 3) & 0xfc) * 255 / 0xfc; \
rgba[2] = ((p << 3) & 0xf8) * 255 / 0xf8; \
@@ -94,29 +88,30 @@
** GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV
**/
+#ifndef GET_VALUE
#ifndef GET_PTR
#define GET_PTR(_x, _y) ( buf + (_x) * 4 + (_y) * pitch)
#endif
+#define GET_VALUE(_x, _y) *(volatile GLuint *)(GET_PTR(_x, _y))
+#define PUT_VALUE(_x, _y, _v) *(volatile GLuint *)(GET_PTR(_x, _y)) = (_v)
+#endif /* GET_VALUE */
+
# define INIT_MONO_PIXEL(p, color) \
p = PACK_COLOR_8888(color[3], color[0], color[1], color[2])
# define WRITE_RGBA(_x, _y, r, g, b, a) \
- do { \
- GLuint * _p = (GLuint *) GET_PTR(_x, _y); \
- _p[0] = ((r << 16) | (g << 8) | (b << 0) | (a << 24)); \
- } while(0)
+ PUT_VALUE(_x, _y, ((r << 16) | \
+ (g << 8) | \
+ (b << 0) | \
+ (a << 24)))
-#define WRITE_PIXEL(_x, _y, p) \
- do { \
- GLuint * _p = (GLuint *) GET_PTR(_x, _y); \
- _p[0] = p; \
- } while(0)
+#define WRITE_PIXEL(_x, _y, p) PUT_VALUE(_x, _y, p)
# if defined( USE_X86_ASM )
# define READ_RGBA(rgba, _x, _y) \
do { \
- GLuint p = *(volatile GLuint *) GET_PTR(_x, _y); \
+ GLuint p = GET_VALUE(_x, _y); \
__asm__ __volatile__( "bswap %0; rorl $8, %0" \
: "=r" (p) : "0" (p) ); \
((GLuint *)rgba)[0] = p; \
@@ -127,14 +122,14 @@
*/
# define READ_RGBA( rgba, _x, _y ) \
do { \
- GLuint p = *(volatile GLuint *) GET_PTR(_x, _y); \
+ GLuint p = GET_VALUE(_x, _y); \
GLuint t = p; \
*((uint32_t *) rgba) = (t >> 24) | (p << 8); \
} while (0)
# else
# define READ_RGBA( rgba, _x, _y ) \
do { \
- GLuint p = *(volatile GLuint *) GET_PTR(_x, _y); \
+ GLuint p = GET_VALUE(_x, _y); \
rgba[0] = (p >> 16) & 0xff; \
rgba[1] = (p >> 8) & 0xff; \
rgba[2] = (p >> 0) & 0xff; \
@@ -393,7 +388,7 @@ static void TAG(ReadRGBASpan)( GLcontext *ctx,
}
-#if !GET_PTR_NONLINEAR && \
+#if defined(GET_PTR) && \
defined(USE_MMX_ASM) && \
(((SPANTMP_PIXEL_FMT == GL_BGRA) && \
(SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV)) || \
@@ -445,7 +440,7 @@ static void TAG2(ReadRGBASpan,_MMX)( GLcontext *ctx,
#endif
-#if !GET_PTR_NONLINEAR && \
+#if defined(GET_PTR) && \
defined(USE_SSE_ASM) && \
(SPANTMP_PIXEL_FMT == GL_BGRA) && \
(SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV)
@@ -480,7 +475,7 @@ static void TAG2(ReadRGBASpan,_SSE2)( GLcontext *ctx,
}
#endif
-#if !GET_PTR_NONLINEAR && \
+#if defined(GET_PTR) && \
defined(USE_SSE_ASM) && \
(SPANTMP_PIXEL_FMT == GL_BGRA) && \
(SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV)
@@ -574,7 +569,7 @@ static void TAG(InitPointers)(struct gl_renderbuffer *rb)
rb->PutMonoValues = TAG(WriteMonoRGBAPixels);
rb->GetValues = TAG(ReadRGBAPixels);
-#if !GET_PTR_NONLINEAR
+#if defined(GET_PTR)
#if defined(USE_SSE_ASM) && \
(SPANTMP_PIXEL_FMT == GL_BGRA) && \
(SPANTMP_PIXEL_TYPE == GL_UNSIGNED_INT_8_8_8_8_REV)
@@ -604,7 +599,7 @@ static void TAG(InitPointers)(struct gl_renderbuffer *rb)
}
else
#endif
-#endif /* GET_PTR_NONLINEAR */
+#endif /* GET_PTR */
{
if (DBG) fprintf( stderr, "Using %s version of GetRow\n", "C" );
rb->GetRow = TAG(ReadRGBASpan);
@@ -619,7 +614,8 @@ static void TAG(InitPointers)(struct gl_renderbuffer *rb)
#undef READ_RGBA
#undef TAG
#undef TAG2
+#undef GET_VALUE
+#undef PUT_VALUE
#undef GET_PTR
-#undef GET_PTR_NONLINEAR
#undef SPANTMP_PIXEL_FMT
#undef SPANTMP_PIXEL_TYPE
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 7663393fba..d539097a66 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -363,7 +363,6 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb,
intel_region_reference(&rb->region, region);
intel_region_release(&old);
- rb->pfMap = region->map;
rb->pfPitch = region->pitch;
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index 5fe0fd8abf..f55d3747f2 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -70,7 +70,6 @@ struct intel_renderbuffer
{
struct gl_renderbuffer Base;
struct intel_region *region;
- void *pfMap; /* possibly paged flipped map pointer */
GLuint pfPitch; /* possibly paged flipped pitch */
GLboolean RenderToTexture; /* RTT? */
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index c9d413ec43..44e2eff680 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -43,57 +43,72 @@ static void
intel_set_span_functions(struct intel_context *intel,
struct gl_renderbuffer *rb);
-/*
- * Deal with tiled surfaces
- */
+static uint32_t
+pread_32(struct intel_renderbuffer *irb, uint32_t offset)
+{
+ uint32_t val;
-#if 0
-/* These are pre-965 tile swizzling functions -- power of two widths */
-static uintptr_t x_tile_swizzle_pow2 (uintptr_t addr, int n)
+ dri_bo_get_subdata(irb->region->buffer, offset, 4, &val);
+
+ return val;
+}
+
+static uint16_t
+pread_16(struct intel_renderbuffer *irb, uint32_t offset)
{
- uintptr_t a = addr;
- uintptr_t base_mask = (((~0) << (n + 4)) | 0xff);
- uintptr_t x_mask = ((~0) << 12) & ~base_mask;
-
- a = ((a & base_mask) |
- ((a >> (n-8)) & 0x7) |
- ((a << 3) & x_mask));
- _mesa_printf ("x_swizzle %08x (base %x yrow %x tile#x %x xsword %x byte %x) %08x\n",
- addr,
- addr >> (n + 4),
- (addr >> (n + 1)) & 0x7,
- (addr >> 9) & ((1 << (n-8)) - 1),
- (addr >> 5) & 0xf,
- (addr & 0x1f),
- a);
- return a;
+ uint16_t val;
+
+ dri_bo_get_subdata(irb->region->buffer, offset, 2, &val);
+
+ return val;
}
-static uintptr_t y_tile_swizzle_pow2 (uintptr_t addr, int n)
+static uint8_t
+pread_8(struct intel_renderbuffer *irb, uint32_t offset)
{
- uintptr_t a = (uintptr_t) addr;
- uintptr_t base_mask = (((~0) << (n + 6)) | 0xf);
- uintptr_t x_mask = ((~0) << 9) & ~base_mask;
-
- a = ((a & base_mask) |
- ((a >> (n-3)) & 0x1f) |
- ((a << 5) & x_mask));
- _mesa_printf ("y_swizzle %08x (base %x yrow %x tile#x %x xoword %x byte %x) %08x\n",
- addr,
- addr >> (n + 6),
- (addr >> (n + 1)) & 0x01f,
- (addr >> 7) & ((1 << (n-6)) - 1),
- (addr >> 4) & 0x7,
- (addr & 0xf),
- a);
- return a;
+ uint8_t val;
+
+ dri_bo_get_subdata(irb->region->buffer, offset, 1, &val);
+
+ return val;
+}
+
+static void
+pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
+{
+ dri_bo_subdata(irb->region->buffer, offset, 4, &val);
+}
+
+static void
+pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
+{
+ dri_bo_subdata(irb->region->buffer, offset, 2, &val);
+}
+
+static void
+pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
+{
+ dri_bo_subdata(irb->region->buffer, offset, 1, &val);
+}
+
+static uint32_t no_tile_swizzle(struct intel_renderbuffer *irb,
+ struct intel_context *intel,
+ int x, int y)
+{
+ x += intel->drawX;
+ y += intel->drawY;
+
+ return (y * irb->region->pitch + x) * irb->region->cpp;
}
-#endif
-static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_context *intel,
+/*
+ * Deal with tiled surfaces
+ */
+
+static uint32_t x_tile_swizzle(struct intel_renderbuffer *irb,
+ struct intel_context *intel,
int x, int y)
{
- GLubyte *buf = (GLubyte *) irb->pfMap;
int tile_stride;
int xbyte;
int x_tile_off, y_tile_off;
@@ -146,13 +161,13 @@ static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
irb->pfPitch, tile_stride);
#endif
- return buf + tile_base + tile_off;
+ return tile_base + tile_off;
}
-static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_context *intel,
+static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
+ struct intel_context *intel,
int x, int y)
{
- GLubyte *buf = (GLubyte *) irb->pfMap;
int tile_stride;
int xbyte;
int x_tile_off, y_tile_off;
@@ -199,7 +214,7 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
- return buf + tile_base + tile_off;
+ return tile_base + tile_off;
}
/*
@@ -214,11 +229,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
const GLint yScale = irb->RenderToTexture ? 1 : -1; \
const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; \
- GLubyte *buf = (GLubyte *) irb->pfMap \
- + (intel->drawY * irb->pfPitch + intel->drawX) * irb->region->cpp;\
GLuint p; \
- assert(irb->pfMap);\
- (void) p; (void) buf;
+ (void) p;
/* XXX FBO: this is identical to the macro in spantmp2.h except we get
* the cliprect info from the context, not the driDrawable.
@@ -251,7 +263,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
#define TAG(x) intel##x##_RGB565
#define TAG2(x,y) intel##x##_RGB565##y
-#define GET_PTR(X,Y) (buf + ((Y) * irb->pfPitch + (X)) * 2)
+#define GET_VALUE(X, Y) pread_16(irb, no_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_16(irb, no_tile_swizzle(irb, intel, X, Y), V)
#include "spantmp2.h"
/* 32 bit, ARGB8888 color spanline and pixel functions
@@ -261,7 +274,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
#define TAG(x) intel##x##_ARGB8888
#define TAG2(x,y) intel##x##_ARGB8888##y
-#define GET_PTR(X,Y) (buf + ((Y) * irb->pfPitch + (X)) * 4)
+#define GET_VALUE(X, Y) pread_32(irb, no_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_32(irb, no_tile_swizzle(irb, intel, X, Y), V)
#include "spantmp2.h"
/* 16 bit RGB565 color tile spanline and pixel functions
@@ -272,8 +286,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
#define TAG(x) intel_XTile_##x##_RGB565
#define TAG2(x,y) intel_XTile_##x##_RGB565##y
-#define GET_PTR(X,Y) x_tile_swizzle(irb, intel, X, Y)
-#define GET_PTR_NONLINEAR 1
+#define GET_VALUE(X, Y) pread_16(irb, x_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_16(irb, x_tile_swizzle(irb, intel, X, Y), V)
#include "spantmp2.h"
#define SPANTMP_PIXEL_FMT GL_RGB
@@ -281,8 +295,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
#define TAG(x) intel_YTile_##x##_RGB565
#define TAG2(x,y) intel_YTile_##x##_RGB565##y
-#define GET_PTR(X,Y) y_tile_swizzle(irb, intel, X, Y)
-#define GET_PTR_NONLINEAR 1
+#define GET_VALUE(X, Y) pread_16(irb, y_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_16(irb, y_tile_swizzle(irb, intel, X, Y), V)
#include "spantmp2.h"
/* 32 bit ARGB888 color tile spanline and pixel functions
@@ -293,8 +307,8 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
#define TAG(x) intel_XTile_##x##_ARGB8888
#define TAG2(x,y) intel_XTile_##x##_ARGB8888##y
-#define GET_PTR(X,Y) x_tile_swizzle(irb, intel, X, Y)
-#define GET_PTR_NONLINEAR 1
+#define GET_VALUE(X, Y) pread_32(irb, x_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_32(irb, x_tile_swizzle(irb, intel, X, Y), V)
#include "spantmp2.h"
#define SPANTMP_PIXEL_FMT GL_BGRA
@@ -302,18 +316,15 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
#define TAG(x) intel_YTile_##x##_ARGB8888
#define TAG2(x,y) intel_YTile_##x##_ARGB8888##y
-#define GET_PTR(X,Y) y_tile_swizzle(irb, intel, X, Y)
-#define GET_PTR_NONLINEAR 1
+#define GET_VALUE(X, Y) pread_32(irb, y_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_32(irb, y_tile_swizzle(irb, intel, X, Y), V)
#include "spantmp2.h"
#define LOCAL_DEPTH_VARS \
struct intel_context *intel = intel_context(ctx); \
struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
- const GLuint pitch = irb->pfPitch/***XXX region->pitch*/; /* in pixels */ \
const GLint yScale = irb->RenderToTexture ? 1 : -1; \
- const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1; \
- char *buf = (char *) irb->pfMap/*XXX use region->map*/ + \
- (intel->drawY * pitch + intel->drawX) * irb->region->cpp; (void) buf;
+ const GLint yBias = irb->RenderToTexture ? 0 : irb->Base.Height - 1;
#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
@@ -321,13 +332,10 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
/**
** 16-bit depthbuffer functions.
**/
-#define WRITE_DEPTH( _x, _y, d ) \
- ((GLushort *)buf)[(_x) + (_y) * pitch] = d;
-
-#define READ_DEPTH( d, _x, _y ) \
- d = ((GLushort *)buf)[(_x) + (_y) * pitch];
-
-
+#define WRITE_DEPTH(_x, _y, d) \
+ pwrite_16(irb, no_tile_swizzle(irb, intel, _x, _y), d)
+#define READ_DEPTH(d, _x, _y) \
+ d = pread_16(irb, no_tile_swizzle(irb, intel, _x, _y))
#define TAG(x) intel##x##_z16
#include "depthtmp.h"
@@ -335,26 +343,20 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
/**
** 16-bit x tile depthbuffer functions.
**/
-#define WRITE_DEPTH( _x, _y, d ) \
- (*((GLushort *)x_tile_swizzle (irb, intel, _x, _y)) = d)
-
-#define READ_DEPTH( d, _x, _y ) \
- d = *((GLushort *)x_tile_swizzle (irb, intel, _x, _y))
-
-
+#define WRITE_DEPTH(_x, _y, d) \
+ pwrite_16(irb, x_tile_swizzle(irb, intel, _x, _y), d)
+#define READ_DEPTH(d, _x, _y) \
+ d = pread_16(irb, x_tile_swizzle(irb, intel, _x, _y))
#define TAG(x) intel_XTile_##x##_z16
#include "depthtmp.h"
/**
** 16-bit y tile depthbuffer functions.
**/
-#define WRITE_DEPTH( _x, _y, d ) \
- (*((GLushort *)y_tile_swizzle (irb, intel, _x, _y)) = d)
-
-#define READ_DEPTH( d, _x, _y ) \
- (d = *((GLushort *)y_tile_swizzle (irb, intel, _x, _y)))
-
-
+#define WRITE_DEPTH(_x, _y, d) \
+ pwrite_16(irb, y_tile_swizzle(irb, intel, _x, _y), d)
+#define READ_DEPTH(d, _x, _y) \
+ d = pread_16(irb, y_tile_swizzle(irb, intel, _x, _y))
#define TAG(x) intel_YTile_##x##_z16
#include "depthtmp.h"
@@ -366,14 +368,13 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
** and stencil values.
**/
/* Change ZZZS -> SZZZ */
-#define WRITE_DEPTH( _x, _y, d ) { \
- GLuint tmp = ((d) >> 8) | ((d) << 24); \
- ((GLuint *)buf)[(_x) + (_y) * pitch] = tmp; \
-}
+#define WRITE_DEPTH(_x, _y, d) \
+ pwrite_32(irb, no_tile_swizzle(irb, intel, _x, _y), \
+ ((d) >> 8) | ((d) << 24))
/* Change SZZZ -> ZZZS */
#define READ_DEPTH( d, _x, _y ) { \
- GLuint tmp = ((GLuint *)buf)[(_x) + (_y) * pitch]; \
+ GLuint tmp = pread_32(irb, no_tile_swizzle(irb, intel, _x, _y)); \
d = (tmp << 8) | (tmp >> 24); \
}
@@ -388,14 +389,13 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
** and stencil values.
**/
/* Change ZZZS -> SZZZ */
-#define WRITE_DEPTH( _x, _y, d ) { \
- GLuint tmp = ((d) >> 8) | ((d) << 24); \
- *((GLuint *)x_tile_swizzle (irb, intel, _x, _y)) = tmp; \
-}
+#define WRITE_DEPTH(_x, _y, d) \
+ pwrite_32(irb, x_tile_swizzle(irb, intel, _x, _y), \
+ ((d) >> 8) | ((d) << 24)) \
/* Change SZZZ -> ZZZS */
#define READ_DEPTH( d, _x, _y ) { \
- GLuint tmp = *((GLuint *)x_tile_swizzle (irb, intel, _x, _y)); \
+ GLuint tmp = pread_32(irb, x_tile_swizzle(irb, intel, _x, _y)); \
d = (tmp << 8) | (tmp >> 24); \
}
@@ -409,14 +409,13 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
** and stencil values.
**/
/* Change ZZZS -> SZZZ */
-#define WRITE_DEPTH( _x, _y, d ) { \
- GLuint tmp = ((d) >> 8) | ((d) << 24); \
- *((GLuint *)y_tile_swizzle (irb, intel, _x, _y)) = tmp; \
-}
+#define WRITE_DEPTH(_x, _y, d) \
+ pwrite_32(irb, y_tile_swizzle(irb, intel, _x, _y), \
+ ((d) >> 8) | ((d) << 24))
/* Change SZZZ -> ZZZS */
#define READ_DEPTH( d, _x, _y ) { \
- GLuint tmp = *((GLuint *)y_tile_swizzle (irb, intel, _x, _y)); \
+ GLuint tmp = pread_32(irb, y_tile_swizzle(irb, intel, _x, _y)); \
d = (tmp << 8) | (tmp >> 24); \
}
@@ -427,15 +426,11 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
/**
** 8-bit stencil function (XXX FBO: This is obsolete)
**/
-#define WRITE_STENCIL( _x, _y, d ) { \
- GLuint tmp = ((GLuint *)buf)[(_x) + (_y) * pitch]; \
- tmp &= 0xffffff; \
- tmp |= ((d) << 24); \
- ((GLuint *) buf)[(_x) + (_y) * pitch] = tmp; \
-}
+#define WRITE_STENCIL(_x, _y, d) \
+ pwrite_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3, d)
-#define READ_STENCIL( d, _x, _y ) \
- d = ((GLuint *)buf)[(_x) + (_y) * pitch] >> 24;
+#define READ_STENCIL(d, _x, _y) \
+ d = pread_8(irb, no_tile_swizzle(irb, intel, _x, _y) + 3);
#define TAG(x) intel##x##_z24_s8
#include "stenciltmp.h"
@@ -443,16 +438,11 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
/**
** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
**/
-#define WRITE_STENCIL( _x, _y, d ) { \
- GLuint *a = (GLuint *) x_tile_swizzle (irb, intel, _x, _y); \
- GLuint tmp = *a; \
- tmp &= 0xffffff; \
- tmp |= ((d) << 24); \
- *a = tmp; \
-}
+#define WRITE_STENCIL(_x, _y, d) \
+ pwrite_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3, d)
-#define READ_STENCIL( d, _x, _y ) \
- (d = *((GLuint*) x_tile_swizzle (irb, intel, _x, _y)) >> 24)
+#define READ_STENCIL(d, _x, _y) \
+ d = pread_8(irb, x_tile_swizzle(irb, intel, _x, _y) + 3);
#define TAG(x) intel_XTile_##x##_z24_s8
#include "stenciltmp.h"
@@ -460,16 +450,11 @@ static GLubyte *y_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
/**
** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
**/
-#define WRITE_STENCIL( _x, _y, d ) { \
- GLuint *a = (GLuint *) y_tile_swizzle (irb, intel, _x, _y); \
- GLuint tmp = *a; \
- tmp &= 0xffffff; \
- tmp |= ((d) << 24); \
- *a = tmp; \
-}
+#define WRITE_STENCIL(_x, _y, d) \
+ pwrite_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3, d)
-#define READ_STENCIL( d, _x, _y ) \
- (d = *((GLuint*) y_tile_swizzle (irb, intel, _x, _y)) >> 24)
+#define READ_STENCIL(d, _x, _y) \
+ d = pread_8(irb, y_tile_swizzle(irb, intel, _x, _y) + 3)
#define TAG(x) intel_YTile_##x##_z24_s8
#include "stenciltmp.h"
@@ -482,9 +467,6 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb)
if (irb == NULL || irb->region == NULL)
return;
- intel_region_map(intel, irb->region);
-
- irb->pfMap = irb->region->map;
irb->pfPitch = irb->region->pitch;
intel_set_span_functions(intel, rb);
@@ -499,9 +481,6 @@ intel_renderbuffer_unmap(struct intel_context *intel,
if (irb == NULL || irb->region == NULL)
return;
- intel_region_unmap(intel, irb->region);
-
- irb->pfMap = NULL;
irb->pfPitch = 0;
rb->GetRow = NULL;
@@ -559,35 +538,6 @@ intel_map_unmap_buffers(struct intel_context *intel, GLboolean map)
else
intel_renderbuffer_unmap(intel, ctx->ReadBuffer->_ColorReadBuffer);
- /* Account for front/back color page flipping.
- * The span routines use the pfMap and pfPitch fields which will
- * swap the front/back region map/pitch if we're page flipped.
- * Do this after mapping, above, so the map field is valid.
- */
-#if 0
- if (map && ctx->DrawBuffer->Name == 0) {
- struct intel_renderbuffer *irbFront
- = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_FRONT_LEFT);
- struct intel_renderbuffer *irbBack
- = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_BACK_LEFT);
- if (irbBack) {
- /* double buffered */
- if (intel->sarea->pf_current_page == 0) {
- irbFront->pfMap = irbFront->region->map;
- irbFront->pfPitch = irbFront->region->pitch;
- irbBack->pfMap = irbBack->region->map;
- irbBack->pfPitch = irbBack->region->pitch;
- }
- else {
- irbFront->pfMap = irbBack->region->map;
- irbFront->pfPitch = irbBack->region->pitch;
- irbBack->pfMap = irbFront->region->map;
- irbBack->pfPitch = irbFront->region->pitch;
- }
- }
- }
-#endif
-
/* depth buffer (Note wrapper!) */
if (ctx->DrawBuffer->_DepthBuffer) {
if (map)
--
cgit v1.2.3
From 2e3714380027252ba17a11f23eae851d3f77ab02 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Wed, 23 Jul 2008 09:17:07 -0700
Subject: intel: Add a little span cache to spead up readpixels by cutting
syscalls.
---
src/mesa/drivers/dri/intel/intel_fbo.c | 3 +++
src/mesa/drivers/dri/intel/intel_fbo.h | 3 +++
src/mesa/drivers/dri/intel/intel_span.c | 48 ++++++++++++++++++++++++---------
3 files changed, 42 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index d539097a66..254f3efae0 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -153,6 +153,9 @@ intel_delete_renderbuffer(struct gl_renderbuffer *rb)
intel_unpair_depth_stencil(ctx, irb);
}
+ if (irb->span_cache != NULL)
+ _mesa_free(irb->span_cache);
+
if (intel && irb->region) {
intel_region_release(&irb->region);
}
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h
index f55d3747f2..9d15582d78 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.h
+++ b/src/mesa/drivers/dri/intel/intel_fbo.h
@@ -79,6 +79,9 @@ struct intel_renderbuffer
GLuint pf_pending; /**< sequence number of pending flip */
GLuint vbl_pending; /**< vblank sequence number of pending flip */
+
+ uint8_t *span_cache;
+ unsigned long span_cache_offset;
};
extern struct intel_renderbuffer *intel_renderbuffer(struct gl_renderbuffer
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 44e2eff680..06f7c9b4b7 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -43,51 +43,74 @@ static void
intel_set_span_functions(struct intel_context *intel,
struct gl_renderbuffer *rb);
+#define SPAN_CACHE_SIZE 4096
+
+static void
+get_span_cache(struct intel_renderbuffer *irb, uint32_t offset)
+{
+ if (irb->span_cache == NULL) {
+ irb->span_cache = _mesa_malloc(SPAN_CACHE_SIZE);
+ irb->span_cache_offset = -1;
+ }
+
+ if ((offset & ~(SPAN_CACHE_SIZE - 1)) != irb->span_cache_offset) {
+ irb->span_cache_offset = offset & ~(SPAN_CACHE_SIZE - 1);
+ dri_bo_get_subdata(irb->region->buffer, irb->span_cache_offset,
+ SPAN_CACHE_SIZE, irb->span_cache);
+ }
+}
+
+static void
+clear_span_cache(struct intel_renderbuffer *irb)
+{
+ irb->span_cache_offset = -1;
+}
+
static uint32_t
pread_32(struct intel_renderbuffer *irb, uint32_t offset)
{
- uint32_t val;
+ get_span_cache(irb, offset);
- dri_bo_get_subdata(irb->region->buffer, offset, 4, &val);
-
- return val;
+ return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
}
static uint16_t
pread_16(struct intel_renderbuffer *irb, uint32_t offset)
{
- uint16_t val;
-
- dri_bo_get_subdata(irb->region->buffer, offset, 2, &val);
+ get_span_cache(irb, offset);
- return val;
+ return *(uint16_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
}
static uint8_t
pread_8(struct intel_renderbuffer *irb, uint32_t offset)
{
- uint8_t val;
+ get_span_cache(irb, offset);
- dri_bo_get_subdata(irb->region->buffer, offset, 1, &val);
-
- return val;
+ return *(uint8_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
}
static void
pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
{
+ clear_span_cache(irb);
+
dri_bo_subdata(irb->region->buffer, offset, 4, &val);
}
static void
pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
{
+ clear_span_cache(irb);
+
dri_bo_subdata(irb->region->buffer, offset, 2, &val);
}
static void
pwrite_8(struct intel_renderbuffer *irb, uint32_t offset, uint8_t val)
{
+ clear_span_cache(irb);
+
dri_bo_subdata(irb->region->buffer, offset, 1, &val);
}
@@ -481,6 +504,7 @@ intel_renderbuffer_unmap(struct intel_context *intel,
if (irb == NULL || irb->region == NULL)
return;
+ clear_span_cache(irb);
irb->pfPitch = 0;
rb->GetRow = NULL;
--
cgit v1.2.3
From 117533759fc6ee57f65a48e7115d4f564ed167f4 Mon Sep 17 00:00:00 2001
From: Pawel Pieczul
Date: Wed, 23 Jul 2008 15:43:23 -0700
Subject: 965: Fix partially transparent textures in Doom 3 engine games
Numbers of destination depth registers corrected (destination stencil
register was sent as depth register).
---
src/mesa/drivers/dri/i965/brw_wm_emit.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index ba9168b6ef..9b919b9cfe 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -948,15 +948,16 @@ static void emit_fb_write( struct brw_wm_compile *c,
GLuint off = c->key.dest_depth_reg % 2;
if (off != 0) {
- brw_push_insn_state(p);
- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- brw_MOV(p, brw_message_reg(nr), arg1[comp]);
- /* 2nd half? */
- brw_MOV(p, brw_message_reg(nr+1), offset(arg1[comp],1));
- brw_pop_insn_state(p);
+ brw_push_insn_state(p);
+ brw_set_compression_control(p, BRW_COMPRESSION_NONE);
+
+ brw_MOV(p, brw_message_reg(nr), offset(arg1[comp],1));
+ /* 2nd half? */
+ brw_MOV(p, brw_message_reg(nr+1), arg1[comp+1]);
+ brw_pop_insn_state(p);
}
else {
- brw_MOV(p, brw_message_reg(nr), arg1[comp]);
+ brw_MOV(p, brw_message_reg(nr), arg1[comp]);
}
nr += 2;
}
--
cgit v1.2.3
From 9dd73d58ae7850dcfa754cb443093825f00cac9f Mon Sep 17 00:00:00 2001
From: Thomas Hellstrom
Date: Thu, 24 Jul 2008 13:32:59 +0200
Subject: Add new demo "fbo_firecube". Tests fbo render-to-texture for various
internal texture image formats.
---
progs/demos/Makefile | 1 +
progs/demos/fbo_firecube.c | 1041 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 1042 insertions(+)
create mode 100644 progs/demos/fbo_firecube.c
diff --git a/progs/demos/Makefile b/progs/demos/Makefile
index 7fde77f0b4..fedce1cc3d 100644
--- a/progs/demos/Makefile
+++ b/progs/demos/Makefile
@@ -27,6 +27,7 @@ PROGS = \
cubemap \
drawpix \
engine \
+ fbo_firecube \
fire \
fogcoord \
fplight \
diff --git a/progs/demos/fbo_firecube.c b/progs/demos/fbo_firecube.c
new file mode 100644
index 0000000000..0f01476d3f
--- /dev/null
+++ b/progs/demos/fbo_firecube.c
@@ -0,0 +1,1041 @@
+/*
+ * Draw the "fire" test program on the six faces of a cube using
+ * fbo render-to-texture.
+ *
+ * Much of the code comes from David Bucciarelli's "fire"
+ * test program. The rest basically from Brian Paul's "gearbox" and
+ * fbotexture programs.
+ *
+ * By pressing the 'q' key, you can make the driver choose different
+ * internal texture RGBA formats by giving it different "format" and "type"
+ * arguments to the glTexImage2D function that creates the texture
+ * image being rendered to. If the driver doesn't support a texture image
+ * format as a render target, it will usually fall back to software when
+ * drawing the "fire" image, and frame-rate should drop considerably.
+ *
+ * Performance:
+ * The rendering speed of this program is usually dictated by fill rate
+ * and the fact that software fallbacks for glBitMap makes the driver
+ * operate synchronously. Low-end UMA hardware will probably see around
+ * 35 fps with the help screen disabled and 32bpp window- and user
+ * frame-buffers (2008).
+ *
+ * This program is released under GPL, following the "fire" licensing.
+ *
+ * Authors:
+ * David Bucciarelli ("fire")
+ * Brian Paul ("gearbox", "fbotexture")
+ * Thomas Hellstrom (Putting it together)
+ *
+ */
+
+#define GL_GLEXT_PROTOTYPES
+#include
+#include
+#include
+#include
+#include
+#include "readtex.h"
+
+
+/*
+ * Format of texture we render to.
+ */
+
+#define TEXINTFORMAT GL_RGBA
+
+static GLuint texTypes[] =
+ {GL_UNSIGNED_BYTE,
+ GL_UNSIGNED_INT_8_8_8_8_REV,
+ GL_UNSIGNED_SHORT_1_5_5_5_REV,
+ GL_UNSIGNED_SHORT_4_4_4_4_REV,
+ GL_UNSIGNED_INT_8_8_8_8,
+ GL_UNSIGNED_SHORT_5_5_5_1,
+ GL_UNSIGNED_SHORT_4_4_4_4,
+ GL_UNSIGNED_INT_8_8_8_8_REV,
+ GL_UNSIGNED_SHORT_1_5_5_5_REV,
+ GL_UNSIGNED_SHORT_4_4_4_4_REV,
+ GL_UNSIGNED_INT_8_8_8_8,
+ GL_UNSIGNED_SHORT_5_5_5_1,
+ GL_UNSIGNED_SHORT_4_4_4_4,
+ GL_UNSIGNED_SHORT_5_6_5,
+ GL_UNSIGNED_SHORT_5_6_5_REV,
+ GL_UNSIGNED_SHORT_5_6_5,
+ GL_UNSIGNED_SHORT_5_6_5_REV};
+
+static GLuint texFormats[] =
+ {GL_RGBA,
+ GL_RGBA,
+ GL_RGBA,
+ GL_RGBA,
+ GL_RGBA,
+ GL_RGBA,
+ GL_RGBA,
+ GL_BGRA,
+ GL_BGRA,
+ GL_BGRA,
+ GL_BGRA,
+ GL_BGRA,
+ GL_BGRA,
+ GL_RGB,
+ GL_RGB,
+ GL_BGR,
+ GL_BGR};
+
+static const char *texNames[] =
+ {"GL_RGBA GL_UNSIGNED_BYTE",
+ "GL_RGBA GL_UNSIGNED_INT_8_8_8_8_REV",
+ "GL_RGBA GL_UNSIGNED_SHORT_1_5_5_5_REV",
+ "GL_RGBA GL_UNSIGNED_SHORT_4_4_4_4_REV",
+ "GL_RGBA GL_UNSIGNED_INT_8_8_8_8",
+ "GL_RGBA GL_UNSIGNED_INT_5_5_5_1",
+ "GL_RGBA GL_UNSIGNED_INT_4_4_4_4",
+ "GL_BGRA GL_UNSIGNED_INT_8_8_8_8_REV",
+ "GL_BGRA GL_UNSIGNED_SHORT_1_5_5_5_REV",
+ "GL_BGRA GL_UNSIGNED_SHORT_4_4_4_4_REV",
+ "GL_BGRA GL_UNSIGNED_INT_8_8_8_8",
+ "GL_BGRA GL_UNSIGNED_INT_5_5_5_1",
+ "GL_BGRA GL_UNSIGNED_INT_4_4_4_4",
+ "GL_RGB GL_UNSIGNED_INT_5_6_5",
+ "GL_RGB GL_UNSIGNED_INT_5_6_5_REV",
+ "GL_BGR GL_UNSIGNED_INT_5_6_5",
+ "BL_BGR GL_UNSIGNED_INT_5_6_5_REV"};
+
+
+
+
+#ifndef M_PI
+#define M_PI 3.1415926535
+#endif
+
+#define vinit(a,i,j,k) { \
+ (a)[0]=i; \
+ (a)[1]=j; \
+ (a)[2]=k; \
+ }
+
+#define vinit4(a,i,j,k,w) { \
+ (a)[0]=i; \
+ (a)[1]=j; \
+ (a)[2]=k; \
+ (a)[3]=w; \
+ }
+
+
+#define vadds(a,dt,b) { \
+ (a)[0]+=(dt)*(b)[0]; \
+ (a)[1]+=(dt)*(b)[1]; \
+ (a)[2]+=(dt)*(b)[2]; \
+ }
+
+#define vequ(a,b) { \
+ (a)[0]=(b)[0]; \
+ (a)[1]=(b)[1]; \
+ (a)[2]=(b)[2]; \
+ }
+
+#define vinter(a,dt,b,c) { \
+ (a)[0]=(dt)*(b)[0]+(1.0-dt)*(c)[0]; \
+ (a)[1]=(dt)*(b)[1]+(1.0-dt)*(c)[1]; \
+ (a)[2]=(dt)*(b)[2]+(1.0-dt)*(c)[2]; \
+ }
+
+#define clamp(a) ((a) < 0.0 ? 0.0 : ((a) < 1.0 ? (a) : 1.0))
+
+#define vclamp(v) { \
+ (v)[0]=clamp((v)[0]); \
+ (v)[1]=clamp((v)[1]); \
+ (v)[2]=clamp((v)[2]); \
+ }
+
+static GLint WinWidth = 800, WinHeight = 800;
+static GLint TexWidth, TexHeight;
+static GLuint TexObj;
+static GLuint MyFB;
+static GLuint DepthRB;
+static GLboolean WireFrame = GL_FALSE;
+static GLint texType = 0;
+
+static GLint T0 = 0;
+static GLint Frames = 0;
+static GLint Win = 0;
+
+static GLfloat ViewRotX = 20.0, ViewRotY = 30.0, ViewRotZ = 0.0;
+static GLfloat CubeRot = 0.0;
+
+static void
+CheckError(int line)
+{
+ GLenum err = glGetError();
+ if (err) {
+ printf("GL Error 0x%x at line %d\n", (int) err, line);
+ exit(1);
+ }
+}
+
+
+static void
+cleanup(void)
+{
+ glBindFramebufferEXT(GL_FRAMEBUFFER_EXT, 0);
+ glDeleteFramebuffersEXT(1, &MyFB);
+ glDeleteRenderbuffersEXT(1, &DepthRB);
+ glDeleteTextures(1, &TexObj);
+ glutDestroyWindow(Win);
+}
+
+static GLint NiceFog = 1;
+
+#define DIMP 20.0
+#define DIMTP 16.0
+
+#define RIDCOL 0.4
+
+#define NUMTREE 50
+#define TREEINR 2.5
+#define TREEOUTR 8.0
+
+#define AGRAV -9.8
+
+typedef struct
+{
+ int age;
+ float p[3][3];
+ float v[3];
+ float c[3][4];
+}
+ part;
+
+static float treepos[NUMTREE][3];
+
+static float black[3] = { 0.0, 0.0, 0.0 };
+static float blu[3] = { 1.0, 0.2, 0.0 };
+static float blu2[3] = { 1.0, 1.0, 0.0 };
+
+static float fogcolor[4] = { 1.0, 1.0, 1.0, 1.0 };
+
+static float q[4][3] = {
+ {-DIMP, 0.0, -DIMP},
+ {DIMP, 0.0, -DIMP},
+ {DIMP, 0.0, DIMP},
+ {-DIMP, 0.0, DIMP}
+};
+
+static float qt[4][2] = {
+ {-DIMTP, -DIMTP},
+ {DIMTP, -DIMTP},
+ {DIMTP, DIMTP},
+ {-DIMTP, DIMTP}
+};
+
+static int np;
+static float eject_r, dt, maxage, eject_vy, eject_vl;
+static short shadows;
+static float ridtri;
+static int fog = 0;
+static int help = 1;
+
+static part *p;
+
+static GLuint groundid;
+static GLuint treeid;
+
+static float obs[3] = { 2.0, 1.0, 0.0 };
+static float dir[3];
+static float v = 0.0;
+static float alpha = -84.0;
+static float beta = 90.0;
+
+static float
+vrnd(void)
+{
+ return (((float) rand()) / RAND_MAX);
+}
+
+static void
+setnewpart(part * p)
+{
+ float a, v[3], *c;
+
+ p->age = 0;
+
+ a = vrnd() * 3.14159265359 * 2.0;
+
+ vinit(v, sin(a) * eject_r * vrnd(), 0.15, cos(a) * eject_r * vrnd());
+ vinit(p->p[0], v[0] + vrnd() * ridtri, v[1] + vrnd() * ridtri,
+ v[2] + vrnd() * ridtri);
+ vinit(p->p[1], v[0] + vrnd() * ridtri, v[1] + vrnd() * ridtri,
+ v[2] + vrnd() * ridtri);
+ vinit(p->p[2], v[0] + vrnd() * ridtri, v[1] + vrnd() * ridtri,
+ v[2] + vrnd() * ridtri);
+
+ vinit(p->v, v[0] * eject_vl / (eject_r / 2),
+ vrnd() * eject_vy + eject_vy / 2, v[2] * eject_vl / (eject_r / 2));
+
+ c = blu;
+
+ vinit4(p->c[0], c[0] * ((1.0 - RIDCOL) + vrnd() * RIDCOL),
+ c[1] * ((1.0 - RIDCOL) + vrnd() * RIDCOL),
+ c[2] * ((1.0 - RIDCOL) + vrnd() * RIDCOL), 1.0);
+ vinit4(p->c[1], c[0] * ((1.0 - RIDCOL) + vrnd() * RIDCOL),
+ c[1] * ((1.0 - RIDCOL) + vrnd() * RIDCOL),
+ c[2] * ((1.0 - RIDCOL) + vrnd() * RIDCOL), 1.0);
+ vinit4(p->c[2], c[0] * ((1.0 - RIDCOL) + vrnd() * RIDCOL),
+ c[1] * ((1.0 - RIDCOL) + vrnd() * RIDCOL),
+ c[2] * ((1.0 - RIDCOL) + vrnd() * RIDCOL), 1.0);
+}
+
+static void
+setpart(part * p)
+{
+ float fact;
+
+ if (p->p[0][1] < 0.1) {
+ setnewpart(p);
+ return;
+ }
+
+ p->v[1] += AGRAV * dt;
+
+ vadds(p->p[0], dt, p->v);
+ vadds(p->p[1], dt, p->v);
+ vadds(p->p[2], dt, p->v);
+
+ p->age++;
+
+ if ((p->age) > maxage) {
+ vequ(p->c[0], blu2);
+ vequ(p->c[1], blu2);
+ vequ(p->c[2], blu2);
+ }
+ else {
+ fact = 1.0 / maxage;
+ vadds(p->c[0], fact, blu2);
+ vclamp(p->c[0]);
+ p->c[0][3] = fact * (maxage - p->age);
+
+ vadds(p->c[1], fact, blu2);
+ vclamp(p->c[1]);
+ p->c[1][3] = fact * (maxage - p->age);
+
+ vadds(p->c[2], fact, blu2);
+ vclamp(p->c[2]);
+ p->c[2][3] = fact * (maxage - p->age);
+ }
+}
+
+static void
+drawtree(float x, float y, float z)
+{
+ glBegin(GL_QUADS);
+ glTexCoord2f(0.0, 0.0);
+ glVertex3f(x - 1.5, y + 0.0, z);
+
+ glTexCoord2f(1.0, 0.0);
+ glVertex3f(x + 1.5, y + 0.0, z);
+
+ glTexCoord2f(1.0, 1.0);
+ glVertex3f(x + 1.5, y + 3.0, z);
+
+ glTexCoord2f(0.0, 1.0);
+ glVertex3f(x - 1.5, y + 3.0, z);
+
+
+ glTexCoord2f(0.0, 0.0);
+ glVertex3f(x, y + 0.0, z - 1.5);
+
+ glTexCoord2f(1.0, 0.0);
+ glVertex3f(x, y + 0.0, z + 1.5);
+
+ glTexCoord2f(1.0, 1.0);
+ glVertex3f(x, y + 3.0, z + 1.5);
+
+ glTexCoord2f(0.0, 1.0);
+ glVertex3f(x, y + 3.0, z - 1.5);
+
+ glEnd();
+
+}
+
+static void
+calcposobs(void)
+{
+ dir[0] = sin(alpha * M_PI / 180.0);
+ dir[2] = cos(alpha * M_PI / 180.0) * sin(beta * M_PI / 180.0);
+ dir[1] = cos(beta * M_PI / 180.0);
+
+ if (dir[0] < 1.0e-5 && dir[0] > -1.0e-5)
+ dir[0] = 0;
+ if (dir[1] < 1.0e-5 && dir[1] > -1.0e-5)
+ dir[1] = 0;
+ if (dir[2] < 1.0e-5 && dir[2] > -1.0e-5)
+ dir[2] = 0;
+
+ obs[0] += v * dir[0];
+ obs[1] += v * dir[1];
+ obs[2] += v * dir[2];
+}
+
+static void
+printstring(void *font, const char *string)
+{
+ int len, i;
+
+ len = (int) strlen(string);
+ for (i = 0; i < len; i++)
+ glutBitmapCharacter(font, string[i]);
+}
+
+
+static void
+printhelp(void)
+{
+ glColor4f(0.0, 0.0, 0.0, 0.5);
+ glRecti(40, 40, 600, 440);
+
+ glColor3f(1.0, 0.0, 0.0);
+ glRasterPos2i(300, 420);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "Help");
+
+ glRasterPos2i(60, 390);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "h - Toggle Help");
+
+ glRasterPos2i(60, 360);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "t - Increase particle size");
+ glRasterPos2i(60, 330);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "T - Decrease particle size");
+
+ glRasterPos2i(60, 300);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "r - Increase emission radius");
+ glRasterPos2i(60, 270);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "R - Decrease emission radius");
+
+ glRasterPos2i(60, 240);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "f - Toggle Fog");
+ glRasterPos2i(60, 210);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "s - Toggle shadows");
+ glRasterPos2i(60, 180);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "q - Toggle texture format & type");
+ glRasterPos2i(60, 150);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "a - Increase velocity");
+ glRasterPos2i(60, 120);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "z - Decrease velocity");
+ glRasterPos2i(60, 90);
+ printstring(GLUT_BITMAP_TIMES_ROMAN_24, "Arrow Keys - Rotate");
+}
+
+
+static void
+drawfire(void)
+{
+ static char frbuf[80] = "";
+ int j;
+ static double t0 = -1.;
+ double t = glutGet(GLUT_ELAPSED_TIME) / 1000.0;
+ if (t0 < 0.0)
+ t0 = t;
+ dt = (t - t0) * 1.0;
+ t0 = t;
+
+ glBindFramebufferEXT(GL_FRAMEBUFFER_EXT, MyFB);
+
+ glDisable(GL_LIGHTING);
+
+ glShadeModel(GL_FLAT);
+
+ glEnable(GL_BLEND);
+ glBlendFunc(GL_SRC_ALPHA, GL_ONE_MINUS_SRC_ALPHA);
+
+ glEnable(GL_FOG);
+ glFogi(GL_FOG_MODE, GL_EXP);
+ glFogfv(GL_FOG_COLOR, fogcolor);
+ glFogf(GL_FOG_DENSITY, 0.1);
+
+
+ glViewport(0, 0, (GLint) TexWidth, (GLint) TexHeight);
+ glMatrixMode(GL_PROJECTION);
+ glLoadIdentity();
+ gluPerspective(70.0, TexWidth/ (float) TexHeight, 0.1, 30.0);
+
+ glMatrixMode(GL_MODELVIEW);
+ glLoadIdentity();
+
+ if (NiceFog)
+ glHint(GL_FOG_HINT, GL_NICEST);
+ else
+ glHint(GL_FOG_HINT, GL_DONT_CARE);
+
+ glEnable(GL_DEPTH_TEST);
+
+ if (fog)
+ glEnable(GL_FOG);
+ else
+ glDisable(GL_FOG);
+
+ glDepthMask(GL_TRUE);
+ glClearColor(1.0, 1.0, 1.0, 1.0);
+ glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT);
+
+
+ glPushMatrix();
+ calcposobs();
+ gluLookAt(obs[0], obs[1], obs[2],
+ obs[0] + dir[0], obs[1] + dir[1], obs[2] + dir[2],
+ 0.0, 1.0, 0.0);
+
+ glColor4f(1.0, 1.0, 1.0, 1.0);
+
+ glEnable(GL_TEXTURE_2D);
+
+ glBindTexture(GL_TEXTURE_2D, groundid);
+ glBegin(GL_QUADS);
+ glTexCoord2fv(qt[0]);
+ glVertex3fv(q[0]);
+ glTexCoord2fv(qt[1]);
+ glVertex3fv(q[1]);
+ glTexCoord2fv(qt[2]);
+ glVertex3fv(q[2]);
+ glTexCoord2fv(qt[3]);
+ glVertex3fv(q[3]);
+ glEnd();
+
+ glEnable(GL_ALPHA_TEST);
+ glAlphaFunc(GL_GEQUAL, 0.9);
+
+ glBindTexture(GL_TEXTURE_2D, treeid);
+ for (j = 0; j < NUMTREE; j++)
+ drawtree(treepos[j][0], treepos[j][1], treepos[j][2]);
+
+ glDisable(GL_TEXTURE_2D);
+ glDepthMask(GL_FALSE);
+ glDisable(GL_ALPHA_TEST);
+
+ if (shadows) {
+ glBegin(GL_TRIANGLES);
+ for (j = 0; j < np; j++) {
+ glColor4f(black[0], black[1], black[2], p[j].c[0][3]);
+ glVertex3f(p[j].p[0][0], 0.1, p[j].p[0][2]);
+
+ glColor4f(black[0], black[1], black[2], p[j].c[1][3]);
+ glVertex3f(p[j].p[1][0], 0.1, p[j].p[1][2]);
+
+ glColor4f(black[0], black[1], black[2], p[j].c[2][3]);
+ glVertex3f(p[j].p[2][0], 0.1, p[j].p[2][2]);
+ }
+ glEnd();
+ }
+
+ glBegin(GL_TRIANGLES);
+ for (j = 0; j < np; j++) {
+ glColor4fv(p[j].c[0]);
+ glVertex3fv(p[j].p[0]);
+
+ glColor4fv(p[j].c[1]);
+ glVertex3fv(p[j].p[1]);
+
+ glColor4fv(p[j].c[2]);
+ glVertex3fv(p[j].p[2]);
+
+ setpart(&p[j]);
+ }
+ glEnd();
+
+
+ glDisable(GL_TEXTURE_2D);
+ glDisable(GL_ALPHA_TEST);
+ glDisable(GL_DEPTH_TEST);
+ glDisable(GL_FOG);
+
+ glMatrixMode(GL_PROJECTION);
+ glLoadIdentity();
+ glOrtho(-0.5, 639.5, -0.5, 479.5
+ , -1.0, 1.0);
+ glMatrixMode(GL_MODELVIEW);
+ glLoadIdentity();
+
+ glColor3f(1.0, 0.0, 0.0);
+ glRasterPos2i(10, 10);
+ printstring(GLUT_BITMAP_HELVETICA_18, frbuf);
+ glColor3f(0.0, 0.0, 1.0);
+ glRasterPos2i(10, 450);
+ printstring(GLUT_BITMAP_HELVETICA_18, texNames[texType]);
+ glColor3f(1.0, 0.0, 0.0);
+ glRasterPos2i(10, 470);
+ printstring(GLUT_BITMAP_HELVETICA_10,
+ "Fire V1.5 Written by David Bucciarelli (tech.hmw@plus.it)");
+
+ if (help)
+ printhelp();
+
+ glPopMatrix();
+ glDepthMask(GL_TRUE);
+ glBindFramebufferEXT(GL_FRAMEBUFFER_EXT, 0);
+ Frames++;
+
+ {
+ GLint t = glutGet(GLUT_ELAPSED_TIME);
+ if (t - T0 >= 2000) {
+ GLfloat seconds = (t - T0) / 1000.0;
+ GLfloat fps = Frames / seconds;
+ sprintf(frbuf, "Frame rate: %f", fps);
+ T0 = t;
+ Frames = 0;
+ }
+ }
+
+}
+
+static void
+regen_texImage(void)
+{
+ glBindTexture(GL_TEXTURE_2D, TexObj);
+ glTexImage2D(GL_TEXTURE_2D, 0, TEXINTFORMAT, TexWidth, TexHeight, 0,
+ texFormats[texType], texTypes[texType], NULL);
+ glBindFramebufferEXT(GL_FRAMEBUFFER_EXT, MyFB);
+ glFramebufferTexture2DEXT(GL_FRAMEBUFFER_EXT, GL_COLOR_ATTACHMENT0_EXT,
+ GL_TEXTURE_2D, TexObj, 0);
+ glBindFramebufferEXT(GL_FRAMEBUFFER_EXT, 0);
+}
+
+static void
+key(unsigned char key, int x, int y)
+{
+ switch (key) {
+ case 27:
+ cleanup();
+ exit(0);
+ break;
+
+ case 'a':
+ v += 0.0005;
+ break;
+ case 'z':
+ v -= 0.0005;
+ break;
+ case 'h':
+ help = (!help);
+ break;
+ case 'f':
+ fog = (!fog);
+ break;
+ case 's':
+ shadows = !shadows;
+ break;
+ case 'R':
+ eject_r -= 0.03;
+ break;
+ case 'r':
+ eject_r += 0.03;
+ break;
+ case 't':
+ ridtri += 0.005;
+ break;
+ case 'T':
+ ridtri -= 0.005;
+ break;
+ case 'v':
+ ViewRotZ += 5.0;
+ break;
+ case 'V':
+ ViewRotZ -= 5.0;
+ break;
+ case 'w':
+ WireFrame = !WireFrame;
+ break;
+ case 'q':
+ if (++texType > 16)
+ texType = 0;
+ regen_texImage();
+ break;
+ case 'n':
+ NiceFog = !NiceFog;
+ printf("NiceFog %d\n", NiceFog);
+ break;
+ }
+ glutPostRedisplay();
+}
+
+static void
+inittextures(void)
+{
+ GLenum gluerr;
+ GLubyte tex[128][128][4];
+
+ glGenTextures(1, &groundid);
+ glBindTexture(GL_TEXTURE_2D, groundid);
+
+ glPixelStorei(GL_UNPACK_ALIGNMENT, 4);
+ if (!LoadRGBMipmaps("../images/s128.rgb", GL_RGB)) {
+ fprintf(stderr, "Error reading a texture.\n");
+ exit(-1);
+ }
+
+ glTexParameterf(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_REPEAT);
+ glTexParameterf(GL_TEXTURE_2D, GL_TEXTURE_WRAP_T, GL_REPEAT);
+
+ glTexParameterf(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER,
+ GL_LINEAR_MIPMAP_LINEAR);
+ glTexParameterf(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_LINEAR);
+
+ glTexEnvf(GL_TEXTURE_ENV, GL_TEXTURE_ENV_MODE, GL_DECAL);
+
+ glGenTextures(1, &treeid);
+ glBindTexture(GL_TEXTURE_2D, treeid);
+
+ if (1)
+ {
+ int w, h;
+ GLenum format;
+ int x, y;
+ GLubyte *image = LoadRGBImage("../images/tree3.rgb", &w, &h, &format);
+
+ if (!image) {
+ fprintf(stderr, "Error reading a texture.\n");
+ exit(-1);
+ }
+
+ for (y = 0; y < 128; y++)
+ for (x = 0; x < 128; x++) {
+ tex[x][y][0] = image[(y + x * 128) * 3];
+ tex[x][y][1] = image[(y + x * 128) * 3 + 1];
+ tex[x][y][2] = image[(y + x * 128) * 3 + 2];
+ if ((tex[x][y][0] == tex[x][y][1]) &&
+ (tex[x][y][1] == tex[x][y][2]) && (tex[x][y][2] == 255))
+ tex[x][y][3] = 0;
+ else
+ tex[x][y][3] = 255;
+ }
+
+ if ((gluerr = gluBuild2DMipmaps(GL_TEXTURE_2D, 4, 128, 128, GL_RGBA,
+ GL_UNSIGNED_BYTE, (GLvoid *) (tex)))) {
+ fprintf(stderr, "GLULib%s\n", (char *) gluErrorString(gluerr));
+ exit(-1);
+ }
+ }
+ else {
+ if (!LoadRGBMipmaps("../images/tree2.rgba", GL_RGBA)) {
+ fprintf(stderr, "Error reading a texture.\n");
+ exit(-1);
+ }
+ }
+
+ glTexParameterf(GL_TEXTURE_2D, GL_TEXTURE_WRAP_S, GL_REPEAT);
+ glTexParameterf(GL_TEXTURE_2D, GL_TEXTURE_WRAP_T, GL_REPEAT);
+
+ glTexParameterf(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER,
+ GL_LINEAR_MIPMAP_LINEAR);
+ glTexParameterf(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_LINEAR);
+
+ glTexEnvf(GL_TEXTURE_ENV, GL_TEXTURE_ENV_MODE, GL_MODULATE);
+}
+
+static void
+inittree(void)
+{
+ int i;
+ float dist;
+
+ for (i = 0; i < NUMTREE; i++)
+ do {
+ treepos[i][0] = vrnd() * TREEOUTR * 2.0 - TREEOUTR;
+ treepos[i][1] = 0.0;
+ treepos[i][2] = vrnd() * TREEOUTR * 2.0 - TREEOUTR;
+ dist =
+ sqrt(treepos[i][0] * treepos[i][0] +
+ treepos[i][2] * treepos[i][2]);
+ } while ((dist < TREEINR) || (dist > TREEOUTR));
+}
+
+static int
+init_fire(int ac, char *av[])
+{
+ int i;
+
+ np = 800;
+ eject_r = -0.65;
+ dt = 0.015;
+ eject_vy = 4;
+ eject_vl = 1;
+ shadows = 1;
+ ridtri = 0.25;
+
+ maxage = 1.0 / dt;
+
+ if (ac == 2)
+ np = atoi(av[1]);
+
+
+ inittextures();
+
+ p = (part *) malloc(sizeof(part) * np);
+
+ for (i = 0; i < np; i++)
+ setnewpart(&p[i]);
+
+ inittree();
+
+ return (0);
+}
+
+
+
+
+
+
+static void
+DrawCube(void)
+{
+ static const GLfloat texcoords[4][2] = {
+ { 0, 0 }, { 1, 0 }, { 1, 1 }, { 0, 1 }
+ };
+ static const GLfloat vertices[4][2] = {
+ { -1, -1 }, { 1, -1 }, { 1, 1 }, { -1, 1 }
+ };
+ static const GLfloat xforms[6][4] = {
+ { 0, 0, 1, 0 },
+ { 90, 0, 1, 0 },
+ { 180, 0, 1, 0 },
+ { 270, 0, 1, 0 },
+ { 90, 1, 0, 0 },
+ { -90, 1, 0, 0 }
+ };
+ static const GLfloat mat[4] = { 1.0, 1.0, 0.5, 1.0 };
+ GLint i, j;
+
+ glMaterialfv(GL_FRONT_AND_BACK, GL_AMBIENT_AND_DIFFUSE, mat);
+ glEnable(GL_TEXTURE_2D);
+
+ glPushMatrix();
+ glRotatef(ViewRotX, 1.0, 0.0, 0.0);
+ glRotatef(15, 1, 0, 0);
+ glRotatef(CubeRot, 0, 1, 0);
+ glScalef(4, 4, 4);
+
+ for (i = 0; i < 6; i++) {
+ glPushMatrix();
+ glRotatef(xforms[i][0], xforms[i][1], xforms[i][2], xforms[i][3]);
+ glTranslatef(0, 0, 1.1);
+ glBegin(GL_POLYGON);
+ glNormal3f(0, 0, 1);
+ for (j = 0; j < 4; j++) {
+ glTexCoord2fv(texcoords[j]);
+ glVertex2fv(vertices[j]);
+ }
+ glEnd();
+ glPopMatrix();
+ }
+ glPopMatrix();
+
+ glDisable(GL_TEXTURE_2D);
+}
+
+
+static void
+draw(void)
+{
+ float ar;
+ static GLfloat pos[4] = {5.0, 5.0, 10.0, 0.0};
+
+ drawfire();
+
+ glLightfv(GL_LIGHT0, GL_POSITION, pos);
+ glLightModeli(GL_LIGHT_MODEL_COLOR_CONTROL,
+ GL_SEPARATE_SPECULAR_COLOR);
+
+ glEnable(GL_LIGHTING);
+ glEnable(GL_LIGHT0);
+ glEnable(GL_DEPTH_TEST);
+ glEnable(GL_NORMALIZE);
+ glDisable(GL_BLEND);
+ glDisable(GL_FOG);
+
+ glMatrixMode(GL_MODELVIEW);
+ glLoadIdentity();
+ glTranslatef(0.0, 0.0, -40.0);
+
+ glClear(GL_DEPTH_BUFFER_BIT);
+
+ /* draw textured cube */
+
+ glViewport(0, 0, WinWidth, WinHeight);
+ glClearColor(0.5, 0.5, 0.8, 0.0);
+ glClear(GL_COLOR_BUFFER_BIT);
+
+ ar = (float) (WinWidth) / WinHeight;
+ glMatrixMode(GL_PROJECTION);
+ glLoadIdentity();
+ glFrustum(-ar, ar, -1.0, 1.0, 5.0, 60.0);
+ glMatrixMode(GL_MODELVIEW);
+ glBindTexture(GL_TEXTURE_2D, TexObj);
+
+ DrawCube();
+
+ /* finish up */
+ glutSwapBuffers();
+}
+
+
+static void
+idle(void)
+{
+ static double t0 = -1.;
+ double dt, t = glutGet(GLUT_ELAPSED_TIME) / 1000.0;
+ if (t0 < 0.0)
+ t0 = t;
+ dt = t - t0;
+ t0 = t;
+
+ CubeRot = fmod(CubeRot + 15.0 * dt, 360.0); /* 15 deg/sec */
+
+ glutPostRedisplay();
+}
+
+
+/* change view angle */
+static void
+special(int k, int x, int y)
+{
+ (void) x;
+ (void) y;
+ switch (k) {
+ case GLUT_KEY_UP:
+ ViewRotX += 5.0;
+ break;
+ case GLUT_KEY_DOWN:
+ ViewRotX -= 5.0;
+ break;
+ case GLUT_KEY_LEFT:
+ ViewRotY += 5.0;
+ break;
+ case GLUT_KEY_RIGHT:
+ ViewRotY -= 5.0;
+ break;
+ default:
+ return;
+ }
+ glutPostRedisplay();
+}
+
+
+/* new window size or exposure */
+static void
+reshape(int width, int height)
+{
+ WinWidth = width;
+ WinHeight = height;
+}
+
+
+static void
+init_fbotexture()
+{
+ GLint i;
+
+ /* gen framebuffer id, delete it, do some assertions, just for testing */
+ glGenFramebuffersEXT(1, &MyFB);
+ glBindFramebufferEXT(GL_FRAMEBUFFER_EXT, MyFB);
+ glGetIntegerv(GL_FRAMEBUFFER_BINDING_EXT, &i);
+
+ /* Make texture object/image */
+ glGenTextures(1, &TexObj);
+ glBindTexture(GL_TEXTURE_2D, TexObj);
+ /* make one image level. */
+ glTexImage2D(GL_TEXTURE_2D, 0, TEXINTFORMAT, TexWidth, TexHeight, 0,
+ texFormats[texType], texTypes[texType], NULL);
+
+ glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MIN_FILTER, GL_NEAREST);
+ glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_NEAREST);
+ glTexEnvi(GL_TEXTURE_ENV, GL_TEXTURE_ENV_MODE, GL_MODULATE);
+ glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_BASE_LEVEL, 0);
+ glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAX_LEVEL, 0);
+
+ CheckError(__LINE__);
+
+ /* Render color to texture */
+ glFramebufferTexture2DEXT(GL_FRAMEBUFFER_EXT, GL_COLOR_ATTACHMENT0_EXT,
+ GL_TEXTURE_2D, TexObj, 0);
+ CheckError(__LINE__);
+
+
+ /* make depth renderbuffer */
+ glGenRenderbuffersEXT(1, &DepthRB);
+ glBindRenderbufferEXT(GL_RENDERBUFFER_EXT, DepthRB);
+ glRenderbufferStorageEXT(GL_RENDERBUFFER_EXT, GL_DEPTH_COMPONENT16,
+ TexWidth, TexHeight);
+ CheckError(__LINE__);
+ glGetRenderbufferParameterivEXT(GL_RENDERBUFFER_EXT,
+ GL_RENDERBUFFER_DEPTH_SIZE_EXT, &i);
+ CheckError(__LINE__);
+ printf("Depth renderbuffer size = %d bits\n", i);
+
+ /* attach DepthRB to MyFB */
+ glFramebufferRenderbufferEXT(GL_FRAMEBUFFER_EXT, GL_DEPTH_ATTACHMENT_EXT,
+ GL_RENDERBUFFER_EXT, DepthRB);
+ CheckError(__LINE__);
+ glBindFramebufferEXT(GL_FRAMEBUFFER_EXT, 0);
+
+ /*
+ * Check for completeness.
+ */
+
+}
+
+
+static void
+init(int argc, char *argv[])
+{
+ GLint i;
+
+ if (!glutExtensionSupported("GL_EXT_framebuffer_object")) {
+ fprintf(stderr, "Sorry, GL_EXT_framebuffer_object is required!\n");
+ exit(1);
+ }
+
+ TexWidth = 512;
+ TexHeight = 512;
+
+ init_fbotexture();
+ init_fire(argc, argv);
+
+
+ for ( i=1; i
Date: Thu, 24 Jul 2008 13:35:35 +0200
Subject: Fix a typo.
---
progs/demos/fbo_firecube.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/progs/demos/fbo_firecube.c b/progs/demos/fbo_firecube.c
index 0f01476d3f..ed87dd133c 100644
--- a/progs/demos/fbo_firecube.c
+++ b/progs/demos/fbo_firecube.c
@@ -99,7 +99,7 @@ static const char *texNames[] =
"GL_RGB GL_UNSIGNED_INT_5_6_5",
"GL_RGB GL_UNSIGNED_INT_5_6_5_REV",
"GL_BGR GL_UNSIGNED_INT_5_6_5",
- "BL_BGR GL_UNSIGNED_INT_5_6_5_REV"};
+ "GL_BGR GL_UNSIGNED_INT_5_6_5_REV"};
--
cgit v1.2.3
From 6118d830a63d1637587671bdfa9810f3e31c24e7 Mon Sep 17 00:00:00 2001
From: Ian Romanick
Date: Thu, 24 Jul 2008 08:39:51 -0700
Subject: Revert "965: Fix color clamping issues"
This reverts commit b993d539a76e7f1446890a85e4b61deec4d4162d. The
patch was applied incorrectly. Actual fix coming soon. Sorry for the
noise.
---
src/mesa/drivers/dri/i965/brw_vs_emit.c | 26 +++-----------------------
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 8c7bc98c61..7767d1369c 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1160,29 +1160,9 @@ void brw_vs_emit(struct brw_vs_compile *c )
}
if (inst->DstReg.File == PROGRAM_OUTPUT
- && inst->DstReg.Index != VERT_RESULT_HPOS
- && c->output_regs[inst->DstReg.Index].used_in_src) {
- /* Result color clamping.
- *
- * When destination register is an output register and it's
- * primary/secondary front/back color, we have to clamp the result
- * to [0,1]. This is done by enabling the saturation bit for the
- * last instruction.
- *
- * We don't use brw_set_saturate() as it modifies
- * p->current->header.saturate, which affects all the subsequent
- * instructions. Instead, we directly modify the header of the last
- * (already stored) instruction.
- */
- if (inst->DstReg.File == PROGRAM_OUTPUT) {
- if ((inst->DstReg.Index == VERT_RESULT_COL0) ||
- (inst->DstReg.Index == VERT_RESULT_COL1) ||
- (inst->DstReg.Index == VERT_RESULT_BFC0) ||
- (inst->DstReg.Index == VERT_RESULT_BFC1)) {
- p->store[p->nr_insn-1].header.saturate = 1;
- }
- }
- }
+ &&inst->DstReg.Index != VERT_RESULT_HPOS
+ &&c->output_regs[inst->DstReg.Index].used_in_src)
+ brw_MOV(p, get_dst(c, inst->DstReg), dst);
release_tmps(c);
}
--
cgit v1.2.3
From 9a4be9785f932bedf727fbf88244ac1b158b09a5 Mon Sep 17 00:00:00 2001
From: Jesse Barnes
Date: Thu, 24 Jul 2008 09:11:37 -0700
Subject: intel: remove buffer swap debug output
Accidentally pushed as part of the last commit.
---
src/mesa/drivers/dri/intel/intel_buffers.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c
index 348c490af0..75542a9775 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -709,10 +709,8 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target)
if (!dPriv->vblFlags ||
(dPriv->vblFlags & VBLANK_FLAG_NO_IRQ) ||
- intelScreen->drmMinor < (intel_fb->pf_active ? 9 : 6)) {
- printf("swap schedule failed: bad flags or drm minor\n");
+ intelScreen->drmMinor < (intel_fb->pf_active ? 9 : 6))
return GL_FALSE;
- }
interval = driGetVBlankInterval(dPriv);
@@ -720,10 +718,8 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target)
if (dPriv->vblFlags & VBLANK_FLAG_SYNC) {
swap.seqtype |= DRM_VBLANK_NEXTONMISS;
- } else if (interval == 0) {
- printf("swap schedule failed: bad interval\n");
+ } else if (interval == 0)
return GL_FALSE;
- }
swap.drawable = dPriv->hHWDrawable;
target = swap.sequence = dPriv->vblSeq + interval;
@@ -769,7 +765,6 @@ intelScheduleSwap(__DRIdrawablePrivate * dPriv, GLboolean *missed_target)
}
ret = GL_FALSE;
- printf("swap schedule failed: vblank swap failed\n");
}
UNLOCK_HARDWARE(intel);
@@ -799,7 +794,6 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv)
_mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */
if (!intelScheduleSwap(dPriv, &missed_target)) {
- printf("schedule swap failed, trying to wait manually\n");
driWaitForVBlank(dPriv, &missed_target);
/*
--
cgit v1.2.3
From 51bfb6aa992043f780a1641e6d53282374526c66 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Thu, 24 Jul 2008 14:27:11 -0600
Subject: query/print GLSL version string
---
progs/xdemos/glxinfo.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/progs/xdemos/glxinfo.c b/progs/xdemos/glxinfo.c
index 35b6ed16b0..6cf127afa2 100644
--- a/progs/xdemos/glxinfo.c
+++ b/progs/xdemos/glxinfo.c
@@ -523,6 +523,13 @@ print_screen_info(Display *dpy, int scrnum, Bool allowDirect, GLboolean limits)
printf("OpenGL vendor string: %s\n", glVendor);
printf("OpenGL renderer string: %s\n", glRenderer);
printf("OpenGL version string: %s\n", glVersion);
+#ifdef GL_VERSION_2_0
+ if (glVersion[0] >= '2' && glVersion[1] == '.') {
+ char *v = (char *) glGetString(GL_SHADING_LANGUAGE_VERSION);
+ printf("OpenGL shading language version string: %s\n", v);
+ }
+#endif
+
printf("OpenGL extensions:\n");
print_extension_list(glExtensions);
if (limits)
--
cgit v1.2.3
From d8ababdcc2e359b4325b036bf7ae5447498a6521 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Thu, 24 Jul 2008 14:28:43 -0600
Subject: mesa: don't include Mesa version in GL_SHADING_LANGUAGE_VERSION
string
---
src/mesa/main/getstring.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/getstring.c b/src/mesa/main/getstring.c
index 55fb42096d..58c6c2f49f 100644
--- a/src/mesa/main/getstring.c
+++ b/src/mesa/main/getstring.c
@@ -57,8 +57,10 @@ _mesa_GetString( GLenum name )
static const char *version_2_0 = "2.0 Mesa " MESA_VERSION_STRING;
static const char *version_2_1 = "2.1 Mesa " MESA_VERSION_STRING;
-#if FEATURE_ARB_shading_language_100
- static const char *sl_version_110 = "1.10 Mesa " MESA_VERSION_STRING;
+#if FEATURE_ARB_shading_language_120_foo /* support not complete! */
+ static const char *sl_version = "1.20";
+#elif FEATURE_ARB_shading_language_100
+ static const char *sl_version = "1.10";
#endif
if (!ctx)
@@ -151,7 +153,7 @@ _mesa_GetString( GLenum name )
#if FEATURE_ARB_shading_language_100
case GL_SHADING_LANGUAGE_VERSION_ARB:
if (ctx->Extensions.ARB_shading_language_100)
- return (const GLubyte *) sl_version_110;
+ return (const GLubyte *) sl_version;
goto error;
#endif
#if FEATURE_NV_fragment_program || FEATURE_ARB_fragment_program || \
--
cgit v1.2.3
From 948f6e302ca3b6e0aa4d74eaef2e17dfb31bdfd5 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Thu, 24 Jul 2008 14:47:28 -0600
Subject: mesa: move extensions->version code into separate function
---
src/mesa/main/getstring.c | 142 +++++++++++++++++++++++-----------------------
1 file changed, 72 insertions(+), 70 deletions(-)
diff --git a/src/mesa/main/getstring.c b/src/mesa/main/getstring.c
index 58c6c2f49f..48c815772d 100644
--- a/src/mesa/main/getstring.c
+++ b/src/mesa/main/getstring.c
@@ -33,6 +33,76 @@
#include "extensions.h"
+/**
+ * Examine enabled GL extensions to determine GL version.
+ * \return version string
+ */
+static const char *
+compute_version(const GLcontext *ctx)
+{
+ static const char *version_1_2 = "1.2 Mesa " MESA_VERSION_STRING;
+ static const char *version_1_3 = "1.3 Mesa " MESA_VERSION_STRING;
+ static const char *version_1_4 = "1.4 Mesa " MESA_VERSION_STRING;
+ static const char *version_1_5 = "1.5 Mesa " MESA_VERSION_STRING;
+ static const char *version_2_0 = "2.0 Mesa " MESA_VERSION_STRING;
+ static const char *version_2_1 = "2.1 Mesa " MESA_VERSION_STRING;
+
+ const GLboolean ver_1_3 = (ctx->Extensions.ARB_multisample &&
+ ctx->Extensions.ARB_multitexture &&
+ ctx->Extensions.ARB_texture_border_clamp &&
+ ctx->Extensions.ARB_texture_compression &&
+ ctx->Extensions.ARB_texture_cube_map &&
+ ctx->Extensions.EXT_texture_env_add &&
+ ctx->Extensions.ARB_texture_env_combine &&
+ ctx->Extensions.ARB_texture_env_dot3);
+ const GLboolean ver_1_4 = (ver_1_3 &&
+ ctx->Extensions.ARB_depth_texture &&
+ ctx->Extensions.ARB_shadow &&
+ ctx->Extensions.ARB_texture_env_crossbar &&
+ ctx->Extensions.ARB_texture_mirrored_repeat &&
+ ctx->Extensions.ARB_window_pos &&
+ ctx->Extensions.EXT_blend_color &&
+ ctx->Extensions.EXT_blend_func_separate &&
+ ctx->Extensions.EXT_blend_minmax &&
+ ctx->Extensions.EXT_blend_subtract &&
+ ctx->Extensions.EXT_fog_coord &&
+ ctx->Extensions.EXT_multi_draw_arrays &&
+ ctx->Extensions.EXT_point_parameters &&
+ ctx->Extensions.EXT_secondary_color &&
+ ctx->Extensions.EXT_stencil_wrap &&
+ ctx->Extensions.EXT_texture_lod_bias &&
+ ctx->Extensions.SGIS_generate_mipmap);
+ const GLboolean ver_1_5 = (ver_1_4 &&
+ ctx->Extensions.ARB_occlusion_query &&
+ ctx->Extensions.ARB_vertex_buffer_object &&
+ ctx->Extensions.EXT_shadow_funcs);
+ const GLboolean ver_2_0 = (ver_1_5 &&
+ ctx->Extensions.ARB_draw_buffers &&
+ ctx->Extensions.ARB_point_sprite &&
+ ctx->Extensions.ARB_shader_objects &&
+ ctx->Extensions.ARB_vertex_shader &&
+ ctx->Extensions.ARB_fragment_shader &&
+ ctx->Extensions.ARB_texture_non_power_of_two &&
+ ctx->Extensions.EXT_blend_equation_separate);
+ const GLboolean ver_2_1 = (ver_2_0 &&
+ ctx->Extensions.ARB_shading_language_120 &&
+ ctx->Extensions.EXT_pixel_buffer_object &&
+ ctx->Extensions.EXT_texture_sRGB);
+ if (ver_2_1)
+ return version_2_1;
+ if (ver_2_0)
+ return version_2_0;
+ if (ver_1_5)
+ return version_1_5;
+ if (ver_1_4)
+ return version_1_4;
+ if (ver_1_3)
+ return version_1_3;
+ return version_1_2;
+}
+
+
+
/**
* Query string-valued state. The return value should _not_ be freed by
* the caller.
@@ -50,12 +120,6 @@ _mesa_GetString( GLenum name )
GET_CURRENT_CONTEXT(ctx);
static const char *vendor = "Brian Paul";
static const char *renderer = "Mesa";
- static const char *version_1_2 = "1.2 Mesa " MESA_VERSION_STRING;
- static const char *version_1_3 = "1.3 Mesa " MESA_VERSION_STRING;
- static const char *version_1_4 = "1.4 Mesa " MESA_VERSION_STRING;
- static const char *version_1_5 = "1.5 Mesa " MESA_VERSION_STRING;
- static const char *version_2_0 = "2.0 Mesa " MESA_VERSION_STRING;
- static const char *version_2_1 = "2.1 Mesa " MESA_VERSION_STRING;
#if FEATURE_ARB_shading_language_120_foo /* support not complete! */
static const char *sl_version = "1.20";
@@ -81,71 +145,9 @@ _mesa_GetString( GLenum name )
case GL_VENDOR:
return (const GLubyte *) vendor;
case GL_RENDERER:
- return (const GLubyte *) renderer;
+ return (const GLubyte *) renderer;
case GL_VERSION:
- /* tests for 1.3: */
- if (ctx->Extensions.ARB_multisample &&
- ctx->Extensions.ARB_multitexture &&
- ctx->Extensions.ARB_texture_border_clamp &&
- ctx->Extensions.ARB_texture_compression &&
- ctx->Extensions.ARB_texture_cube_map &&
- ctx->Extensions.EXT_texture_env_add &&
- ctx->Extensions.ARB_texture_env_combine &&
- ctx->Extensions.ARB_texture_env_dot3) {
- /* tests for 1.4: */
- if (ctx->Extensions.ARB_depth_texture &&
- ctx->Extensions.ARB_shadow &&
- ctx->Extensions.ARB_texture_env_crossbar &&
- ctx->Extensions.ARB_texture_mirrored_repeat &&
- ctx->Extensions.ARB_window_pos &&
- ctx->Extensions.EXT_blend_color &&
- ctx->Extensions.EXT_blend_func_separate &&
- ctx->Extensions.EXT_blend_minmax &&
- ctx->Extensions.EXT_blend_subtract &&
- ctx->Extensions.EXT_fog_coord &&
- ctx->Extensions.EXT_multi_draw_arrays &&
- ctx->Extensions.EXT_point_parameters && /*aka ARB*/
- ctx->Extensions.EXT_secondary_color &&
- ctx->Extensions.EXT_stencil_wrap &&
- ctx->Extensions.EXT_texture_lod_bias &&
- ctx->Extensions.SGIS_generate_mipmap) {
- /* tests for 1.5: */
- if (ctx->Extensions.ARB_occlusion_query &&
- ctx->Extensions.ARB_vertex_buffer_object &&
- ctx->Extensions.EXT_shadow_funcs) {
- /* tests for 2.0: */
- if (ctx->Extensions.ARB_draw_buffers &&
- ctx->Extensions.ARB_point_sprite &&
- ctx->Extensions.ARB_shader_objects &&
- ctx->Extensions.ARB_vertex_shader &&
- ctx->Extensions.ARB_fragment_shader &&
- ctx->Extensions.ARB_texture_non_power_of_two &&
- ctx->Extensions.EXT_blend_equation_separate) {
- /* tests for 2.1: */
- if (ctx->Extensions.ARB_shading_language_120 &&
- ctx->Extensions.EXT_pixel_buffer_object &&
- ctx->Extensions.EXT_texture_sRGB) {
- return (const GLubyte *) version_2_1;
- }
- else {
- return (const GLubyte *) version_2_0;
- }
- }
- else {
- return (const GLubyte *) version_1_5;
- }
- }
- else {
- return (const GLubyte *) version_1_4;
- }
- }
- else {
- return (const GLubyte *) version_1_3;
- }
- }
- else {
- return (const GLubyte *) version_1_2;
- }
+ return (const GLubyte *) compute_version(ctx);
case GL_EXTENSIONS:
if (!ctx->Extensions.String)
ctx->Extensions.String = _mesa_make_extension_string(ctx);
--
cgit v1.2.3
From 94979950e8991bd44899eb4067c3ae43449ce51e Mon Sep 17 00:00:00 2001
From: Dave Airlie
Date: Fri, 25 Jul 2008 16:31:38 +1000
Subject: intel: disable zero-copy TFP.
patch from Fedora. maybe someone can fix this later but for now
lets try and release Mesa so ajax can live his life and get Xorg 7.4 out.
---
src/mesa/drivers/dri/intel/intel_screen.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 5233e58fc9..467d022f44 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -391,10 +391,12 @@ intelHandleBufferAttach(__DRIdrawablePrivate *dPriv,
intel_renderbuffer_set_region(rb, region);
}
+#if 0
static const __DRItexOffsetExtension intelTexOffsetExtension = {
{ __DRI_TEX_OFFSET },
intelSetTexOffset,
};
+#endif
static const __DRItexBufferExtension intelTexBufferExtension = {
{ __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
@@ -407,7 +409,9 @@ static const __DRIextension *intelScreenExtensions[] = {
&driSwapControlExtension.base,
&driFrameTrackingExtension.base,
&driMediaStreamCounterExtension.base,
+#if 0
&intelTexOffsetExtension.base,
+#endif
&intelTexBufferExtension.base,
NULL
};
--
cgit v1.2.3
From d4244683a61f66cfb78408a37cf2587587847f96 Mon Sep 17 00:00:00 2001
From: Dave Airlie
Date: Fri, 25 Jul 2008 19:56:56 +1000
Subject: i965: make tex offset override work..
should fix fd.o 14441
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 50 +++++++++++++++---------
1 file changed, 31 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 0d91391964..d7758075d1 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -155,6 +155,7 @@ struct brw_wm_surface_key {
GLint width, height, depth;
GLint pitch, cpp;
GLboolean tiled;
+ GLuint offset;
};
static dri_bo *
@@ -173,8 +174,10 @@ brw_create_texture_surface( struct brw_context *brw,
/* This is ok for all textures with channel width 8bit or less:
*/
/* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
-
- surf.ss1.base_addr = key->bo->offset; /* reloc */
+ if (key->bo)
+ surf.ss1.base_addr = key->bo->offset; /* reloc */
+ else
+ surf.ss1.base_addr = key->offset;
surf.ss2.mip_count = key->last_level - key->first_level;
surf.ss2.width = key->width - 1;
@@ -198,17 +201,17 @@ brw_create_texture_surface( struct brw_context *brw,
bo = brw_upload_cache(&brw->cache, BRW_SS_SURFACE,
key, sizeof(*key),
- &key->bo, 1,
+ &key->bo, key->bo ? 1 : 0,
&surf, sizeof(surf),
NULL, NULL);
-
- /* Emit relocation to surface contents */
- dri_emit_reloc(bo,
- DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
- 0,
- offsetof(struct brw_surface_state, ss1),
- key->bo);
-
+ if (key->bo) {
+ /* Emit relocation to surface contents */
+ dri_emit_reloc(bo,
+ DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+ 0,
+ offsetof(struct brw_surface_state, ss1),
+ key->bo);
+ }
return bo;
}
@@ -223,26 +226,35 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit )
int ret = 0;
memset(&key, 0, sizeof(key));
+
+ if (intelObj->imageOverride) {
+ key.pitch = intelObj->pitchOverride / intelObj->mt->cpp;
+ key.depth = intelObj->depthOverride;
+ key.bo = NULL;
+ key.offset = intelObj->textureOffset;
+ } else {
+ key.pitch = intelObj->mt->pitch;
+ key.depth = firstImage->Depth;
+ key.bo = intelObj->mt->region->buffer;
+ key.offset = 0;
+ ret |= dri_bufmgr_check_aperture_space(key.bo);
+ }
+
key.target = tObj->Target;
key.depthmode = tObj->DepthMode;
key.format = firstImage->TexFormat->MesaFormat;
- key.bo = intelObj->mt->region->buffer;
key.first_level = intelObj->firstLevel;
key.last_level = intelObj->lastLevel;
key.width = firstImage->Width;
key.height = firstImage->Height;
- key.pitch = intelObj->mt->pitch;
key.cpp = intelObj->mt->cpp;
- key.depth = firstImage->Depth;
key.tiled = intelObj->mt->region->tiled;
- ret |= dri_bufmgr_check_aperture_space(key.bo);
-
dri_bo_unreference(brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS]);
brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_search_cache(&brw->cache, BRW_SS_SURFACE,
- &key, sizeof(key),
- &key.bo, 1,
- NULL);
+ &key, sizeof(key),
+ &key.bo, key.bo ? 1 : 0,
+ NULL);
if (brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] == NULL) {
brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_create_texture_surface(brw, &key);
}
--
cgit v1.2.3
From 04c98089d15d27e541561d3fb35b9c28b699833b Mon Sep 17 00:00:00 2001
From: Dave Airlie
Date: Fri, 25 Jul 2008 19:57:35 +1000
Subject: Revert "intel: disable zero-copy TFP."
This reverts commit 94979950e8991bd44899eb4067c3ae43449ce51e.
I've fixed it instead
---
src/mesa/drivers/dri/intel/intel_screen.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 467d022f44..5233e58fc9 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -391,12 +391,10 @@ intelHandleBufferAttach(__DRIdrawablePrivate *dPriv,
intel_renderbuffer_set_region(rb, region);
}
-#if 0
static const __DRItexOffsetExtension intelTexOffsetExtension = {
{ __DRI_TEX_OFFSET },
intelSetTexOffset,
};
-#endif
static const __DRItexBufferExtension intelTexBufferExtension = {
{ __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
@@ -409,9 +407,7 @@ static const __DRIextension *intelScreenExtensions[] = {
&driSwapControlExtension.base,
&driFrameTrackingExtension.base,
&driMediaStreamCounterExtension.base,
-#if 0
&intelTexOffsetExtension.base,
-#endif
&intelTexBufferExtension.base,
NULL
};
--
cgit v1.2.3
From 9bc9e0ecb0fb2069b2c123e665eb2118e358098f Mon Sep 17 00:00:00 2001
From: Dave Airlie
Date: Fri, 25 Jul 2008 20:32:22 +1000
Subject: i965: fixup format for TFP zero copy
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d7758075d1..2ba3eb4de8 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -169,7 +169,17 @@ brw_create_texture_surface( struct brw_context *brw,
surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
surf.ss0.surface_type = translate_tex_target(key->target);
- surf.ss0.surface_format = translate_tex_format(key->format, key->depthmode);
+
+ if (key->bo)
+ surf.ss0.surface_format = translate_tex_format(key->format, key->depthmode);
+ else {
+ switch(key->depth) {
+ case 32: surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break;
+ default:
+ case 24: surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM; break;
+ case 16: surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM; break;
+ }
+ }
/* This is ok for all textures with channel width 8bit or less:
*/
@@ -233,6 +243,7 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit )
key.bo = NULL;
key.offset = intelObj->textureOffset;
} else {
+ key.format = firstImage->TexFormat->MesaFormat;
key.pitch = intelObj->mt->pitch;
key.depth = firstImage->Depth;
key.bo = intelObj->mt->region->buffer;
@@ -242,7 +253,6 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit )
key.target = tObj->Target;
key.depthmode = tObj->DepthMode;
- key.format = firstImage->TexFormat->MesaFormat;
key.first_level = intelObj->firstLevel;
key.last_level = intelObj->lastLevel;
key.width = firstImage->Width;
--
cgit v1.2.3
From ff60e3fa031504b403766324b1fae3ccacec6650 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 25 Jul 2008 12:17:58 -0700
Subject: intel: If a tex image doesn't fit in the object's tree, make a
temporary tree.
Previously, we would just store the data as malloced memory hanging off the
object, which would get memcpyed in at validate time. This broke an
oglconform render-to-texture test, since validate wasn't called but a miptree
was expected.
---
src/mesa/drivers/dri/intel/intel_tex_image.c | 21 ++++++++++++++++++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 6d57b2b7dd..b8dcd1e061 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -395,10 +395,25 @@ intelTexImage(GLcontext * ctx,
intel_miptree_reference(&intelImage->mt, intelObj->mt);
assert(intelImage->mt);
- }
+ } else if (intelImage->base.Border == 0) {
+ int comp_byte = 0;
+
+ if (intelImage->base.IsCompressed) {
+ comp_byte =
+ intel_compressed_num_bytes(intelImage->base.TexFormat->MesaFormat);
+ }
- if (!intelImage->mt)
- DBG("XXX: Image did not fit into tree - storing in local memory!\n");
+ /* Didn't fit in the object miptree, but it's suitable for inclusion in
+ * a miptree, so create one just for our level and store it in the image.
+ * It'll get moved into the object miptree at validate time.
+ */
+ intelImage->mt = intel_miptree_create(intel, target, internalFormat,
+ level, level,
+ width, height, depth,
+ intelImage->base.TexFormat->TexelBytes,
+ comp_byte);
+
+ }
/* PBO fastpaths:
*/
--
cgit v1.2.3
From e5022c3fdf9888857f22f9a1690035ff3f90d36b Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Fri, 25 Jul 2008 12:40:16 -0700
Subject: mesa: Return 0 for cube map face of non-cubemap framebuffer
attachments.
Fixes some oglconform fbo testcases.
---
src/mesa/main/fbobject.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 8e9948cb45..cecc89ac38 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -1493,7 +1493,10 @@ _mesa_GetFramebufferAttachmentParameterivEXT(GLenum target, GLenum attachment,
return;
case GL_FRAMEBUFFER_ATTACHMENT_TEXTURE_CUBE_MAP_FACE_EXT:
if (att->Type == GL_TEXTURE) {
- *params = GL_TEXTURE_CUBE_MAP_POSITIVE_X + att->CubeMapFace;
+ if (att->Texture->Target == GL_TEXTURE_CUBE_MAP)
+ *params = GL_TEXTURE_CUBE_MAP_POSITIVE_X + att->CubeMapFace;
+ else
+ *params = 0;
}
else {
_mesa_error(ctx, GL_INVALID_ENUM,
--
cgit v1.2.3
From 477fa8fe1241aedde281defca52f02a8e7385733 Mon Sep 17 00:00:00 2001
From: Nicolai Haehnle
Date: Sat, 26 Jul 2008 16:15:33 +0200
Subject: r300: Always emit LOAD_VBPNTR immediately before index-based
rendering
This fixes one type of lockup I've been seeing on my test system.
---
src/mesa/drivers/dri/r300/r300_render.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c
index 69ff6d573e..58bc088443 100644
--- a/src/mesa/drivers/dri/r300/r300_render.c
+++ b/src/mesa/drivers/dri/r300/r300_render.c
@@ -269,13 +269,24 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx,
return;
if (vb->Elts) {
- r300EmitAOS(rmesa, rmesa->state.aos_count, start);
if (num_verts > 65535) {
/* not implemented yet */
WARN_ONCE("Too many elts\n");
return;
}
+ /* Note: The following is incorrect, but it's the best I can do
+ * without a major refactoring of how DMA memory is handled.
+ * The problem: Ensuring that both vertex arrays *and* index
+ * arrays are at the right position, and then ensuring that
+ * the LOAD_VBPNTR, DRAW_INDX and INDX_BUFFER packets are emitted
+ * at once.
+ *
+ * So why is the following incorrect? Well, it seems like
+ * allocating the index array might actually evict the vertex
+ * arrays. *sigh*
+ */
r300EmitElts(ctx, vb->Elts, num_verts);
+ r300EmitAOS(rmesa, rmesa->state.aos_count, start);
r300FireEB(rmesa, rmesa->state.elt_dma.aos_offset, num_verts, type);
} else {
r300EmitAOS(rmesa, rmesa->state.aos_count, start);
--
cgit v1.2.3
From 85e44fcd51b2f2e0bb0c97161fdde1971767eefd Mon Sep 17 00:00:00 2001
From: Nicolai Haehnle
Date: Sat, 26 Jul 2008 16:16:23 +0200
Subject: r200: Do not set second coordinate clamping for 1D textures
Fixes piglit's tex1d-border test.
---
src/mesa/drivers/dri/r200/r200_tex.c | 64 +++++++++++++++++++-----------------
1 file changed, 33 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c
index e7a37dd4c9..24b9b3b696 100644
--- a/src/mesa/drivers/dri/r200/r200_tex.c
+++ b/src/mesa/drivers/dri/r200/r200_tex.c
@@ -102,37 +102,39 @@ static void r200SetTexWrap( r200TexObjPtr t, GLenum swrap, GLenum twrap, GLenum
_mesa_problem(NULL, "bad S wrap mode in %s", __FUNCTION__);
}
- switch ( twrap ) {
- case GL_REPEAT:
- t->pp_txfilter |= R200_CLAMP_T_WRAP;
- break;
- case GL_CLAMP:
- t->pp_txfilter |= R200_CLAMP_T_CLAMP_GL;
- is_clamp = GL_TRUE;
- break;
- case GL_CLAMP_TO_EDGE:
- t->pp_txfilter |= R200_CLAMP_T_CLAMP_LAST;
- break;
- case GL_CLAMP_TO_BORDER:
- t->pp_txfilter |= R200_CLAMP_T_CLAMP_GL;
- is_clamp_to_border = GL_TRUE;
- break;
- case GL_MIRRORED_REPEAT:
- t->pp_txfilter |= R200_CLAMP_T_MIRROR;
- break;
- case GL_MIRROR_CLAMP_EXT:
- t->pp_txfilter |= R200_CLAMP_T_MIRROR_CLAMP_GL;
- is_clamp = GL_TRUE;
- break;
- case GL_MIRROR_CLAMP_TO_EDGE_EXT:
- t->pp_txfilter |= R200_CLAMP_T_MIRROR_CLAMP_LAST;
- break;
- case GL_MIRROR_CLAMP_TO_BORDER_EXT:
- t->pp_txfilter |= R200_CLAMP_T_MIRROR_CLAMP_GL;
- is_clamp_to_border = GL_TRUE;
- break;
- default:
- _mesa_problem(NULL, "bad T wrap mode in %s", __FUNCTION__);
+ if (t->base.tObj->Target != GL_TEXTURE_1D) {
+ switch ( twrap ) {
+ case GL_REPEAT:
+ t->pp_txfilter |= R200_CLAMP_T_WRAP;
+ break;
+ case GL_CLAMP:
+ t->pp_txfilter |= R200_CLAMP_T_CLAMP_GL;
+ is_clamp = GL_TRUE;
+ break;
+ case GL_CLAMP_TO_EDGE:
+ t->pp_txfilter |= R200_CLAMP_T_CLAMP_LAST;
+ break;
+ case GL_CLAMP_TO_BORDER:
+ t->pp_txfilter |= R200_CLAMP_T_CLAMP_GL;
+ is_clamp_to_border = GL_TRUE;
+ break;
+ case GL_MIRRORED_REPEAT:
+ t->pp_txfilter |= R200_CLAMP_T_MIRROR;
+ break;
+ case GL_MIRROR_CLAMP_EXT:
+ t->pp_txfilter |= R200_CLAMP_T_MIRROR_CLAMP_GL;
+ is_clamp = GL_TRUE;
+ break;
+ case GL_MIRROR_CLAMP_TO_EDGE_EXT:
+ t->pp_txfilter |= R200_CLAMP_T_MIRROR_CLAMP_LAST;
+ break;
+ case GL_MIRROR_CLAMP_TO_BORDER_EXT:
+ t->pp_txfilter |= R200_CLAMP_T_MIRROR_CLAMP_GL;
+ is_clamp_to_border = GL_TRUE;
+ break;
+ default:
+ _mesa_problem(NULL, "bad T wrap mode in %s", __FUNCTION__);
+ }
}
t->pp_txformat_x &= ~R200_CLAMP_Q_MASK;
--
cgit v1.2.3
From 902e401a384a8213d1239aae42bc2b7071ad6bd8 Mon Sep 17 00:00:00 2001
From: Eric Anholt
Date: Sat, 26 Jul 2008 17:12:04 -0700
Subject: intel: Don't return a renderbuffer with alpha when just GL_RGB is
requested.
Fixes oglconform rbGetterFuncs testcase. The span code for this mode hasn't
actually been tested.
---
src/mesa/drivers/dri/intel/intel_fbo.c | 8 +++++
src/mesa/drivers/dri/intel/intel_span.c | 64 +++++++++++++++++++++++++++++++++
2 files changed, 72 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 254f3efae0..5bd2ebfdcf 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -212,6 +212,14 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
case GL_RGB10:
case GL_RGB12:
case GL_RGB16:
+ rb->_ActualFormat = GL_RGB8;
+ rb->DataType = GL_UNSIGNED_BYTE;
+ rb->RedBits = 8;
+ rb->GreenBits = 8;
+ rb->BlueBits = 8;
+ rb->AlphaBits = 0;
+ cpp = 4;
+ break;
case GL_RGBA:
case GL_RGBA2:
case GL_RGBA4:
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 06f7c9b4b7..079b9e6a9d 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -74,6 +74,15 @@ pread_32(struct intel_renderbuffer *irb, uint32_t offset)
return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
}
+static uint32_t
+pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
+{
+ get_span_cache(irb, offset);
+
+ return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
+ 0xff000000;
+}
+
static uint16_t
pread_16(struct intel_renderbuffer *irb, uint32_t offset)
{
@@ -98,6 +107,14 @@ pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
dri_bo_subdata(irb->region->buffer, offset, 4, &val);
}
+static void
+pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
+{
+ clear_span_cache(irb);
+
+ dri_bo_subdata(irb->region->buffer, offset, 3, &val);
+}
+
static void
pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
{
@@ -301,6 +318,17 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
#define PUT_VALUE(X, Y, V) pwrite_32(irb, no_tile_swizzle(irb, intel, X, Y), V)
#include "spantmp2.h"
+/* 32 bit, xRGB8888 color spanline and pixel functions
+ */
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x) intel##x##_xRGB8888
+#define TAG2(x,y) intel##x##_xRGB8888##y
+#define GET_VALUE(X, Y) pread_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
/* 16 bit RGB565 color tile spanline and pixel functions
*/
@@ -343,6 +371,27 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
#define PUT_VALUE(X, Y, V) pwrite_32(irb, y_tile_swizzle(irb, intel, X, Y), V)
#include "spantmp2.h"
+/* 32 bit xRGB888 color tile spanline and pixel functions
+ */
+
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x) intel_XTile_##x##_xRGB8888
+#define TAG2(x,y) intel_XTile_##x##_xRGB8888##y
+#define GET_VALUE(X, Y) pread_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x) intel_YTile_##x##_xRGB8888
+#define TAG2(x,y) intel_YTile_##x##_xRGB8888##y
+#define GET_VALUE(X, Y) pread_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
#define LOCAL_DEPTH_VARS \
struct intel_context *intel = intel_context(ctx); \
struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
@@ -677,6 +726,21 @@ intel_set_span_functions(struct intel_context *intel,
break;
}
}
+ else if (rb->_ActualFormat == GL_RGB8) {
+ /* 8888 RGBx */
+ switch (tiling) {
+ case I915_TILING_NONE:
+ default:
+ intelInitPointers_xRGB8888(rb);
+ break;
+ case I915_TILING_X:
+ intel_XTile_InitPointers_xRGB8888(rb);
+ break;
+ case I915_TILING_Y:
+ intel_YTile_InitPointers_xRGB8888(rb);
+ break;
+ }
+ }
else if (rb->_ActualFormat == GL_RGBA8) {
/* 8888 RGBA */
switch (tiling) {
--
cgit v1.2.3
From 1bdf5e09a049d8d60bf147f9d88bbdb2b8588752 Mon Sep 17 00:00:00 2001
From: Nicolai Haehnle
Date: Sun, 27 Jul 2008 15:14:07 +0200
Subject: r500: Redirect TEX writes to output registers
While R500 fragment program texture instructions appear to support writemasks,
they cannot write to the output FIFO immediately, so we need to insert a MOV
for these instructions.
This fixes piglit's fp-fragment-position and fp-incomplete-tex tests.
---
src/mesa/drivers/dri/r300/r500_fragprog.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c
index 7b18efa69d..c78deab2ac 100644
--- a/src/mesa/drivers/dri/r300/r500_fragprog.c
+++ b/src/mesa/drivers/dri/r300/r500_fragprog.c
@@ -74,6 +74,13 @@ static GLboolean transform_TEX(
inst.DstReg.File = PROGRAM_TEMPORARY;
inst.DstReg.Index = radeonFindFreeTemporary(t);
inst.DstReg.WriteMask = WRITEMASK_XYZW;
+ } else if (inst.Opcode != OPCODE_KIL && inst.DstReg.File != PROGRAM_TEMPORARY) {
+ int tempreg = radeonFindFreeTemporary(t);
+
+ inst.DstReg.File = PROGRAM_TEMPORARY;
+ inst.DstReg.Index = tempreg;
+ inst.DstReg.WriteMask = WRITEMASK_XYZW;
+ destredirect = GL_TRUE;
}
tgt = radeonAppendInstructions(t->Program, 1);
--
cgit v1.2.3
From 0973d348d7a9c8d50829a33112dceb4e7f7a61ef Mon Sep 17 00:00:00 2001
From: Nicolai Haehnle
Date: Sun, 27 Jul 2008 16:36:05 +0200
Subject: r500: Handle non-native swizzles in texture instructions
This fixes piglit's fp-kil and fp-generic/kil-swizzle tests.
---
src/mesa/drivers/dri/r300/r500_fragprog.c | 89 ++++++++++++++++++-------
src/mesa/drivers/dri/r300/radeon_program_pair.c | 16 ++++-
2 files changed, 79 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c
index c78deab2ac..3fbdb30acf 100644
--- a/src/mesa/drivers/dri/r300/r500_fragprog.c
+++ b/src/mesa/drivers/dri/r300/r500_fragprog.c
@@ -269,44 +269,87 @@ static GLboolean is_native_swizzle(GLuint opcode, struct prog_src_register reg)
GLuint relevant;
int i;
- if (reg.Abs)
+ if (opcode == OPCODE_TEX ||
+ opcode == OPCODE_TXB ||
+ opcode == OPCODE_TXP ||
+ opcode == OPCODE_KIL) {
+ if (reg.Abs)
+ return GL_FALSE;
+
+ if (reg.NegateAbs)
+ reg.NegateBase ^= 15;
+
+ if (opcode == OPCODE_KIL) {
+ if (reg.Swizzle != SWIZZLE_NOOP)
+ return GL_FALSE;
+ } else {
+ for(i = 0; i < 4; ++i) {
+ GLuint swz = GET_SWZ(reg.Swizzle, i);
+ if (swz == SWIZZLE_NIL) {
+ reg.NegateBase &= ~(1 << i);
+ continue;
+ }
+ if (swz >= 4)
+ return GL_FALSE;
+ }
+ }
+
+ if (reg.NegateBase)
+ return GL_FALSE;
+
return GL_TRUE;
+ } else {
+ /* ALU instructions support almost everything */
+ if (reg.Abs)
+ return GL_TRUE;
- relevant = 0;
- for(i = 0; i < 3; ++i) {
- GLuint swz = GET_SWZ(reg.Swizzle, i);
- if (swz != SWIZZLE_NIL && swz != SWIZZLE_ZERO)
- relevant |= 1 << i;
- }
- if ((reg.NegateBase & relevant) && ((reg.NegateBase & relevant) != relevant))
- return GL_FALSE;
+ relevant = 0;
+ for(i = 0; i < 3; ++i) {
+ GLuint swz = GET_SWZ(reg.Swizzle, i);
+ if (swz != SWIZZLE_NIL && swz != SWIZZLE_ZERO)
+ relevant |= 1 << i;
+ }
+ if ((reg.NegateBase & relevant) && ((reg.NegateBase & relevant) != relevant))
+ return GL_FALSE;
- return GL_TRUE;
+ return GL_TRUE;
+ }
}
/**
- * Implement a non-native swizzle. This function assumes that
- * is_native_swizzle returned true.
+ * Implement a MOV with a potentially non-native swizzle.
+ *
+ * The only thing we *cannot* do in an ALU instruction is per-component
+ * negation. Therefore, we split the MOV into two instructions when necessary.
*/
static void nqssadce_build_swizzle(struct nqssadce_state *s,
struct prog_dst_register dst, struct prog_src_register src)
{
struct prog_instruction *inst;
+ GLuint negatebase[2] = { 0, 0 };
+ int i;
- _mesa_insert_instructions(s->Program, s->IP, 2);
- inst = s->Program->Instructions + s->IP;
+ for(i = 0; i < 4; ++i) {
+ GLuint swz = GET_SWZ(src.Swizzle, i);
+ if (swz == SWIZZLE_NIL)
+ continue;
+ negatebase[GET_BIT(src.NegateBase, i)] |= 1 << i;
+ }
- inst[0].Opcode = OPCODE_MOV;
- inst[0].DstReg = dst;
- inst[0].DstReg.WriteMask &= src.NegateBase;
- inst[0].SrcReg[0] = src;
+ _mesa_insert_instructions(s->Program, s->IP, (negatebase[0] ? 1 : 0) + (negatebase[1] ? 1 : 0));
+ inst = s->Program->Instructions + s->IP;
- inst[1].Opcode = OPCODE_MOV;
- inst[1].DstReg = dst;
- inst[1].DstReg.WriteMask &= ~src.NegateBase;
- inst[1].SrcReg[0] = src;
+ for(i = 0; i <= 1; ++i) {
+ if (!negatebase[i])
+ continue;
- s->IP += 2;
+ inst->Opcode = OPCODE_MOV;
+ inst->DstReg = dst;
+ inst->DstReg.WriteMask = negatebase[i];
+ inst->SrcReg[0] = src;
+ inst++;
+ s->IP++;
+ }
}
static GLuint build_dtm(GLuint depthmode)
diff --git a/src/mesa/drivers/dri/r300/radeon_program_pair.c b/src/mesa/drivers/dri/r300/radeon_program_pair.c
index 8762422801..4307994d74 100644
--- a/src/mesa/drivers/dri/r300/radeon_program_pair.c
+++ b/src/mesa/drivers/dri/r300/radeon_program_pair.c
@@ -265,11 +265,21 @@ static void final_rewrite(struct pair_state *s, struct prog_instruction *inst)
inst->SrcReg[0] = tmp;
break;
case OPCODE_MOV:
- inst->SrcReg[1] = inst->SrcReg[0];
+ /* AMD say we should use CMP.
+ * However, when we transform
+ * KIL -r0;
+ * into
+ * CMP tmp, -r0, -r0, 0;
+ * KIL tmp;
+ * we get incorrect behaviour on R500 when r0 == 0.0.
+ * It appears that the R500 KIL hardware treats -0.0 as less
+ * than zero.
+ */
+ inst->SrcReg[1].File = PROGRAM_BUILTIN;
+ inst->SrcReg[1].Swizzle = SWIZZLE_1111;
inst->SrcReg[2].File = PROGRAM_BUILTIN;
inst->SrcReg[2].Swizzle = SWIZZLE_0000;
- inst->Opcode = OPCODE_CMP;
- // TODO: disable output modifiers on R500
+ inst->Opcode = OPCODE_MAD;
break;
case OPCODE_MUL:
inst->SrcReg[2].File = PROGRAM_BUILTIN;
--
cgit v1.2.3
From 322677b8789c031024fb3fb4618f27e7a6ffec5d Mon Sep 17 00:00:00 2001
From: Nicolai Haehnle
Date: Sun, 27 Jul 2008 18:18:59 +0200
Subject: r300: Implement hardware acceleration for ColorLogicOp
---
src/mesa/drivers/dri/r300/r300_cmdbuf.c | 2 ++
src/mesa/drivers/dri/r300/r300_context.h | 1 +
src/mesa/drivers/dri/r300/r300_reg.h | 4 ++-
src/mesa/drivers/dri/r300/r300_render.c | 2 --
src/mesa/drivers/dri/r300/r300_state.c | 44 +++++++++++++++++++++++++++++++-
5 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 4dc3161449..c069660eea 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -477,6 +477,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
ALLOC_STATE(blend_color, always, 2, 0);
r300->hw.blend_color.cmd[0] = cmdpacket0(R300_RB3D_BLEND_COLOR, 1);
}
+ ALLOC_STATE(rop, always, 2, 0);
+ r300->hw.rop.cmd[0] = cmdpacket0(R300_RB3D_ROPCNTL, 1);
ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
r300->hw.cb.cmd[R300_CB_CMD_0] = cmdpacket0(R300_RB3D_COLOROFFSET0, 1);
r300->hw.cb.cmd[R300_CB_CMD_1] = cmdpacket0(R300_RB3D_COLORPITCH0, 1);
diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h
index 98af6d8f10..d2017f8afe 100644
--- a/src/mesa/drivers/dri/r300/r300_context.h
+++ b/src/mesa/drivers/dri/r300/r300_context.h
@@ -516,6 +516,7 @@ struct r300_hw_state {
struct r300_state_atom bld; /* blending (4E04) */
struct r300_state_atom cmk; /* colormask (4E0C) */
struct r300_state_atom blend_color; /* constant blend color */
+ struct r300_state_atom rop; /* ropcntl */
struct r300_state_atom cb; /* colorbuffer (4E28) */
struct r300_state_atom rb3d_dither_ctl; /* (4E50) */
struct r300_state_atom rb3d_aaresolve_ctl; /* (4E88) */
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index ec2b58377c..562cd6afdb 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -2249,7 +2249,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* 3D ROP Control. Stalls the 2d/3d datapath until it is idle. */
#define R300_RB3D_ROPCNTL 0x4e18
-/* TODO: fill in content here */
+# define R300_RB3D_ROPCNTL_ROP_ENABLE 0x00000004
+# define R300_RB3D_ROPCNTL_ROP_MASK (15 << 8)
+# define R300_RB3D_ROPCNTL_ROP_SHIFT 8
/* Color Compare Flip. Stalls the 2d/3d datapath until it is idle. */
#define R300_RB3D_CLRCMP_FLIPE 0x4e1c
diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c
index 58bc088443..0a199e6faa 100644
--- a/src/mesa/drivers/dri/r300/r300_render.c
+++ b/src/mesa/drivers/dri/r300/r300_render.c
@@ -377,8 +377,6 @@ static int r300Fallback(GLcontext * ctx)
|| ctx->Stencil.WriteMask[0] !=
ctx->Stencil.WriteMask[1]));
- FALLBACK_IF(ctx->Color.ColorLogicOpEnabled);
-
if (ctx->Extensions.NV_point_sprite || ctx->Extensions.ARB_point_sprite)
FALLBACK_IF(ctx->Point.PointSprite);
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index 6931de4421..ec17974d78 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -321,6 +321,44 @@ static void r300BlendFuncSeparate(GLcontext * ctx,
r300SetBlendState(ctx);
}
+/**
+ * Translate LogicOp enums into hardware representation.
+ * Both use a very logical bit-wise layout, but unfortunately the order
+ * of bits is reversed.
+ */
+static GLuint translate_logicop(GLenum logicop)
+{
+ GLuint bits = logicop - GL_CLEAR;
+ bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
+ return bits << R300_RB3D_ROPCNTL_ROP_SHIFT;
+}
+
+/**
+ * Used internally to update the r300->hw hardware state to match the
+ * current OpenGL state.
+ */
+static void r300SetLogicOpState(GLcontext *ctx)
+{
+ r300ContextPtr r300 = R300_CONTEXT(ctx);
+ R300_STATECHANGE(r300, rop);
+ if (RGBA_LOGICOP_ENABLED(ctx)) {
+ r300->hw.rop.cmd[1] = R300_RB3D_ROPCNTL_ROP_ENABLE |
+ translate_logicop(ctx->Color.LogicOp);
+ } else {
+ r300->hw.rop.cmd[1] = 0;
+ }
+}
+
+/**
+ * Called by Mesa when an application program changes the LogicOp state
+ * via glLogicOp.
+ */
+static void r300LogicOpcode(GLcontext *ctx, GLenum logicop)
+{
+ if (RGBA_LOGICOP_ENABLED(ctx))
+ r300SetLogicOpState(ctx);
+}
+
static void r300ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
@@ -2117,8 +2155,10 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
case GL_ALPHA_TEST:
r300SetAlphaState(ctx);
break;
- case GL_BLEND:
case GL_COLOR_LOGIC_OP:
+ r300SetLogicOpState(ctx);
+ /* fall-through, because logic op overrides blending */
+ case GL_BLEND:
r300SetBlendState(ctx);
break;
case GL_CLIP_PLANE0:
@@ -2188,6 +2228,7 @@ static void r300ResetHwState(r300ContextPtr r300)
r300UpdateTextureState(ctx);
r300SetBlendState(ctx);
+ r300SetLogicOpState(ctx);
r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
@@ -2755,6 +2796,7 @@ void r300InitStateFuncs(struct dd_function_table *functions)
functions->Fogfv = r300Fogfv;
functions->FrontFace = r300FrontFace;
functions->ShadeModel = r300ShadeModel;
+ functions->LogicOpcode = r300LogicOpcode;
/* ARB_point_parameters */
functions->PointParameterfv = r300PointParameter;
--
cgit v1.2.3
From e88be7d375032fbddb34a77debe6604fa029492c Mon Sep 17 00:00:00 2001
From: Nicolai Haehnle
Date: Sun, 27 Jul 2008 21:18:29 +0200
Subject: r300: Fix point minmax size
There are 6 subpixel units per pixel, not 16.
---
src/mesa/drivers/dri/r300/r300_state.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
index ec17974d78..cce07d338b 100644
--- a/src/mesa/drivers/dri/r300/r300_state.c
+++ b/src/mesa/drivers/dri/r300/r300_state.c
@@ -881,12 +881,12 @@ static void r300PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * pa
case GL_POINT_SIZE_MIN:
R300_STATECHANGE(r300, ga_point_minmax);
r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MIN_MASK;
- r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MinSize * 16.0);
+ r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MinSize * 6.0);
break;
case GL_POINT_SIZE_MAX:
R300_STATECHANGE(r300, ga_point_minmax);
r300->hw.ga_point_minmax.cmd[1] &= ~R300_GA_POINT_MINMAX_MAX_MASK;
- r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MaxSize * 16.0)
+ r300->hw.ga_point_minmax.cmd[1] |= (GLuint)(ctx->Point.MaxSize * 6.0)
<< R300_GA_POINT_MINMAX_MAX_SHIFT;
break;
case GL_POINT_DISTANCE_ATTENUATION:
--
cgit v1.2.3
From c117d0efd28887069607f405be99fbc09fcb4cab Mon Sep 17 00:00:00 2001
From: Nicolai Haehnle
Date: Sun, 27 Jul 2008 21:31:49 +0200
Subject: r300: Implement ARB_shadow_ambient; add STATE_SHADOW_AMBIENT
---
src/mesa/drivers/dri/r300/r300_context.c | 1 +
src/mesa/drivers/dri/r300/r300_fragprog.c | 37 ++++++++++++++++++++++------
src/mesa/drivers/dri/r300/r500_fragprog.c | 41 ++++++++++++++++++++++---------
src/mesa/shader/prog_statevars.c | 28 +++++++++++++++++----
src/mesa/shader/prog_statevars.h | 5 ++--
5 files changed, 86 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index a9c581b236..fcf571d206 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -101,6 +101,7 @@ const struct dri_extension card_extensions[] = {
{"GL_ARB_multitexture", NULL},
{"GL_ARB_point_parameters", GL_ARB_point_parameters_functions},
{"GL_ARB_shadow", NULL},
+ {"GL_ARB_shadow_ambient", NULL},
{"GL_ARB_texture_border_clamp", NULL},
{"GL_ARB_texture_compression", GL_ARB_texture_compression_functions},
{"GL_ARB_texture_cube_map", NULL},
diff --git a/src/mesa/drivers/dri/r300/r300_fragprog.c b/src/mesa/drivers/dri/r300/r300_fragprog.c
index d390de54b8..453dda7431 100644
--- a/src/mesa/drivers/dri/r300/r300_fragprog.c
+++ b/src/mesa/drivers/dri/r300/r300_fragprog.c
@@ -58,6 +58,20 @@ static void reset_srcreg(struct prog_src_register* reg)
reg->Swizzle = SWIZZLE_NOOP;
}
+static struct prog_src_register shadow_ambient(struct gl_program *program, int tmu)
+{
+ gl_state_index fail_value_tokens[STATE_LENGTH] = {
+ STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0
+ };
+ struct prog_src_register reg = { 0, };
+
+ fail_value_tokens[2] = tmu;
+ reg.File = PROGRAM_STATE_VAR;
+ reg.Index = _mesa_add_state_reference(program->Parameters, fail_value_tokens);
+ reg.Swizzle = SWIZZLE_WWWW;
+ return reg;
+}
+
/**
* Transform TEX, TXP, TXB, and KIL instructions in the following way:
* - premultiply texture coordinates for RECT
@@ -92,8 +106,12 @@ static GLboolean transform_TEX(
tgt->Opcode = OPCODE_MOV;
tgt->DstReg = inst.DstReg;
- tgt->SrcReg[0].File = PROGRAM_BUILTIN;
- tgt->SrcReg[0].Swizzle = comparefunc == GL_ALWAYS ? SWIZZLE_1111 : SWIZZLE_0000;
+ if (comparefunc == GL_ALWAYS) {
+ tgt->SrcReg[0].File = PROGRAM_BUILTIN;
+ tgt->SrcReg[0].Swizzle = SWIZZLE_1111;
+ } else {
+ tgt->SrcReg[0] = shadow_ambient(t->Program, inst.TexSrcUnit);
+ }
return GL_TRUE;
}
@@ -153,6 +171,7 @@ static GLboolean transform_TEX(
GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func;
GLuint depthmode = compiler->fp->state.unit[inst.TexSrcUnit].depth_texture_mode;
int rcptemp = radeonFindFreeTemporary(t);
+ int pass, fail;
tgt = radeonAppendInstructions(t->Program, 3);
@@ -190,16 +209,18 @@ static GLboolean transform_TEX(
tgt[2].DstReg = orig_inst->DstReg;
tgt[2].SrcReg[0].File = PROGRAM_TEMPORARY;
tgt[2].SrcReg[0].Index = tgt[1].DstReg.Index;
- tgt[2].SrcReg[1].File = PROGRAM_BUILTIN;
- tgt[2].SrcReg[2].File = PROGRAM_BUILTIN;
if (comparefunc == GL_LESS || comparefunc == GL_GREATER) {
- tgt[2].SrcReg[1].Swizzle = SWIZZLE_1111;
- tgt[2].SrcReg[2].Swizzle = SWIZZLE_0000;
+ pass = 1;
+ fail = 2;
} else {
- tgt[2].SrcReg[1].Swizzle = SWIZZLE_0000;
- tgt[2].SrcReg[2].Swizzle = SWIZZLE_1111;
+ pass = 2;
+ fail = 1;
}
+
+ tgt[2].SrcReg[pass].File = PROGRAM_BUILTIN;
+ tgt[2].SrcReg[pass].Swizzle = SWIZZLE_1111;
+ tgt[2].SrcReg[fail] = shadow_ambient(t->Program, inst.TexSrcUnit);
} else if (destredirect) {
tgt = radeonAppendInstructions(t->Program, 1);
diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c
index 3fbdb30acf..a84ba13c12 100644
--- a/src/mesa/drivers/dri/r300/r500_fragprog.c
+++ b/src/mesa/drivers/dri/r300/r500_fragprog.c
@@ -31,6 +31,20 @@
#include "radeon_program_alu.h"
+static struct prog_src_register shadow_ambient(struct gl_program *program, int tmu)
+{
+ gl_state_index fail_value_tokens[STATE_LENGTH] = {
+ STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0
+ };
+ struct prog_src_register reg = { 0, };
+
+ fail_value_tokens[2] = tmu;
+ reg.File = PROGRAM_STATE_VAR;
+ reg.Index = _mesa_add_state_reference(program->Parameters, fail_value_tokens);
+ reg.Swizzle = SWIZZLE_WWWW;
+ return reg;
+}
+
/**
* Transform TEX, TXP, TXB, and KIL instructions in the following way:
* - premultiply texture coordinates for RECT
@@ -63,11 +77,13 @@ static GLboolean transform_TEX(
tgt = radeonAppendInstructions(t->Program, 1);
tgt->Opcode = OPCODE_MOV;
- tgt->DstReg.File = inst.DstReg.File;
- tgt->DstReg.Index = inst.DstReg.Index;
- tgt->DstReg.WriteMask = inst.DstReg.WriteMask;
- tgt->SrcReg[0].File = PROGRAM_BUILTIN;
- tgt->SrcReg[0].Swizzle = comparefunc == GL_ALWAYS ? SWIZZLE_1111 : SWIZZLE_0000;
+ tgt->DstReg = inst.DstReg;
+ if (comparefunc == GL_ALWAYS) {
+ tgt->SrcReg[0].File = PROGRAM_BUILTIN;
+ tgt->SrcReg[0].Swizzle = SWIZZLE_1111;
+ } else {
+ tgt->SrcReg[0] = shadow_ambient(t->Program, inst.TexSrcUnit);
+ }
return GL_TRUE;
}
@@ -91,6 +107,7 @@ static GLboolean transform_TEX(
GLuint comparefunc = GL_NEVER + compiler->fp->state.unit[inst.TexSrcUnit].texture_compare_func;
GLuint depthmode = compiler->fp->state.unit[inst.TexSrcUnit].depth_texture_mode;
int rcptemp = radeonFindFreeTemporary(t);
+ int pass, fail;
tgt = radeonAppendInstructions(t->Program, 3);
@@ -128,16 +145,18 @@ static GLboolean transform_TEX(
tgt[2].DstReg = orig_inst->DstReg;
tgt[2].SrcReg[0].File = PROGRAM_TEMPORARY;
tgt[2].SrcReg[0].Index = tgt[1].DstReg.Index;
- tgt[2].SrcReg[1].File = PROGRAM_BUILTIN;
- tgt[2].SrcReg[2].File = PROGRAM_BUILTIN;
if (comparefunc == GL_LESS || comparefunc == GL_GREATER) {
- tgt[2].SrcReg[1].Swizzle = SWIZZLE_1111;
- tgt[2].SrcReg[2].Swizzle = SWIZZLE_0000;
+ pass = 1;
+ fail = 2;
} else {
- tgt[2].SrcReg[1].Swizzle = SWIZZLE_0000;
- tgt[2].SrcReg[2].Swizzle = SWIZZLE_1111;
+ pass = 2;
+ fail = 1;
}
+
+ tgt[2].SrcReg[pass].File = PROGRAM_BUILTIN;
+ tgt[2].SrcReg[pass].Swizzle = SWIZZLE_1111;
+ tgt[2].SrcReg[fail] = shadow_ambient(t->Program, inst.TexSrcUnit);
} else if (destredirect) {
tgt = radeonAppendInstructions(t->Program, 1);
diff --git a/src/mesa/shader/prog_statevars.c b/src/mesa/shader/prog_statevars.c
index 539057b438..e446e1c419 100644
--- a/src/mesa/shader/prog_statevars.c
+++ b/src/mesa/shader/prog_statevars.c
@@ -132,7 +132,7 @@ _mesa_fetch_state(GLcontext *ctx, const gl_state_index state[],
ADD_3V(value, p, eye_z);
NORMALIZE_3FV(value);
value[3] = 1.0;
- }
+ }
return;
case STATE_POSITION_NORMALIZED:
COPY_4V(value, ctx->Light.Light[ln].EyePosition);
@@ -240,11 +240,11 @@ _mesa_fetch_state(GLcontext *ctx, const gl_state_index state[],
}
}
case STATE_TEXENV_COLOR:
- {
+ {
/* state[1] is the texture unit */
const GLuint unit = (GLuint) state[1];
COPY_4V(value, ctx->Texture.Unit[unit].EnvColor);
- }
+ }
return;
case STATE_FOG_COLOR:
COPY_4V(value, ctx->Fog.Color);
@@ -374,7 +374,7 @@ _mesa_fetch_state(GLcontext *ctx, const gl_state_index state[],
}
}
return;
-
+
case STATE_VERTEX_PROGRAM:
{
/* state[1] = {STATE_ENV, STATE_LOCAL} */
@@ -458,6 +458,20 @@ _mesa_fetch_state(GLcontext *ctx, const gl_state_index state[],
case STATE_PCM_BIAS:
COPY_4V(value, ctx->Pixel.PostColorMatrixBias);
break;
+ case STATE_SHADOW_AMBIENT:
+ {
+ const int unit = (int) state[2];
+ const struct gl_texture_object *texObj
+ = ctx->Texture.Unit[unit]._Current;
+ if (texObj) {
+ value[0] = texObj->ShadowAmbient;
+ value[1] = texObj->ShadowAmbient;
+ value[2] = texObj->ShadowAmbient;
+ value[3] = texObj->ShadowAmbient;
+ }
+ }
+ return;
+
default:
/* unknown state indexes are silently ignored
* should be handled by the driver.
@@ -532,6 +546,7 @@ _mesa_program_state_flags(const gl_state_index state[STATE_LENGTH])
case STATE_INTERNAL:
switch (state[1]) {
case STATE_TEXRECT_SCALE:
+ case STATE_SHADOW_AMBIENT:
return _NEW_TEXTURE;
case STATE_FOG_PARAMS_OPTIMIZED:
return _NEW_FOG;
@@ -711,6 +726,9 @@ append_token(char *dst, gl_state_index k)
case STATE_PCM_BIAS:
append(dst, "PCMbias");
break;
+ case STATE_SHADOW_AMBIENT:
+ append(dst, "ShadowAmbient");
+ break;
default:
;
}
@@ -861,7 +879,7 @@ _mesa_load_state_parameters(GLcontext *ctx,
for (i = 0; i < paramList->NumParameters; i++) {
if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR) {
- _mesa_fetch_state(ctx,
+ _mesa_fetch_state(ctx,
(gl_state_index *) paramList->Parameters[i].StateIndexes,
paramList->ParameterValues[i]);
}
diff --git a/src/mesa/shader/prog_statevars.h b/src/mesa/shader/prog_statevars.h
index 64820a5b68..da75ca77a1 100644
--- a/src/mesa/shader/prog_statevars.h
+++ b/src/mesa/shader/prog_statevars.h
@@ -77,7 +77,7 @@ typedef enum gl_state_index_ {
STATE_SPECULAR,
STATE_EMISSION,
STATE_SHININESS,
- STATE_HALF_VECTOR,
+ STATE_HALF_VECTOR,
STATE_POSITION,
STATE_ATTENUATION,
@@ -94,7 +94,7 @@ typedef enum gl_state_index_ {
STATE_TEXGEN_OBJECT_Q,
STATE_TEXENV_COLOR,
-
+
STATE_DEPTH_RANGE,
STATE_VERTEX_PROGRAM,
@@ -113,6 +113,7 @@ typedef enum gl_state_index_ {
STATE_PT_BIAS, /**< Pixel transfer RGBA bias */
STATE_PCM_SCALE, /**< Post color matrix RGBA scale */
STATE_PCM_BIAS, /**< Post color matrix RGBA bias */
+ STATE_SHADOW_AMBIENT, /**< ARB_shadow_ambient fail value; token[2] is texture unit index */
STATE_INTERNAL_DRIVER /* first available state index for drivers (must be last) */
} gl_state_index;
--
cgit v1.2.3
From c1fb448ce8dd98f8e5fd5a39707f96cc14535bd4 Mon Sep 17 00:00:00 2001
From: Nicolai Haehnle
Date: Sun, 27 Jul 2008 21:40:17 +0200
Subject: r300: Fix a crash related to depth textures (triggered by Glest w/
shadowmaps)
---
src/mesa/drivers/dri/r300/r300_tex.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c
index c8f02c4ef5..f7f49729bc 100644
--- a/src/mesa/drivers/dri/r300/r300_tex.c
+++ b/src/mesa/drivers/dri/r300/r300_tex.c
@@ -944,6 +944,8 @@ static void r300TexParameter(GLcontext * ctx, GLenum target,
break;
case GL_DEPTH_TEXTURE_MODE:
+ if (!texObj->Image[0][texObj->BaseLevel])
+ return;
if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat
== GL_DEPTH_COMPONENT) {
r300SetDepthTexMode(texObj);
--
cgit v1.2.3
From 57aea290e1e0a26d1e74df6cff777eb9f038f1f8 Mon Sep 17 00:00:00 2001
From: Michel Dänzer
Date: Mon, 28 Jul 2008 10:49:43 +0200
Subject: r300: Fix off-by-one error in calculation of scissor cliprect.
Fixes http://bugs.freedesktop.org/show_bug.cgi?id=16123 .
---
src/mesa/drivers/dri/r300/radeon_state.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/r300/radeon_state.c b/src/mesa/drivers/dri/r300/radeon_state.c
index af2c3bcacd..d81318ce20 100644
--- a/src/mesa/drivers/dri/r300/radeon_state.c
+++ b/src/mesa/drivers/dri/r300/radeon_state.c
@@ -125,8 +125,8 @@ void radeonUpdateScissor(GLcontext* ctx)
radeon->state.scissor.rect.x1 = x1;
radeon->state.scissor.rect.y1 = y1;
- radeon->state.scissor.rect.x2 = x1 + ctx->Scissor.Width - 1;
- radeon->state.scissor.rect.y2 = y1 + ctx->Scissor.Height - 1;
+ radeon->state.scissor.rect.x2 = x1 + ctx->Scissor.Width;
+ radeon->state.scissor.rect.y2 = y1 + ctx->Scissor.Height;
radeonRecalcScissorRects(radeon);
}
--
cgit v1.2.3
From b5095ab97f4cf4d2d0e5b99b7813a2e466c2459c Mon Sep 17 00:00:00 2001
From: Florent Thoumie
Date: Mon, 28 Jul 2008 14:44:43 +0100
Subject: autoconf: disable dri drivers build if being asked
Allow --with-dri-drivers={,no} to disable DRI drivers build.
Signed-off-by: Florent Thoumie
Signed-off-by: Robert Noland
---
configure.ac | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/configure.ac b/configure.ac
index 9014f8e158..c87dce6546 100644
--- a/configure.ac
+++ b/configure.ac
@@ -624,7 +624,10 @@ dnl If $with_dri_drivers is yes, directories will be added through
dnl platform checks
DRI_DIRS=""
case "$with_dri_drivers" in
-no|yes) ;;
+no) ;;
+yes)
+ DRI_DIRS="yes"
+ ;;
*)
# verify the requested driver directories exist
dri_drivers=`IFS=', '; echo $with_dri_drivers`
@@ -670,7 +673,7 @@ if test "$mesa_driver" = dri; then
# converted to use the new interface. i810 are missing
# because there is no x86-64 system where they could *ever*
# be used.
- if test "x$DRI_DIRS" = x; then
+ if test "x$DRI_DIRS" = "xyes"; then
DRI_DIRS="i915 i965 mach64 mga r128 r200 r300 radeon \
savage tdfx unichrome swrast"
fi
@@ -678,13 +681,13 @@ if test "$mesa_driver" = dri; then
powerpc*)
# Build only the drivers for cards that exist on PowerPC.
# At some point MGA will be added, but not yet.
- if test "x$DRI_DIRS" = x; then
+ if test "x$DRI_DIRS" = "xyes"; then
DRI_DIRS="mach64 r128 r200 r300 radeon tdfx swrast"
fi
;;
sparc*)
# Build only the drivers for cards that exist on sparc`
- if test "x$DRI_DIRS" = x; then
+ if test "x$DRI_DIRS" = "xyes"; then
DRI_DIRS="mach64 r128 r200 r300 radeon ffb swrast"
fi
;;
@@ -703,7 +706,7 @@ if test "$mesa_driver" = dri; then
# ffb and gamma are missing because they have not been converted
# to use the new interface.
- if test "x$DRI_DIRS" = x; then
+ if test "x$DRI_DIRS" = "xyes"; then
DRI_DIRS="i810 i915 i965 mach64 mga r128 r200 r300 radeon tdfx \
unichrome savage sis swrast"
fi
@@ -718,7 +721,7 @@ if test "$mesa_driver" = dri; then
esac
# default drivers
- if test "x$DRI_DIRS" = x; then
+ if test "x$DRI_DIRS" = "xyes"; then
DRI_DIRS="i810 i915 i965 mach64 mga r128 r200 r300 radeon s3v \
savage sis tdfx trident unichrome ffb swrast"
fi
@@ -1041,7 +1044,11 @@ fi
if test "$mesa_driver" = dri; then
# cleanup the drivers var
dri_dirs=`echo $DRI_DIRS | $SED 's/^ *//;s/ */ /;s/ *$//'`
+if test "x$DRI_DIRS" = x; then
+ echo " DRI drivers: no"
+else
echo " DRI drivers: $dri_dirs"
+fi
echo " DRI driver dir: $DRI_DRIVER_INSTALL_DIR"
echo " TTM API support: $ttmapi"
fi
--
cgit v1.2.3
From 44c7f37b448201ad1276883ae5e6f7a3bdc4e7ac Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Tue, 29 Jul 2008 07:38:13 -0600
Subject: disable GL_ARB_shading_language_120 until 1.20 features are complete
---
src/mesa/main/extensions.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 709499f730..3774d56369 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -204,7 +204,7 @@ _mesa_enable_sw_extensions(GLcontext *ctx)
ctx->Extensions.ARB_shading_language_100 = GL_TRUE;
#endif
#if FEATURE_ARB_shading_language_120
- ctx->Extensions.ARB_shading_language_120 = GL_TRUE;
+ ctx->Extensions.ARB_shading_language_120 = GL_FALSE; /* not quite done */
#endif
ctx->Extensions.ARB_shadow = GL_TRUE;
ctx->Extensions.ARB_texture_border_clamp = GL_TRUE;
@@ -419,7 +419,7 @@ _mesa_enable_2_1_extensions(GLcontext *ctx)
ctx->Extensions.EXT_texture_sRGB = GL_TRUE;
#endif
#ifdef FEATURE_ARB_shading_language_120
- ctx->Extensions.ARB_shading_language_120 = GL_TRUE;
+ ctx->Extensions.ARB_shading_language_120 = GL_FALSE; /* not quite done */
#endif
}
--
cgit v1.2.3
From 1a5c99f4b5ccbc71f3649092c723b5e295456314 Mon Sep 17 00:00:00 2001
From: Brian Paul
Date: Tue, 29 Jul 2008 16:46:08 -0600
Subject: document GLSL 1.20 status
---
docs/shading.html | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/docs/shading.html b/docs/shading.html
index 02f393cc9e..2cd17c76ac 100644
--- a/docs/shading.html
+++ b/docs/shading.html
@@ -28,6 +28,7 @@ Contents
Stand-alone GLSL Compiler
Compiler Implementation
Compiler Validation
+GLSL 1.20 support
@@ -318,5 +319,39 @@ should be added.
+
+
+GLSL 1.20 support
+
+
+Support for GLSL version 1.20 is underway. Status as follows.
+
+
+Supported
+
+mat2x3, mat2x4
, etc. types and functions
+transpose(), outerProduct(), matrixCompMult()
functions
+(but untested)
+- precision qualifiers (lowp, mediump, highp)
+
+
+Partially Complete
+
+
+Not Completed
+
+array.length()
method
+float[5] a;
array syntax
+centroid
qualifier
+- unsized array constructors
+
- initializers for uniforms
+
- const initializers calling built-in functions
+
+
+
+
+