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2018-08-16bin: split `write_if_different()` outEric Engestrom1-7/+14
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-08-16bin: whitespace cleanupEric Engestrom1-3/+3
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-08-16radv: Revert divisor = 0 case for vertex attribute extension.Bas Nieuwenhuizen1-1/+1
Seems like DXVK depends on that and it might get reverted upstream. Since apps are not supposed to use 0 in v2 anyway, we should be safe implementing the old behavior there. Fixes: 66e12451ac4 "radv: Update to new VK_EXT_vertex_attribute_divisor to version 2." CC: 18.2 <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-16radv: Possible on-demand compilation fix.Bas Nieuwenhuizen1-0/+8
Seems that in a single case we use the renderpass before checking the pipeline, so check the renderpass before we use it. Fixes: fbcd1673144 "radv: Add on-demand compilation of built-in shaders." Tested-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-16mesa/st: fix array indices off-by-one error in remappingGert Wollny2-6/+6
When moving the array sizes from the old list to the new one it was not taken into account that the array indices start with one, but the array_size array started at index zero, which resulted in incorrect array sizes when arrays were merged. Correct this by copying the array_size values of the retained arrays with an offset of -1. Also fix whitespaces for the replaced lines. Fixes: d8c2119f9b0b257a23ceb398f6d0d78da916417e mesa/st/glsl_to_tgsi: Expose array live range tracking and merging Signed-off-by: Gert Wollny <gw.fossdev@gmail.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-08-15meson: fix build for egl platform_x11 without dri3 and gbmAlexander Tsoy1-1/+1
Compiling EGL's platform_x11 without dri3 and gbm yields this compile failure: platform_x11 needs inc_loader: ../mesa-18.2.0-rc2/src/egl/drivers/dri2/platform_x11.c:48:10: fatal error: loader.h: No such file or directory #include "loader.h" ^~~~~~~~~~ Fixes: 108d257a1685 ("meson: build libEGL") Bugzilla: https://bugs.gentoo.org/663534 Reviewed-by: Matt Turner <mattst88@gmail.com>
2018-08-15Revert "intel/nir: Call nir_lower_io_to_scalar_early"Jason Ekstrand1-12/+5
Commit 4434591bf56a6b0 caused substantially more URB messages in geometry and tessellation shaders. Before we can really enable this sort of optimization, We either need some way of combining them back together into vectors or we need to do cross-stage vector element elimination without splitting everything into scalars. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107510 Fixes: 4434591bf56a6 "intel/nir: Call nir_lower_io_to_scalar_early" Acked-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Mark Janes <mark.a.janes@intel.com>
2018-08-15i965: do not emit empty surface stateErik Faye-Lund1-0/+5
If called with an empty size, brw_emit_buffer_surface_state asserts. We already have a dedicated helper for uploading nothing, so let's use that instead. Avoids an assert in dEQP-GLES31.functional.shaders.opaque_type_indexing.ssbo.const_literal_vertex when running a debug build of i965. Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-08-15intel/ppgtt: 4096 replaced by PAGE_SIZESergii Romantsov1-6/+6
Usage of number 4096 replaced by PAGE_SIZE. Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-08-15intel/ppgtt: memory address alignmentSergii Romantsov1-4/+3
Kernel (for ppgtt) requires memory address to be aligned to page size (4096). -v2: added marking that also fixes initial commit 01058a552294. -v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned instead of alignment of offsets (Chris Wilson). -v4: changes related to PAGE_SIZE moved to separate commit -v5: restored alignment to page-size for 0-size. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997 Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.) Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure to brw_bufmgr.) Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-08-16radv: add Doom workaroundTimothy Arceri1-0/+3
Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-15i965: Emitting 3DSTATE_SO_BUFFER of 0-size.Sergii Romantsov1-4/+5
Avoided filling of whole structure and bo-allocation if size of surface is 0. Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
2018-08-15virgl: report actual max-texture sizesErik Faye-Lund2-0/+10
Instead of doing conservative guesses, we should report the max levels based on the max sizes we get from GL on the host. Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>
2018-08-15virgl: do not use SP_MAX_TEXTURE_*_LEVELS definesErik Faye-Lund1-7/+3
These macro-names are also used for softpipe, so let's avoid confusion by avoiding them. Besides, they are just used in one place in virgl, so let's just inline them into the place they are used instead. While we're at it, fixup an error in the comment for the 3D version. Mesa subtracts computes max-size by doing by 2^(n-1), which means this should be 256 cubed, not 512 cubed. The other comments are correct. Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>
2018-08-15docs: Add news item for 18.1.6Dylan Baker1-0/+6
2018-08-15radv: disable the auto-waitcnt-before-barrier LLVM optionSamuel Pitoiset3-1/+4
This option allows us to remove additional s_waitcnt instructions because s_barrier internally does s_waitcnt 0. Though, apparently there is a problem with LDS accesses that causes rendering issues with FFXV and DXVK. Disable this optimization for now (RadeonSI still uses it). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107460 CC: 18.2 <mesa-stable@lists.freedesktop.org> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-15radv: fix memory leaks in radv_load_meta_pipeline()Samuel Pitoiset1-2/+3
Reported by Coverity. Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-15radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITSSamuel Pitoiset1-3/+1
The last parameter of radeon_set_sh_reg_seq() is the number of dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but it was initialized to 0. COMPUTE_RESOURCE_LIMITS is correctly set when generating compute pipelines, so we don't need to initialize it. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-15docs: update calendar 18.2.0-rc3 is outAndres Gomez1-8/+2
Signed-off-by: Andres Gomez <agomez@igalia.com>
2018-08-15radv/meta_decompress: fix pointer to integer conversionMauro Rossi1-1/+1
VK_NULL_HANDLE replaces NULL to avoid following building error: external/mesa/src/amd/vulkan/radv_meta_decompress.c:365:54: error: incompatible pointer to integer conversion passing 'void *' to parameter of type 'VkShaderModule' (aka 'unsigned long long') [-Werror,-Wint-conversion] VkResult ret = create_pipeline(cmd_buffer->device, NULL, samples, ^~~~ prebuilts/clang/host/linux-x86/clang-4053586/lib64/clang/5.0.300080/include/stddef.h:105:16: note: expanded from macro 'NULL' # define NULL ((void*)0) ^~~~~~~~~~ external/mesa/src/amd/vulkan/radv_meta_decompress.c:97:32: note: passing argument to parameter 'vs_module_h' here VkShaderModule vs_module_h, ^ 1 error generated. Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.") Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-15egl/android: fix regression in drm_gralloc path (v2)Mauro Rossi1-0/+23
This patch fixes a regression in mesa 18.2 and mesa-dev branches for HAVE_DRM_GRALLOC code path which is causing black screen on Android and prevents boot due to SIGSEGV MAPERR crash related to unproper handling of drm_gralloc drm FD in new droid_open_device() path. Problem is due to c7bb82136b ("egl/android: Add DRM node probing and filtering") To avoid the crash the former existing working droid_open_device() is restored, renamed droid_open_device_drm_gralloc() and kept within HAVE_DRM_GRALLOC braces. Tested with mesa-dev and mesa 18.2 branch and oreo-x86 bootanimation and Androdi GUI booting is fixed with i965, nouveau, radeon. The changes are compatible with gbm_gralloc, I've tested build with hwc too. (v2) remove indentation from HAVE_DRM_GRALLOC pre-processor directive NOTE: Definition of enum{} for GRALLOC_MODULE_PERFORM_GET_DRM_FD is not necessary and it's actually causing a redefinition building error, because in HAVE_DRM_GRALLOC path gralloc_drm.h is already exported by libgralloc_drm which is currently still a dependency. Fixes: c7bb82136b ("egl/android: Add DRM node probing and filtering") Cc: "18.2" <mesa-stable@lists.freedesktop.org> Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
2018-08-15mesa: shader dump/read support for ARB programsTapani Pälli3-7/+31
Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106283 Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2018-08-15glsl: Avoid calling get_array_element for scalar constantsDanylo Piliaiev1-1/+1
Accessing scalar constant as an array in function call or initializer list triggered assert in get_array_element. Examples: func(0[0]); vec2 t = { 0[0], 0 }; Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107550 Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-08-14radeonsi: enable 1 missing PS_SU perf counter on PolarisMarek Olšák1-1/+1
2018-08-14radeonsi: use radeon_info::nameMarek Olšák3-40/+12
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-08-14ac: add radeon_info::nameMarek Olšák3-2/+12
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-08-14radeonsi: split si_clear_buffer to remove enum si_methodMarek Olšák6-53/+60
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: replace CP_DMA_USE_L2 with enum si_cache_policyMarek Olšák2-26/+41
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: declare coher in si_copy_bufferMarek Olšák1-8/+7
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: make PFP_SYNC_ME an explicit CP DMA flagMarek Olšák1-17/+25
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: don't use emit_data->args in load_emitMarek Olšák1-94/+37
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: don't use emit_data->args in store_emitMarek Olšák1-92/+71
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: don't use emit_data->args in atomic_emitMarek Olšák3-36/+47
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: don't use emit_data->args in build_interp_intrinsicMarek Olšák1-19/+13
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: inline atomic_fetch_argsMarek Olšák1-74/+51
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: inline store_fetch_argsMarek Olšák1-61/+42
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: inline load_fetch_argsMarek Olšák1-39/+28
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: merge txq_emit and resq_emitMarek Olšák1-48/+45
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: inline resq_fetch_argsMarek Olšák1-62/+34
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: inline txq_fetch_argsMarek Olšák1-26/+7
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: use get_resinfo directly in lower_gather4_integerMarek Olšák1-13/+12
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: inline tex_fetch_args into build_tex_intrinsicMarek Olšák1-222/+188
The diff looks like it moves code that I didn't touch. Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: remove fetch_args callbacks for ALU instructionsMarek Olšák2-103/+55
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: move internal TGSI shaders into si_shaderlib_tgsi.cMarek Olšák8-319/+348
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14radeonsi: implement EXT_window_rectanglesMarek Olšák9-2/+112
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14gallium/u_blitter: save/restore window rectanglesMarek Olšák2-0/+29
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14noop: implement set_window_rectanglesMarek Olšák1-0/+8
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14ddebug: implement set_window_rectanglesMarek Olšák1-0/+12
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-14i965: Add a new CFL PCI ID.Rodrigo Vivi1-0/+1
One more CFL ID added to spec. Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl: Add a new CFL PCI ID.") Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Anuj Phogat <anuj.phogat@gmail.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-08-14freedreno/ir3: add support for a6xx 'merged' register setRob Clark2-2/+24
Starting with a6xx, half and full precision registers conflict. Which makes things a bit more efficient, ie. if some parts of the shader are heavy on half-precision and others on full precision, you don't have to allocate the worst case for both. But it means we need to setup some additional conflicts. Signed-off-by: Rob Clark <robdclark@gmail.com>
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