~johnharr/scheduler - i915 GPU scheduler patches

Age	Commit message (Expand)	Author	Files	Lines
2016-04-03	MIPS: tlb-r4k: panic if the MMU doesn't support PAGE_SIZE	Paul Burton	1	-0/+5
2015-06-21	MIPS: BCM77xx: Remove legacy __cpuinit{,data} sections that crept in	Paul Gortmaker	1	-1/+1
2015-05-15	MIPS: tlb-r4k: Fix PG_ELPA comment	James Hogan	1	-1/+1
2015-04-13	Merge branch '4.0-fixes' into mips-for-linux-next	Ralf Baechle	1	-0/+12
2015-04-01	MIPS: Add R16000 detection	Joshua Kinard	1	-1/+2
2015-03-19	MIPS: Add support for XPA.	Steven J. Hill	1	-0/+12
2015-02-20	MIPS: Add set/clear CP0 macros for PageGrain register	Steven J. Hill	1	-3/+3
2014-11-24	MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT	Ralf Baechle	1	-1/+1
2014-11-19	MIPS: tlb-r4k: Add missing HTW stop/start sequences	Markos Chandras	1	-0/+4
2014-08-02	MIPS: mm: Use the Hardware Page Table Walker if the core supports it	Markos Chandras	1	-0/+12
2014-07-30	MIPS: BCM47XX: Detect more then 128 MiB of RAM (HIGHMEM)	Rafał Miłecki	1	-1/+1
2014-07-30	Revert "MIPS: Delete unused function add_temporary_entry."	Rafał Miłecki	1	-0/+47
2014-05-29	Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into mips-f...	Ralf Baechle	1	-1/+33
2014-05-24	MIPS: MT: Remove SMTC support	Ralf Baechle	1	-38/+16
2014-05-02	MIPS: tlb-r4k: Add CPU PM callback to reconfigure TLB	James Hogan	1	-1/+33
2014-03-31	MIPS: Loongson: Add basic Loongson-3 CPU support	Huacai Chen	1	-2/+3
2014-01-22	MIPS: Add support for FTLBs	Leonid Yegoshin	1	-7/+22
2014-01-22	MIPS: mm: Use the TLBINVF instruction to flush the VTLB	Leonid Yegoshin	1	-6/+12
2014-01-22	MIPS: mm: Move UNIQUE_ENTRYHI macro to a header file	Markos Chandras	1	-6/+1
2013-10-29	MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips.	Ralf Baechle	1	-16/+21
2013-09-17	MIPS: Optimize current_cpu_type() for better code.	Ralf Baechle	1	-0/+1
2013-07-14	MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code	Paul Gortmaker	1	-2/+2
2013-05-16	Revert "MIPS: Allow ASID size to be determined at boot time."	David Daney	1	-1/+1
2013-05-09	Merge branch 'mti-next' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhi...	Ralf Baechle	1	-1/+1
2013-05-08	MIPS: Allow ASID size to be determined at boot time.	Steven J. Hill	1	-1/+1
2013-05-08	MIPS: Export routines needed by the KVM module.	Sanjay Lal	1	-0/+2
2013-02-01	MIPS: Whitespace cleanup.	Ralf Baechle	1	-1/+1
2012-12-14	Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus	Linus Torvalds	1	-1/+21
2012-12-12	MIPS: Transparent Huge Pages support	Ralf Baechle	1	-0/+20
2012-12-12	MIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORT	David Daney	1	-1/+1
2012-12-04	MIPS: Avoid mcheck by flushing page range in huge_ptep_set_access_flags()	David Daney	1	-14/+4
2012-10-17	MIPS: hugetlbfs: Fix hazard between tlb write and pagemask restoration.	Ralf Baechle	1	-0/+1
2012-09-13	MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.	Steven J. Hill	1	-1/+1
2012-03-28	Disintegrate asm/system.h for MIPS	David Howells	1	-1/+0
2012-01-11	Merge branch 'next/generic' into mips-for-linux-next	Ralf Baechle	1	-53/+14
2012-01-11	MIPS: Delete unused function add_temporary_entry.	Ralf Baechle	1	-47/+0
2012-01-11	MIPS: Flush huge TLB	Hillf Danton	1	-6/+14
2011-12-07	MIPS: Fix Jazz 64-bit build error.	Ralf Baechle	1	-0/+1
2011-10-24	MIPS: Remove __init from add_wired_entry()	Manuel Lauss	1	-2/+2
2011-04-06	update David Miller's old email address	Justin P. Mattock	1	-1/+1
2010-02-27	MIPS: Implement Read Inhibit/eXecute Inhibit	David Daney	1	-3/+16
2010-02-27	MIPS: Remove #if 0 r4k_update_mmu_cache_hwbug	David Daney	1	-34/+0
2010-02-27	MIPS: Remove probe_tlb().	David Daney	1	-31/+0
2009-09-17	MIPS: Remove useless zero initializations.	Ralf Baechle	1	-1/+1
2009-06-24	MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.	Ralf Baechle	1	-0/+1
2009-06-17	MIPS: TLB support for hugetlbfs.	David Daney	1	-11/+32
2009-05-20	MIPS: 64-bit: Fix system lockup.	Greg Ungerer	1	-4/+2
2009-01-11	MIPS: Only write c0_framemask on CPUs which have this register.	Ralf Baechle	1	-1/+4
2008-04-28	[MIPS] All MIPS32 processors support64-bit physical addresses.	Chris Dearman	1	-1/+1
2008-03-12	[MIPS] Fix loads of section missmatches	Ralf Baechle	1	-4/+4