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| author | Dave Gordon <david.s.gordon@intel.com> | 2016-05-18 20:11:19 +0100 |
|---|---|---|
| committer | John Harrison <John.C.Harrison@Intel.com> | 2016-06-28 17:19:32 +0100 |
| commit | 03628da19c188979eb1eaa7f15d82d19d3d8b351 (patch) | |
| tree | 01d9249eb081b7118b6b9c686fa4befe5cd8a6cb /Documentation/spi | |
| parent | a21a4f47f5e9cf4d5ca5be4784cf4571157c01bd (diff) | |
drm/i915: Various attempts to fix mid-thread preemption
The changes in gen8_emit_pipe_control_qw_store_index() and
gen8_emit_flush_coherentl3_wa() are probably necessary, or at least more
strictly correct than the current code.
OTOH turning preemption off/on in gen9_init_indirectctx_bb() and
gen9_init_perctx_bb() is just a hack, in case it isn't really fixed in
SKL D1+.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Diffstat (limited to 'Documentation/spi')
0 files changed, 0 insertions, 0 deletions