diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-04-11 16:56:25 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-04-12 19:07:13 +0300 |
| commit | 9918271efc7ab9e5efc9580270f67c126901b06f (patch) | |
| tree | df8b78bad760f4a1ed77fbbe4898278bc3dc7cd1 | |
| parent | ad22d10654ea0e5eb46fa46ae3f716bfc1d43ce3 (diff) | |
drm/i915: Skip display irq setup if display irqs aren't flagged as enabled
During runtime PM we'll be reinitializing interrupt support from the
ground up. However since the display power well will be off at that
time, well end up with a ton of unclaimed register accesses from the
display irq setup. Since we turned off the power well already before
runtime suspend, we've flagged display irqs as disabled during runtime
PM transitions. So we can just check that flag to see if we should do
skip display irqs during irq setup.
During driver load display irqs will be flagged as enabled since we've
turned on the power well already, however the power well code will have
skipped the display irq setup since irq support as a whole wasn't yet
enabled when the power well was enabled. So we'll want to do the display
irq setup in that case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460382992-28728-4-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 0fcd8b24a1de..68981aee35b7 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3329,7 +3329,8 @@ static void valleyview_irq_preinstall(struct drm_device *dev) I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_reset(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_reset(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); } @@ -3406,7 +3407,8 @@ static void cherryview_irq_preinstall(struct drm_device *dev) I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_reset(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_reset(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); } @@ -3728,7 +3730,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev) #endif spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_postinstall(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_postinstall(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); @@ -3834,7 +3837,8 @@ static int cherryview_irq_postinstall(struct drm_device *dev) gen8_gt_irq_postinstall(dev_priv); spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_postinstall(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_postinstall(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); @@ -3867,7 +3871,8 @@ static void valleyview_irq_uninstall(struct drm_device *dev) I915_WRITE(HWSTAM, 0xffffffff); spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_reset(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_reset(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); } @@ -3886,7 +3891,8 @@ static void cherryview_irq_uninstall(struct drm_device *dev) GEN5_IRQ_RESET(GEN8_PCU_); spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_reset(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_reset(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); } |