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authorJohn Harrison <John.C.Harrison@Intel.com>2014-09-08 14:31:24 +0100
committerJohn Harrison <John.C.Harrison@Intel.com>2016-05-06 14:12:51 +0100
commit61350574b209353dab5ea7c7c2cef03f6d6f0c83 (patch)
treec401f5a8df712d9a443f7788518579a1b24469ad
parent41c6d062c16ba87026e172aebae1d0f64056712d (diff)
drm/i915: Force MMIO flips when scheduler enabled
MMIO flips are the preferred mechanism now but more importantly, pipe based flips cause issues for the scheduler. Specifically, submitting work to the rings around the side of the scheduler could cause that work to be lost if the scheduler generates a pre-emption event on that ring. For: VIZ-1587 Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 276bbd34fcd0..531553de0453 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -47,6 +47,7 @@
#include <linux/dma_remapping.h>
#include <linux/reservation.h>
#include <linux/dma-buf.h>
+#include "i915_scheduler.h"
/* Primary plane formats for gen <= 3 */
static const uint32_t i8xx_primary_formats[] = {
@@ -11241,6 +11242,8 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
return true;
else if (i915.enable_execlists)
return true;
+ else if (i915_scheduler_is_enabled(engine->dev))
+ return true;
else if (obj->base.dma_buf &&
!reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
false))