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authorTim Gore <tim.gore@intel.com>2016-02-23 16:40:12 +0000
committerJohn Harrison <John.C.Harrison@Intel.com>2016-06-28 17:19:28 +0100
commite0771b38800a32e3e9dc5d65976d9a8ed115e19c (patch)
tree37406ed643f0f46fbeeb1788eb7a70e0d73a1dd2
parentd09607f665c825b4ee7e5f6a2c9cea1fc07e278d (diff)
drm/i915/gen9: add WaEnableSamplerGPGPUPreemptionSupport
WaEnableSamplerGPGPUPreemptionSupport fixes a problem related to mid thread pre-emption. Change-Id: Idea8e709eaa94e5d7addf901b4fb5d40fd744603 Tracked-On: https://jira01.devtools.intel.com/browse/OAM-21345 Signed-off-by: Tim Gore <tim.gore@intel.com>
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c8
2 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4daecbdaffe2..e02efb18cb1e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7159,6 +7159,7 @@ enum skl_disp_power_wells {
#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
#define GEN9_ENABLE_YV12_BUGFIX (1<<4)
+#define GEN9_ENABLE_GPGPU_PREEMPTION (1<<2)
/* Audio */
#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 317019cf86d6..9f279026f805 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -960,9 +960,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
}
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
- if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
- WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
- GEN9_ENABLE_YV12_BUGFIX);
+ /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */
+ WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
+ GEN9_ENABLE_YV12_BUGFIX |
+ GEN9_ENABLE_GPGPU_PREEMPTION);
+
/* Wa4x4STCOptimizationDisable:skl,bxt */
/* WaDisablePartialResolveInVc:skl,bxt */