drm/i915: rationalise PIPE_CONTROL flag naming & add commentary

The names used for the various flag bits in the PIPE_CONTROL instruction
are neither self-consistent nor self-explanatory, nor, in some cases,
easily mapped to the names used in the BSpec,

This patch renames a few of them to reduce ambiguity (DC != Depth
Cache) or increase consistency (e.g. remove "ENABLE" everywhere),
and explain which bits are supposed to go where (pre-SNB vs SNB vs
post-SNB).

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>

4 files changed, 36 insertions, 20 deletions

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index a337f33bec5b..fbdd9da32c14 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -199,7 +199,7 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
 	      },
 	      {
 			.offset = 1,
-		        .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
+		        .mask = (PIPE_CONTROL_GEN7_GLOBAL_GTT |
 				 PIPE_CONTROL_STORE_DATA_INDEX),
 			.expected = 0,
 			.condition_offset = 1,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e02efb18cb1e..b1a9865cbf6d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -477,31 +477,47 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define   ASYNC_FLIP                (1<<22)
 #define   DISPLAY_PLANE_A           (0<<20)
 #define   DISPLAY_PLANE_B           (1<<20)
+
+/* 'len' here should be 4 pre-SNB, 5 for SNB/IVB/HSW, 6 thereafter */
 #define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
 #define   PIPE_CONTROL_FLUSH_L3				(1<<27)
-#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
+#define   PIPE_CONTROL_LLC_FB_FLUSH			(1<<26)
+#define   PIPE_CONTROL_GEN7_GLOBAL_GTT			(1<<24)	/* gen7+ */
 #define   PIPE_CONTROL_MMIO_WRITE			(1<<23)
 #define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
 #define   PIPE_CONTROL_CS_STALL				(1<<20)
 #define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
 #define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
+/*
+ * Pre-SNB, bits 15-8 only (where valid) were part of the opcode word.
+ * For SNB+, they're in the separate 'flags' word, after the opcode.
+ */
 #define   PIPE_CONTROL_QW_WRITE				(1<<14)
 #define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
 #define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
-#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)
+#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)	/* gen5 */
 #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */
 #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */
 #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */
 #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)
 #define   PIPE_CONTROL_NOTIFY				(1<<8)
-#define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */
-#define   PIPE_CONTROL_DC_FLUSH_ENABLE			(1<<5)
+#define   PIPE_CONTROL_POSTSYNC_FLUSH			(1<<7)	/* gen7+ */
+#define   PIPE_CONTROL_L3_DC_FLUSH			(1<<5)
 #define   PIPE_CONTROL_VF_CACHE_INVALIDATE		(1<<4)
 #define   PIPE_CONTROL_CONST_CACHE_INVALIDATE		(1<<3)
 #define   PIPE_CONTROL_STATE_CACHE_INVALIDATE		(1<<2)
+/*
+ * On ILK, bits 1-0 were in DWord 1 (32-bit address).
+ * For SNB+, they're still in DWord 1, but it's now 'flags'
+ */
 #define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)
 #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)
-#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+
+/*
+ * The GGTT bit was part of DWord 1 (address) pre-SNB, then part of DWord 2
+ * (address) in SNB, then replaced by bit 24 of the opcode word in Gen7+
+ */
+#define   PIPE_CONTROL_GLOBAL_GTT 			(1<<2)	/* in addr dword */
 
 /*
  * Commands used only by the command parser
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9a70f1cfea90..ba2bd0849765 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1136,7 +1136,7 @@ gen8_emit_pipe_control_qw_store_index(struct drm_i915_gem_request *request,
 
 	cmd = GFX_OP_PIPE_CONTROL(6);
 
-	opts = PIPE_CONTROL_GLOBAL_GTT_IVB;	/* Address via GGTT	*/
+	opts = PIPE_CONTROL_GEN7_GLOBAL_GTT;	/* Address via GGTT	*/
 	opts |= PIPE_CONTROL_STORE_DATA_INDEX;	/* Index into HWSP	*/
 	opts |= PIPE_CONTROL_CS_STALL;		/* Stall CS until done	*/
 	opts |= PIPE_CONTROL_QW_WRITE;		/* Write QWord		*/
@@ -1570,7 +1570,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
 
 	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
 	wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
-				   PIPE_CONTROL_DC_FLUSH_ENABLE));
+				   PIPE_CONTROL_L3_DC_FLUSH));
 	wa_ctx_emit(batch, index, 0);
 	wa_ctx_emit(batch, index, 0);
 	wa_ctx_emit(batch, index, 0);
@@ -1657,7 +1657,7 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
 
 	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
 	wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
-				   PIPE_CONTROL_GLOBAL_GTT_IVB |
+				   PIPE_CONTROL_GEN7_GLOBAL_GTT |
 				   PIPE_CONTROL_CS_STALL |
 				   PIPE_CONTROL_QW_WRITE));
 	wa_ctx_emit(batch, index, scratch_addr);
@@ -2102,8 +2102,8 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 	if (flush_domains) {
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
-		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
-		flags |= PIPE_CONTROL_FLUSH_ENABLE;
+		flags |= PIPE_CONTROL_L3_DC_FLUSH;
+		flags |= PIPE_CONTROL_POSTSYNC_FLUSH;
 	}
 
 	if (invalidate_domains) {
@@ -2114,7 +2114,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_QW_WRITE;
-		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+		flags |= PIPE_CONTROL_GEN7_GLOBAL_GTT;
 
 		/*
 		 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9f279026f805..c243b324c56c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -332,8 +332,8 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
 	if (flush_domains) {
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
-		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
-		flags |= PIPE_CONTROL_FLUSH_ENABLE;
+		flags |= PIPE_CONTROL_L3_DC_FLUSH;
+		flags |= PIPE_CONTROL_POSTSYNC_FLUSH;
 	}
 	if (invalidate_domains) {
 		flags |= PIPE_CONTROL_TLB_INVALIDATE;
@@ -347,7 +347,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
 		 * TLB invalidate requires a post-sync write.
 		 */
 		flags |= PIPE_CONTROL_QW_WRITE;
-		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+		flags |= PIPE_CONTROL_GEN7_GLOBAL_GTT;
 
 		flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 
@@ -405,8 +405,8 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
 	if (flush_domains) {
 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
-		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
-		flags |= PIPE_CONTROL_FLUSH_ENABLE;
+		flags |= PIPE_CONTROL_L3_DC_FLUSH;
+		flags |= PIPE_CONTROL_POSTSYNC_FLUSH;
 	}
 	if (invalidate_domains) {
 		flags |= PIPE_CONTROL_TLB_INVALIDATE;
@@ -416,7 +416,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 		flags |= PIPE_CONTROL_QW_WRITE;
-		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
+		flags |= PIPE_CONTROL_GEN7_GLOBAL_GTT;
 
 		/* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 		ret = gen8_emit_pipe_control(req,
@@ -1301,9 +1301,9 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
 
 		seqno = i915_gem_request_get_seqno(signaller_req);
 		intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
-		intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
+		intel_ring_emit(signaller, PIPE_CONTROL_GEN7_GLOBAL_GTT |
 					   PIPE_CONTROL_QW_WRITE |
-					   PIPE_CONTROL_FLUSH_ENABLE);
+					   PIPE_CONTROL_POSTSYNC_FLUSH);
 		intel_ring_emit(signaller, lower_32_bits(gtt_offset));
 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 		intel_ring_emit(signaller, seqno);