diff options
| author | Dave Gordon <david.s.gordon@intel.com> | 2016-05-18 20:11:19 +0100 |
|---|---|---|
| committer | John Harrison <John.C.Harrison@Intel.com> | 2016-06-28 17:19:32 +0100 |
| commit | 03628da19c188979eb1eaa7f15d82d19d3d8b351 (patch) | |
| tree | 01d9249eb081b7118b6b9c686fa4befe5cd8a6cb | |
| parent | a21a4f47f5e9cf4d5ca5be4784cf4571157c01bd (diff) | |
drm/i915: Various attempts to fix mid-thread preemption
The changes in gen8_emit_pipe_control_qw_store_index() and
gen8_emit_flush_coherentl3_wa() are probably necessary, or at least more
strictly correct than the current code.
OTOH turning preemption off/on in gen9_init_indirectctx_bb() and
gen9_init_perctx_bb() is just a hack, in case it isn't really fixed in
SKL D1+.
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 8f5d1051ac48..701169d43df4 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1169,6 +1169,7 @@ gen8_emit_pipe_control_qw_store_index(struct drm_i915_gem_request *request, intel_logical_ring_emit(ringbuf, data1); intel_logical_ring_emit(ringbuf, data2); + opts &= ~PIPE_CONTROL_STALL_AT_SCOREBOARD; opts |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; opts |= flags; /* Extra flag bits */ intel_logical_ring_emit(ringbuf, cmd); @@ -1319,6 +1320,7 @@ emit_preemption_control(struct drm_i915_gem_request *req) intel_logical_ring_emit(ringbuf, mid_thread_mode); intel_logical_ring_emit_reg(ringbuf, GEN8_CS_CHICKEN1); intel_logical_ring_emit(ringbuf, mid_thread_mode | allow_mid_object); + intel_logical_ring_emit(ringbuf, MI_NOOP); } /* @@ -1724,6 +1726,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); wa_ctx_emit(batch, index, l3sqc4_flush); + wa_ctx_emit(batch, index, MI_NOOP); wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | @@ -1910,9 +1913,11 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); /* WaDisableCtxRestoreArbitration:skl,bxt */ - if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) + if (IS_SKL_REVID(dev, 0, REVID_FOREVER) || + IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); + wa_ctx_emit(batch, index, MI_NOOP); + } /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); @@ -1946,9 +1951,11 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine, } /* WaDisableCtxRestoreArbitration:skl,bxt */ - if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) + if (IS_SKL_REVID(dev, 0, REVID_FOREVER) || + IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); + wa_ctx_emit(batch, index, MI_NOOP); + } wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |