diff options
| author | Rafael Antognolli <rafael.antognolli@intel.com> | 2019-04-29 11:05:07 -0700 |
|---|---|---|
| committer | Rafael Antognolli <rafael.antognolli@intel.com> | 2019-10-30 19:51:03 +0000 |
| commit | d3995c19ebad8c0502ef3a6a88935a6e45d57c11 (patch) | |
| tree | ba59af1fa9f9b66a422d51b36c00015184a2f1d0 | |
| parent | f573cd4757355c5ffe66c90ad6e08265865ec730 (diff) | |
iris: Add Tile Cache Flush for Unified Cache.
| -rw-r--r-- | src/gallium/drivers/iris/iris_context.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 20 |
2 files changed, 21 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index 70279a6a91f..b917e3e0de6 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -222,6 +222,7 @@ enum pipe_control_flags PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), PIPE_CONTROL_STALL_AT_SCOREBOARD = (1 << 23), PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24), + PIPE_CONTROL_TILE_CACHE_FLUSH = (1 << 25), }; #define PIPE_CONTROL_CACHE_FLUSH_BITS \ diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 394781fd584..da181b187a1 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6788,6 +6788,23 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, flags |= PIPE_CONTROL_CS_STALL; } + if (GEN_GEN >= 12 && ((flags & PIPE_CONTROL_RENDER_TARGET_FLUSH) || + (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH))) { + /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush + * Enable): + * + * Unified Cache (Tile Cache Disabled): + * + * When the Color and Depth (Z) streams are enabled to be cached in + * the DC space of L2, Software must use "Render Target Cache Flush + * Enable" and "Depth Cache Flush Enable" along with "Tile Cache + * Flush" for getting the color and depth (Z) write data to be + * globally observable. In this mode of operation it is not required + * to set "CS Stall" upon setting "Tile Cache Flush" bit. + */ + flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; + } + if (GEN_GEN == 9 && devinfo->gt == 4) { /* TODO: The big Skylake GT4 post sync op workaround */ } @@ -6910,6 +6927,9 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, } iris_emit_cmd(batch, GENX(PIPE_CONTROL), pc) { +#if GEN_GEN >= 12 + pc.TileCacheFlushEnable = flags & PIPE_CONTROL_TILE_CACHE_FLUSH; +#endif pc.LRIPostSyncOperation = NoLRIOperation; pc.PipeControlFlushEnable = flags & PIPE_CONTROL_FLUSH_ENABLE; pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH; |