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| author | Christian Gmeiner <cgmeiner@igalia.com> | 2024-03-06 15:02:28 +0100 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2024-03-12 17:02:44 +0000 |
| commit | 20678b92048c0644201c3767455ec6b6d7df4d00 (patch) | |
| tree | 6786732da52e9e82c6697beb6b10c5741777eb0c | |
| parent | ccc99bd42dcd629556741e2da9bcd9fd52725fd7 (diff) | |
etnaviv: isa: Fix #instruction-tex-src0-src1-src2 bitset
src1 got wrong values.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
| -rw-r--r-- | src/etnaviv/isa/etnaviv.xml | 6 | ||||
| -rw-r--r-- | src/etnaviv/isa/tests/disasm.cpp | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/etnaviv/isa/etnaviv.xml b/src/etnaviv/isa/etnaviv.xml index 50fc3112c04..65eef03c59e 100644 --- a/src/etnaviv/isa/etnaviv.xml +++ b/src/etnaviv/isa/etnaviv.xml @@ -692,9 +692,9 @@ SPDX-License-Identifier: MIT <pattern pos="70">1</pattern> <!-- SRC1_USE --> <field name="SRC1_REG" low="71" high="79" type="uint"/> <field name="SRC1" low="81" high="90" type="#instruction-src"> - <param name="SRC2_REG" as="SRC_REG"/> - <param name="SRC2_AMODE" as="SRC_AMODE"/> - <param name="SRC2_RGROUP" as="SRC_RGROUP"/> + <param name="SRC1_REG" as="SRC_REG"/> + <param name="SRC1_AMODE" as="SRC_AMODE"/> + <param name="SRC1_RGROUP" as="SRC_RGROUP"/> </field> <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> diff --git a/src/etnaviv/isa/tests/disasm.cpp b/src/etnaviv/isa/tests/disasm.cpp index 542d6f5b96a..320284c0a5e 100644 --- a/src/etnaviv/isa/tests/disasm.cpp +++ b/src/etnaviv/isa/tests/disasm.cpp @@ -112,7 +112,7 @@ INSTANTIATE_TEST_SUITE_P(Opcodes, DisasmTest, disasm_state{ {0x00000057, 0x00002800, 0x00000040, 0x00000002}, "texkill.gt.pack void, t2.xxxx, u0.xxxx, void\n" }, disasm_state{ {0x07811018, 0x15001f20, 0x00000000, 0x00000000}, "texld t1, tex0.xyzw, t1.xyyy, void, void\n" }, disasm_state{ {0x07811019, 0x39002f20, 0x00000000, 0x00000000}, "texldb t1, tex0.xyzw, t2.xyzw, void, void\n" }, - disasm_state{ {0x0781101a, 0x15001f20, 0x00a80140, 0x003f8018}, "texldd t1, tex0.xyzw, t1.xyyy, t1.xyyy, t1.zwww\n" }, + disasm_state{ {0x0781101a, 0x15001f20, 0x00a80140, 0x003f8018}, "texldd t1, tex0.xyzw, t1.xyyy, t2.xyyy, t1.zwww\n" }, disasm_state{ {0x4781101b, 0x39003f20, 0x00000000, 0x00000000}, "texldl t1, tex8.xyzw, t3.xyzw, void, void\n" }, disasm_state{ {0x00801021, 0x00000004, 0x00000000, 0x00000008}, "sqrt t0.x___, void, void, t0.xxxx\n" }, disasm_state{ {0x03001022, 0x00000005, 0x00000000, 0x00154008}, "sin.rtz t0.zy, void, void, t0.yyyy\n" }, @@ -306,7 +306,7 @@ INSTANTIATE_TEST_SUITE_P(texldlpcf, DisasmTest, testing::Values( // taken from dEQP-GLES3.functional.shaders.texture_functions.texturelod.sampler2dshadow_vertex (GC7000) disasm_state{ {0x04011809, 0x00000004, 0x00000000, 0x002a8018}, "mov.sat t1.___w, void, void, t1.zzzz\n"}, - disasm_state{ {0x0081102f, 0x29001800, 0x00010140, 0x003fc018}, "texldlpcf t1.x___, tex0.xxxx, t1.xyzz, t1.xxxx, t1.wwww\n"}, + disasm_state{ {0x0081102f, 0x29001800, 0x00010140, 0x003fc018}, "texldlpcf t1.x___, tex0.xxxx, t1.xyzz, t2.xxxx, t1.wwww\n"}, disasm_state{ {0x07011009, 0x00000004, 0x00000000, 0x20390018}, "mov t1._yzw, void, void, u1.xyzw\n"} ) ); |